Frequency following sampling and dual frequency calibration method and system for synchronization check set

Abstract

This invention provides a frequency following sampling and dual-frequency calibration method and system for synchronization inspection devices, relating to the field of power system signal processing technology. The method includes: calculating the frequency of the rising edge of the system-side voltage signal and the rising edge of the voltage signal to be paralleled on the target side to generate a stable frequency on the system side and a stable frequency on the target side; determining the validity and balance of the stable frequencies on the system side and the target side, using a frequency following strategy to determine the effective following frequency and outputting the frequency balance result; dynamically selecting the signal sampling mode by calling a timer reconfiguration function, synchronously sampling the system-side voltage signal and the voltage signal to be paralleled on the target side, and performing a Fourier transform based on the frequency balance result to generate the voltage amplitude on the system side and the voltage amplitude on the target side; and calibrating and correcting the voltage amplitude on the system side and the voltage amplitude on the target side using a linear interpolation algorithm to generate a standard voltage amplitude on the system side and the standard voltage amplitude on the target side, thereby eliminating spectral leakage and improving the measurement accuracy of the voltage amplitude.

Description

Technical Field

[0001] This invention relates to the field of power system signal processing technology, and in particular to a frequency following sampling and dual-frequency calibration method and system for synchronization inspection devices. Background Technology

[0002] With the accelerated construction of power systems, the synchronization inspection device, as a core device to ensure the safe grid connection, needs to quickly and accurately detect and calibrate the voltage amplitude when there is a deviation or even loss of synchronization between the stable frequency on the system side and the stable frequency on the side to be connected, so as to provide a reliable basis for the closing operation.

[0003] Existing synchronous inspection technologies have significant shortcomings in frequency adaptability and amplitude calibration. Current technologies use a fixed sampling frequency to acquire voltage signals. When the stable frequency on the system side and the stable frequency on the side to be connected deviate, it is difficult to guarantee full-cycle sampling conditions, leading to spectral leakage and the picket fence effect in the Fourier transform, resulting in a significant decrease in measurement accuracy. Hardware differences exist between different MCUs (embedded microcontrollers). Existing technologies, using fixed gain compensation or single-frequency calibration, cannot simultaneously eliminate voltage amplitude measurement errors under both 50Hz and 60Hz operating conditions. This results in poor measurement consistency when multiple devices are interchanged, making it difficult to meet the requirements of high-precision grid-connected testing.

[0004] Therefore, it is necessary to provide a frequency following sampling and dual-frequency calibration method and system for synchronous inspection devices to solve the above-mentioned technical problems. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a frequency following sampling and dual-frequency calibration method and system for synchronous inspection devices, which solves the problems of fixed sampling frequency being unable to adapt to dual-channel frequency offset, insufficient calibration accuracy at a single frequency point, and poor measurement consistency among different devices.

[0006] The present invention provides a frequency following sampling and dual-frequency calibration method for a synchronization inspection device, the method comprising: The rising edges of the system-side voltage signal and the voltage signal to be connected are acquired in parallel and the frequencies are calculated to generate the system-side stable frequency and the stable frequency of the to be connected side. The effectiveness and balance between the system-side stable frequency and the stable frequency to be paralleled are determined, and a frequency following strategy is adopted to determine the effective following frequency and output the frequency balance result. Based on the effective following frequency and the frequency balance result, the timer reconfiguration function is called to dynamically select the signal sampling mode. The system-side voltage signal and the voltage signal to be paralleled are synchronously sampled according to the signal sampling mode, and Fourier transform is performed according to the frequency balance result to generate the system-side voltage amplitude and the voltage amplitude to be paralleled. Using the first reference frequency and the second reference frequency, a linear interpolation algorithm is used to calibrate and correct the voltage amplitude of the system side and the voltage amplitude of the side to be connected, thereby generating the standard voltage amplitude of the system side and the standard voltage amplitude of the side to be connected.

[0007] Preferably, the parallel acquisition of the rising edges of the system-side voltage signal and the voltage signal to be paralleled, and the calculation of their frequencies to generate the system-side stable frequency and the stable frequency to be paralleled, specifically includes: The rising edge of the system-side voltage signal is identified through the first input capture channel of the timer, and the time data of two consecutive rising edges of the system-side voltage signal is obtained. The rising edge of the voltage signal to be paralleled is identified through the second input capture channel of the timer, and the time data of two consecutive rising edges of the voltage signal to be paralleled is obtained. Calculate the time difference between the rising edges of two consecutive system-side voltage signals, construct a time difference sequence, and call the frequency calculation function to calculate the real-time frequency on the system side. The calculation method for the real-time frequency of the side to be connected corresponding to the rising edge of the voltage signal to be connected is the same as above; For the real-time frequency of the system side and the real-time frequency of the side to be connected, a differential amplitude limiting filter algorithm is used for frequency correction in sequence, and a moving average filter algorithm is used for averaging to generate the stable frequency of the system side and the stable frequency of the side to be connected.

[0008] Preferably, determining the validity of the system-side stable frequency and the stable frequency to be paralleled, and using the frequency following strategy to determine the effective following frequency, specifically includes: Preset the effective range of stable frequency on the system side and the effective range of stable frequency on the side to be connected; If the system-side stable frequency is within the effective range of the system-side stable frequency, and the stable frequency of the side to be connected is within the effective range of the stable frequency of the side to be connected, then it is determined that both the system-side stable frequency and the stable frequency of the side to be connected are valid, and the stable frequency with the smaller value between the system-side stable frequency and the stable frequency of the side to be connected is assigned as the effective following frequency. The system-side stable frequency is assigned the valid following frequency only when the system-side validity flag is valid; The stable frequency of the side to be paralleled is assigned the value of the effective following frequency only when the validity flag of the side to be paralleled is valid; If both the system-side stable frequency and the side-to-be-parallel stable frequency are invalid, then the preset default frequency is invoked and assigned the value of the valid following frequency.

[0009] Preferably, determining the balance between the system-side stable frequency and the stable frequency to be paralleled, and outputting the frequency balance result, specifically includes: The frequency balance result includes a frequency balance state and a frequency imbalance state, and calculates the stable frequency on the system side. With the stable frequency to be paralleled The corresponding absolute value of frequency difference ; A preset frequency balance threshold is set. If the absolute value of the frequency difference is less than or equal to the frequency balance threshold, it is determined that the stable frequency on the system side and the stable frequency on the side to be paralleled are maintained in the frequency balance state. If the absolute value of the frequency difference is greater than the frequency balance threshold, it is determined that the stable frequency on the system side and the stable frequency on the side to be paralleled remain in the frequency imbalance state.

[0010] Preferably, the step of dynamically selecting the signal sampling mode by calling the timer reconfiguration function based on the effective tracking frequency and the frequency balance result specifically includes: If the effective following frequency is inconsistent with the current sampling clock frequency, then the effective following frequency is input to the timer reconfiguration function; The preset sampling point number of the timer is read, which includes a first preset sampling point number and a second preset sampling point number. When the frequency balance result is the frequency balance state, the first sampling clock frequency is obtained by calculating the product of the effective following frequency and the first preset sampling point number through the timer reconfiguration function. When the frequency balance result is the frequency imbalance state, the second sampling clock frequency is obtained by calculating the product of the effective following frequency and the second preset number of sampling points through the timer reconfiguration function.

[0011] Preferably, the step of synchronously sampling the system-side voltage signal and the voltage signal to be paralleled according to the signal sampling mode, and performing a Fourier transform based on the frequency balance result to generate the system-side voltage amplitude and the voltage amplitude to be paralleled specifically includes: When the frequency balance result is a frequency balance state, the system-side voltage signal and the voltage signal to be paralleled are synchronously sampled based on the first sampling clock frequency to obtain a first system-side sampling sequence and a first parallel-side sampling sequence, which are then summarized to obtain a first sampling sequence. When the frequency balance result is a frequency imbalance state, the system-side voltage signal and the voltage signal to be paralleled are synchronously sampled based on the second sampling clock frequency to obtain a second system-side sampling sequence and a second parallel-side sampling sequence, and then summarized to obtain a second sampling sequence. The second sampled sequence is reconstructed using an interpolation reconstruction algorithm to obtain the interpolation mapping position S. The corresponding calculation formula is as follows: In the formula, i represents the sampling point number in the second sampling sequence; Indicates the effective tracking frequency; K represents the sampling density coefficient; Indicates the system-side stable frequency or the frequency to be stabilized on the side to be connected; Decompose the interpolation mapping position S into integer parts. Given the fractional part B=SA, the amplitude of the sampling points in the second sampling sequence is reconstructed using a linear interpolation formula to generate the reconstructed amplitude y. The corresponding calculation formula is as follows: In the formula, This represents the amplitude at the Ath sampling point; This represents the amplitude at the (A+1)th sampling point; M represents the interpolation scaling factor. This represents the floor function; The reconstructed amplitude y is stored in the reconstruction buffer according to the sampling point number to obtain the system-side equiphase sampling sequence and the equiphase sampling sequence to be connected, and the equiphase sampling sequence is generated by summarizing them. The Fourier analysis algorithm is used to perform Fourier transform on the first sampling sequence or the equiphase sampling sequence to generate the system-side voltage amplitude and the equiphase sampling sequence to be connected.

[0012] Preferably, while generating the system-side voltage amplitude and the voltage amplitude to be connected, a moving average filtering algorithm is used to perform average filtering on the first sampling sequence or the second sampling sequence to generate the system-side ADC average value. Average value of ADC to be combined The corresponding calculation formula is as follows: In the formula, This represents the amplitude of the j-th sampling point in the first system-side sampling sequence or the second system-side sampling sequence; This represents the amplitude of the u-th sampling point in either the first or second parallel sampling sequence.

[0013] Preferably, the step of using a first reference frequency and a second reference frequency to calibrate and correct the system-side voltage amplitude and the voltage amplitude to be paralleled using a linear interpolation algorithm to generate system-side standard voltage amplitude and paralleled-side standard voltage amplitude specifically includes: Obtain factory calibration data, which includes calibration voltage amplitude. First reference frequency Second reference frequency The system-side ADC calibration average value corresponding to the first reference frequency. The average calibration value of the ADC on the target side corresponding to the first reference frequency. The system-side ADC calibration average value corresponding to the second reference frequency. The average calibration value of the ADC on the side to be paralleled corresponding to the second reference frequency. ; Based on the first reference frequency and the second reference frequency, the system-side frequency coefficients are constructed using a normalized mapping function. Frequency coefficients to be paralleled The corresponding calculation formula is as follows: In the formula, Indicates the stable frequency on the system side; Indicates the stable frequency of the side to be paralleled; According to the system-side frequency coefficient The frequency coefficients of the side to be paralleled The theoretical average value of the system-side ADC is calculated using the linear interpolation algorithm. Theoretical average value of ADC to be combined The corresponding calculation formula is as follows: ; The system-side voltage amplitude and the voltage amplitude to be connected are corrected using a ratio calculation formula to generate the system-side standard voltage amplitude. Standard voltage amplitude to be paralleled .

[0014] Preferably, the first reference frequency The second reference frequency is 50Hz. It is 60Hz.

[0015] A frequency-following sampling and dual-frequency calibration system for a synchronous inspection device, the system comprising: The stable frequency calculation module is used to acquire the rising edge of the system-side voltage signal and the rising edge of the voltage signal to be connected in parallel and perform frequency calculation to generate the stable frequency of the system-side and the stable frequency of the side to be connected. The frequency following module is used to determine the effectiveness and balance between the stable frequency on the system side and the stable frequency on the side to be paralleled, and to determine the effective following frequency using a frequency following strategy and output the frequency balance result. The sampling mode selection module is used to dynamically select the signal sampling mode by calling the timer reconfiguration function based on the effective following frequency and the frequency balance result. According to the signal sampling mode, the system-side voltage signal and the voltage signal to be paralleled are synchronously sampled, and Fourier transform is performed according to the frequency balance result to generate the system-side voltage amplitude and the voltage amplitude to be paralleled. The voltage amplitude calibration module is used to calibrate and correct the system-side voltage amplitude and the voltage amplitude to be connected side using a linear interpolation algorithm based on a first reference frequency and a second reference frequency, thereby generating a system-side standard voltage amplitude and a voltage amplitude to be connected standard side.

[0016] Compared with the prior art, the frequency following sampling and dual-frequency calibration method and system for synchronous inspection devices provided by the present invention have the following advantages: This invention generates stable frequencies for the system and the target voltage by acquiring the rising edges of the system-side voltage signal and the voltage signal to be paralleled in parallel and performing frequency calculations. It then determines the validity and balance of these frequencies, employs a frequency-following strategy to determine the effective following frequency, and outputs the frequency balance result. Based on the effective following frequency and the frequency balance result, it dynamically selects the signal sampling mode by calling a timer reconfiguration function. According to the signal sampling mode, it synchronously samples the system-side and target voltage signals and performs Fourier transform based on the frequency balance result to generate the system-side and target voltage amplitudes. Using a first and a second reference frequency, it employs a linear interpolation algorithm to calibrate and correct the system-side and target voltage amplitudes, generating standard system-side and target voltage amplitudes, thereby eliminating spectral leakage and improving the measurement accuracy of the voltage amplitude.

[0017] This invention is applied to a synchronization inspection device for embedded microcontrollers. By constructing a collaborative processing mechanism of effective following frequency sampling and dual reference frequency calibration, this invention solves the problem of decreased measurement accuracy under grid frequency offset conditions in traditional fixed sampling methods, significantly improving the accuracy and stability of voltage amplitude measurement. This invention achieves synchronous following of the sampling clock frequency and the effective following frequency through dynamic timer reconfiguration. It performs synchronous sampling of the voltage signal under frequency balance conditions and constructs an equal-phase sampling sequence by combining oversampling and interpolation reconstruction strategies under frequency imbalance conditions, ensuring that the Fourier transform window always contains a complete integer number of voltage cycle cycles, thus solving the spectral leakage and picket fence effects problems caused by traditional fixed sampling modes. This invention introduces a dual-frequency factory calibration mechanism with a first and second reference frequency, combined with a linear interpolation algorithm to perform real-time calibration and correction of the system-side voltage amplitude and the voltage amplitude to be paralleled, eliminating measurement errors caused by hardware discreteness of different devices, solving the problem that traditional single-frequency calibration cannot cover different operating conditions, and improving the consistency of measurement results between different devices. Attached Figure Description

[0018] Figure 1 A flowchart of a frequency following sampling and dual-frequency calibration method for a synchronization inspection device provided in an embodiment of the present invention; Figure 2 This is a system block diagram of a frequency-following sampling and dual-frequency calibration system for a synchronous inspection device provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] like Figure 1 The diagram shown is a flowchart of a frequency following sampling and dual-frequency calibration method for a synchronization inspection device provided in an embodiment of the present invention. Figure 1 The execution entity of the method shown can be a software and / or hardware device. The execution entity of this application can include, but is not limited to, at least one of the following: user equipment, network equipment, etc. User equipment can include, but is not limited to, computers, smartphones, personal digital assistants (PDAs), and the aforementioned electronic devices. Network equipment can include, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud based on cloud computing consisting of a large number of computers or network servers. Cloud computing is a type of distributed computing, consisting of a super virtual computer composed of a group of loosely coupled computers. This embodiment does not limit this. Steps S1 to S5 are detailed as follows: S1, acquire the rising edge of the system-side voltage signal and the rising edge of the voltage signal to be connected in parallel and perform frequency calculation to generate the system-side stable frequency and the stable frequency of the side to be connected. The process of acquiring the rising edges of the system-side voltage signal and the voltage signal to be paralleled on both sides and performing frequency calculations to generate the system-side stable frequency and the stable frequency to be paralleled on both sides specifically includes: The rising edge of the system-side voltage signal is identified through the first input capture channel of the timer, and the time data of two consecutive rising edges of the system-side voltage signal is obtained. The rising edge of the voltage signal to be paralleled is identified through the second input capture channel of the timer, and the time data of two consecutive rising edges of the voltage signal to be paralleled is obtained. Calculate the time difference between the rising edges of two consecutive system-side voltage signals, construct a time difference sequence, and call the frequency calculation function to calculate the real-time frequency on the system side. The calculation method for the real-time frequency of the side to be connected corresponding to the rising edge of the voltage signal to be connected is the same as above; For the real-time frequency of the system side and the real-time frequency of the side to be connected, a differential amplitude limiting filter algorithm is used for frequency correction in sequence, and a moving average filter algorithm is used for averaging to generate the stable frequency of the system side and the stable frequency of the side to be connected.

[0021] The system-side voltage signal refers to the AC voltage signal from the grid side or bus side, used to characterize the current operating status of the power system. The voltage signal to be connected to the grid refers to the AC voltage signal from the side to be connected, used to determine whether the grid connection conditions are met. Both the system-side voltage signal and the voltage signal to be connected to the grid are periodic sinusoidal signals. The rising edge refers to the transition edge of the AC voltage signal when it crosses zero potential during the transition from low to high level. The system-side stable frequency and the voltage signal to be connected stable frequency refer to the frequency values ​​that can truly reflect the operating status of the grid on the system side and the grid on the side to be connected, respectively, without sudden interference and random fluctuations.

[0022] In power system synchronous grid connection detection scenarios, the grid frequency is affected by factors such as load changes, power generation fluctuations, and line faults, causing it to drift around the nominal value. Furthermore, there is a frequency difference between the real-time frequency on the system side and the real-time frequency on the side to be connected. If traditional fixed sampling frequencies are used to acquire voltage signals, it is difficult to guarantee that the number of sampling points per cycle is an integer, thus violating the integer-cycle sampling condition of the Fourier transform, leading to spectral leakage and the picket-fence effect, and reducing the measurement accuracy of the voltage amplitude. Therefore, it is necessary to accurately measure the real-time frequencies of the system-side voltage signal and the voltage signal on the side to be connected, and then eliminate interference through filtering to obtain the stable frequencies on the system side and the side to be connected. Based on the first and second input acquisition channels of an embedded microcontroller's timer, the rising edges of the system-side voltage signal and the voltage signal on the side to be connected are acquired in parallel. Through this dual-channel parallel acquisition mechanism, the periodic information of the two voltage signals can be acquired under the same time reference, avoiding the time deviation caused by serial acquisition.

[0023] The time data difference refers to the difference between two consecutive rising edges of the system-side voltage signal or two consecutive rising edges of the voltage signal to be paralleled, used to represent the time length of a complete voltage signal cycle. A time difference sequence is a data set composed of time data differences from multiple consecutive cycles, used to describe the dynamic trend of frequency change. The complete cycle of the voltage signal is obtained from the time data differences, and the real-time frequency of the system-side and the real-time frequency of the side to be paralleled are obtained by calculating the reciprocal of the time data differences.

[0024] Due to noise interference, harmonic distortion, and transient fluctuations in the actual power grid environment, the directly calculated real-time frequencies on the system side and the side to be connected exhibit jitter or anomalous abrupt changes, necessitating frequency correction. The differential amplitude limiting filter algorithm calculates the real-time frequency difference by performing a differential operation on two adjacent real-time frequencies on the system side or two adjacent real-time frequencies on the side to be connected, and limits this difference to a preset threshold range to suppress abrupt interference. This preset threshold is set according to the allowable real-time frequency fluctuation range of the power grid, for example, ±0.5Hz, and is used to filter out anomalous jumps in the real-time frequencies on the system side and the side to be connected. The moving average filter algorithm calculates a moving average of multiple real-time frequencies on the system side or multiple real-time frequencies on the side to be connected within a preset moving window, effectively reducing the impact of random noise. The real-time frequencies on the system side and the side to be connected are processed independently using differential amplitude limiting filtering and moving average processing to obtain stable frequencies on the system side and the side to be connected.

[0025] S2, determine the effectiveness and balance between the system-side stable frequency and the stable frequency to be paralleled, use a frequency following strategy to determine the effective following frequency and output the frequency balance result; Determining the validity of the system-side stable frequency and the target-side stable frequency, and using the frequency following strategy to determine the effective following frequency, specifically includes: Preset the effective range of stable frequency on the system side and the effective range of stable frequency on the side to be connected; If the system-side stable frequency is within the effective range of the system-side stable frequency, and the stable frequency of the side to be connected is within the effective range of the stable frequency of the side to be connected, then it is determined that both the system-side stable frequency and the stable frequency of the side to be connected are valid, and the stable frequency with the smaller value between the system-side stable frequency and the stable frequency of the side to be connected is assigned as the effective following frequency. The system-side stable frequency is assigned the valid following frequency only when the system-side validity flag is valid; The stable frequency of the side to be paralleled is assigned the value of the effective following frequency only when the validity flag of the side to be paralleled is valid; If both the system-side stable frequency and the side-to-be-parallel stable frequency are invalid, then the preset default frequency is invoked and assigned the value of the valid following frequency.

[0026] Among these, effectiveness is used to analyze whether the stable frequency on the system side and the stable frequency on the side to be connected are within a reasonable power grid operating range, and to determine whether the current stable frequency on the system side and the stable frequency on the side to be connected are reliable. Frequency balance result refers to the degree of deviation between the stable frequency on the system side and the stable frequency on the side to be connected, and is used to determine whether the two power grids are in a state of near synchronization. Effective following frequency refers to the target frequency used to drive the sampling clock frequency reconfiguration, which ensures that the sampling window covers the complete voltage signal cycle, while also taking into account the synchronization of the voltage signals on both sides.

[0027] Using an invalid following frequency to configure the sampling clock frequency will distort the Fourier transform results, leading to device malfunctions or failures to operate. If the absolute value of the frequency difference between the system-side stable frequency and the stable frequency to be paralleled is not distinguished and the same signal sampling mode is used, spectral leakage and the picket fence effect will occur when the absolute value of the frequency difference is large, causing the voltage amplitude measurement error to exceed the grid connection allowable range. Therefore, it is necessary to first verify the validity of the system-side stable frequency and the stable frequency to be paralleled, screen out reliable and valid following frequencies, then determine the sampling clock frequency through a following frequency strategy, and simultaneously determine the absolute value of the frequency difference to output the frequency balance result. Multi-branch logic is used to cover different operating conditions, ensuring stable system operation under abnormal circumstances.

[0028] Based on the normal operating frequency range and abnormal fluctuation frequency range of the power grid, effective intervals for the system-side stable frequency and the stable frequency range of the side to be connected are defined. The system-side stable frequency and the stable frequency of the side to be connected are compared with their respective effective intervals. When both the system-side stable frequency and the stable frequency of the side to be connected fall within their respective effective intervals, they are determined to be effective. In this case, to ensure that the sampling window covers the complete voltage signal cycle and to avoid the voltage signal cycle being truncated due to an excessively high sampling clock frequency, the stable frequency with the smaller value between the system-side stable frequency and the stable frequency of the side to be connected is selected as the effective following frequency, ensuring that the voltage signal meets the full cycle sampling condition.

[0029] When only the system-side stable frequency is valid, the system-side stable frequency is assigned as the valid following frequency; when only the waiting-to-be-parallel stable frequency is valid, the waiting-to-be-parallel stable frequency is assigned as the valid following frequency, ensuring that the system can still operate stably based on the other side's stable frequency when the stable frequency on one side is abnormal or lost.

[0030] When neither the system-side stable frequency nor the target-side stable frequency is within the corresponding valid range, it indicates that the signals on both sides are abnormal or the measurement has failed. In this case, the preset default frequency is called as the valid following frequency to ensure the basic operating status of the system.

[0031] Determine the balance between the system-side stable frequency and the stable frequency of the side to be paralleled, and output the frequency balance result, specifically including: The frequency balance result includes a frequency balance state and a frequency imbalance state, and calculates the stable frequency on the system side. With the stable frequency to be paralleled The corresponding absolute value of frequency difference ; A preset frequency balance threshold is set. If the absolute value of the frequency difference is less than or equal to the frequency balance threshold, it is determined that the stable frequency on the system side and the stable frequency on the side to be paralleled are maintained in the frequency balance state. If the absolute value of the frequency difference is greater than the frequency balance threshold, it is determined that the stable frequency on the system side and the stable frequency on the side to be paralleled remain in the frequency imbalance state.

[0032] Among them, the absolute value of frequency difference refers to the absolute value of the difference between the stable frequency on the system side and the stable frequency on the side to be paralleled, which is used to quantify the degree of deviation between the stable frequency on the system side and the stable frequency on the side to be paralleled.

[0033] A preset frequency balance threshold is used to distinguish between frequency balanced and frequency unbalanced states. When the absolute value of the frequency difference is less than or equal to the frequency balance threshold, the stable frequency on the system side and the stable frequency on the side to be paralleled are determined to be in a frequency balanced state, and the stable frequencies on both sides are basically the same. A unified sampling strategy can be used for whole-cycle sampling. When the absolute value of the frequency difference is greater than the frequency balance threshold, the stable frequency on the system side and the stable frequency on the side to be paralleled are determined to be in a frequency unbalanced state. At this time, there is a significant difference between the stable frequencies on both sides, and an oversampling and interpolation reconstruction strategy is required to ensure the effectiveness of the Fourier transform.

[0034] S3, based on the effective following frequency and the frequency balance result, call the timer reconfiguration function to dynamically select the signal sampling mode, synchronously sample the system-side voltage signal and the voltage signal to be paralleled according to the signal sampling mode, and perform Fourier transform according to the frequency balance result to generate the system-side voltage amplitude and the voltage amplitude to be paralleled. The step of dynamically selecting the signal sampling mode by calling the timer reconfiguration function based on the effective tracking frequency and the frequency balance result specifically includes: If the effective following frequency is inconsistent with the current sampling clock frequency, then the effective following frequency is input to the timer reconfiguration function; The preset sampling point number of the timer is read, which includes a first preset sampling point number and a second preset sampling point number. When the frequency balance result is the frequency balance state, the first sampling clock frequency is obtained by calculating the product of the effective following frequency and the first preset sampling point number through the timer reconfiguration function. When the frequency balance result is the frequency imbalance state, the second sampling clock frequency is obtained by calculating the product of the effective following frequency and the second preset number of sampling points through the timer reconfiguration function.

[0035] The signal sampling modes include synchronous integer-cycle sampling mode and oversampling interpolation reconstruction mode. Synchronous integer-cycle sampling mode samples the voltage signal using a first sampling clock frequency, while oversampling interpolation reconstruction mode samples the voltage signal using a second sampling clock frequency. The first sampling clock frequency refers to the sampling clock frequency under frequency balance conditions, which is equal to 18 times the effective following frequency, ensuring 18 equal-phase sampling points are collected per cycle. The second sampling clock frequency refers to the sampling clock frequency under frequency imbalance conditions, which is equal to 36 times the effective following frequency, ensuring 36 sampling points are collected per cycle. The first preset number of sampling points is 18, and the second preset number of sampling points is 36.

[0036] The signal sampling mode is determined based on the frequency balance results, and the corresponding sampling clock frequency is calculated. When the system-side stable frequency and the target-side stable frequency are in a frequency balance state, the product of the first preset number of sampling points and the effective following frequency is used as the first sampling clock frequency to ensure uniform acquisition of a fixed number of points within a complete cycle. When the system-side stable frequency and the target-side stable frequency are in a frequency imbalance state, the product of the second preset number of sampling points and the effective following frequency is used as the second sampling clock frequency to increase the sampling density.

[0037] The step of synchronously sampling the system-side voltage signal and the voltage signal to be paralleled according to the signal sampling mode, and performing a Fourier transform based on the frequency balance result to generate the system-side voltage amplitude and the voltage amplitude to be paralleled specifically includes: When the frequency balance result is a frequency balance state, the system-side voltage signal and the voltage signal to be paralleled are synchronously sampled based on the first sampling clock frequency to obtain a first system-side sampling sequence and a first parallel-side sampling sequence, which are then summarized to obtain a first sampling sequence. When the frequency balance result is a frequency imbalance state, the system-side voltage signal and the voltage signal to be paralleled are synchronously sampled based on the second sampling clock frequency to obtain a second system-side sampling sequence and a second parallel-side sampling sequence, and then summarized to obtain a second sampling sequence. The second sampled sequence is reconstructed using an interpolation reconstruction algorithm to obtain the interpolation mapping position S. The corresponding calculation formula is as follows: In the formula, i represents the sampling point number in the second sampling sequence; Indicates the effective tracking frequency; K represents the sampling density coefficient; Indicates the system-side stable frequency or the frequency to be stabilized on the side to be connected; Decompose the interpolation mapping position S into integer parts. Given the fractional part B=SA, the amplitude of the sampling points in the second sampling sequence is reconstructed using a linear interpolation formula to generate the reconstructed amplitude y. The corresponding calculation formula is as follows: In the formula, This represents the amplitude at the Ath sampling point; This represents the amplitude at the (A+1)th sampling point; M represents the interpolation scaling factor. This represents the floor function; The reconstructed amplitude y is stored in the reconstruction buffer according to the sampling point number to obtain the system-side equiphase sampling sequence and the equiphase sampling sequence to be connected, and the equiphase sampling sequence is generated by summarizing them. The Fourier analysis algorithm is used to perform Fourier transform on the first sampling sequence or the equiphase sampling sequence to generate the system-side voltage amplitude and the equiphase sampling sequence to be connected.

[0038] The first sampling sequence refers to a data set of 18 sampling points per cycle obtained by synchronously sampling the system-side voltage signal and the voltage signal to be paralleled based on the first sampling clock frequency. The sampling points in the first sampling sequence are evenly distributed on the time axis and correspond to complete integer signal cycles. The second sampling sequence refers to a data set of 36 sampling points per cycle obtained by oversampling the system-side voltage signal and the voltage signal to be paralleled based on the second sampling clock frequency. The sampling density in the second sampling sequence is higher, but the phase is not completely aligned with the actual voltage signal. It needs to be converted into an equal-phase sampling sequence after interpolation and reconstruction to meet the integer-cycle analysis conditions of Fourier transform.

[0039] The phase of the sampling points in the second sampling sequence exhibits a nonlinear shift. Directly performing a Fourier transform would lead to spectral energy leakage, affecting the accuracy of voltage amplitude calculation. By leveraging the proportional relationship between the effective following frequency and the system-side stable frequency or the synchronizing frequency of the target side, the positions of the sampling points in the second system-side sampling sequence and the second target-side sampling sequence are recalibrated on the time axis. The interpolation mapping position is calculated, reflecting the relative position of the equal-phase sampling points in the second sampling sequence, ensuring that the reconstructed equal-phase sampling points are distributed at fixed phase intervals within a complete cycle. The sampling density coefficient K is used to adjust the distribution density of the equal-phase sampling points during the interpolation process.

[0040] Furthermore, the interpolation mapping position is decomposed into an integer part A and a fractional part B. The integer part A represents the index position of the isophase sampling point in the second sampling sequence, used to locate the isophase sampling point between the A-th and A+1-th sampling points in the second sampling sequence. The fractional part B represents the relative offset ratio of the isophase sampling point relative to the A-th sampling point, used to characterize the specific position of the isophase sampling point between the A-th and A+1-th sampling points. The interpolation scaling factor M is a weighting coefficient used to measure the positional relationship between two adjacent sampling points of the isophase sampling point in the second sampling sequence. According to the linear interpolation formula, with the amplitude of the A-th sampling point as the benchmark, the amplitude difference between the A-th and A+1-th sampling points is linearly weighted according to the scaling factor M to generate the reconstructed amplitude of the isophase sampling point. The above linear interpolation calculation is performed on the second system-side sampling sequence and the second sampling sequence to be merged, respectively, and the reconstructed amplitude is calculated sequentially according to the sampling point number.

[0041] The reconstructed amplitudes are sequentially written into the reconstruction buffer according to the sampling point sequence number. The reconstruction buffer is a pre-allocated contiguous storage area within the embedded microcontroller's internal RAM, used to store the reconstructed amplitudes corresponding to equal-phase sampling points in sequence, generating an equal-phase sampling sequence with the same format as the first sampling sequence. The equal-phase sampling points in this sequence are uniformly distributed at fixed phase intervals within a complete cycle, containing 18 equal-phase sampling points per cycle. A Fourier analysis algorithm is used to perform a frequency domain transformation on the first sampling sequence or the equal-phase sampling sequence, extracting the real and imaginary parts of the fundamental component and performing modulo operations to calculate the system-side voltage amplitude and the voltage amplitude to be paralleled.

[0042] While generating the system-side voltage amplitude and the voltage amplitude to be connected, a moving average filtering algorithm is used to perform average filtering on the first sampling sequence or the second sampling sequence to generate the system-side ADC average value. Average value of ADC to be combined The corresponding calculation formula is as follows: In the formula, This represents the amplitude of the j-th sampling point in the first system-side sampling sequence or the second system-side sampling sequence; This represents the amplitude of the u-th sampling point in either the first or second parallel sampling sequence.

[0043] The system-side ADC average value refers to the arithmetic mean of the amplitudes of all sampling points within a complete sampling period of the system-side voltage signal, reflecting the overall voltage amplitude level of the system-side voltage signal. Similarly, the parallel-side ADC average value refers to the arithmetic mean of the amplitudes of all sampling points within a complete sampling period of the parallel-side voltage signal, reflecting the overall voltage amplitude level of the parallel-side voltage signal.

[0044] S4. Using the first reference frequency and the second reference frequency, a linear interpolation algorithm is used to calibrate and correct the voltage amplitude of the system side and the voltage amplitude of the side to be connected, generating the standard voltage amplitude of the system side and the standard voltage amplitude of the side to be connected.

[0045] The step of using a first reference frequency and a second reference frequency, and employing a linear interpolation algorithm to calibrate and correct the system-side voltage amplitude and the voltage amplitude to be paralleled, to generate system-side standard voltage amplitude and the voltage amplitude to be paralleled standard voltage amplitude, specifically includes: Obtain factory calibration data, which includes calibration voltage amplitude. First reference frequency Second reference frequency The system-side ADC calibration average value corresponding to the first reference frequency. The average calibration value of the ADC on the target side corresponding to the first reference frequency. The system-side ADC calibration average value corresponding to the second reference frequency. The average calibration value of the ADC on the side to be paralleled corresponding to the second reference frequency. ; Based on the first reference frequency and the second reference frequency, the system-side frequency coefficients are constructed using a normalized mapping function. Frequency coefficients to be paralleled The corresponding calculation formula is as follows: In the formula, Indicates the stable frequency on the system side; Indicates the stable frequency of the side to be paralleled; According to the system-side frequency coefficient The frequency coefficients of the side to be paralleled The theoretical average value of the system-side ADC is calculated using the linear interpolation algorithm. Theoretical average value of ADC to be combined The corresponding calculation formula is as follows: ; The system-side voltage amplitude and the voltage amplitude to be connected are corrected using a ratio calculation formula to generate the system-side standard voltage amplitude. Standard voltage amplitude to be paralleled .

[0046] The theoretical average value of the system-side ADC refers to the theoretically measurable average value of the system-side ADC when the calibration voltage amplitude is input at the current first or second reference frequency. The theoretical average value of the ADC to be paralleled refers to the theoretically measurable average value of the ADC to be paralleled when the calibration voltage amplitude is input at the current first or second reference frequency.

[0047] Specifically, the current system-side stable frequency and the tandem-side stable frequency are mapped to the [0,1] interval by a normalized mapping function, generating system-side frequency coefficients and tandem-side frequency coefficients, which respectively represent the relative positions of the system-side stable frequency and the tandem-side stable frequency between the first reference frequency and the second reference frequency, thereby uniformly calibrating the cross-frequency conditions.

[0048] Furthermore, using a linear interpolation algorithm with the first and second reference frequencies as endpoints, the system-side ADC calibration average value and the parallel-side ADC calibration average value are used. Linear weighting is then applied based on the system-side frequency coefficient corresponding to the system-side stable frequency and the parallel-side frequency coefficient corresponding to the parallel-side stable frequency, thereby obtaining the theoretical average value of the system-side ADC at the current system-side stable frequency and the theoretical average value of the parallel-side ADC at the current parallel-side stable frequency. By using the ratio of the theoretical average value of the system-side ADC to the actual average value of the system-side ADC, and the ratio of the theoretical average value of the ADC to be paralleled to the actual average value of the ADC to be paralleled, the voltage amplitude of the system-side ADC and the voltage amplitude of the ADC to be paralleled are reversed through the ratio calculation formula, thereby eliminating the gain error caused by different hardware.

[0049] The first reference frequency The second reference frequency is 50Hz. It is 60Hz.

[0050] Understandably, the dual-frequency factory calibration mechanism eliminates measurement errors caused by the hardware discreteness of different devices, and effectively compensates for the deviation of voltage amplitude calculation caused by frequency drift, thus greatly improving the reliability and versatility of the device.

[0051] like Figure 2 The diagram shown is a system block diagram of a frequency following sampling and dual-frequency calibration system for a synchronous inspection device provided in an embodiment of the present invention. The system includes: The stable frequency calculation module is used to acquire the rising edge of the system-side voltage signal and the rising edge of the voltage signal to be connected in parallel and perform frequency calculation to generate the stable frequency of the system-side and the stable frequency of the side to be connected. The frequency following module is used to determine the effectiveness and balance between the stable frequency on the system side and the stable frequency on the side to be paralleled, and to determine the effective following frequency using a frequency following strategy and output the frequency balance result. The sampling mode selection module is used to dynamically select the signal sampling mode by calling the timer reconfiguration function based on the effective following frequency and the frequency balance result. According to the signal sampling mode, the system-side voltage signal and the voltage signal to be paralleled are synchronously sampled, and Fourier transform is performed according to the frequency balance result to generate the system-side voltage amplitude and the voltage amplitude to be paralleled. The voltage amplitude calibration module is used to calibrate and correct the system-side voltage amplitude and the voltage amplitude to be connected side using a linear interpolation algorithm based on a first reference frequency and a second reference frequency, thereby generating a system-side standard voltage amplitude and a voltage amplitude to be connected standard side.

[0052] Figure 2 The system of the illustrated embodiment can be used to perform corresponding operations. Figure 1 The steps in the method embodiments shown are implemented in a similar manner and have similar technical effects, and will not be repeated here.

[0053] An electronic device includes a memory and a processor, wherein the memory stores a computer program, and when the processor runs the computer program stored in the memory, the processor performs the steps of the frequency following sampling and dual-frequency calibration method for a synchronization inspection device as described in any of the preceding claims.

[0054] like Figure 3 The diagram shown is a hardware structure schematic of an electronic device according to an embodiment of the present invention. The electronic device 30 includes: a processor 31, a memory 32, and a computer program; wherein... The memory 32 is used to store the computer program, and the memory may also be flash memory. The computer program is, for example, an application program or functional module that implements the above method.

[0055] Processor 31 is configured to execute the computer program stored in the memory to implement the various steps performed by the device in the above method. For details, please refer to the relevant descriptions in the preceding method embodiments.

[0056] Alternatively, the memory 32 can be either standalone or integrated with the processor 31.

[0057] When the memory 32 is a device independent of the processor 31, the device may further include: Bus 33 is used to connect the memory 32 and the processor 31.

[0058] A readable storage medium storing a computer program, which, when executed by a processor, is used to implement the steps of the frequency following sampling and dual-frequency calibration method for a synchronization check device as described in any of the above claims.

[0059] The readable storage medium can be a computer storage medium or a communication medium. A communication medium includes any medium that facilitates the transfer of computer programs from one location to another. A computer storage medium can be any available medium accessible to a general-purpose or special-purpose computer. For example, a readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application-Specific Integrated Circuit (ASIC). Alternatively, the ASIC can be located in a user equipment. Of course, the processor and the readable storage medium can also exist as discrete components in a communication device. The readable storage medium can be a read-only memory (ROM), random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0060] The present invention also provides a program product including executable instructions stored in a readable storage medium. At least one processor of the device can read the executable instructions from the readable storage medium, and the at least one processor executes the executable instructions to cause the device to implement the methods provided in the various embodiments described above.

[0061] In the embodiments of the above-described device, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor.

[0062] Through the above embodiments, this invention generates stable frequencies on the system side and the side to be paralleled by acquiring the rising edges of the system-side voltage signal and the voltage signal to be paralleled in parallel and performing frequency calculations; it judges the effectiveness and balance of the stable frequencies on the system side and the side to be paralleled, and uses a frequency following strategy to determine the effective following frequency and outputs the frequency balance result; based on the effective following frequency and the frequency balance result, it calls the timer reconfiguration function to dynamically select the signal sampling mode, and synchronously samples the system-side voltage signal and the voltage signal to be paralleled according to the signal sampling mode, and performs Fourier transform according to the frequency balance result to generate the voltage amplitude on the system side and the voltage amplitude on the side to be paralleled; using the first reference frequency and the second reference frequency, it uses a linear interpolation algorithm to calibrate and correct the voltage amplitude on the system side and the voltage amplitude on the side to be paralleled, generating the standard voltage amplitude on the system side and the standard voltage amplitude on the side to be paralleled, thereby eliminating spectral leakage and improving the measurement accuracy of the voltage amplitude.

[0063] This invention is applied to a synchronization inspection device for embedded microcontrollers. By constructing a collaborative processing mechanism of effective following frequency sampling and dual reference frequency calibration, this invention solves the problem of decreased measurement accuracy under grid frequency offset conditions in traditional fixed sampling methods, significantly improving the accuracy and stability of voltage amplitude measurement. This invention achieves synchronous following of the sampling clock frequency and the effective following frequency through dynamic timer reconfiguration. It performs synchronous sampling of the voltage signal under frequency balance conditions and constructs an equal-phase sampling sequence by combining oversampling and interpolation reconstruction strategies under frequency imbalance conditions, ensuring that the Fourier transform window always contains a complete integer number of voltage cycle cycles, thus solving the spectral leakage and picket fence effects problems caused by traditional fixed sampling modes. This invention introduces a dual-frequency factory calibration mechanism with a first and second reference frequency, combined with a linear interpolation algorithm to perform real-time calibration and correction of the system-side voltage amplitude and the voltage amplitude to be paralleled, eliminating measurement errors caused by hardware discreteness of different devices, solving the problem that traditional single-frequency calibration cannot cover different operating conditions, and improving the consistency of measurement results between different devices.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A frequency following sampling and dual frequency calibration method for a synchronous inspection device, characterized in that, The method includes: The rising edges of the system-side voltage signal and the voltage signal to be connected are acquired in parallel and the frequencies are calculated to generate the system-side stable frequency and the stable frequency of the to be connected side. The effectiveness and balance between the system-side stable frequency and the stable frequency to be paralleled are determined, and a frequency following strategy is adopted to determine the effective following frequency and output the frequency balance result. Based on the effective following frequency and the frequency balance result, the timer reconfiguration function is called to dynamically select the signal sampling mode. The system-side voltage signal and the voltage signal to be paralleled are synchronously sampled according to the signal sampling mode, and Fourier transform is performed according to the frequency balance result to generate the system-side voltage amplitude and the voltage amplitude to be paralleled. Using the first reference frequency and the second reference frequency, a linear interpolation algorithm is used to calibrate and correct the voltage amplitude of the system side and the voltage amplitude of the side to be connected, thereby generating the standard voltage amplitude of the system side and the standard voltage amplitude of the side to be connected.

2. The frequency following sampling and dual frequency calibration method for a synchronous inspection device according to claim 1, wherein, The process of acquiring the rising edges of the system-side voltage signal and the voltage signal to be paralleled on both sides and performing frequency calculations to generate the system-side stable frequency and the stable frequency to be paralleled on both sides specifically includes: The rising edge of the system-side voltage signal is identified through the first input capture channel of the timer, and the time data of two consecutive rising edges of the system-side voltage signal is obtained. The rising edge of the voltage signal to be paralleled is identified through the second input capture channel of the timer, and the time data of two consecutive rising edges of the voltage signal to be paralleled is obtained. Calculate the time difference between the rising edges of two consecutive system-side voltage signals, construct a time difference sequence, and call the frequency calculation function to calculate the real-time frequency on the system side. The calculation method for the real-time frequency of the side to be connected corresponding to the rising edge of the voltage signal to be connected is the same as above; For the real-time frequency of the system side and the real-time frequency of the side to be connected, a differential amplitude limiting filter algorithm is used for frequency correction in sequence, and a moving average filter algorithm is used for averaging to generate the stable frequency of the system side and the stable frequency of the side to be connected.

3. The frequency following sampling and dual frequency calibration method for a synchronous inspection device of claim 1, wherein, Determining the validity of the system-side stable frequency and the target-side stable frequency, and using the frequency following strategy to determine the effective following frequency, specifically includes: Preset the effective range of stable frequency on the system side and the effective range of stable frequency on the side to be connected; If the system-side stable frequency is within the effective range of the system-side stable frequency, and the stable frequency of the side to be connected is within the effective range of the stable frequency of the side to be connected, then it is determined that both the system-side stable frequency and the stable frequency of the side to be connected are valid, and the stable frequency with the smaller value between the system-side stable frequency and the stable frequency of the side to be connected is assigned as the effective following frequency. The system-side stable frequency is assigned the valid following frequency only when the system-side validity flag is valid; The stable frequency of the side to be paralleled is assigned the value of the effective following frequency only when the validity flag of the side to be paralleled is valid; If both the system-side stable frequency and the side-to-be-parallel stable frequency are invalid, then the preset default frequency is invoked and assigned the value of the valid following frequency.

4. The frequency following sampling and dual-frequency calibration method for a synchronous inspection device according to claim 1, characterized in that, Determine the balance between the system-side stable frequency and the stable frequency of the side to be paralleled, and output the frequency balance result, specifically including: The frequency balance result includes a frequency balance state and a frequency imbalance state, and calculates the stable frequency on the system side. With the frequency to be stabilized The corresponding absolute value of frequency difference ; A preset frequency balance threshold is set. If the absolute value of the frequency difference is less than or equal to the frequency balance threshold, it is determined that the stable frequency on the system side and the stable frequency on the side to be paralleled are maintained in the frequency balance state. If the absolute value of the frequency difference is greater than the frequency balance threshold, it is determined that the stable frequency on the system side and the stable frequency on the side to be paralleled remain in the frequency imbalance state.

5. The frequency following sampling and dual-frequency calibration method for a synchronous inspection device according to claim 4, characterized in that, The step of dynamically selecting the signal sampling mode by calling the timer reconfiguration function based on the effective tracking frequency and the frequency balance result specifically includes: If the effective following frequency is inconsistent with the current sampling clock frequency, then the effective following frequency is input to the timer reconfiguration function; The preset sampling point number of the timer is read, which includes a first preset sampling point number and a second preset sampling point number. When the frequency balance result is the frequency balance state, the first sampling clock frequency is obtained by calculating the product of the effective following frequency and the first preset sampling point number through the timer reconfiguration function. When the frequency balance result is the frequency imbalance state, the second sampling clock frequency is obtained by calculating the product of the effective following frequency and the second preset number of sampling points through the timer reconfiguration function.

6. The frequency following sampling and dual-frequency calibration method for a synchronous inspection device according to claim 1, characterized in that, The step of synchronously sampling the system-side voltage signal and the voltage signal to be paralleled according to the signal sampling mode, and performing a Fourier transform based on the frequency balance result to generate the system-side voltage amplitude and the voltage amplitude to be paralleled specifically includes: When the frequency balance result is a frequency balance state, the system-side voltage signal and the voltage signal to be paralleled are synchronously sampled based on the first sampling clock frequency to obtain a first system-side sampling sequence and a first parallel-side sampling sequence, which are then summarized to obtain a first sampling sequence. When the frequency balance result is a frequency imbalance state, the system-side voltage signal and the voltage signal to be paralleled are synchronously sampled based on the second sampling clock frequency to obtain a second system-side sampling sequence and a second parallel-side sampling sequence, and then summarized to obtain a second sampling sequence. The second sampled sequence is reconstructed using an interpolation reconstruction algorithm to obtain the interpolation mapping position S. The corresponding calculation formula is as follows: In the formula, i represents the sampling point number in the second sampling sequence; Indicates the effective tracking frequency; K represents the sampling density coefficient; Indicates the system-side stable frequency or the frequency to be stabilized on the side to be connected; Decompose the interpolation mapping position S into integer parts. Given the fractional part B=SA, the amplitude of the sampling points in the second sampling sequence is reconstructed using a linear interpolation formula to generate the reconstructed amplitude y. The corresponding calculation formula is as follows: In the formula, This represents the amplitude at the Ath sampling point; This represents the amplitude at the (A+1)th sampling point; M represents the interpolation scaling factor. This represents the floor function; The reconstructed amplitude y is stored in the reconstruction buffer according to the sampling point number to obtain the system-side equiphase sampling sequence and the equiphase sampling sequence to be connected, and the equiphase sampling sequence is generated by summarizing them. The Fourier analysis algorithm is used to perform Fourier transform on the first sampling sequence or the equiphase sampling sequence to generate the system-side voltage amplitude and the equiphase sampling sequence to be connected.

7. The frequency following sampling and dual-frequency calibration method for a synchronous inspection device according to claim 6, characterized in that, While generating the system-side voltage amplitude and the voltage amplitude to be connected, a moving average filtering algorithm is used to perform average filtering on the first sampling sequence or the second sampling sequence to generate the system-side ADC average value. Average value of ADC to be combined The corresponding calculation formula is as follows: In the formula, This represents the amplitude of the j-th sampling point in the first system-side sampling sequence or the second system-side sampling sequence; This represents the amplitude of the u-th sampling point in either the first or second parallel sampling sequence.

8. The frequency following sampling and dual-frequency calibration method for a synchronous inspection device according to claim 1, characterized in that, The step of using a first reference frequency and a second reference frequency, and employing a linear interpolation algorithm to calibrate and correct the system-side voltage amplitude and the voltage amplitude to be paralleled, to generate system-side standard voltage amplitude and the voltage amplitude to be paralleled standard voltage amplitude, specifically includes: Obtain factory calibration data, which includes calibration voltage amplitude. First reference frequency Second reference frequency The system-side ADC calibration average value corresponding to the first reference frequency. The average calibration value of the ADC on the target side corresponding to the first reference frequency. The system-side ADC calibration average value corresponding to the second reference frequency. The average calibration value of the ADC on the parallel side corresponding to the second reference frequency. ; Based on the first reference frequency and the second reference frequency, the system-side frequency coefficients are constructed using a normalized mapping function. Frequency coefficients to be paralleled The corresponding calculation formula is as follows: In the formula, Indicates the stable frequency on the system side; Indicates the stable frequency of the side to be paralleled; According to the system-side frequency coefficient The frequency coefficients of the side to be paralleled The theoretical average value of the system-side ADC is calculated using the linear interpolation algorithm. Theoretical average value of ADC to be combined The corresponding calculation formula is as follows: ； The system-side voltage amplitude and the voltage amplitude to be connected are corrected using a ratio calculation formula to generate the system-side standard voltage amplitude. Standard voltage amplitude to be paralleled .

9. The frequency following sampling and dual-frequency calibration method for a synchronous inspection device according to claim 1, characterized in that, The first reference frequency The second reference frequency is 50Hz. It is 60Hz.

10. A frequency following sampling and dual-frequency calibration system for a synchronization inspection device, applied to the frequency following sampling and dual-frequency calibration method for a synchronization inspection device as described in any one of claims 1-9, characterized in that, The system includes: The stable frequency calculation module is used to acquire the rising edge of the system-side voltage signal and the rising edge of the voltage signal to be connected in parallel and perform frequency calculation to generate the stable frequency of the system-side and the stable frequency of the side to be connected. The frequency following module is used to determine the effectiveness and balance between the stable frequency on the system side and the stable frequency on the side to be paralleled, and to determine the effective following frequency using a frequency following strategy and output the frequency balance result. The sampling mode selection module is used to dynamically select the signal sampling mode by calling the timer reconfiguration function based on the effective following frequency and the frequency balance result. According to the signal sampling mode, the system-side voltage signal and the voltage signal to be paralleled are synchronously sampled, and Fourier transform is performed according to the frequency balance result to generate the system-side voltage amplitude and the voltage amplitude to be paralleled. The voltage amplitude calibration module is used to calibrate and correct the system-side voltage amplitude and the voltage amplitude to be connected side using a linear interpolation algorithm based on a first reference frequency and a second reference frequency, thereby generating a system-side standard voltage amplitude and a voltage amplitude to be connected standard side.

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