Circuit and method for enhancing charge / discharge noise characteristics and vehicle system including same

Abstract

The present invention relates to a circuit for enhancing charge / discharge noise characteristics. The circuit for enhancing charge / discharge noise characteristics comprises: a register that detects an abnormal signal and outputs a first MCU reset signal and a register signal; a first delay circuit that delays the first MCU reset signal output from the register to output a second MCU reset signal; an AND gate that receives the second MCU reset signal and the register signal and outputs a third MCU reset signal; a second delay circuit that delays the third MCU reset signal output from the AND gate to output a fourth MCU reset signal; and an MCU that performs a reset operation on the basis of the first MCU reset signal or the fourth MCU reset signal.

Description

Charge / discharge noise characteristic enhancement circuit, method, and vehicle system including the same

[0001] The present invention relates to a circuit for enhancing charge / discharge noise characteristics, a method, and a vehicle system including the same. Specifically, it relates to a circuit, a method, and a vehicle system including the same for enhancing noise generated during the charging and discharging of a battery.

[0002]

[0003] A battery management system (BMS) refers to a system for monitoring, managing, and / or controlling the status of a battery. For example, a battery management system may include multiple microcontroller units (MCUs). Meanwhile, when the battery management system detects an abnormal signal, it transmits a reset command to the corresponding MCU to cut off the system's power. However, abnormal signals can be incorrectly detected due to noise generated during battery charging and discharging, leading to a problem where the MCU is unintentionally reset.

[0004]

[0005] The present invention provides a circuit for enhancing charge / discharge noise characteristics, a method, a computer program stored on a computer-readable medium, a computer-readable medium storing the computer program, and a system (device) for solving the above-mentioned problems.

[0006]

[0007] The present invention may be implemented in various ways, including a circuit for enhancing charge / discharge noise characteristics, a method, a system (device), a computer program stored on a computer-readable medium, or a computer-readable medium on which a computer program is stored.

[0008] According to one embodiment of the present invention, a charge / discharge noise characteristic enhancement circuit includes: a register that detects an abnormal signal and outputs a first MCU reset signal and a register signal; a first delay circuit that delays the first MCU reset signal output from the register and outputs a second MCU reset signal; an AND gate that receives the second MCU reset signal and the register signal and outputs a third MCU reset signal; a second delay circuit that delays the third MCU reset signal output from the AND gate and outputs a fourth MCU reset signal; and an MCU that performs a reset operation based on the first MCU reset signal or the fourth MCU reset signal.

[0009] According to one embodiment of the present invention, a comparator is further included to determine whether the battery is in normal operation and whether it is in charge / discharge operation based on a current value received from a current sensor.

[0010] According to one embodiment of the present invention, a comparator determines whether the battery is in normal operation and whether it is in charge / discharge operation based on whether the current value received from the current sensor is higher than a threshold value.

[0011] According to one embodiment of the present invention, a first switch connecting a register and an MCU is further included. When a current value received from a current sensor is determined to be lower than a threshold, the first switch is controlled to turn ON by a first comparison signal output by a comparator.

[0012] According to one embodiment of the present invention, a second switch connecting a register and a first delay circuit is further included. When a current value received from a current sensor is determined to be higher than a threshold, the second switch is controlled to turn ON by a second comparison signal output by a comparator.

[0013] According to one embodiment of the present invention, it further includes a buffer that receives a register signal and transmits it to a first delay circuit.

[0014] According to one embodiment of the present invention, the first delay circuit outputs a second MCU reset signal when the first MCU reset signal is maintained as a HIGH signal during the first delay time.

[0015] According to one embodiment of the present invention, the AND gate outputs a third MCU reset signal when both the second MCU reset signal and the register signal are HIGH signals.

[0016] According to one embodiment of the present invention, the second delay circuit outputs a fourth MCU reset signal when the third MCU reset signal is maintained as a HIGH signal during the second delay time.

[0017] According to one embodiment of the present invention, a vehicle system comprises a battery pack, a charger / discharger for charging and discharging the battery pack, a current sensor connected between the battery pack and the charger / discharger to provide a current value flowing from the battery pack to a battery management system, and a battery management system including a charger / discharge noise characteristic enhancement circuit for detecting an abnormal signal and resetting an MCU.

[0018] According to one embodiment of the present invention, a charge / discharge noise characteristic enhancement circuit includes: a register that detects an abnormal signal and outputs a first MCU reset signal and a register signal; a first delay circuit that delays the first MCU reset signal output from the register and outputs a second MCU reset signal; an AND gate that receives the second MCU reset signal and the register signal and outputs a third MCU reset signal; a second delay circuit that delays the third MCU reset signal output from the AND gate and outputs a fourth MCU reset signal; and an MCU that performs a reset operation based on the first MCU reset signal or the fourth MCU reset signal.

[0019] According to one embodiment of the present invention, a battery charge / discharge noise enhancement method performed by at least one processor comprises: generating a first MCU reset signal and a register signal using a register; generating a second MCU reset signal by delaying the first MCU reset signal using a first delay circuit; generating a third MCU reset signal by providing the second MCU reset signal and the register signal to an AND gate; generating a fourth MCU reset signal by delaying the third MCU reset signal using a second delay circuit; and performing a reset operation of the MCU based on the fourth MCU reset signal.

[0020] According to one embodiment of the present invention, the method further includes the step of determining whether the battery is in normal operation and whether it is in charge / discharge operation based on a current value received from a current sensor using a comparator.

[0021] According to one embodiment of the present invention, the step of generating a second MCU reset signal by delaying a first MCU reset signal using a first delay circuit includes the step of determining whether the first MCU reset signal is maintained as a HIGH signal during a first delay time, and the step of generating a second MCU reset signal when it is determined that the first MCU reset signal is maintained as a HIGH signal during the first delay time.

[0022] According to one embodiment of the present invention, the step of generating a fourth MCU reset signal by delaying a third MCU reset signal using a second delay circuit includes the step of determining whether the third MCU reset signal is maintained as a HIGH signal during a second delay time, and the step of generating a fourth MCU reset signal when it is determined that the third MCU reset signal is maintained as a HIGH signal during the second delay time.

[0023] According to one embodiment of the present invention, the step of generating a fourth MCU reset signal by delaying a third MCU reset signal using a second delay circuit further includes the step of determining whether abnormal operation of the MCU is detected during the second delay time. If it is determined that the third MCU reset signal remains a HIGH signal during the second delay time, the step of generating a fourth MCU reset signal includes the step of generating a fourth MCU reset signal if the third MCU reset signal remains a HIGH signal during the second delay time and abnormal operation of the MCU is detected.

[0024] According to one embodiment of the present invention, the step of determining whether an abnormal operation of the MCU is detected during a second delay time includes: determining whether a reset register signal output from a reset register is a HIGH signal; determining whether a register signal is a HIGH signal when the reset register signal is a HIGH signal; determining whether a power-off command is output when the register signal is a HIGH signal; and determining that an abnormal operation of the MCU is detected when it is determined that a power-off command is output.

[0025]

[0026] In various embodiments of the present invention, a vehicle and / or vehicle system can perform MCU reset control by precisely distinguishing between noise and actual abnormal signals generated during the charging and discharging of a battery pack.

[0027] In various embodiments of the present invention, the battery management system enhances the noise characteristics generated during the charging and discharging of a battery and / or battery pack based on a charge / discharge noise characteristic enhancement circuit, and based on this, can effectively prevent the MCU from being incorrectly reset due to charge / discharge noise.

[0028] The effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by a person skilled in the art to which the present invention pertains (referred to as "person skilled in the art") from the description in the claims.

[0029]

[0030] Embodiments of the present invention will be described with reference to the accompanying drawings described below, wherein similar reference numerals indicate similar elements, but are not limited thereto.

[0031] FIG. 1 is a drawing showing an example of a vehicle including a charge / discharge noise characteristic enhancement circuit according to one embodiment of the present disclosure.

[0032] FIG. 2 is an exemplary drawing illustrating the operation of a charge / discharge noise characteristic enhancement circuit during general operation according to one embodiment of the present disclosure.

[0033] FIG. 3 is an exemplary diagram showing the operation of a charging / discharging noise characteristic enhancement circuit during a charging / discharging operation of a battery according to one embodiment of the present disclosure.

[0034] FIG. 4 is a flowchart illustrating an example of a method for enhancing charge / discharge noise characteristics according to one embodiment of the present disclosure.

[0035] FIG. 5 is a flowchart illustrating an example of a method for detecting abnormal operation of an MCU according to one embodiment of the present disclosure.

[0036] FIG. 6 shows an exemplary computing device for carrying out the above-described method and / or embodiments, etc.

[0037]

[0038] Hereinafter, specific details for implementing the present invention will be described in detail with reference to the attached drawings. However, in the following description, specific descriptions regarding widely known functions or configurations will be omitted if there is a risk of unnecessarily obscuring the essence of the present invention.

[0039] In the attached drawings, identical or corresponding components are assigned the same reference numerals. Additionally, in the description of the following embodiments, the description of identical or corresponding components may be omitted. However, even if a description of a component is omitted, it is not intended that such component is not included in any embodiment.

[0040] The advantages and features of the embodiments disclosed in this specification, and the methods for achieving them, will become clear by referring to the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms, and these embodiments are provided merely to fully inform a person skilled in the art of the scope of the invention.

[0041] The terms used in this specification will be briefly explained, and the disclosed embodiments will be described in detail. The terms used in this specification have been selected to be as widely used as possible, taking into account their functions in the present invention; however, these terms may vary depending on the intent of those skilled in the relevant field, case law, or the emergence of new technologies. Additionally, in specific cases, terms may be arbitrarily selected by the applicant, and in such cases, their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this invention should be defined not merely by their names, but based on their meanings and the overall content of the present invention.

[0042] In this specification, singular expressions include plural expressions unless the context clearly specifies them as singular. Additionally, plural expressions include singular expressions unless the context clearly specifies them as plural. Throughout the specification, when a part is described as including a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0043] In the present invention, terms such as 'comprising', 'comprising', etc. may indicate the presence of features, steps, actions, elements and / or components, but do not exclude the addition of one or more other functions, steps, actions, elements, components and / or combinations thereof.

[0044] In the present invention, where a specific component is described as being 'combined,' 'combined,' 'connected,' 'associated,' or 'reacted' to any other component, the specific component may be directly combined, combined, connected, and / or associated with, or reacted to the other component, but is not limited thereto. For example, one or more intermediate components may exist between the specific component and the other component. Additionally, in the present invention, "and / or" may include each of the one or more listed items or a combination of at least some of the one or more items.

[0045] In the present invention, terms such as 'first', 'second', etc., are used to distinguish a specific component from another component, and the components described above are not limited by these terms. For example, the 'first' component may be used to refer to an element of the same or similar form as the 'second' component.

[0046] FIG. 1 is a drawing illustrating an example of a vehicle (100) including a charge / discharge noise characteristic enhancement circuit (112) according to one embodiment of the present disclosure. According to one embodiment, the vehicle (and / or vehicle system) (100) may refer to an electric vehicle and an autonomous vehicle that obtains power by rotating a motor with electricity stored in a battery. For example, the vehicle (100) may include components such as a battery management system (BMS) (110) for monitoring and controlling the state of a battery, such as a cell, module, or pack, a battery pack (120), a charge / discharger (140) for managing the charge / discharge of the battery pack (120), and a current sensor (130) for detecting current during general operation and charge / discharge.

[0047] According to one embodiment, the battery management system (110) may include a plurality of micro control units (MCUs) for monitoring, managing, and / or controlling the state of the battery. Here, an MCU may refer to a unit that integrates a processor, memory, and programmable input / output modules, and the battery management system (110) may monitor, manage, and / or control the state of the battery using the plurality of MCUs. When an abnormal signal associated with the battery is detected, the battery management system (110) may reset the associated MCU to cut off power to the entire system.

[0048] According to one embodiment, the battery management system (110) may include a charge / discharge noise characteristic enhancement circuit (112) to prevent an abnormal signal from being incorrectly detected due to noise generated during the charging and discharging of the battery pack (120). For example, the charge / discharge noise characteristic enhancement circuit (112) can determine whether the battery pack (120) is in a charging / discharging state based on a current value detected by a current sensor (130). Additionally, the charge / discharge noise characteristic enhancement circuit (112) can distinguish between an abnormal signal and noise generated during charging and discharging, and perform an operation to prevent the MCU from being reset due to the noise.

[0049] In FIG. 1, the vehicle (100) is shown to include a battery management system (110), a battery pack (120), a current sensor (130), and a charger / discharger (140), but this is to explain the operation of the charging / discharging noise characteristic enhancement circuit (112), and the vehicle (100) may further include various sensors, devices and / or systems, etc. With such a configuration, the vehicle (100) and / or vehicle system can precisely distinguish between noise and actual abnormal signals generated during the charging / discharging of the battery pack (120) and perform MCU reset control.

[0050] FIG. 2 is an exemplary diagram illustrating the operation of a charge / discharge noise characteristic enhancement circuit (112) during normal operation according to one embodiment of the present disclosure. As illustrated, the charge / discharge noise characteristic enhancement circuit (112) may include a register (202) for detecting abnormal signals, a first delay circuit (204), an AND gate (206), a second delay circuit (208), an MCU (210), a comparator (212), a buffer (214), etc. In FIG. 2, the gray dashed line may indicate the flow of current.

[0051] According to one embodiment, when the battery management system detects an abnormal signal, the MCU (210) may be reset by a HIGH signal output from the register (202). In this case, the battery management system may perform an operation to distinguish between the actual occurrence of an abnormal signal and an error caused by noise generated during charging and discharging based on the noise characteristic enhancement circuit (112).

[0052] According to one embodiment, when an abnormal signal is detected due to charge / discharge noise or an actual abnormal phenomenon, a first MCU reset signal may be output from the 'Out 1' output port of the register (202) and a register signal may be output from the 'Out 2' output port. In this case, the comparator (212) may establish a path between the register (202) and the MCU (210) by performing ON / OFF control of a first switch directly connecting the register (202) and the MCU (210) or a second switch connecting the register (202) and the first delay circuit (204).

[0053] According to one embodiment, a comparator (212) can be used to determine whether the battery is in normal operation and whether it is in charge / discharge operation. For example, a current value received from a current sensor may be input to the (+) input port of the comparator (212), and a set threshold may be input to the (-) input port. Here, the threshold may be set to a value slightly larger than the current that normally flows in the battery. That is, if the current value received from the current sensor is lower than the threshold, the comparator (212) may output a first comparison signal (low voltage signal) to control the first switch to ON and control the second switch to OFF.

[0054] When the first switch is controlled to ON by the comparator (212), the first MCU reset signal output from the register (202) can be immediately provided to the MCU (210). In this case, the MCU (210) can perform a reset operation based on the first MCU reset signal.

[0055] FIG. 3 is an exemplary diagram illustrating the operation of a charge / discharge noise characteristic enhancement circuit (112) during a charge / discharge operation of a battery according to one embodiment of the present disclosure. As illustrated, the charge / discharge noise characteristic enhancement circuit (112) may include a register (202) for detecting an abnormal signal, a first delay circuit (204), an AND gate (206), a second delay circuit (208), an MCU (210), a comparator (212), a buffer (214), etc. In FIG. 3, the gray dashed line may indicate the flow of current.

[0056] According to one embodiment, when an abnormal signal is detected due to charge / discharge noise or an actual abnormal phenomenon, a first MCU reset signal may be output from the 'Out 1' output port of the register (202) and a register signal may be output from the 'Out 2' output port. As described above in FIG. 2, a current value received from a current sensor may be input to the (+) input port of the comparator (212), and a set threshold may be input to the (-) input port. For example, if the current value received from the current sensor is higher than the threshold, the comparator (212) may output a second comparison signal (high voltage signal) to control the second switch ON and control the first switch OFF.

[0057] When the second switch is controlled to ON by the comparator (212), the first MCU reset signal output from the register (202) can be input to the first delay circuit (204). In this case, the first delay circuit (204) can delay the first MCU reset signal and output the second MCU reset signal. For example, the first delay circuit (204) can detect whether the first MCU reset signal remains a HIGH signal during the first delay time and output the second MCU reset signal based on this. That is, if a HIGH signal is temporarily output due to charge / discharge noise, the first MCU reset signal will be converted to a LOW signal, so that it can be primarily determined whether the abnormal signal is due to charge / discharge noise during the first delay time.

[0058] If the first MCU reset signal is maintained as a HIGH signal during the first delay time, the second MCU reset signal may be provided to the AND gate (206). In this case, the register signal output from the register (202) at the 'Out 2' output port may also be provided to the AND gate (206) via the buffer (214). According to one embodiment, the AND gate (206) may output a third MCU reset signal of HIGH signal when both the second MCU reset signal and the register signal are HIGH signals.

[0059] The third MCU reset signal output by the AND gate (206) can be provided to the second delay circuit (208). In this case, the second delay circuit (208) can delay the third MCU reset signal to output a fourth MCU reset signal. For example, the second delay circuit (208) can detect whether the third MCU reset signal remains a HIGH signal during the second delay time and output a fourth MCU reset signal based on this. That is, if a HIGH signal is temporarily output due to charge / discharge noise, the third MCU reset signal will be converted to a LOW signal, so that it can be secondarily determined whether the abnormal signal is due to charge / discharge noise during the second delay time. In this case, the MCU (210) can perform a reset operation based on the fourth MCU reset signal.

[0060] Additionally, when the third MCU reset signal is provided to the second delay circuit (208), an algorithm for determining charge / discharge noise may be executed together. For example, the battery management system may determine whether the reset register signal output from the reset register is a HIGH signal. If the reset register signal is a HIGH signal, the battery management system may determine whether the register signal of the abnormal signal detection register is a HIGH signal. If the register signal is a HIGH signal, the battery management system may determine whether a power cutoff command has been output. If it is determined that a power cutoff command has been output, it may be determined that an actual abnormal signal, rather than charge / discharge noise, has occurred.

[0061] With this configuration, the battery management system can enhance the noise characteristics generated during charging and discharging of the battery and / or battery pack based on a charging and discharging noise characteristic enhancement circuit, and effectively prevent the MCU (210) from being incorrectly reset due to charging and discharging noise.

[0062] FIG. 4 is a flowchart illustrating an example of a method (400) for enhancing charge / discharge noise characteristics according to one embodiment of the present disclosure. The method for enhancing charge / discharge noise characteristics (400) may be performed by at least one processor (e.g., at least one processor of a vehicle system and / or battery management system). The method for enhancing charge / discharge noise characteristics (400) may be initiated by the processor generating a first MCU reset signal and a register signal using a register (S410). Generally, when an abnormal signal is detected, the first MCU reset signal and the register signal may have a value of 1, i.e., a HIGH signal.

[0063] According to one embodiment, the generated first MCU reset signal can be transmitted to a first delay circuit. For example, when charging or discharging a battery, an associated switch (e.g., a second switch) may be controlled to ON by a comparator, and the generated first MCU reset signal can be transmitted to the first delay circuit. In this case, the processor can use the first delay circuit to delay the first MCU reset signal and generate a second MCU reset signal (S420). For example, the processor can continuously detect a change in the first MCU reset signal output from a register during the first delay time of the first delay circuit, and if the HIGH signal is maintained, generate a second MCU reset signal.

[0064] According to one embodiment, the processor can generate a third MCU reset signal by providing a second MCU reset signal and a register signal to an AND gate (S430). For example, the register signal may be provided to the AND gate through a buffer, and the processor can generate a third MCU reset signal by using the AND gate when both the second MCU reset signal and the register signal have a HIGH signal. At this time, the generated third MCU reset signal may be provided to a second delay circuit.

[0065] According to one embodiment, the processor can generate a fourth MCU reset signal by delaying a third MCU reset signal using a second delay circuit (S440). For example, the processor can generate a fourth MCU reset signal if the HIGH signal is maintained by continuously detecting a change in the third MCU reset signal output from an AND gate during the second delay time of the second delay circuit. In this case, the processor may generate the fourth MCU reset signal by determining whether abnormal operation of the MCU is detected in addition to whether the third MCU reset signal is maintained as a HIGH signal. When the fourth MCU reset signal is generated in this manner, the processor can perform a reset operation of the MCU based on the fourth MCU reset signal (S450).

[0066] FIG. 5 is a flowchart illustrating an example of an MCU abnormal operation detection method (500) according to one embodiment of the present disclosure. The MCU abnormal operation detection method (500) may be performed by at least one processor (e.g., at least one processor of a vehicle system and / or battery management system). The MCU abnormal operation detection method (500) may be initiated by the processor determining whether a reset register signal is '0' (LOW signal) (S510). Here, the reset register may be a separate register from the abnormal signal detection register.

[0067] According to one embodiment, if the processor determines that the reset register signal is '0', it determines that no abnormal signal associated with the battery is detected and can perform normal operation of the MCU (S520). On the other hand, if the reset register signal is determined to be '1' (HIGH signal), the processor can determine whether the signal of the abnormal signal detection register is '1' (S530).

[0068] In the event of a normal abnormal signal, the reset register signal and the abnormal signal detection register signal will both be '1', so the processor can determine that it is an abnormal reset if the register signal is determined to be '0' (S560). In this case, the processor can perform normal operation of the MCU (S570).

[0069] Meanwhile, if the register signal is determined to be '1', the processor can determine whether a power cutoff command has been output (S540). In a normal abnormal signal occurrence situation, when both the reset register signal and the abnormal signal detection register signal are '1', a power cutoff command will be output; therefore, if the power cutoff command is not output, the processor can determine that it is an abnormal reset (S560). In this case, the processor can perform normal operation of the MCU (S570).

[0070] On the other hand, if it is determined that a power cutoff command has been output, the processor can clear the register and cut off the power to the MCU (S550). In the event of an abnormal signal, the values ​​of both the reset register signal and the register signal are converted to '1', and the power to the MCU can be cut off by the power cutoff command. That is, the processor can determine that an abnormal signal has occurred only when all three conditions are satisfied. In addition, if the processor does not satisfy any of the three conditions, it can determine that an incorrect signal has been detected due to charge / discharge noise and perform or command the normal operation of the MCU.

[0071] FIG. 6 illustrates an exemplary computing device (600) for performing the above-described method and / or embodiment, etc. According to one embodiment, the computing device (600) may include the above-described vehicle system and / or battery management system. For example, the computing device (600) may refer to any module, device and / or system for information processing.

[0072] The computing device (600) includes a processor (610), memory (620), storage device (630), communication device (640), a high-speed interface (650) connected to the memory (620) and a high-speed expansion port, and a low-speed interface (660) connected to a low-speed bus and storage device. Each of the components (610, 620, 630, 640 and 650) may be interconnected using various buses and may be mounted on the same main board or connected in other suitable ways. The processor (610) may be configured to process instructions of a computer program by performing basic arithmetic, logic, and input / output operations. For example, the processor (610) may process instructions stored in memory (620), storage device (630), etc., and / or instructions executed within the computing device (600) to display graphic information on an external input / output device (670), such as a display device coupled to the high-speed interface (650).

[0073] The communication device (640) may provide a configuration or function for the input / output device (670) and the computing device (600) to communicate with each other via a network, and may provide a configuration or function to support the input / output device (670) and / or the computing device (600) communicating with other external devices, etc. For example, a request or data generated by the processor of an external device according to any program code may be transmitted to the computing device (600) via a network under the control of the communication device (640). Conversely, a control signal or command provided under the control of the processor (610) of the computing device (600) may be transmitted to another external device via the communication device (640) and the network.

[0074] In FIG. 6, the computing device (600) is depicted as including one processor (610), one memory (620), etc., but is not limited thereto, and the computing device (600) may be implemented using multiple memories, multiple processors and / or multiple buses, etc. Additionally, in FIG. 6, it is described as having one computing device (600), but is not limited thereto, and multiple computing devices may interact and perform operations necessary to execute the method described above.

[0075] Memory (620) can store information within a computing device (600). According to one embodiment, memory (620) may be composed of a volatile memory unit or a plurality of memory units. Additionally or alternatively, memory (620) may be composed of a non-volatile memory unit or a plurality of memory units. Furthermore, memory (620) may be composed of other forms of computer-readable media, such as a magnetic disk or an optical disk. Additionally, memory (620) may store an operating system and at least one program code and / or instruction.

[0076] The storage device (630) may be one or more mass storage devices for storing data for the computing device (600). For example, the storage device (630) may be a computer-readable medium including a magnetic disc such as a hard disk or removable disk, an optical disc, a semiconductor memory device such as an EPROM (Erasable Programmable Read-Only Memory), an EEPROM (Electrically Erasable PROM), or a flash memory device, or may be configured to include such a computer-readable medium. Additionally, a computer program may be tangibly implemented on such a computer-readable medium.

[0077] The high-speed interface (650) and the low-speed interface (660) may be means for interaction with an input / output device (670). For example, the input device may include a device such as a camera including an audio sensor and / or an image sensor, a keyboard, a microphone, a mouse, etc., and the output device may include a device such as a display, a speaker, a haptic feedback device, etc. In another example, the high-speed interface (650) and the low-speed interface (660) may be means for interfacing with a device in which the configuration or function for performing input and output is integrated into one, such as a touchscreen, etc.

[0078] According to one embodiment, the high-speed interface (650) manages bandwidth-intensive operations for the computing device (600), while the low-speed interface (660) may manage less bandwidth-intensive operations than the high-speed interface (650), but such function assignments are merely exemplary. According to one embodiment, the high-speed interface (650) may be coupled to high-speed expansion ports capable of accommodating memory (620), an input / output device (670), and various expansion cards (not shown). Additionally, the low-speed interface (660) may be coupled to a storage device (630) and a low-speed expansion port. Furthermore, the low-speed expansion port, which may include various communication ports (e.g., USB, Bluetooth, Ethernet, wireless Ethernet), may be coupled to one or more input / output devices (670), such as a keyboard, a pointing device, or a scanner, or to a networking device such as a router or a switch via a network adapter.

[0079] In FIG. 6, the input / output device (670) is depicted as not being included in the computing device (600), but is not limited thereto and may be configured as a single device with the computing device (600). Additionally, in FIG. 6, the high-speed interface (650) and / or low-speed interface (660) are depicted as elements configured separately from the processor (610), but is not limited thereto and the high-speed interface (650) and / or low-speed interface (660) may be configured to be included in the processor.

[0080] The methods and / or various embodiments described above may be realized in digital electronic circuits, computer hardware, firmware, software, and / or combinations thereof. Various embodiments of the present invention may be executed by a data processing device, for example, one or more programmable processors and / or one or more computing devices, or implemented as a computer program stored on a computer-readable medium and / or on a computer-readable medium. The computer program described above may be written in any form of programming language, including a compiled language or an interpreted language, and may be distributed in any form, such as a standalone program, a module, or a subroutine. The computer program may be distributed through a single computing device, a plurality of computing devices connected through the same network, and / or a plurality of computing devices distributed to be connected through a plurality of different networks.

[0081] The above-described methods and / or various embodiments may be performed by one or more processors configured to execute one or more computer programs that process, store, and / or manage any functions, functions, etc. by operating based on input data or generating output data. For example, the methods and / or various embodiments of the present invention may be performed by special-purpose logic circuits such as a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC), and an apparatus and / or system for performing the methods and / or embodiments of the present invention may be implemented as a special-purpose logic circuit such as an FPGA or an ASIC.

[0082] One or more processors executing a computer program may include one or more processors of a general-purpose or special-purpose microprocessor and / or any type of digital computing device. The processor may receive instructions and / or data from each of read-only memory and random access memory, or receive instructions and / or data from read-only memory and random access memory. In the present invention, components of a computing device performing the methods and / or embodiments may include one or more processors for executing instructions and one or more memories for storing instructions and / or data.

[0083] According to one embodiment, a computing device may exchange data with one or more mass storage devices for storing data. For example, the computing device may receive and / or receive data from a magnetic disc or an optical disc, and may transfer data to a magnetic disc or an optical disc. A computer-readable medium suitable for storing instructions and / or data associated with a computer program may include, but is not limited to, any form of non-volatile memory including semiconductor memory devices such as EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable PROM), and flash memory devices. For example, the computer-readable medium may include magnetic discs such as internal hard disks or removable disks, photomagnetic discs, CD-ROMs, and DVD-ROMs.

[0084] To provide interaction with a user, the computing device may include, but is not limited to, a display device for providing or displaying information to the user (e.g., CRT (Cathode Ray Tube), LCD (Liquid Crystal Display), etc.) and a pointing device (e.g., keyboard, mouse, trackball, etc.) on which the user can provide input and / or commands, etc. on the computing device. That is, the computing device may further include any other type of device for providing interaction with the user. For example, the computing device may provide any form of sensory feedback to the user for interaction with the user, including visual feedback, auditory feedback and / or tactile feedback. In this regard, the user may provide input to the computing device through various gestures such as visual, vocal, and motion.

[0085] In the present invention, various embodiments may be implemented in a computing device comprising back-end components (e.g., data servers), middleware components (e.g., application servers), and / or front-end components. In this case, the components may be interconnected by any form or medium of digital data communication, such as a communication network. According to one embodiment, the communication network may be composed of a wired network such as Ethernet, Power Line Communication, telephone line communication devices, and RS-serial communication, a mobile communication network, a Wireless LAN (WLAN), a wireless network such as Wi-Fi, Bluetooth, and ZigBee, or a combination thereof. For example, the communication network may include a Local Area Network (LAN), a Wide Area Network (WAN), etc.

[0086] A computing device based on the exemplary embodiments described herein may be implemented using hardware and / or software configured to interact with a user, including a user device, a user interface (UI) device, a user terminal, or a client device. For example, the computing device may include a portable computing device such as a laptop computer. Additionally or alternatively, the computing device may include, but is not limited to, Personal Digital Assistants (PDAs), tablet PCs, game consoles, wearable devices, Internet of Things (IoT) devices, Virtual Reality (VR) devices, Augmented Reality (AR) devices, etc. The computing device may further include other types of devices configured to interact with a user. Additionally, the computing device may include a portable communication device suitable for wireless communication over a network such as a mobile communication network (e.g., a mobile phone, a smartphone, a wireless cellular phone, etc.). A computing device may be configured to communicate wirelessly with a network server using wireless communication technologies and / or protocols such as radio frequency (RF), microwave frequency (MWF) and / or infrared frequency (IRF).

[0087] Various embodiments of the present invention, including specific structural and functional details, are exemplary. Accordingly, the embodiments of the present invention are not limited to those described above and may be implemented in various other forms. Furthermore, the terms used in the present invention are intended to describe some embodiments and are not to be interpreted as limiting the embodiments. For example, singular words and the above may be interpreted to include plural forms unless the context clearly indicates otherwise.

[0088] In this invention, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which such concepts belong. Furthermore, commonly used terms, such as those defined in advance, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology.

[0089] Although the present invention has been described in relation to some embodiments, various modifications and changes may be made without departing from the scope of the invention as understood by a person skilled in the art to which the invention pertains. Furthermore, such modifications and changes should be considered to fall within the scope of the claims appended to this specification.

Claims

1. As a circuit for enhancing charge / discharge noise characteristics, A register that detects an abnormal signal and outputs a first MCU reset signal and a register signal; A first delay circuit that delays the first MCU reset signal output from the register and outputs a second MCU reset signal; An AND gate that receives the second MCU reset signal and the register signal and outputs a third MCU reset signal; A second delay circuit that delays the third MCU reset signal output from the AND gate and outputs a fourth MCU reset signal; and An MCU (micro control unit) that performs a reset operation based on the first MCU reset signal or the fourth MCU reset signal; A charge / discharge noise characteristic enhancement circuit including 2. In Paragraph 1, A comparator that determines whether the battery is in normal operation and whether it is in charge / discharge operation based on the current value received from a current sensor; A charge / discharge noise characteristic enhancement circuit that further includes 3. In Paragraph 2, The above comparator is, A charge / discharge noise characteristic enhancement circuit that determines whether the battery is in normal operation and whether it is in charge / discharge operation based on whether the current value received from the current sensor is higher than a threshold value.

4. In Paragraph 2, A first switch connecting the above register and the above MCU; Includes more, A charge / discharge noise characteristic enhancement circuit in which, when the current value received from the current sensor is determined to be lower than a threshold value, the first switch is controlled to ON by a first comparison signal output by the comparator.

5. In Paragraph 2, A second switch connecting the above register and the above first delay circuit; Includes more, A charge / discharge noise characteristic enhancement circuit in which, when the current value received from the current sensor is determined to be higher than a threshold value, the second switch is controlled to ON by a second comparison signal output by the comparator.

6. In Paragraph 1, A buffer that receives the above register signal and transmits it to the above first delay circuit; A charge / discharge noise characteristic enhancement circuit that further includes 7. In Paragraph 1, The above first delay circuit is, A charge / discharge noise characteristic enhancement circuit that outputs a second MCU reset signal when the first MCU reset signal is maintained as a HIGH signal during a first delay time.

8. In Paragraph 1, The above AND gate is, A charge / discharge noise characteristic enhancement circuit that outputs the third MCU reset signal when both the second MCU reset signal and the register signal are HIGH signals.

9. In Paragraph 1, The above second delay circuit is, A charge / discharge noise characteristic enhancement circuit that outputs the fourth MCU reset signal when the third MCU reset signal is maintained as a HIGH signal during the second delay time.

10. As a vehicle system, battery pack; A charger / discharger that performs charging and discharging of the above battery pack; A current sensor connected between the battery pack and the charger / discharger to provide a current value flowing from the battery pack to a battery management system; and A battery management system (BMS) including a charge / discharge noise enhancement circuit for detecting abnormal signals and resetting the MCU A vehicle system including 11. In Paragraph 10, The above charge / discharge noise characteristic enhancement circuit is, A register that detects an abnormal signal and outputs a first MCU reset signal and a register signal; A first delay circuit that delays the first MCU reset signal output from the register and outputs a second MCU reset signal; An AND gate that receives the second MCU reset signal and the register signal and outputs a third MCU reset signal; A second delay circuit that delays the third MCU reset signal output from the AND gate and outputs a fourth MCU reset signal; and An MCU that performs a reset operation based on the first MCU reset signal or the fourth MCU reset signal; A vehicle system including 12. A battery charge / discharge noise enhancement method performed by at least one processor, A step of generating a first MCU reset signal and a register signal using a register; A step of generating a second MCU reset signal by delaying the first MCU reset signal using a first delay circuit; A step of generating a third MCU reset signal by providing the second MCU reset signal and the register signal to an AND gate; A step of generating a fourth MCU reset signal by delaying the third MCU reset signal using a second delay circuit; and A step of performing a reset operation of the MCU based on the above-mentioned fourth MCU reset signal; A battery charge / discharge noise enhancement method including 13. In Paragraph 12, A step of determining whether the battery is in normal operation and whether it is in charge / discharge operation based on the current value received from the current sensor using a comparator; A battery charge / discharge noise enhancement method including further 14. In Paragraph 12, The step of generating a second MCU reset signal by delaying the first MCU reset signal using the first delay circuit is: A step of determining whether the first MCU reset signal is maintained as a HIGH signal during a first delay time; and A step of generating the second MCU reset signal when it is determined that the first MCU reset signal remains a HIGH signal during the first delay time; A battery charge / discharge noise enhancement method including 15. In Paragraph 12, The step of generating a fourth MCU reset signal by delaying the third MCU reset signal using the second delay circuit is: A step of determining whether the third MCU reset signal remains a HIGH signal during a second delay time; and A step of generating the fourth MCU reset signal when it is determined that the third MCU reset signal remains a HIGH signal during the second delay time; A battery charge / discharge noise enhancement method including 16. In Paragraph 15, The step of generating a fourth MCU reset signal by delaying the third MCU reset signal using the second delay circuit is: A step of determining whether abnormal operation of the MCU is detected during the second delay time; Includes more, If it is determined that the third MCU reset signal remains a HIGH signal during the second delay time, the step of generating the fourth MCU reset signal is: A step of generating the fourth MCU reset signal when the third MCU reset signal is maintained as a HIGH signal during the second delay time and abnormal operation of the MCU is detected; A battery charge / discharge noise enhancement method including 17. In Paragraph 16, The step of determining whether abnormal operation of the MCU is detected during the second delay time is: A step of determining whether a reset register signal output from a reset register is a HIGH signal; A step of determining whether the register signal is a HIGH signal when the reset register signal is a HIGH signal; A step of determining whether a power cutoff command has been output when the above register signal is a HIGH signal; and A step of determining that an abnormal operation of the MCU has been detected when it is determined that the above power cut-off command has been output; A battery charge / discharge noise enhancement method including

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