Data writing method, memory storage device and memory control circuit unit

Abstract

This invention proposes a data writing method, a memory storage device, and a memory control circuit unit for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes multiple word lines, each word line containing multiple physical strings. The data writing method includes: for a first word line, writing first data to a first physical string of the first word line using a first instruction according to a first write mode; and writing at least second data to a second physical string of the first word line using a second instruction according to a second write mode, wherein the data length of the first data is different from the data length of the second data, and the first physical string is different from the second physical string.

Description

Technical Field

[0001] This disclosure relates to a data writing method, and more particularly to a method for writing data to a physical string on a word line, a memory storage device, and a memory control circuit unit. Background Technology

[0002] The rapid growth of portable electronic devices such as mobile phones and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the aforementioned portable electronic devices due to their non-volatile data, low power consumption, small size, and lack of mechanical structure.

[0003] The total page size may differ between different rewritable nonvolatile memory modules. Generally, each page contains user data and corresponding error correction codes. After deducting the space occupied by the aforementioned data and error correction codes, if there is still unused remaining length in the page, the current practice is to fill the remaining segment with redundant data to meet the requirements of the page write format.

[0004] The aforementioned redundant data itself has no substantial data meaning; its function is merely to fill page space. However, to avoid the bit distribution of the written data being too concentrated, which could affect the reliability of the memory cells, most manufacturers currently require that the written data have sufficient randomness during write operations. Therefore, even redundant data still needs to be randomized by the system before being written to the rewritable non-volatile memory module.

[0005] In this architecture, each write operation requires the transmission of user data, error correction codes, and randomized redundant data. This not only increases the total amount of data transmitted but also requires the controller to perform additional data randomization and transmission-related processing, resulting in reduced write performance and increased power consumption. Summary of the Invention

[0006] This disclosure proposes a data writing method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes multiple word lines, each word line containing multiple physical strings. The data writing method includes: for a first word line, using a first instruction in a first write mode to transfer first data to the rewritable non-volatile memory module to write the first data to a first physical string of the first word line; and using a second instruction in a second write mode to transfer second data to the rewritable non-volatile memory module to write at least the second data to a second physical string of the first word line, wherein the data length of the first data carried by the first instruction is different from the data length of the second data carried by the second instruction, and the first physical string is different from the second physical string.

[0007] In one embodiment disclosed herein, the first instruction is different from the second instruction.

[0008] In one embodiment disclosed herein, the first data includes first valid data, first parity data, and first redundant data. The second data includes second valid data and second parity data, and the data length of the first data is greater than the data length of the second data.

[0009] In one embodiment disclosed herein, a first write mode is used to temporarily store first data in a buffer within a rewritable non-volatile memory module before writing it to a first physical string. A second write mode is used to temporarily store second valid data and second parity data in a buffer. The address of the first valid data in the buffer is aligned with the address of the second valid data in the buffer, and the address of the first parity data in the buffer is aligned with the address of the second parity data in the buffer. The second write mode is used to write the second valid data, the second parity data, and the first redundant data to a second physical string.

[0010] In one embodiment disclosed herein, the total length of the first valid data, the first parity data, and the first redundant data written to the first physical string is the same as the total length of the second valid data, the second parity data, and the first redundant data written to the second physical string.

[0011] In one embodiment disclosed herein, the data writing method further includes: for the second word line, writing third data to the third physical string of the second word line according to the first writing mode. The first physical string and the third physical string share multiple bit lines, and the third data includes second redundant data, which is the inverse of the first redundant data.

[0012] In one embodiment disclosed herein, the aforementioned first redundant data comprises multiple sub-redundant data, which are distributed across multiple fields of the buffer. The second write mode uses another second instruction to change the write start address to one of the fields.

[0013] In one embodiment of this disclosure, the first redundant data described above is randomly generated.

[0014] In one embodiment disclosed herein, the second instruction is executed after the first instruction, and the programmed order of the second physical string is after the programmed order of the first physical string.

[0015] Embodiments of the present invention provide a memory storage device, including a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface is coupled to a host system. The rewritable non-volatile memory module includes multiple word lines, each word line containing multiple physical strings. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module to perform the data writing method described above.

[0016] Embodiments of the present invention provide a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is coupled to a host system. The memory interface is coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface to execute the aforementioned data writing method.

[0017] The above data writing method can save data transmission time, thereby improving writing speed.

[0018] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0022] Figure 4A This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0023] Figure 4B This is a schematic diagram of a storage cell array according to an exemplary embodiment of the present invention;

[0024] Figure 5This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0025] Figure 6 This is a schematic diagram illustrating the management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;

[0026] Figure 7 This is a schematic diagram illustrating the writing of data to a physical string according to one embodiment;

[0027] Figure 8 This is a schematic diagram illustrating, according to one embodiment, the writing of data to the physical string on the next word line;

[0028] Figure 9 This is a schematic diagram illustrating redundant data distributed across multiple fields according to another embodiment;

[0029] Figure 10 This is a flowchart illustrating a data writing method according to one embodiment. Detailed Implementation

[0030] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description are considered identical or similar when they appear in different drawings. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples of systems and methods within the scope of the claims of the present invention.

[0031] The terms "first," "second," etc., used in this article do not specifically refer to order or sequence; they are merely used to distinguish elements or operations described using the same technical terms.

[0032] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as control circuitry). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0033] Figure 1 This is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0034] Please refer to Figure 1 and Figure 2The host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be coupled to a system bus 110.

[0035] In one exemplary embodiment, the host system 11 can be coupled to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transfer interface 114. Furthermore, the host system 11 can be coupled to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0036] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 via wired or wireless means.

[0037] In one exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be coupled to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0038] In one exemplary embodiment, the host system 11 is a computer system. In another exemplary embodiment, the host system 11 may be any system capable of substantially cooperating with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may each include… Figure 3 The memory storage device 30 and the host system 31.

[0039] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 3 The memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0040] Figure 4A This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 4A The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43. The rewritable non-volatile memory module 43 includes a buffer 46. This buffer 46 is, for example, a random access memory used to temporarily store data from the memory control circuit unit 42.

[0041] The interface unit 41 is used to couple to the host system 11. The memory storage device 10 can communicate with the host system 11 via the interface unit 41. In an exemplary embodiment, the interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 may be packaged in the same chip as the memory control circuit unit 42, or the connection interface unit 41 may be disposed outside the chip containing the memory control circuit unit 42.

[0042] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0043] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one storage cell), a quadruple-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one storage cell), other flash memory modules, or other memory modules with the same characteristics.

[0044] Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, and thus the one or more bits stored in that memory cell can be retrieved.

[0045] Figure 4B This is a schematic diagram of a storage cell array according to an exemplary embodiment of the present invention. Please refer to... Figure 4B The memory cell array 44 includes multiple memory cells 402 for storing data, multiple select gate drain (SGD) transistors 412 and multiple select gate source (SGS) transistors 414, multiple bit lines 404(1)~404(3) connecting these memory cells 402, multiple word lines 406(1)~406(N), and a common source line 408, where N is a positive integer. Specifically, the memory cells 402 are arranged in an array at the intersections of the bit lines 404(1)~404(3) and the word lines 406(1)~406(N), such as... Figure 4B As shown. Figure 4BThis is merely an example, and the present invention does not limit the number of word lines and bit lines in a single memory cell array 44. Furthermore, the rewritable non-volatile memory module 43 may include multiple memory cell arrays 44. These memory cell arrays 44 may be stacked horizontally and / or vertically.

[0046] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than two bits, then physical programming units on the same word line can be classified into at least lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0047] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the data length of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the data length of each physical sector may be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of storage units that are erased. For example, a physical erase unit is a physical block.

[0048] Storage units on the same word line can be divided into multiple physical strings. For example, word line 406(1) contains M storage units, where M is a positive integer. The first to the M / 4th storage units on word line 406(1) form the first physical string, the M / 4+1 to the M / 2th storage units form the second physical string, the M / 2+1 to the 3M / 4th storage units form the third physical string, and the 3M / 4+1 to the Mth storage units form the fourth physical string. These physical strings can store valid data and parity data. Valid data, for example, comes from the host system 11, and parity data is the error correcting code (ECC) and / or error detecting code (EDC) corresponding to the valid data. The purpose of parity data is to check or repair errors generated by valid data. In some embodiments, the data length of valid data that can be stored in a physical string is the same as the data length of the physical programming unit described above, but this invention is not limited thereto.

[0049] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Please refer to... Figure 5 The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0050] The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to describing the operation of the memory control circuit unit 42 and the memory storage device 10.

[0051] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware form. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0052] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in program code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0053] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are coupled to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues a sequence of erase instructions to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuitry is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuitry 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0054] The host interface 52 is coupled to the memory management circuitry 51. The memory management circuitry 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to acquire and identify instructions and data from the host system 11. For example, instructions and data from the host system 11 can be transmitted to the memory management circuitry 51 through the host interface 52. Furthermore, the memory management circuitry 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the invention is not limited thereto, and the host interface 52 can also be compatible with SATA, PATA, IEEE 1394, USB, SD, UHS-I, UHS-II, MS, MMC, eMMC, UFS, CF, IDE, or other suitable data transmission standards.

[0055] Memory interface 53 is coupled to memory management circuitry 51 and used to access rewritable non-volatile memory module 43. For example, memory management circuitry 51 can access rewritable non-volatile memory module 43 through memory interface 53. That is, data to be written to rewritable non-volatile memory module 43 is converted by memory interface 53 into a format acceptable to rewritable non-volatile memory module 43. Specifically, if memory management circuitry 51 needs to access rewritable non-volatile memory module 43, memory interface 53 transmits a corresponding instruction sequence. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection (GC) operations, etc.). These instruction sequences are generated by memory management circuitry 51 and transmitted to rewritable non-volatile memory module 43 through memory interface 53. These instruction sequences may include one or more signals or data on a bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code and memory address.

[0056] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0057] Error checking and correction circuit 54 is coupled to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 obtains a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correction code and / or error check code for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correction code and / or error check code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correction code and / or error check code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correction code and / or error check code. For example, the error checking and correction circuit 54 can use various encoding / decoding algorithms such as Low-Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code to encode and decode data.

[0058] The buffer memory 55 is coupled to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0059] In one exemplary embodiment, Figure 4A The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4A The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0060] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Please refer to... Figure 6 The memory management circuit 51 can logically group the physical units 610(0)~610(C) in the rewritable non-volatile memory module 43 into the storage area 601, the spare area 602 and the system area 603.

[0061] In one exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In another exemplary embodiment, a physical unit may also consist of multiple consecutive or non-consecutive physical addresses.

[0062] In one exemplary embodiment, physical units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 The host system 11 contains user data. For example, physical units 610(0) to 610(A) in storage area 601 can store valid and invalid data. Physical units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, this physical unit can be associated (or added) to free area 602. In addition, physical units in free area 602 (or physical units that do not store valid data) can be erased. When new data is written, one or more physical units can be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0063] In one exemplary embodiment, memory management circuitry 51 may configure logic units 612(0) to 612(D) to map physical units 610(0) to 610(A) in memory area 601. In one exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logic unit may also correspond to a logical programmable unit or consist of multiple consecutive or non-consecutive logical addresses.

[0064] It should be noted that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped to a logical unit, it means that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped to any logical unit, it means that the data currently stored in this physical unit is invalid data.

[0065] In one exemplary embodiment, the memory management circuit 51 may record management data (also known as logic-to-physical mapping information) describing the mapping relationship between logical units and physical units in at least one logic-to-physical mapping table (L2Ptable). When the host system 11 wants to read data from or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 according to the information in this logic-to-physical mapping table.

[0066] In one exemplary embodiment, the memory management circuit 51 may store specific types of data in the system area 603. For example, physical units 610(B+1) to 610(C) in the system area 603 may be dedicated to storing data of high importance and / or data that is not intended to be accessed or modified by the host system 11. For example, data of high importance and / or data that is not intended to be accessed or modified by the host system 11 may include a logical-to-physical mapping table, a bad block management table, a wear leveling table, a valid data management table, and / or other types of management data, which are not limited by the present invention. The logical-to-physical mapping table is used to record mapping information. This mapping information may reflect the mapping relationship between logical units and physical units. The bad block management table is used to record information related to at least one bad block in the rewritable non-volatile memory module 43. The wear leveling table may be used to record information related to the wear status of at least one physical unit in the rewritable non-volatile memory module 43 (e.g., read count, write count, and / or erase count). The valid data management table can be used to record information related to the valid count of at least one physical cell in the rewritable nonvolatile memory module 43.

[0067] In one exemplary embodiment, the memory management circuitry 51 may not map any logical units to physical units in system area 603. Therefore, data stored in system area 603 can be prevented from being accessed or modified by the host system 11.

[0068] Please refer to Figure 4A Here, it is assumed that the memory control circuit unit 42 receives multiple data entries from the host system 11 and intends to write these data entries into the rewritable non-volatile memory module 43. Specifically, the memory control circuit unit 42 uses at least two write modes (referred to as the first write mode and the second write mode, respectively). For different physical strings on the same word line of the rewritable non-volatile memory module 43, the memory control circuit unit 42 uses different write modes to write data to these physical strings. For example, according to the first write mode, the memory control circuit unit 42 uses a single first instruction to transfer first data to the rewritable non-volatile memory module 43 to write the first data to the first physical string, and according to the second write mode, uses a single second instruction to transfer second data to the rewritable non-volatile memory module 43 to at least write the second data to the second physical string, where the first physical string is different from the second physical string, and the first and second physical strings belong to the same word line. Furthermore, the data length of the first data carried by the first instruction is different from the data length of the second data carried by the second instruction. In some embodiments, different physical strings on the same word line can store the same length of effective data, but different write modes are used in the above approach. Therefore, the length of the first data is different from the length of the second data. This approach can save the amount of data that needs to be transmitted and can increase the write speed.

[0069] Specifically Figure 7 This is a schematic diagram illustrating the writing of data to a physical string according to one embodiment. In this example, the memory control circuit unit 42 divides the data from the host system 11 into multiple valid data, each valid data having a data length of 4K. In this example, word line 406(1) contains physical strings 751~754, each physical string can store valid data with a data length of 16K, so one physical string can store four valid data. Physical strings on the same word line must be written (programmed) in a programmed order. In this example, the programmed order of physical string 752 is after the programmed order of physical string 751; the programmed order of physical string 753 is after the programmed order of physical string 752; and the programmed order of physical string 754 is after the programmed order of physical string 753. The memory control circuit unit 42 generates corresponding parity data for each valid data. For example, the first data 710 contains four valid data 711 and four parity data 712 (for simplicity, ...). Figure 7 (Only one valid data and one parity data are indicated in the first data). Since four valid data and four parity data cannot fill all the space of a physical string, according to the specifications of some manufacturers, the memory control circuit unit 42 will generate additional redundant data 713, which will also be included in the first data 710. In some embodiments, this redundant data 713 is randomly generated.

[0070] A write mode may contain multiple instructions, one of which is to write data into buffer 46 of the rewritable nonvolatile memory module 43, and another instruction instructs the rewritable nonvolatile memory module 43 to write the data in buffer 46 into the corresponding physical string. Figure 7 The symbols O1 to O8 indicate the order of operations, used to represent the execution order of instructions.

[0071] The first data 710 is written to the physical string 751 using a single first instruction according to the first write mode. In some embodiments, the first instruction is used to temporarily store the first data 710 in the buffer 46. If the data length carried by the first instruction is the same as the capacity of the buffer 46, the first instruction directly writes the data into the buffer 46. If the data length carried by the first instruction is less than the capacity of the buffer 46, the first instruction first clears the buffer 46 and then writes the data into the buffer 46. In this example, the data length of the first data is the same as the capacity of the buffer 46; in other words, the original data in the buffer 46 is not retained after the first instruction is executed. After the first instruction is executed (corresponding to operation sequence O1), the buffer 46 stores valid data 711, parity data 712, and redundant data 713. The first write mode also includes another instruction, which, after being executed by the rewritable non-volatile memory module 43, writes the first data 710 in the buffer 46 into the physical string 751 (corresponding to operation sequence O2).

[0072] Next, the memory control circuit unit 42 combines the valid data 721 from the host system 11 and the corresponding parity data 722 to form the second data 720. The second data 720 contains four valid data entries and four parity data entries. Again, for simplicity... Figure 7 Only one valid data entry and one parity data entry were marked. The second data entry 720 does not contain redundant data, therefore the data length of the first data entry 710 will be greater than the data length of the second data entry 720.

[0073] The memory control circuit unit 42 uses a second instruction to write the second data 720 to the physical string 752 according to the second write mode. In this embodiment, the second instruction is used to write data to the buffer 46 without clearing the buffer 46. Therefore, if the data length carried by the second instruction is less than the capacity of the buffer 46, some data will remain in the buffer 46. This characteristic is used in this example to retain redundant data. After executing the second instruction, the second data 720 is temporarily stored in the buffer 46 (corresponding to operation sequence O3). In this embodiment, the address of valid data 711 in the buffer 46 is aligned with the address of valid data 721 in the buffer 46, and the address of parity data 712 in the buffer 46 is aligned with the address of parity data 722 in the buffer 46. Therefore, after executing the second instruction, the original valid data 711 and parity data 712 in the buffer 46 are overwritten, but the redundant data 713 in the buffer 46 is retained.

[0074] Another instruction in the second write mode instructs the rewritable non-volatile memory module 43 to write the valid data 721, parity data 722, and redundant data 713 from the buffer 46 to the physical string 752 (corresponding to operation sequence O4). It is worth noting that in the second write mode, the memory control circuit unit 42 and the rewritable non-volatile memory module 43 transfer the second data 720. Since the second data 720 does not contain redundant data, the transfer amount is relatively small, which shortens the time required to write data and is equivalent to increasing the write speed. In other words, the first write mode is used to transfer redundant data, but the second write mode reuses this redundant data stored in the buffer 46. Furthermore, the total length of the valid data (including valid data 711), parity data (including parity data 712), and redundant data 713 written to the first physical string 751 is the same as the total length of the valid data (including valid data 721), parity data (including parity data 722), and redundant data 713 written to the second physical string 752. In the second write mode, although the memory control circuit unit 42 transmits less data to the rewritable non-volatile memory module 43, the rewritable non-volatile memory module 43 writes the same total length of data to the second physical string 752.

[0075] The second write mode is also used for other physical strings on the same word line. Specifically, the third data 730 is first written to buffer 46 (corresponding to operation order O5), and then the third data 730 and redundant data 713 are written to physical string 753 (corresponding to operation order O6). Similarly, the fourth data 740 is first written to buffer 46 (corresponding to operation order O7), and then the fourth data 740 and redundant data 713 are written to physical string 754 (corresponding to operation order O8). Therefore, redundant data does not need to be transmitted when writing the third data 730 and the fourth data 740. Therefore, the second instruction is executed after the first instruction. In other words, the first physical string 751 in word line 406(1) uses the first write mode, while the subsequent physical strings 752~754 all use the second write mode.

[0076] In some embodiments, the first instruction described above differs from the second instruction. The identifier of the first instruction is, for example, "80", and the identifier of the second instruction is, for example, "85". The second instruction is also referred to as the copy back instruction.

[0077] In other embodiments, both the first write mode and the second write mode use the second instruction. Specifically, in the first write mode, the second instruction writes the first data to buffer 46. Although the second instruction does not clear buffer 46 first, since the length of the first data is the same as the capacity of buffer 46, all space in buffer 46 will be overwritten with the first data. In the second write mode, the second instruction writes the second data to buffer 46, and the remaining operations have been described above.

[0078] Figure 8 This is a schematic diagram illustrating, according to one embodiment, the writing of data to the physical string on the next word line. Please refer to... Figure 8 Here, data needs to be written to physical strings 851~854 on word line 406(2). Figure 7 Similarly, data 810 is written to physical string 851 according to the first write mode, and data 810 includes redundant data 813. Data 820, 830, and 840 are written to physical strings 852-854 respectively according to the second write mode, and data 820, 830, and 840 do not contain redundant data. The difference is that the redundant data 813 is inversely related to... Figure 7 The redundant data 713 has the following structure: if the first three bits of redundant data 713 are "101", then the first three bits of redundant data 813 are "010", and so on. The reason for this is that physical string 751 and physical string 851 share multiple bit lines (e.g., bit lines 404(1)~404(3)). If the contents of redundant data 713 and redundant data 813 are the same, then the bits on the same bit line will be the same, which can easily lead to data errors. Making redundant data 813 inversely to redundant data 713 can avoid such errors.

[0079] Figure 9 This is a schematic diagram illustrating, according to another embodiment, the distribution of redundant data across multiple fields. Figure 9 In this embodiment, the first data 910 includes valid data 921-924, parity data 931-934, and redundant data. This redundant data is split into multiple sub-redundant data 941-944. Each sub-redundant data is appended to the corresponding parity data; for example, sub-redundant data 941 follows parity data 931. The first data 910 is written to buffer 46. Specifically, buffer 46 includes multiple fields 911-914, all of the same length. Each field stores one copy of valid data, one copy of parity data, and one copy of sub-redundant data. For example, field 911 stores valid data 921, parity data 931, and sub-redundant data 941.

[0080] In some embodiments, the rewritable nonvolatile memory module 43 supports a partial read instruction that reads only 4K data lengths of data from a single word line (instead of a physical string). However, to use this partial read instruction, the valid data must be evenly distributed throughout the physical string. For example, assuming a physical string of length M, and fields 911-914 are all M / 4 in length, then the starting address of field 912 is M / 4, the starting address of field 913 is M / 2, and the starting address of field 914 is 3M / 4. The partial read instruction can only read 4K data lengths of valid data starting from addresses 0, M / 4, M / 2, and 3M / 4. Figure 7 Or Figure 8 If redundant data is configured in a certain way, some read commands may read incorrect data.

[0081] exist Figure 9 In the embodiment, the first write mode similarly uses a first instruction (or a second instruction) to temporarily store the first data 910 in the buffer 46 before writing it to the first physical string. However, in the second write mode, redundant data does not need to be transmitted. The memory control circuit unit 42 first uses a second instruction to transmit the first set of valid data and parity data to overwrite the valid data 921 and parity data 931. Then, the memory control circuit unit 42 uses another second instruction to change the write start position to the next field 912. At this time, the second instruction does not contain data, but only changes the write start position. Next, the memory control circuit unit 42 uses a second instruction to transmit the second set of valid data and the second set of parity data to overwrite the valid data 922 and parity data 932, and then uses a second instruction to change the write start position to the next field 913. In this way, the second write mode also does not need to transmit redundant data, but writes the corresponding valid data, parity data, and sub-redundant data 941~944 to the second physical string. Similarly, the sub-redundant data 941~944 will be reused.

[0082] Figure 10 This is a flowchart illustrating a data writing method according to one embodiment. In step 1001, according to a first write mode, a first instruction is used to transfer first data to a rewritable non-volatile memory module to write the first data to a first physical string of a first word line. In step 1002, according to a second write mode, a second instruction is used to transfer second data to a rewritable non-volatile memory module to write the second data to a second physical string of the first word line, wherein the data length of the first data carried by the first instruction is different from the data length of the second data carried by the second instruction, and the first physical string is different from the second physical string. Figure 10 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 10 Each step can be implemented as multiple program codes or circuits, but this invention is not limited thereto. Furthermore, Figure 10 The method can be used in conjunction with the above embodiments or alone; in other words, Figure 10 Other steps can also be added between the various steps.

[0083] In the above data writing method, different physical strings on the same word line use different writing modes, which can save data transmission and effectively improve the writing speed.

[0084] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A data write method, characterized by, A rewritable non-volatile memory module is used, wherein the rewritable non-volatile memory module includes multiple word lines, each of the multiple word lines containing multiple physical strings, and the data writing method includes: For the first word line among the plurality of word lines, according to the first write mode, a first instruction is used to transmit first data to the rewritable non-volatile memory module to write the first data into the first physical string among the plurality of physical strings of the first word line; and According to the second write mode, a second instruction is used to transmit second data to the rewritable non-volatile memory module to write the second data to at least the second physical string among the plurality of physical strings of the first word line, wherein the data length of the first data carried by the first instruction is different from the data length of the second data carried by the second instruction, and the first physical string is different from the second physical string.

2. The data write method of claim 1, wherein, The first instruction therein is different from the second instruction therein.

3. The data write method of claim 1, wherein, The first data includes first valid data, first odd / even data, and first redundant data. The second data includes second valid data and second odd / even data, and the data length of the first data is greater than the data length of the second data.

4. The data write method of claim 3, wherein, in The first write mode is used to temporarily store the first data in the buffer of the rewritable non-volatile memory module before writing it to the first physical string. The second write mode is used to temporarily store the second valid data and the second parity data in the buffer, wherein the address of the first valid data in the buffer is aligned with the address of the second valid data in the buffer, and the address of the first parity data in the buffer is aligned with the address of the second parity data in the buffer. The second write mode is used to write the second valid data, the second parity data, and the first redundant data to the second physical string.

5. The data writing method according to claim 4, characterized in that, The total length of the first valid data, the first parity data, and the first redundant data written to the first physical string is the same as the total length of the second valid data, the second parity data, and the first redundant data written to the second physical string.

6. The data writing method according to claim 3, characterized in that, Also includes: For the second word line among the plurality of word lines, the third data is written to the third physical string among the plurality of physical strings of the second word line according to the first write mode, wherein the first physical string and the plurality of third physical strings share multiple bit lines, and the third data includes second redundant data, which is the inverse of the first redundant data.

7. The data writing method according to claim 3, characterized in that, The first redundant data comprises multiple sub-redundant data, which are distributed across multiple fields of the buffer in the rewritable non-volatile memory module. The second write mode uses another second instruction to change the write start address to one of the plurality of fields.

8. The data writing method according to claim 3, characterized in that, The first redundant data is generated randomly.

9. The data writing method according to claim 3, characterized in that, The second instruction is executed after the first instruction, and the programming order of the second physical string is after the programming order of the first physical string.

10. A memory storage device, characterized in that, include: A connection interface unit for coupling to the host system; A rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes multiple word lines, each of the multiple word lines containing multiple physical strings; as well as A memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, is used to perform multiple steps: For the first word line among the plurality of word lines, according to the first write mode, a first instruction is used to transmit the first data to the rewritable non-volatile memory module so as to write the first data to the first physical string among the plurality of physical strings of the first word line; as well as According to the second write mode, a second instruction is used to transmit second data to the rewritable non-volatile memory module to write the second data to at least the second physical string among the plurality of physical strings of the first word line, wherein the data length of the first data carried by the first instruction is different from the data length of the second data carried by the second instruction, and the first physical string is different from the second physical string.

11. The memory storage device according to claim 10, characterized in that, The first instruction therein is different from the second instruction therein.

12. The memory storage device according to claim 10, characterized in that, The first data includes first valid data, first odd / even data, and first redundant data. The second data includes second valid data and second odd / even data, and the data length of the first data is greater than the data length of the second data.

13. The memory storage device according to claim 12, characterized in that, in The first write mode is used to temporarily store the first data in the buffer of the rewritable non-volatile memory module before writing it to the first physical string. The second write mode is used to temporarily store the second valid data and the second parity data in the buffer, wherein the address of the first valid data in the buffer is aligned with the address of the second valid data in the buffer, and the address of the first parity data in the buffer is aligned with the address of the second parity data in the buffer. The second write mode is used to write the second valid data, the second parity data, and the first redundant data to the second physical string.

14. The memory storage device according to claim 13, characterized in that, The total length of the first valid data, the first parity data, and the first redundant data written to the first physical string is the same as the total length of the second valid data, the second parity data, and the first redundant data written to the second physical string.

15. The memory storage device according to claim 12, characterized in that, For the second word line among the plurality of word lines, the memory control circuit unit writes the third data to the third physical string among the plurality of physical strings of the second word line according to the first write mode, wherein the first physical string and the plurality of third physical strings share multiple bit lines, and the third data includes second redundant data, which is inverse of the first redundant data.

16. The memory storage device according to claim 12, characterized in that, The first redundant data comprises multiple sub-redundant data, which are distributed across multiple fields of the buffer in the rewritable non-volatile memory module. The second write mode uses another second instruction to change the write start address to one of the plurality of fields.

17. The memory storage device according to claim 12, characterized in that, The first redundant data is generated randomly.

18. The memory storage device according to claim 12, characterized in that, The second instruction is executed after the first instruction, and the programming order of the second physical string is after the programming order of the first physical string.

19. A memory control circuit unit, characterized in that, This is used to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple word lines, each of which contains multiple physical strings, and the memory control circuit unit includes: Host interface, used to couple to the host system; A memory interface for coupling to the rewritable non-volatile memory module; A memory management circuit, coupled to the host interface and the memory interface, is used to perform multiple steps: For the first word line among the plurality of word lines, according to the first write mode, a first instruction is used to transmit first data to the rewritable non-volatile memory module to write the first data into the first physical string among the plurality of physical strings of the first word line; and According to the second write mode, a second instruction is used to transmit second data to the rewritable non-volatile memory module to write the second data to at least the second physical string among the plurality of physical strings of the first word line, wherein the data length of the first data carried by the first instruction is different from the data length of the second data carried by the second instruction, and the first physical string is different from the second physical string.

20. The memory control circuit unit according to claim 19, characterized in that, The first instruction therein is different from the second instruction therein.

21. The memory control circuit unit according to claim 19, characterized in that, The first data includes first valid data, first odd / even data, and first redundant data. The second data includes second valid data and second odd / even data, and the data length of the first data is greater than the data length of the second data.

22. The memory control circuit unit according to claim 21, characterized in that, in The first write mode is used to temporarily store the first data in the buffer of the rewritable non-volatile memory module before writing it to the first physical string. The second write mode is used to temporarily store the second valid data and the second parity data in the buffer, wherein the address of the first valid data in the buffer is aligned with the address of the second valid data in the buffer, and the address of the first parity data in the buffer is aligned with the address of the second parity data in the buffer. The second write mode is used to write the second valid data, the second parity data, and the first redundant data to the second physical string.

23. The memory control circuit unit according to claim 22, characterized in that, The total length of the first valid data, the first parity data, and the first redundant data written to the first physical string is the same as the total length of the second valid data, the second parity data, and the first redundant data written to the second physical string.

24. The memory control circuit unit according to claim 21, characterized in that, For the second word line among the plurality of word lines, the memory control circuit unit writes the third data to the third physical string among the plurality of physical strings of the second word line according to the first write mode, wherein the first physical string and the plurality of third physical strings share multiple bit lines, and the third data includes second redundant data, which is inverse of the first redundant data.

25. The memory control circuit unit according to claim 21, characterized in that, The first redundant data comprises multiple sub-redundant data, which are distributed across multiple fields of the buffer in the rewritable non-volatile memory module. The second write mode uses another second instruction to change the write start address to one of the plurality of fields.

26. The memory control circuit unit according to claim 21, characterized in that, The first redundant data is generated randomly.

27. The memory control circuit unit according to claim 19, characterized in that, The second instruction is executed after the first instruction, and the programming order of the second physical string is after the programming order of the first physical string.

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