A memory write access control method
By concatenating consecutive write data before memory write access, the latency problem caused by read-modify-write operations in traditional memory write access is solved, thus improving write access efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 沐曦集成电路(南京)有限公司
- Filing Date
- 2026-05-21
- Publication Date
- 2026-06-19
AI Technical Summary
Traditional memory write access requires a read-modify-write operation, which results in additional latency and processor wait time, reducing write access efficiency.
Before performing a memory write access, multiple consecutive write data entries destined for the same write address are concatenated. If they are concatenated into a single valid data entry, the write access operation is performed; otherwise, the number of RMW operations is reduced.
By using data splicing methods, RMW operations are avoided or reduced, thus improving the write access efficiency of the memory.
Smart Images
Figure CN122240037A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip technology, and in particular to a memory write access control method. Background Technology
[0002] In the era of big data, with the increasing demand for data computation, heterogeneous computing chips have become a crucial component of computing infrastructure. Especially for artificial intelligence applications, which require training and inference based on massive datasets, efficient access to memory such as High Bandwidth Memory (HBM) is a critical element. Traditional memory write access requires first determining if the write data at the target memory address is entirely valid. If only part of the write data is valid, the original data at the target memory address needs to be read, partially replaced, with the valid bits of the new write data replacing the corresponding parts of the read data, while the rest of the read data retains its original value. Then, the replaced read data is written back to the target memory address. This operation is a Read-Modify-Write (RMW) operation, a composite operation on memory locations. Because RMW operations require reading data, modifying it, and then writing it, forming a three-step process of "read-modify-write," it introduces additional latency, increasing processor waiting time and thus reducing memory write access efficiency. Therefore, improving memory write access efficiency has become a pressing technical problem. Summary of the Invention
[0003] The purpose of this invention is to provide a memory write access control method that improves the write access efficiency of memory.
[0004] According to one aspect of the present invention, a memory write access control method is provided, comprising: Step S1: Obtain the address to be written and the data to be written corresponding to the write access request to be processed; Step S2: Determine whether there is an address to be written in the preset address cache. If it exists, proceed to step S3; otherwise, proceed to step S7. Step S3: Obtain the cached write data corresponding to the address to be written from the preset data cache area; Step S4: Determine whether the data to be written and the cached write data corresponding to the address to be written can be concatenated. If yes, proceed to step S5; otherwise, proceed to step S6. Step S5: Concatenate the data to be written with the cached write data corresponding to the address to be written and write it to the location of the cached write data corresponding to the address to be written in the preset data cache area, and return to step S1; Step S6: Output the cache write data corresponding to the address to be written and the address to be written, execute the corresponding write access operation, write the data to be written to the location of the cache write data corresponding to the address to be written in the preset data cache area, and return to step S1; Step S7: Write the address to be written to the preset address buffer, write the data to be written to the preset data buffer, and return to step S1.
[0005] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the memory write access control method provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value. It has at least the following beneficial effects: Before performing a memory write access, this invention concatenates multiple consecutive write data entries destined for the same write address as much as possible. If the concatenation results in a single valid data entry before the write access operation is performed, the write operation read-write (RMW) can be avoided. If the concatenation does not result in a single valid data entry, the number of write operation read-write (RMW) occurrences can be reduced, thereby improving the system's memory write access efficiency. Attached Figure Description
[0006] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0007] Figure 1 A flowchart of a memory write access control method provided in an embodiment of the present invention. Detailed Implementation
[0008] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0009] This invention provides a memory write access control method, such as... Figure 1 As shown, it includes: Step S1: Obtain the address to be written and the data to be written corresponding to the write access request to be processed.
[0010] Wherein, the address to be written is the address of the memory to be written corresponding to the write access request to be processed, and the data to be written is the data to be written to the memory corresponding to the write access request to be processed.
[0011] Step S2: Determine whether there is an address to be written in the preset address cache. If it exists, proceed to step S3; otherwise, proceed to step S7.
[0012] Step S3: Obtain the cached write data corresponding to the address to be written from the preset data cache area.
[0013] It should be noted that each write access request contains a corresponding write address and write data. Therefore, when the write address of an access request is cached in the preset address cache area, the write data corresponding to that write address must exist in the preset data cache area.
[0014] Step S4: Determine whether the data to be written and the cached write data corresponding to the address to be written can be concatenated. If yes, proceed to step S5; otherwise, proceed to step S6.
[0015] It should be noted that for two write access requests from the same user, they can be concatenated if the two data requests have the same write address and the corresponding byte bits do not conflict; otherwise, they cannot be concatenated.
[0016] Step S5: Concatenate the data to be written with the cached write data corresponding to the address to be written, and write the concatenation to the location of the cached write data corresponding to the address to be written in the preset data cache area, and return to step S1.
[0017] It should be noted that concatenating the data to be written with the cached write data corresponding to the address to be written and writing it to the location of the cached write data corresponding to the address to be written in the preset data cache area can continue to be concatenated with subsequent new requests. It can be understood that if the concatenated data is fully valid in every byte, then the concatenated data and the corresponding address to be written need to be output directly to perform the corresponding write access operation, and the corresponding address to be written in the preset address cache area should be deleted, and the cached write data corresponding to the address to be written in the preset data cache area should be deleted.
[0018] Step S6: Output the cached write data corresponding to the address to be written and the address to be written, execute the corresponding write access operation, write the data to be written to the location of the cached write data corresponding to the address to be written in the preset data cache area, and return to step S1.
[0019] Step S7: Write the address to be written to the preset address buffer, write the data to be written to the preset data buffer, and return to step S1.
[0020] As one embodiment, the method further includes: Step S10: Open a timing window for each cached write data stored in the preset data cache area. If the cache exceeds the preset time threshold, output the cached write data and the corresponding cached write address from the preset address cache area and execute the corresponding write access operation.
[0021] It should be noted that outputting the cached write data and the corresponding cached write address from the preset address cache area means outputting the cached write data and the corresponding cached write address, and deleting the cached write data and the corresponding cached write address from the preset address cache area. Step S10 can avoid affecting and blocking subsequent data splicing, and ensure the orderly operation of the memory write access control.
[0022] As one embodiment, in step S4, determining whether the data to be written and the cached write data corresponding to the address to be written can be concatenated includes: Step S41: Obtain the valid identifier of each byte of the data to be written and the valid identifier of each byte of the cached write data corresponding to the address to be written. The valid identifier is either valid or invalid.
[0023] Understandably, taking 512 bits of data to be written as an example, the data to be written consists of 64 bytes. If a byte corresponding to the data to be written is valid, it means that new data needs to be written to that byte. If a byte corresponding to the data to be written is invalid, it means that no new data needs to be written to that byte.
[0024] Step S42: If each identical byte of the data to be written and the cached write data corresponding to the address to be written has only one valid identifier or all of them are invalid, then it is determined that the data to be written and the cached write data corresponding to the address to be written can be concatenated; otherwise, it is determined that the data to be written and the cached write data corresponding to the address to be written cannot be concatenated.
[0025] It should be noted that if the data to be written and the cached write data corresponding to the address to be written have the same valid identifier for the same byte, then there is a conflict and data concatenation cannot be performed.
[0026] As one embodiment, step S5, concatenating the data to be written with the cached write data corresponding to the address to be written, includes: Step S51: Traverse the valid identifiers of each byte of the data to be written and the cached write data corresponding to the address to be written. For any byte, if only one side has a valid identifier, then set the data of that byte to the data of the side with the valid identifier. If both are invalid, then set the data of that byte to the data of either the data to be written or the cached write data corresponding to the address to be written.
[0027] It should be noted that if only one side has a valid identifier, it means that for any byte, only one of the data to be written and the cached write data corresponding to the address to be written has a valid identifier, while the other is invalid. In this case, the data corresponding to the side with the valid identifier is the data to be written, and the data of that byte is set to the data of the side with the valid identifier. If both are invalid, then the data to be written and the data in the cached write data corresponding to the address to be written are the same. Therefore, the data of that byte can be set to the data of either the data to be written or the data in the cached write data corresponding to the address to be written.
[0028] As one embodiment, step S5 further includes: Step S52: If the concatenated data is valid in every byte, proceed to step S53; otherwise, proceed to step S54.
[0029] Step S53: Output the concatenated data and the corresponding address to be written, perform the corresponding write access operation, delete the corresponding address to be written in the preset address buffer, delete the cached write data corresponding to the address to be written in the preset data buffer, and return to step S1.
[0030] Step S54: Write the concatenated data to the location of the cache write data corresponding to the address to be written in the preset data cache area, and return to step S1.
[0031] It is understandable that if the concatenated data is not entirely valid in every byte, it may still be concatenated with the data to be written in subsequent pending requests. Therefore, writing the concatenated data to the cache write data location corresponding to the address to be written in the preset data cache will overwrite the original data at that location.
[0032] It should be noted that steps S1-S7 are particularly applicable to application scenarios where all write access requests to be processed originate from the same user. Specifically, different users can be distinguished based on physical functions and virtual functions (VF) and physical functions (PF).
[0033] As an embodiment, the to-be-processed write access requests are all requests from the same user to access M write addresses, where M≥1. M address cache units are set in the preset address buffer, and each write address corresponds to one address cache unit. M data cache units are set in the preset data buffer, and each write address corresponds to one data cache unit. Each data cache unit can cache one write data. The area resources occupied by the preset address buffer and the preset data buffer are less than or equal to a preset area resource threshold. It can be understood that, if the area resources permit, one address cache unit can be set for each address. The step S7 includes: Step S71: Write the to-be-written address into the address buffer corresponding to the to-be-written address, and write the to-be-written data into the data cache unit corresponding to the to-be-written address.
[0034] As an embodiment, the to-be-processed write access requests are all requests from the same user to access M different write addresses, where M≥2. N address cache units are set in the preset address buffer, where N<M. Each address cache unit can store one write address. N data cache units are set in the preset data buffer, and each address cache unit corresponds to one data cache unit. The method further includes: Step S11: If the address cache units in the preset address buffer are full, send a backpressure signal to suspend obtaining the to-be-processed write access requests. When there are idle address cache units, resume obtaining the to-be-processed write access requests.
[0035] It should be noted that through step S11, it can be ensured that each to-be-processed write access request can be subjected to stitching judgment, increasing the possibility of stitching the to-be-written data and reducing the occurrence frequency of the write operation RMW behavior, thereby improving the write access efficiency of the system to the memory.
[0036] The step S7 includes: Step C71: Select a currently idle address cache unit in the preset address buffer as the to-be-written address cache unit.
[0037] Step C72: Write the to-be-written address into the to-be-written address cache unit, and write the to-be-written data into the data cache unit corresponding to the to-be-written address cache unit.
[0038] As an embodiment, the to-be-processed write access requests include write access requests from R users to access M different write addresses. R address cache modules are set in the preset address buffer, and each user corresponds to one address cache module. R data cache modules are set in the preset data buffer, and each user corresponds to one data cache module. The steps S1 - S7 are replaced with: Step G1: Obtain the address to be written, the data to be written, and the user identifier to be written corresponding to the write access request to be processed.
[0039] Step G2: Determine if there is a write address in the address cache module corresponding to the write user identifier in the preset address cache area. If there is, proceed to step G3; otherwise, proceed to step G7.
[0040] Step G3: Obtain the cached write data corresponding to the address to be written from the data cache module corresponding to the user identifier to be written.
[0041] Step G4: Determine whether the data to be written and the cached write data corresponding to the address to be written can be concatenated. If yes, proceed to step G5; otherwise, proceed to step G6.
[0042] Step G5: Concatenate the data to be written with the cached write data corresponding to the address to be written, and write the concatenation to the location of the cached write data corresponding to the address to be written in the data cache module, then return to step G1.
[0043] Step G6: Output the cached write data and the write address corresponding to the write address in the data cache module corresponding to the write user identifier, execute the corresponding write access operation, write the write data to the location of the cached write data corresponding to the write address in the data cache module corresponding to the write user identifier, and return to step G1.
[0044] Step G7: Write the address to be written to the address cache module corresponding to the user identifier to be written, write the data to be written to the data cache module corresponding to the user identifier to be written, and return to step G1.
[0045] As one embodiment, R≥2, M≥1, each address cache module is configured with M address cache units, each write address corresponds to one address cache unit in each address cache module, each data cache module is configured with M data cache units, each write address corresponds to one data cache unit, each data cache unit can cache one write data, and the area resources occupied by the preset address cache area and the preset data cache area are less than or equal to a preset area resource threshold; it can be understood that, if the area resources allow, one address cache unit can be set for each address in each address cache module.
[0046] Step G5 includes: Step G51: Concatenate the data to be written with the cached write data corresponding to the address to be written, and write the concatenation into the data cache unit corresponding to the address to be written in the data cache module, then return to step G1.
[0047] Step G6 includes: Step G61: Output the cache write data corresponding to the write address in the data cache module corresponding to the user identifier to be written and the write address, perform the corresponding write access operation, write the data to be written into the data cache unit corresponding to the write address in the data cache module corresponding to the user identifier to be written, and return to Step G1.
[0048] The said Step G7 includes: Step G71: Write the write address into the address cache unit corresponding to the write address in the address cache module corresponding to the user identifier to be written, and write the data to be written into the data cache unit corresponding to the write address in the data cache module corresponding to the user identifier to be written.
[0049] As an embodiment, R≥2, M≥2. N address cache units are set in each address cache module, N<M. Each address cache unit can store a write address. N data cache units are set in each data cache module. Each address cache unit corresponds to a data cache unit. The method further includes: Step G10: If the address cache units in the address cache module are full, send a backpressure signal based on the user identifier corresponding to this address cache module, pause obtaining the pending write access requests corresponding to the user identifier of this address cache module, and when there are idle address cache units in this address cache module, resume obtaining the pending write access requests corresponding to the user identifier of this address cache module.
[0050] The said Step G5 includes: Step H51: Concatenate the data to be written and the cache write data corresponding to the write address and write them into the data cache unit corresponding to the write address in the data cache module, and return to Step G1.
[0051] The said Step G6 includes: Step H61: Output the cache write data corresponding to the write address in the data cache module corresponding to the user identifier to be written and the write address, perform the corresponding write access operation, write the data to be written into the data cache unit corresponding to the write address in the data cache module corresponding to the user identifier to be written, and return to Step G1.
[0052] The said Step G7 includes: Step H71: Select a currently idle address cache unit from the address cache module corresponding to the user identifier to be written as the address cache unit to be written; Step H71: Write the write address into the address cache unit to be written, and write the data to be written into the data cache unit corresponding to the address cache unit to be written in the data cache module corresponding to the user identifier to be written.
[0053] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.
[0054] In this embodiment of the invention, before performing a memory write access, multiple consecutive write data entries destined for the same write address are concatenated as much as possible. If the concatenation is performed into a single valid data entry before the write access operation is executed, the write operation read-write (RMW) can be avoided. If the concatenation cannot be performed into a single valid data entry, the number of write operation read-write (RMW) occurrences can also be reduced, thereby improving the system's memory write access efficiency.
[0055] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A memory write access control method, characterized in that, include: Step S1: Obtain the address to be written and the data to be written corresponding to the write access request to be processed; Step S2: Determine whether there is an address to be written in the preset address cache. If it exists, proceed to step S3; otherwise, proceed to step S7. Step S3: Obtain the cached write data corresponding to the address to be written from the preset data cache area; Step S4: Determine whether the data to be written and the cached write data corresponding to the address to be written can be concatenated. If yes, proceed to step S5; otherwise, proceed to step S6. Step S5: Concatenate the data to be written with the cached write data corresponding to the address to be written and write it to the location of the cached write data corresponding to the address to be written in the preset data cache area, and return to step S1; Step S6: Output the cache write data corresponding to the address to be written and the address to be written, execute the corresponding write access operation, write the data to be written to the location of the cache write data corresponding to the address to be written in the preset data cache area, and return to step S1; Step S7: Write the address to be written to the preset address buffer, write the data to be written to the preset data buffer, and return to step S1.
2. The method according to claim 1, characterized in that, Also includes: Step S10: Open a timing window for each cached write data stored in the preset data cache area. If the cache exceeds the preset time threshold, output the cached write data and the corresponding cached write address from the preset address cache area and execute the corresponding write access operation.
3. The method according to claim 1 or 2, characterized in that, In step S4, determining whether the data to be written and the cached write data corresponding to the address to be written can be concatenated includes: Step S41: Obtain the valid identifier of each byte of the data to be written and the valid identifier of each byte of the cached write data corresponding to the address to be written. The valid identifier is either valid or invalid. Step S42: If each identical byte of the data to be written and the cached write data corresponding to the address to be written has only one valid identifier or all of them are invalid, then it is determined that the data to be written and the cached write data corresponding to the address to be written can be concatenated; otherwise, it is determined that the data to be written and the cached write data corresponding to the address to be written cannot be concatenated.
4. The method according to claim 1 or 2, characterized in that, In step S5, concatenating the data to be written with the cached write data corresponding to the address to be written includes: Step S51: Traverse the valid identifiers of each byte of the data to be written and the cached write data corresponding to the address to be written. For any byte, if only one side has a valid identifier, then set the data of that byte to the data of the side with the valid identifier. If both are invalid, then set the data of that byte to the data of either the data to be written or the cached write data corresponding to the address to be written.
5. The method according to claim 4, characterized in that, Step S5 further includes: Step S52: If the concatenated data is valid in every byte, then proceed to step S53; otherwise, proceed to step S54. Step S53: Output the spliced data and the corresponding write address to perform the corresponding write access operation, delete the corresponding write address in the preset address buffer, delete the cached write data corresponding to the write address in the preset data buffer, and return to execute Step S1; Step S54: Write the spliced data to the position where the cached write data corresponding to the write address in the preset data buffer is located, and return to Step S1.
6. The method according to claim 1 or 2, wherein the pending write access requests are all requests from the same user to access M write addresses, M≥1, M address cache units are set in the preset address buffer, each write address corresponds to an address cache unit, M data cache units are set in the preset data buffer, each write address corresponds to a data cache unit, each data cache unit can cache a write data, and the area resources occupied by the preset address buffer and the preset data buffer are less than or equal to a preset area resource threshold. The step S7 includes: Step S71: Write the write address to the address cache area corresponding to the write address, and write the write data to the data cache unit corresponding to the write address.
7. The method according to claim 1 or 2, wherein the pending write access requests are all requests from the same user to access M different write addresses, M≥2, N address cache units are set in the preset address buffer, N<M, each address cache unit can store a write address, N data cache units are set in the preset data buffer, each address cache unit corresponds to a data cache unit, and the method further includes: Step S11: If the address cache units in the preset address buffer are full, send a backpressure signal to suspend obtaining the pending write access requests, and when there are idle address cache units, restart obtaining the pending write access requests; The step S7 includes: Step C71: Select a currently idle address cache unit in the preset address buffer as the write address cache unit to be written; Step C72: Write the write address to the write address cache unit to be written, and write the write data to the data cache unit corresponding to the write address cache unit to be written.
8. The method according to claim 1 or 2, wherein the pending write access requests include write access requests from R users to access M different write addresses. R address cache modules are set in the preset address buffer, each user corresponds to an address cache module, R data cache modules are set in the preset data buffer, each user corresponds to a data cache module, and Steps S1 - S7 are replaced with: Step G1: Obtain the write address, write data, and write user identifier corresponding to the pending write access request; Step G2: Determine whether there is a write address in the address cache module corresponding to the write user identifier in the preset address buffer. If so, execute Step G3; otherwise, execute Step G7; Step G3: Obtain the cached write data corresponding to the write address from the data cache module corresponding to the write user identifier; Step G4: Determine whether the data to be written can be concatenated with the cached write data corresponding to the write address. If so, execute Step G5; otherwise, execute Step G6. Step G5: Concatenate the data to be written with the cached write data corresponding to the write address, and write the result to the location of the cached write data corresponding to the write address in the data cache module, then return to Step G1. Step G6: Output the cached write data corresponding to the write address in the data cache module corresponding to the user ID to be written and the write address, perform the corresponding write access operation, and write the data to be written to the location of the cached write data corresponding to the write address in the data cache module corresponding to the user ID to be written, then return to Step G1. Step G7: Write the write address to the address cache module corresponding to the user ID to be written, and write the data to be written to the data cache module corresponding to the user ID to be written, then return to Step G1.
9. The method according to claim 8, wherein R≥2, M≥1. Each address cache module is provided with M address cache units. Each write address corresponds to one address cache unit in each address cache module. Each data cache module is provided with M data cache units. Each write address corresponds to one data cache unit. Each data cache unit can cache one write data. The area resources occupied by the preset address cache area and the preset data cache area are less than or equal to the preset area resource threshold. The said Step G7 includes: Step G71: Write the write address to the address cache unit corresponding to the write address in the address cache module corresponding to the user ID to be written, and write the data to be written to the data cache unit corresponding to the write address in the data cache module corresponding to the user ID to be written.
10. The method according to claim 8, wherein R≥2, M≥2. Each address cache module is provided with N address cache units, where N<M. Each address cache unit can store one write address. Each data cache module is provided with N data cache units. Each address cache unit corresponds to one data cache unit. The method further includes: Step G10: If there is an address cache unit in the address cache module that is full, send a backpressure signal based on the user ID corresponding to the address cache module, and pause obtaining the pending write access requests corresponding to the user ID of the address cache module. When there is an idle address cache unit in the address cache module, resume obtaining the pending write access requests corresponding to the user ID of the address cache module. The said Step G7 includes: Step H71: Select a currently idle address cache unit from the address cache module corresponding to the user ID to be written as the address cache unit to be written. Step H71: Write the write address to the address cache unit to be written, and write the data to be written to the data cache unit corresponding to the address cache unit to be written in the data cache module corresponding to the user ID to be written.