Managing parity data in a storage system

Abstract

Methods, apparatus, and systems for managing parity data generation are provided. In one aspect, a storage system includes a storage device and a memory controller coupled to the storage device. The storage device includes memory blocks programmable in a first storage mode or a second storage mode, wherein the first storage mode has a lower storage density compared to the second storage mode. The memory controller is configured to perform operations including: generating parity data corresponding to user data based on the second storage mode; writing the user data and parity data to a first set of memory blocks in the first storage mode; and writing the user data and parity data read from the first set of memory blocks to a second set of memory blocks in the second storage mode.

Description

Technical Field

[0001] This disclosure generally relates to memory devices and memory systems, and in particular, to the management of parity data in memory systems. Background Technology

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations (e.g., programming (writing) and erasing operations) can be performed on flash memory to change the threshold voltage of each memory cell to a corresponding level. For NAND flash memory, erasing operations can be performed at the block level, programming operations can be performed at the page level, and reading operations can be performed at the page level. Summary of the Invention

[0003] This disclosure relates to methods, apparatus, and systems for managing parity data in a storage system. One aspect of this disclosure features a storage system including a storage device and a memory controller coupled to the storage device. The storage device includes memory blocks programmable in a first storage mode or a second storage mode, wherein the first storage mode has a lower storage density compared to the second storage mode. The memory controller is configured to perform operations including: generating parity data corresponding to user data based on the second storage mode; writing the user data and parity data to a first set of memory blocks in the first storage mode; and writing the user data and parity data read from the first set of memory blocks to a second set of memory blocks in the second storage mode.

[0004] In some implementations, the first storage mode is a single-level cell (SLC) mode, where storage cells in the first group of storage blocks store one bit of data. The second storage mode is a multi-level cell (MLC) mode, where storage cells in the second group of storage blocks store two or more bits of data. Parity data includes Redundant Array of Independent Disks (RAID) parity data.

[0005] In some implementations, the second storage mode is a quad-level cell (QLC) mode. The parity data consists of N parity data portions. Each parity data portion is generated by performing an exclusive OR (XOR) operation on the M user data portions in the first set of storage blocks. Each of the M user data portions corresponds to one of the M word lines, where N and M are positive integers. The M word lines are spaced three word lines apart.

[0006] In some implementations, the second storage mode is a five-level cell (PLC) mode. The parity data consists of N parity data portions. Each parity data portion is generated by performing an XOR operation on M user data portions in the first set of storage blocks. Each of the M user data portions corresponds to one word line out of the M word lines, where N and M are positive integers. The M word lines are spaced four word lines apart.

[0007] In some implementations, the independent redundant array of disks (RAID) encoder of the memory controller is disabled when user data and parity data are written to the second set of storage blocks.

[0008] In some implementations, data in the first set of storage blocks is associated with sequentially numbered first set of pages, and data in the second set of storage blocks is associated with sequentially numbered second set of pages. Writing user data and parity data read from the first set of storage blocks to the second set of storage blocks includes: reading data associated with one or more first pages in the first set of pages; and writing the data to one or more second pages in the second set of pages. The number of pages in the one or more first pages and the number of pages in the one or more second pages are the same.

[0009] In some implementations, the first position of the parity data relative to the user data in the first set of storage blocks is the same as the second position of the parity data relative to the user data in the second set of storage blocks.

[0010] In some implementations, the memory controller is configured to perform operations in response to a write command received from the host to write user data.

[0011] In some implementations, the operation includes: in response to detecting a write failure while writing user data and parity data to the second set of storage blocks, reading user data and parity data from the first set of storage blocks again.

[0012] In some implementations, the operation includes: in response to detecting a read failure while reading user data from the second set of storage blocks, recovering the user data using parity data from the second set of storage blocks.

[0013] Another aspect of this disclosure is a memory controller. The memory controller includes a processor and an interface. The processor is configured to perform operations including: generating parity data corresponding to user data based on a second memory mode having a higher storage density compared to a first memory mode; sending one or more first write commands through the interface to write the user data and parity data to a first set of storage blocks in the first memory mode; sending one or more read commands through the interface to read the user data and parity data from the first set of storage blocks; and sending one or more second write commands through the interface to write the user data and parity data to a second set of storage blocks in the second memory mode.

[0014] In some implementations, the independent redundant array of disks (RAID) encoder of the memory controller is disabled when user data and parity data are written to the second set of storage blocks.

[0015] In some implementations, the first storage mode is a single-level cell (SLC) mode, where storage cells in the first set of storage blocks store one bit of data. The second storage mode is a multi-level cell (MLC) mode, where storage cells in the second set of storage blocks store two or more bits of data. Parity data includes Redundant Array of Independent Disks (RAID) parity data.

[0016] In some implementations, the second storage mode is QLC mode. The parity data consists of N parity data portions. Each parity data portion is generated by performing an XOR operation on M user data portions in the first set of storage blocks. Each of the M user data portions corresponds to one of the M word lines, where N and M are positive integers. The M word lines are spaced three word lines apart.

[0017] In some implementations, the second storage mode is a five-level cell (PLC) mode. The parity data consists of N parity data portions. Each parity data portion is generated by performing an XOR operation on M user data portions in the first set of storage blocks. Each of the M user data portions corresponds to one word line out of the M word lines, where N and M are positive integers. The M word lines are spaced four word lines apart.

[0018] In some implementations, the operation includes: in response to detecting a write failure while writing user data and parity data to the second set of storage blocks, reading user data and parity data from the first set of storage blocks again.

[0019] In some implementations, the operation includes: in response to detecting a read failure while reading user data from the second set of storage blocks, recovering the user data using parity data from the second set of storage blocks.

[0020] Another aspect of this disclosure is a method for operating a storage system. The method includes: generating parity data corresponding to user data based on a second storage mode having a higher storage density compared to a first storage mode; writing the user data and parity data to a first set of storage blocks in the first storage mode; and writing the user data and parity data read from the first set of storage blocks to a second set of storage blocks in the second storage mode.

[0021] In some implementations, the method further includes: in response to detecting a write failure while writing user data and parity data to the second set of storage blocks, reading user data and parity data from the first set of storage blocks again.

[0022] In some implementations, the method further includes: in response to detecting a read failure while reading user data from the second set of storage blocks, using parity data from the second set of storage blocks to recover the user data.

[0023] Another aspect of this disclosure is a non-transitory computer-readable medium. The non-transitory computer-readable medium stores one or more instructions executable by a storage system to perform operations including: generating parity data corresponding to user data based on a second storage mode having a higher storage density than a first storage mode; writing the user data and parity data to a first set of storage blocks in the first storage mode; and writing the user data and parity data read from the first set of storage blocks to a second set of storage blocks in the second storage mode.

[0024] While generally described as computer-implemented software embodied on a tangible medium for processing and transforming corresponding data, some or all of these aspects may be computer-implemented methods or further included in a corresponding system or other device for performing the functions described. Details of these and other aspects and implementations of this disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of this disclosure will be apparent from the specification, drawings, and claims. Attached Figure Description

[0025] Figure 1 A block diagram of an example system with storage devices is shown.

[0026] Figures 2A-2B An example storage product is shown.

[0027] Figure 3AAn example of a schematic diagram of a storage device including peripheral circuitry is shown.

[0028] Figure 3B An example of a schematic diagram of a storage block including strings is shown.

[0029] Figure 4 Some example peripheral circuits are shown.

[0030] Figure 5 An example block diagram of a sample memory controller that interacts with the host and storage devices is shown.

[0031] Figure 6A An example data structure in an example storage device is shown.

[0032] Figure 6B This demonstrates writing data to, for example... Figure 6A Example procedures for example storage devices are shown.

[0033] Figure 7A An example data structure in an example storage device is shown.

[0034] Figure 7B This demonstrates writing data to, for example... Figure 7A Example procedures for example storage devices are shown.

[0035] Figure 7C This demonstrates writing data to, for example... Figure 7A Another example process for the example storage device shown.

[0036] Figure 8 A flowchart illustrating an example process for operating a storage system is shown.

[0037] In the various figures, the same reference numerals and designations indicate the same elements. Detailed Implementation

[0038] This specification relates to memory controllers, storage systems, and methods for managing parity data in storage systems. Redundant Array of Independent Disks (RAID) parity data can be used to recover data in the event of read failures (e.g., due to a word line failure). Storage systems can generate RAID parity data by performing an exclusive OR (XOR) operation on portions of the data across one or more word lines.

[0039] The storage devices of a storage system can be configured to operate in multi-level cell (MLC) mode (e.g., quad-level cell (QLC) mode). In some cases, to increase the speed of write operations, the storage system can first perform cache writes by writing data to storage blocks configured in single-level cell (SLC) mode, and then move data from SLC mode storage blocks to MLC mode storage blocks by writing data read from SLC mode storage blocks to MLC mode storage blocks. For example, when the MLC mode is QLC mode, during cache writes, the storage system can generate first RAID parity data by implementing a 2WL redundant disk array (RAID) scheme and write the first RAID parity data to an SLC mode storage block. When moving data from an SLC mode storage block to a QLC mode storage block, the storage system can generate second RAID parity data by implementing a 1WL RAID scheme and write the second RAID parity data to a QLC mode storage block. A large buffer space in the memory controller may be required to store the intermediate results used to generate the first and second RAID parity data. The required buffer space may sometimes exceed the storage capacity provided by the memory controller's random-access memory (RAM) (e.g., parity buffer), or even exceed the storage capacity of the entire RAM. In such cases, the memory controller may need to perform swapping operations by sending intermediate results to storage devices for temporary storage and retrieving them when needed, which can impact the overall efficiency of write operations.

[0040] In some cases, when moving data from an SLC-mode storage block to an MLC-mode storage block, instead of generating a second RAID parity data, the memory controller can perform read verification on the data written to the MLC-mode storage block (e.g., by decoding the corresponding low-density parity check (LDPC) code) to determine if the data can be successfully read. This may require additional time to perform the read verification, potentially impacting the overall performance of the storage system.

[0041] This disclosure provides techniques for generating RAID parity data while reducing the need for buffer space. In some implementations, during cache writes, the storage system can generate RAID parity data by implementing a RAID scheme compatible with MLC mode (e.g., QLC mode). For example, when writing data to an SLC mode storage block, the storage system can implement a 4WL RAID scheme such that the generated RAID parity data is the same as when writing data to a QLC mode storage block and generating the corresponding RAID parity data by implementing a 1WL RAID scheme. Therefore, when moving data from an SLC mode storage block to a QLC mode storage block, the storage system can read the data and RAID parity data from the SLC mode storage block and write them directly to the QLC mode storage block without needing to generate RAID parity data again.

[0042] The described techniques can achieve one or more technical effects. For example, since the storage system does not need to generate RAID parity data when moving data to storage blocks in MLC mode (e.g., QLC mode), the need for buffer space can be reduced, and the speed of write operations can be increased. As another example, since MLC mode storage blocks also include RAID parity data, the storage system does not need to perform read verification on data stored in MLC mode storage blocks. Furthermore, the described techniques can generate RAID parity data that is valid for both SLC mode and MLC mode storage blocks. For example, RAID parity data can be used to recover data in the event of a programming failure in an SLC mode storage block, and / or to recover data in the event of a read failure in an MLC mode storage block. In some implementations, additional or different technical effects can be achieved.

[0043] The technology can be applied to various types of semiconductor devices, such as non-volatile memory (NVM) devices (e.g., NAND flash memory or NOR flash memory), volatile memory devices (e.g., DRAM), resistive random-access memory (RRAM), phase-change memory (PCM) (e.g., PCRAM), spin-transfer torque (STT)-magnetoresistive random-access memory (MRAM), etc. The technology can also be applied to charge-trapping based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate based memory devices. The technology can also be applied to three-dimensional (3D) memory devices. The technology can be applied to various memory types, such as memory devices configured to operate in a single-level cell (SLC) mode where one bit can be stored per cell, or in a multi-level cell (MLC) mode where two or more bits can be stored per cell. For example, a memory device configured to operate in MLC mode can store two bits per cell, three bits per cell (also known as triple-level cell (TLC) mode), four bits per cell (also known as quad-level cell (QLC) mode), or five bits per cell (also known as five-level cell (PLC) mode). Additionally or alternatively, the technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC), universal flash storage (UFS), solid-state drives (SSDs), embedded systems, etc.

[0044] Figure 1A block diagram of an example system 100 having storage devices according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a storage system 102 having one or more storage devices 104 and a memory controller 106. The host 108 may include one or more processors of an electronic device. The processor may be a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The host 108 may be configured to send data and commands to or receive data and commands from the storage system 102.

[0045] Storage device 104 can be any storage device disclosed herein, such as a NAND flash memory device. Note that, for illustrative purposes, NAND flash memory is merely one example of a storage device. It can include any suitable solid-state non-volatile memory, such as NOR flash memory, ferroelectric RAM (Fe RAM), phase-change memory (PCM), magnetoresistive random-access memory (MRAM), spin-transfertorque magnetic random-access memory (STT-RAM), or resistive random-access memory (RRAM), etc. In some implementations, storage device 104 includes a three-dimensional (3D) NAND flash memory device.

[0046] The memory controller 106 may be executed by a microprocessor, a microcontroller unit (MCU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gated logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform the various functions described in detail below.

[0047] According to some implementations, memory controller 106 is coupled to storage device 104 and host 108 and configured to control storage device 104. Memory controller 106 can manage data stored in storage device 104 and can communicate with host 108. In some implementations, memory controller 106 is designed to operate in low duty cycle environments such as Secure Digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller 106 is designed to operate in high duty cycle environments such as solid-state drives (SSDs) or embedded multi-media cards (eMMCs) used for data storage in mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. Memory controller 106 can be configured to control the operation of storage device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the storage device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, logical-to-physical mapping management, wear leveling, etc. In some implementations, the memory controller 106 is also configured to handle error correction codes (ECCs) relating to data read from or written to the storage device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the storage device 104.

[0048] The memory controller 106 can communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnection (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc. The memory controller 106 is configured to receive and send commands to host 108, and to execute or perform various functions and operations provided in this disclosure, which will be described later.

[0049] The memory controller 106 and one or more storage devices 104 can be integrated into various types of storage devices. For example, the memory controller 106 and one or more storage devices 104 can be packaged in a universal flash memory (UFS) package or an eMMC package. Figure 2A In one example shown, the memory controller 106 and a single storage device 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association, PCMCIA), a CF card, a smart media (SM) card, a Memory Stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108. In such a way... Figure 2B In another example shown, the memory controller 106 and multiple storage devices 104 can be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1The SSD connector 208 is coupled to the host 108. In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0050] Figure 3A An example of a schematic circuit diagram of a memory device 300 according to some aspects of this disclosure is shown. The memory device 300 may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. The memory array 301 may be a NAND flash memory array including NAND memory cells 306 arranged in rows and columns. In some implementations, the memory cells 306 in the columns (e.g., along the z-direction) of the memory array 301 are series-coupled and vertically stacked. The memory cells 306 in the rows (e.g., along the x-direction) of the memory array 301 are coupled to and controlled by word lines 318. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge depending on the number of electrons trapped within the storage layer of the memory cell 306. The logic state (i.e., data) of each memory cell 306 may be determined based on a threshold voltage Vth of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0051] In some implementations, storage device 300 can be configured to operate in single-cell (SLC) mode. To increase storage density, storage device 300 can also be configured to operate in multi-cell (MLC) mode, where more than one bit can be stored per cell. MLC mode can include three-cell (TLC), four-cell (QLC), five-cell (PLC), or any combination thereof. In SLC mode, storage cell 306 stores one bit and has two logical states: logic {1 and 0}, i.e., states ER and S1. In MLC mode, storage cell 306 stores two bits and has four logical states: logic {11, 10, 01, and 00}, i.e., states ER, M1, M2, and M3. In TLC mode, storage unit 306 stores 3 bits and has eight logic states: {111, 110, 101, 100, 011, 010, 001, 000}, i.e., state ER and states T1-T7. In QLC mode, storage unit 306 stores 4 bits and has 16 logic states: {1111, 1110, 1101, 1100, 1011, 1010, 1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001, 0000}, i.e., state ER and states Q1-Q15. In PLC mode, storage unit 306 stores 5 bits and has 32 logic states: state ER and states Q1-Q31.

[0052] like Figure 3AAs shown, memory cells 306 in a column of memory array 301 can be coupled at their source terminals to a source select gate (SSG) transistor 310 and at their drain terminals to a drain select gate (DSG) transistor 312. The SSG transistor 310 and DSG transistor 312 can be configured to activate selected columns of memory array 301 during read and program operations. In some implementations, the sources of SSG transistors in the same memory block are coupled via the same source line 314 (also known as the common source line (CSL)). The drain of each DSG transistor is coupled to a corresponding bit line 316. From the bit line 316, data can be read from or written to memory cells in a column of memory array 301. In some implementations, each column of the memory array 301 is configured to be selected or deselected by applying a DSG select voltage or a DSG deselect voltage to the gate of the corresponding DSG transistor 312 via one or more DSG lines 313 and / or by applying a select voltage or a deselect voltage to the gate of the corresponding SSG transistor 310 via one or more SSG lines 315.

[0053] In some implementations, memory cells 306 in adjacent columns can be coupled via word lines 318. Word lines 318 can select which row of memory cells 306 is affected by read and program operations. In SLC mode, a row of memory cells 306 (e.g., memory cells in string 334 coupled to the same word line 318) can store one logical data page and therefore corresponds to one logical page. In MLC mode, a row of memory cells 306 can store two logical data pages and therefore corresponds to two logical pages (e.g., next page and previous page). In TLC mode, a row of memory cells 306 can store three logical data pages and therefore corresponds to three logical pages (e.g., next page, middle page, and previous page). In QLC mode, a row of memory cells 306 can store four logical data pages and therefore corresponds to four logical pages (e.g., next page, middle page, previous page, and extra page). In PLC mode, a row of memory cells 306 can store five logical data pages and therefore corresponds to five logical pages.

[0054] In some implementations, the storage array 301 may include multiple storage blocks (e.g., such as...). Figure 3B The storage block 304 shown can be used, and each storage block can include multiple strings 334. Figure 3AAs shown, each string 334 may include memory cells 306 arranged in rows (e.g., coupled to word lines along the X direction) and columns (e.g., connected in series along the Z direction). Different strings 334 in the same memory block are coupled together to the same source line 314. The DSG lines 313 of different strings 334 are spaced apart from each other, such that each string 334 in the memory block can be selected or deselected by applying a selection voltage or a non-selection voltage to the corresponding DSG line 313.

[0055] Peripheral circuitry 302 can be coupled to memory array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of memory array 301.

[0056] Figure 3B An example schematic diagram of a memory block 304 comprising a string 334 is shown according to some aspects of this disclosure. In some implementations, each memory block 304 may serve as a basic data unit for an erase operation, such that memory cells 306 in the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage may be used to bias the source line 314 coupled to the selected memory block 304. For example, the erase voltage may be a high positive voltage (e.g., 20V or higher). In some implementations, the erase operation may be performed at a half-block level, a quarter-block level, or a level with any suitable number of memory blocks or a fraction of memory blocks.

[0057] In some implementations, storage blocks 304 in storage device 300 can be configured to operate in different storage modes. For example, in the storage device, one or more storage blocks are configured to operate in SLC mode, and one or more storage blocks are configured to operate in MLC mode (e.g., QLC mode or PLC mode). When data is written to the storage device, the storage device can first write the data to the storage blocks in SLC mode (e.g., cache write), which can reduce programming time and save buffer space. Then, the storage device can read data from the storage blocks in SLC mode and then write the data to the storage blocks in MLC mode, so that the data can be stored in the storage blocks in MLC mode.

[0058] Storage block 304 may include multiple strings 334. In some implementations, storage block 304 may be divided into storage fingers 344. Each storage finger 344 may include one or more strings 334. The SSG transistors 310 of the strings 334 in the same storage finger 344 are coupled to the same SSG line 315. For example, the SSG transistors 310 of the strings 334 of the first storage finger 344a are coupled to a first SSG line represented by SSG0; the SSG transistors 310 of the strings 334 of the second storage finger 344b are coupled to a second SSG line represented by SSG1.

[0059] In some implementations, the DSG transistors 312 in different strings 334 are coupled to different DSG lines 313. For example, the DSG transistors 312 in the first string in the memory block 304 are coupled to the first DSG line represented by DSG0; the DSG transistors 312 in the second string in the memory block 304 are coupled to the second DSG line represented by DSG1; the DSG transistors 312 in the third string in the memory block 304 are coupled to the third DSG line represented by DSG2; and the DSG transistors 312 in the fourth string in the memory block 304 are coupled to the fourth DSG line represented by DSG3.

[0060] In some implementations, memory cells at the same vertical position (e.g., along the z-direction) in all strings 334 of memory block 304 are coupled to the same word line. That is, the word line can be coupled to a row of memory cells in each string 334 of memory block 304.

[0061] In some implementations, memory block 304 may include a different number of memory fingers 344, and each memory finger 344 may include a different number of strings 334. In some implementations, strings 334 are not arranged as memory fingers 344, such that the SSG transistors of all strings 334 of memory block 304 are coupled to the same SSG line.

[0062] Figure 4Examples of peripheral circuitry 302 according to some aspects of this disclosure are shown. Peripheral circuitry 302 can be coupled to memory array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. Example peripheral circuitry 302 includes a page buffer / sensor amplifier 404, a column decoder / bit line driver 406, a row decoder / word line driver 408, a voltage generator 410, control logic 412, a register 414, an interface 416, and a data bus. In some examples, it may also include... Figure 4 Additional peripheral circuitry not shown.

[0063] Page buffer / sensor amplifier 404 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic 412. In one example, page buffer / sensor amplifier 404 can store one page of programmed data (written data) in memory array 301. In another example, page buffer / sensor amplifier 404 can perform a programming verification operation to ensure that data has been properly programmed into memory cell 306 coupled to selected word line 418. In yet another example, page buffer / sensor amplifier 404 can also sense a low-power signal from bit line 316 representing data bits stored in memory cell 306 and amplify small voltage swings to a recognizable logic level during read operations. Column decoder / bit line driver 406 can be configured to be controlled by control logic 412 and select one or more columns of memory cells by applying a bit line voltage generated from voltage generator 410.

[0064] The row decoder / word line driver 408 can be configured to be controlled by control logic 412 and to select / deselect memory blocks of memory array 301 and select / deselect word lines 418 of memory blocks. The row decoder / word line driver 408 can also be configured to drive word lines 418 using word line voltages generated from voltage generator 410. In some implementations, the row decoder / word line driver 408 can also select / deselect and drive SSG lines 315 and DSG lines 313. As described in detail below, the row decoder / word line driver 408 is configured to apply a programming voltage to the selected word line 418 during programming operations on memory cells 306 coupled to the selected word line 418.

[0065] Voltage generator 410 can be configured to be controlled by control logic 412 and generate word line voltages (e.g., read voltage, programming voltage, turn-on voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0066] Control logic 412 can be coupled to each of the aforementioned peripheral circuits and configured to control the operation of each peripheral circuit. Register 414 can be coupled to control logic 412 and includes a status register, a command register, and an address register for storing status information, command opcode (OP code), and command address for controlling the operation of each peripheral circuit.

[0067] Interface 416 can be coupled to control logic 412 and used as a control buffer to buffer and relay control commands received from the host (not shown) to control logic 412, and to buffer and relay status information received from control logic 412 to the host. Interface 416 can also be coupled to column decoder / bit line driver 406 via a data bus and used as a data input / output (I / O) interface and data buffer to buffer and relay data to and from memory array 301.

[0068] Figure 5 An example block diagram of a memory controller 106 interacting with host 108 and storage device 104 according to some aspects of this disclosure is shown.

[0069] The memory controller 106 may include a front interface 502, one or more processors 503, random access memory (RAM) 506, and a rear interface 510. RAM 506 may include one or more parity buffers 508. The memory controller 106 may include error correction code (ECC) circuitry 512, garbage collection (GC) circuitry 514, and redundant array of independent disks (RAID) circuitry 516. In some examples, the memory controller 106 may also include... Figure 5 Additional components not shown.

[0070] The front interface 502 can be configured to handle communication between the host 108 and the memory controller 106. In some implementations, the front interface 502 can communicate with the host 108 according to a specific communication protocol. For example, the front interface 502 can communicate with the host 108 through at least one of various interface protocols, such as USB, MMC, PCI, PCI-E, ATA, Serial ATA, Parallel ATA, SCSI, ESDI, IDE, FireWire, etc. In some implementations, the front interface 502 can receive requests from the host 108 and forward them to the rear interface 510, allowing the rear interface 510 to fulfill the requests. Examples of requests may include, but are not limited to, read requests to read data stored in a memory block of the storage device 104, erase requests to erase data in a memory block, write requests to write new data to a memory block, reformat requests to reformat the storage device 104, or any other suitable request. In some implementations, the front interface 502 can receive data from the rear interface 510 and send data to the host 108.

[0071] The rear interface 510 can be configured to fulfill requests from the host 108. In some implementations, the rear interface 510 can receive requests from the host 108 via the front interface 502 and perform one or more operations to fulfill the requests. For example, the rear interface 510 can be configured to control the operation of the storage device 104 (e.g., read, erase, or program operations) in response to receiving a request (e.g., a read request, erase request, or program request) from the host 108. The rear interface 510 can also be configured to manage various functions regarding the storage or data to be stored in the storage device 104, including but not limited to bad block management, error correction, wear leveling, garbage collection, RAID parity, etc.

[0072] ECC circuit 512 is configured to process error correction codes regarding data read from or written to storage device 104. Example error correction codes may include, but are not limited to, Hamming codes, Reed-Solomon codes, low-density parity-check (LDPC) codes, etc. In some implementations, ECC circuit 512 includes an LPDC encoder configured to generate parity data based on the LDPC code of user data received from host 108, such that both user data and parity data can be sent to storage device 104 for storage. ECC circuit 512 may also include an LDPC decoder configured to decode the data including user data and parity data. The ECC circuit can determine whether the data stored in the block has been successfully read (e.g., without errors). If the data stored in the block has been successfully read, the back interface 510 can forward the data to the front interface 502, allowing the front interface 502 to return the data to host 108. However, if the data stored in the storage block has not been successfully read, the back interface 510 can generate data describing read errors on the storage block.

[0073] GC circuit 514 can be configured to migrate data from a source storage block to a target storage block, such that the source storage block can be erased to make it available for writing new data. For example, GC circuit 514 can be configured to select a source and a target storage block in storage device 104, read valid data from the source storage block by sending a read command to storage device 104, write valid data to the target storage block by sending a write command to storage device 104, and then erase the source storage block. In some implementations, GC circuit 514 can be configured to perform foreground garbage collection on storage device 104, wherein garbage collection is performed when there are not enough storage blocks available for writing new data. In some implementations, GC circuit 514 can be configured to perform background garbage collection on storage device 104, wherein garbage collection is performed when the storage device is idle (e.g., when there are no pending commands to be executed by the storage device).

[0074] RAID circuitry 516 can be configured as a RAID encoder and / or a RAID decoder. RAID circuitry 516 (e.g., a RAID encoder) can be configured to generate RAID parity data by performing an encoding operation on data to be written to storage device 104, such that the data and the corresponding RAID parity data can be written to the storage device for storage. In the event of data failure, RAID circuitry 516 (e.g., a RAID decoder) can be configured to recover damaged data portions by performing a decoding operation on the undamaged data portions and the corresponding RAID parity data. Storage device 104 can be managed under a RAID scheme that employs striping, mirroring, and / or parity techniques to create large, reliable data storage across multiple storage units. In some implementations, storage device 104 may include one or more dies, each die comprising multiple planes. Each plane comprises multiple storage blocks. Each storage block can store data in multiple pages (e.g., logical pages). Pages located at the same position across different planes in at least one die (e.g., associated with word lines of the same number and included in strings of the same number) can form page lines. The RAID circuit 516 can perform an XOR operation between data in one or more page lines to generate corresponding RAID parity data.

[0075] In some implementations, page lines 602 can be grouped into multiple rounds. The RAID circuitry 516 can perform a separate encoding operation on each page line within the same round, ensuring that no two page lines in the same round share the same RAID parity data. Furthermore, one or more rounds can form a fund. After encoding the page lines included in the fund to generate corresponding RAID parity data, the corresponding RAID parity data can be written to the last round of the fund, for example, to the last page of each page line included in the last round of the fund. In some implementations, the number of page lines 602 included in a round can be set according to the RAID scheme implemented by the memory controller. For example, in a 1WL RAID scheme, the number of page lines included in a round can be the same as the number of page lines associated with one word line; in a 2WL RAID scheme, the number of page lines included in a round can be the same as the number of page lines associated with two word lines. Furthermore, the number of rounds included in the fund can be set according to the ratio of RAID parity to user data in the storage device. For example, under the same RAID scheme, if more rounds are included in the reserve, the ratio of RAID parity to user data is greater.

[0076] As Figure 6A and Figure 7AIn the example shown, the storage device includes two dies, DIE0 and DIE1. Each die includes eight planes, PL0-PL7. Each plane includes multiple memory blocks. Thus, each page line 602, 702 includes 16 pages located at the same position across 16 planes. Each memory block includes pages associated with multiple word lines (e.g., WL0-WLn). The number of pages associated with a word line depends on the storage mode of the memory block and the number of strings included in the memory block (e.g., string 334 in Figure 3). For example, memory blocks 600, 700 are configured to operate in SLC mode and each memory block 600, 700 includes eight strings, such that each word line is associated with eight page lines 602, 702 (one page line from each string). For example, WL0 is associated with page lines 0-7, WL1 is associated with page lines 8-15, and so on. In another example, storage blocks 620 and 720 are configured to operate in QLC mode, and each storage block 620 and 720 includes 8 strings, such that each word line is associated with 32 page lines 602 and 702 (from the four page lines of each string: the next page line, the middle page line, the previous page line, and the additional page line). For example, WL0 is associated with page lines 0-31, WL1 is associated with page lines 32-63, and so on.

[0077] It should be noted that the storage device may include any other suitable number of dies and other suitable number of planes, and each page line may include any other suitable number of pages.

[0078] Return to reference Figure 5 One or more processors 503 are configured to control the operation of the memory controller 106. One or more processors 503 are configured to control read operations, program operations, erase operations, or other operations of the memory device 104.

[0079] RAM 506 is configured to serve as operating memory for one or more processors 503, cache memory between storage device 104 and host 108, and / or buffer memory between storage device 104 and host 108. In some implementations, RAM 506 may be Static Random-Access Memory (SRAM). RAM 506 may include one or more parity buffers 508 configured to store RAID parity data and / or intermediate results of XOR operations used to generate RAID parity data. In some implementations, RAM 506 may also include one or more read buffers configured to temporarily store data read from storage device 104, one or more copy buffers configured to temporarily store data to be written to storage device 104, etc.

[0080] In some implementations, each parity buffer 508 may have a limited storage space (e.g., 320KB). If the RAID parity data and / or intermediate results exceed the storage space of the parity buffer 508, the memory controller 106 may use other buffers in RAM 506 (e.g., read buffers and copy buffers) to store the RAID parity data and / or intermediate results. If the RAID parity data and / or intermediate results exceed the available buffer space in RAM 506, the memory controller 106 may perform a swapping operation, for example, sending the RAID parity data and / or intermediate results from the parity buffer 508 to storage device 104 for temporary storage, and retrieving the RAID parity data and / or intermediate results from storage device 104 when needed.

[0081] Figure 6A Storage devices (e.g., according to some aspects of this disclosure) are shown. Figures 1-2B and Figure 5 Storage device 104, Figure 3A Example data structure of storage device 300. Figure 6B This demonstrates writing data to, for example... Figure 6A Example process 650 of the storage device is shown. The storage device may include a storage block 600 programmable in a storage mode with lower storage density (e.g., SLC mode) and a storage block 620 programmable in a storage mode with higher storage density (e.g., MLC mode, such as QLC mode or PLC mode). In the following description, storage block 600 in SLC mode and storage block 620 in QLC mode are used as examples.

[0082] At 652, the host (e.g., Figure 1 and Figure 5 The host (108) sends user data to the memory controller. The host can also send one or more write commands instructing the memory controller (e.g., ...) to write user data to the memory device. Figures 1-2B and Figure 5 (Memory controller 106). In response to receiving user data, the memory controller may first perform a cache write by writing the user data to a storage block 600 in SLC mode. Then, the memory controller may write the user data to a storage block in a storage mode with higher storage density (e.g., a storage block 620 in QLC mode).

[0083] At position 654, the memory controller generates first RAID parity data 604a and 604b (collectively referred to as 604) corresponding to the user data based on SLC mode. In some implementations, the RAID circuitry (e.g., Figure 5The RAID circuit 516 can implement a 1WL protection scheme, such that each round includes a page line 602 associated with a word line. In some implementations, such as Figure 6A As shown, the RAID circuitry of the memory controller can implement a 2WL RAID scheme, such that each round includes page lines 602 associated with two adjacent word lines. The first RAID parity data 604a of the reserve (e.g., fund0) includes multiple parity pages 606. Parity pages 606 are generated by performing an XOR operation between data pages in a set of page lines 602, where this set of page lines 602 includes page lines 602 from each round of the reserve. Before writing the parity pages 606 to the storage block 600, the memory controller can allocate parity buffers to store each parity page 606 and / or corresponding intermediate results used to generate the parity pages 606. For the storage block 600 in SLC mode and the 2WL RAID scheme, the number of parity pages included in a reserve RAID parity data 604 is twice the number of strings included in the storage block 600. Therefore, the required number of parity buffers is twice the number of strings included in the storage block 600.

[0084] As an example, as shown in the data structure of storage block 600 in SLC mode, each reserve comprises 8 rounds (e.g., Round 0 to Round 7). Each round comprises 16 page lines associated with two adjacent word lines. The RAID parity data 604 for each reserve comprises 16 parity pages 606. The memory controller can allocate 16 parity buffers. Before writing a parity page to storage block 600, each parity buffer stores the parity page and / or intermediate results used to generate a parity page.

[0085] For example, the first parity page of Fund0's RAID parity data 604a generated based on XOR operation is: page line 0 ⊕ page line 16 ⊕ page line 32 ⊕… ⊕ page line 112; the second parity page of Fund0's RAID parity data 604a generated based on XOR operation is: page line 1 ⊕ page line 17 ⊕ page line 33 ⊕… ⊕ page line 113; …; the last parity page of Fund0's RAID parity data 604a generated based on XOR operation is: page line 15 ⊕ page line 31 ⊕ page line 47 ⊕… ⊕ page line 127.

[0086] At 656, the memory controller sends one or more first write commands to write user data and first RAID parity data 604 to the SLC mode storage block 600.

[0087] At 658, in response to receiving one or more first write commands, the storage device writes user data and first RAID parity data 604 to the SLC mode storage block 600. For example, the RAID parity data 604a of Fund0 is written to the last page of the last round of page lines 602 of Fund0; the RAID parity data 604b of Fund1 is written to the last page of the last round of page lines 602 of Fund1. In some implementations, the storage device writes data to the storage block 600 in page line numbering order (e.g., from page line 0, to page line 1, ..., to page line n). In some cases, the memory controller generates the RAID parity data 604b of Fund1 only after the RAID parity data 604a of Fund0 has been written to the storage block 600.

[0088] At 660, the memory controller sends one or more read commands to read user data from storage block 600. In some implementations, RAID parity data 604 is not read from storage block 600 during 660.

[0089] At 662, the memory controller generates second RAID parity data 624 corresponding to the user data based on QLC mode. In some implementations, the RAID circuitry can implement a 1WL protection scheme, such that each round includes a page line 602 associated with a word line. The reserve (e.g., fund0) of the second RAID parity data 624 includes multiple parity pages 606. The parity pages 606 of the second RAID parity data 624 are generated by performing an XOR operation between data in a set of page lines 602, where the set of page lines 602 includes page lines 602 from each round of the reserve. For the storage block 620 under QLC mode and the 1WL RAID scheme, the number of parity pages included in a reserve of RAID parity data 624 is four times the number of strings included in the storage block 620. Therefore, the number of parity buffers required is four times the number of strings included in the storage block 620.

[0090] As an example, as shown in the data structure of storage block 620 in QLC mode, each reserve consists of 8 rounds (e.g., Round 0 to Round 7). Each round includes 32 page lines associated with one word line. The RAID parity data 624 for each reserve includes 32 parity pages 606. The memory controller can allocate 32 parity buffers. Before writing the parity page 606 to storage block 600, each parity buffer stores the parity page 606 and / or intermediate results used to generate a parity page 606. A total of 48 parity buffers may be needed during process 650 (16 parity buffers for generating RAID parity data 604 during cache writes, and 32 parity buffers for generating RAID parity data when moving data to the QLC mode storage block), which may exceed the buffer space of the memory controller's RAM. In this scenario, the memory controller may need to perform swapping operations by writing parity buffers and / or intermediate results to the storage device and retrieving them from the storage device when needed, which could affect the overall efficiency of write operations.

[0091] For example, the first parity page of Fund0's RAID parity data 624 generated based on XOR operation: page line 0 ⊕ page line 32 ⊕ page line 64 ⊕… ⊕ page line 224; the second parity page of Fund0's RAID parity data 624 generated based on XOR operation: page line 1 ⊕ page line 33 ⊕ page line 65 ⊕… ⊕ page line 225; …; the last parity page of Fund0's RAID parity data 624 generated based on XOR operation: page line 31 ⊕ page line 63 ⊕ page line 95 ⊕… ⊕ page line 255.

[0092] At 664, the memory controller sends one or more second write commands to write user data and second RAID parity data 624 to storage block 620 in QLC mode.

[0093] At 666, in response to receiving one or more write commands, the storage device writes user data and second RAID parity data 624 to storage block 620 in QLC mode. For example, the RAID parity data 624 of Fund0 is written to the last page of page line 602 of the last round of Fund0.

[0094] In some implementations, the storage device may include a storage block configured to operate in PLC mode. After a cache write, data is read from the SLC mode storage block and written to the PLC mode storage block. At 662, the memory controller generates second RAID parity data corresponding to the user data based on the PLC mode. For example, in a 1WL RAID scheme, each reserve may include 8 rounds, and each round may include 40 page lines (e.g., five page lines from each of eight strings). At 664, the memory controller may send one or more second write commands to write the user data and second RAID parity data to the PLC mode storage block. At 666, in response to receiving one or more second write commands, the storage device may write the user data and second RAID parity data to the PLC mode storage block. For example, the second RAID parity data of the reserve may include 40 parity pages 606, where each parity page 606 is the last page of the page lines included in the last round of the reserve.

[0095] By implementing process 650, although user data written to SLC mode storage block 600 (e.g., during cache writes) and user data written to QLC mode storage block 620 (e.g., when data is moved to QLC mode storage block) can be the same, the first RAID parity data 604 and the second RAID parity data 624 can be different. Furthermore, as... Figure 6A As shown, the position of the second RAID parity data 624 relative to the user data in storage block 620 may differ from the position of the first RAID parity data 604 relative to the user data in storage block 600. For example, the first RAID parity data 604 may be stored in page lines 112-127, 240-255, etc., while the second RAID parity data 624 may be stored in page lines 224-255, etc.

[0096] Figure 7A Storage devices (e.g., according to some aspects of this disclosure) are shown. Figures 1-2B and Figure 5 Storage device 104, Figure 3A Example data structure of storage device 300. Figure 7B This demonstrates writing data to, for example... Figure 7AExample process 750 of the storage device is shown. The storage device may include a storage block 700 programmable in a storage mode with lower storage density (e.g., SLC mode) and a storage block 720 programmable in a storage mode with higher storage density (e.g., MLC mode, such as QLC mode or PLC mode). Hereinafter, storage block 700 in SLC mode and storage block 720 in QLC mode are used as examples for illustration.

[0097] At 752, the host (e.g., Figure 1 and Figure 5 The host (108) sends user data to the memory controller. The host can also send one or more write commands to the memory controller (e.g., ...). Figures 1-2B and Figure 5 (Memory controller 106). One or more write commands instruct user data to be written to the storage device. In response to receiving user data, the memory controller may first perform a cache write by writing the user data to a storage block 700 in SLC mode (e.g., storage block 700). Then, the memory controller may write the user data to a storage block in a storage mode with higher storage density (e.g., storage block 720 in QLC mode).

[0098] At 754, the memory controller generates RAID parity data 704 corresponding to the user data based on a storage mode with higher storage density (e.g., QLC mode), and the storage block 720 is configured to operate in this storage mode. For example, RAID circuitry (e.g., Figure 5 The RAID circuit 516 can implement a 4WL RAID scheme during cache writes, where each round includes page lines 702 associated with four word lines. Parity pages 706 of the reserved RAID parity data 704 are generated by performing an XOR operation between the data in a set of page lines 702. The set of page lines 702 includes page lines 702 from each round of the reserve, i.e., each set of page lines 702 is associated with one word line in a set of word lines spaced three word lines apart from each other. For storage block 700 in SLC mode and the 4WL RAID scheme, the number of parity pages included in a reserve RAID parity data 704 is four times the number of strings included in storage block 700. Therefore, the number of parity buffers required is four times the number of strings included in storage block 700.

[0099] As an example, as shown in the data structure of storage block 700 in SLC mode, each reserve comprises 8 rounds (e.g., Round 0 to Round 7). Each round comprises 32 page lines associated with four word lines (e.g., 8 page lines associated with each of the 4 word lines). The RAID parity data 704 for each reserve comprises 32 parity pages 706. The memory controller can allocate 32 parity buffers. Each parity buffer stores the parity page and / or intermediate results used to generate a parity page before writing the parity page to storage block 700.

[0100] For example, the first parity page of Fund0's RAID parity data 704 generated based on XOR operation is: page line 0 ⊕ page line 32 ⊕ page line 64 ⊕… ⊕ page line 224; the second parity page of Fund0's RAID parity data 704 generated based on XOR operation is: page line 1 ⊕ page line 33 ⊕ page line 65 ⊕… ⊕ page line 225; …; the last parity page of Fund0's RAID parity data 704 generated based on XOR operation is: page line 31 ⊕ page line 63 ⊕ page line 95 ⊕… ⊕ page line 255.

[0101] At 756, the memory controller sends one or more first write commands to write user data and RAID parity data 704 to the SLC mode storage block 700.

[0102] At 758, in response to receiving one or more first write commands, the storage device writes user data and RAID parity data 704 to the SLC mode storage block 700. For example, the RAID parity data 704 of Fund0 is written to the last page of the last round of page line 702 of Fund0. In some implementations, the storage device writes data to the storage block 700 in page line numbering order (e.g., from page line 0, to page line 1, ..., to page line n).

[0103] At 760, the memory controller sends one or more read commands to read user data and RAID parity data 704 from storage block 700. In response to receiving one or more read commands, the storage device sends the user data and RAID parity data 704 to the memory controller. In some implementations, the storage device sends data in page line number order (e.g., from page line 0 to page line 1, ..., to page line n).

[0104] At 762, the memory controller disables the RAID encoder of the RAID circuitry, so that when data is written during 764-766, the memory controller will not generate RAID parity data.

[0105] At 764, the memory controller sends one or more second write commands to write user data and RAID parity data 704 to the QLC mode storage block 720.

[0106] At 766, in response to receiving one or more second write commands, the storage device writes user data and RAID parity data 704 to the QLC-mode storage block 720. Since the RAID parity data 704 is generated based on QLC mode, the storage device can write the user data and RAID parity data 704 to the same location in storage block 720 as it was read from storage block 700. For example, data read from page line X (X = 0, 1, 2, 3, ...) of storage block 700 can be written to page line X of storage block 720. Therefore, the location of the RAID parity data 704 relative to the user data in storage block 700 is the same as the location of the RAID parity data 704 relative to the user data in storage block 720. For example, as... Figure 7A As shown, in storage block 700, the RAID parity data 704 of Fund0 is stored in the last page of page lines 224-255; in storage block 720, the RAID parity data 704 of Fund0 is also stored in the last page of page lines 224-255.

[0107] In some implementations, storage block 720 can be configured to operate in another suitable storage mode, and the RAID scheme used to generate RAID parity data 704 at 754 can be adjusted according to the storage mode of storage block 720. For example, storage block 720 can be configured to operate in PLC mode. In this case, at 754, when generating RAID parity data 704, the RAID circuitry can implement a 5WL RAID scheme, where each round includes page lines 702 associated with five word lines. Parity pages 706 of the reserved RAID parity data 704 can be generated by performing an XOR operation between the data in a set of page lines 702. This set of page lines 702 can include page lines 702 from each reserved round, that is, each of the set of page lines 702 is associated with one word line in a set of word lines spaced four word lines apart from each other.

[0108] By implementing process 750, the RAID circuitry does not need to generate RAID parity data when data read from storage block 700 is written to storage block 720. Furthermore, compared to process 650, process 750 requires fewer parity buffers, which saves buffer space and reduces the need for swapping operations.

[0109] Figure 7C This demonstrates writing data to, for example... Figure 7AAnother example of the storage device shown is process 780. Processes 782, 784, 786, and 788 of process 780 may be the same as or similar to processes 752, 754, 756, and 758 of process 750, respectively.

[0110] At 790, instead of sending one or more read commands that would allow the storage device to send user data and RAID parity data 704 from storage block 700 to the memory controller, the memory controller may send one or more commands to move user data and RAID parity data 704 directly from storage block 700 in SLC mode to storage block 720 in QLC mode without sending the data to the memory controller.

[0111] At 792, in response to receiving one or more commands for mobile user data and RAID parity data 704, the storage device may write the user data and RAID parity data 704 to storage block 720. For example, the storage device may retrieve data from page line X (X = 0, 1, 2, 3, ...) of storage block 700 and write the data to page line X of storage block 720.

[0112] Figure 8 A flowchart of an example process 800 for operating a storage system according to some aspects of this disclosure is shown. Process 800 can be performed by any suitable device or system as described herein, for example, according to... Figures 1-7C The described example technology. For example, process 800 may be comprised of storage devices (e.g., Figures 1-2B and Figure 5 Storage device 104, Figure 3A The memory device 300) and the memory controller (e.g., Figures 1-2B and Figure 5 The memory system (e.g., memory controller 106) of the memory controller 106 Figure 1 The storage system 102) performs the operation. The storage device may include a storage block programmable in a first storage mode (e.g., SLC mode) or a second storage mode (e.g., MLC mode, such as QLC mode or PLC mode) having a higher storage density than the first storage mode.

[0113] The operations shown in process 800 are not exhaustive, and other operations can be performed before, after, or between any of the shown operations. Furthermore, some operations can be performed simultaneously, or in conjunction with... Figure 8 The different orders of execution are shown. In some implementations, some of the operations may be performed by one or more components of the device or system, such as the memory controller of the storage system.

[0114] At 802, the memory controller generates parity data corresponding to the user data based on the second memory mode (e.g., Figure 7A RAID parity data 704).

[0115] In some implementations, the second storage mode is QLC mode. Therefore, the memory controller generates parity data by implementing a 4WLRAID scheme. For example, the parity data consists of N parity data portions (e.g., Figure 7A Parity page 706), where each parity data section is obtained by combining M user data sections (e.g., ...). Figure 7A The page line 702 is generated by performing an XOR operation. Each user data segment in the M user data segments corresponds to one of the M word lines (e.g., WL0, WL4, WL8, ..., WL28) spaced three word lines apart from each other. N and M are positive integers. The number of parity buffers required is four times the number of strings included in a storage block in SLC mode.

[0116] In some implementations, the second storage mode is a PLC mode. Therefore, the memory controller generates parity data by implementing a 5WLRAID scheme. For example, the parity data includes N parity data portions (e.g., Figure 7A Parity page 706), where each parity data section is obtained by combining M user data sections (e.g., ...). Figure 7A The page line 702 is generated by performing an XOR operation. Each of the M user data sections corresponds to one of the M word lines (e.g., WL0, WL5, WL10, ..., WL35) spaced four word lines apart. N and M are positive integers. The number of parity buffers required is five times the number of strings included in a storage block in SLC mode.

[0117] In some implementations, the first storage mode is XLC mode, where storage blocks configured in the first storage mode can store X bits of data per storage cell (X is a positive integer). The second storage mode is YLC mode, where storage blocks configured in YLC mode can store Y bits of data per storage cell (Y is an integer greater than X). Therefore, the memory controller generates parity data by implementing a (K / X)WL RAID scheme, where K is the least common multiple of X and Y. For example, the parity data consists of N parity data portions (e.g., ...). Figure 7A Parity page 706), where each parity data section is obtained by combining M user data sections (e.g., ...). Figure 7APage line 702 is generated by performing an XOR operation. Each of the M user data sections corresponds to one of the M word lines spaced K / X word lines apart. The number of parity buffers required is the same as K times the number of strings included in the storage block of the first storage mode.

[0118] As an example, if the first storage mode is MLC (Multi-Level Cell) with 2 bits per cell and the second storage mode is QLC (Quickly Logic Cell) mode, parity data can be generated by implementing a 2WL (2-Will-L) RAID scheme. As another example, if the first storage mode is MLC with 2 bits per cell and the second storage mode is PLC (Programmable Logic Cell) mode, parity data can be generated by implementing a 5WL RAID scheme.

[0119] At 802, the storage device writes user data and parity data into the first set of storage blocks of the first storage mode (e.g., Figure 7A SLC mode storage block 700).

[0120] At 804, the storage device writes the user data and parity data read from the first set of storage blocks into the second set of storage blocks of the second storage mode (e.g., ...). Figure 7A (QLC mode storage block 720). In some implementations, the first position of parity data relative to user data in the first set of storage blocks is the same as the second position of parity data relative to user data in the second set of storage blocks.

[0121] In some implementations, if a write operation fails when writing user data and parity data to the second set of memory blocks, the memory controller can read the failed data portion again from the first set of memory blocks. If a read operation fails when reading user data from the second set of memory blocks, the memory controller can recover the damaged data portion by reading the parity data corresponding to the damaged data portion from the second set of memory blocks and performing an XOR operation on the parity data and the undamaged user data. For example, as... Figure 7A As shown, if a damaged page exists in page line 0 of storage block 720, the memory controller can recover the damaged page by performing an XOR operation on the parity page in page line 224 and other data pages in page line 0, page line 32, page line 64, ..., page line 224.

[0122] This disclosure also provides a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores one or more instructions (e.g., firmware of a memory controller) that can be executed by a computer system. When executed by a computer system, the instructions in the storage medium can be implemented for managing, etc. Figures 1-8 The method for parity checking data is shown.

[0123] The non-transitory computer-readable storage medium can be an internal storage unit of the device described in any of the foregoing embodiments. For example, the non-transitory computer-readable storage medium can be a hard disk or internal memory of the device. The non-transitory computer-readable storage medium can also be an external storage device of the device, such as an insertable hard disk, a smart media card (SMC), a secure digital card (SD) card, a flash memory card, etc. Furthermore, the non-transitory computer-readable storage medium can also include both internal storage units and external storage devices.

[0124] While this specification contains numerous details of specific implementations, these should not be construed as limiting the scope of the claims, but rather as descriptions of features that may be specific to a particular implementation. Specific features described herein in the context of an individual implementation may also be implemented in combination within that single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any sub-combination in multiple implementations. Furthermore, although previously described features may be described as functioning in a particular combination and even initially claimed, in some cases, one or more features from the claimed combination may be removed from the combination, and the claimed combination may be for sub-combinations or variations thereof.

[0125] As used in this disclosure, unless the context clearly indicates otherwise, the terms “a,” “an,” or “the” are used to include one or more. Unless otherwise indicated, the term “or” is used to mean a non-exclusive “or.” The phrase “at least one of A and B” has the same meaning as “A, B, or A and B.” Furthermore, all wording and terms used in this disclosure that are not otherwise defined are for descriptive purposes only and not for limitation. Any use of section headings is intended to aid in reading the document and is not to be construed as restrictive; information relating to a section heading may appear within or outside that particular section.

[0126] As used in this disclosure, the terms “about” or “approximately” may allow for a degree of variability in a value or range, for example, within 10% of a specified value, within 1% of a specified value, or within a specified limit of a range.

[0127] As used in this disclosure, the term “substantially” means the majority or most, at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or higher.

[0128] Values ​​expressed in range format should be interpreted flexibly to include not only the numerical values ​​explicitly stated as the limits of the range, but also all individual numerical values ​​or subranges contained within that range, as if each numerical value and subrange were explicitly stated. For example, the range “0.1% to about 5%” or “0.1% to 5%” should be interpreted to include about 0.1% to about 5%, as well as the individual values ​​(e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the indicated range. Unless otherwise stated, the statement “X to Y” has the same meaning as “about X to about Y”. Similarly, unless otherwise stated, the statement “X, Y, or Z” has the same meaning as “about X, about Y, or about Z”.

[0129] Specific implementations of the subject matter have been described. Other implementations, variations, and arrangements of the described implementations are within the scope of the appended claims and will be apparent to those skilled in the art. Although operations are depicted in a specific order in the drawings or claims, such operations are not required to be performed in the specific order shown or in a sequential order, or all shown operations must be performed (some operations may be considered optional) to achieve the desired result. In certain cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and performed when deemed appropriate.

[0130] Furthermore, not all implementations require the spacing or integration of the various system modules and components described in the previously described implementations, and the described components and systems can typically be integrated together or packaged into multiple products.

[0131] Therefore, the example implementations described above do not limit or constrain this disclosure. Other changes, substitutions, and modifications are possible without departing from the spirit and scope of this disclosure.

[0132] The foregoing description of a particular implementation can be readily modified and / or adapted to various applications. Therefore, based on the teachings and instructions presented herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed implementation.

[0133] The breadth and scope of this disclosure should not be limited by any of the exemplary implementations described above, but should be defined solely by the appended claims and their equivalents. Therefore, other implementations are also within the scope of the claims.

Claims

1. A storage system, comprising: A storage device comprising memory blocks programmable in a first storage mode or a second storage mode, wherein the first storage mode has a lower storage density compared to the second storage mode; and A memory controller coupled to the storage device, wherein the memory controller is configured to perform operations including the following: Based on the second storage mode, generate parity check data corresponding to the user data; The user data and the parity data are written to the first group of storage blocks in the first storage mode; and The user data and the parity data read from the first set of storage blocks are written to the second set of storage blocks in the second storage mode.

2. The storage system according to claim 1, wherein, The first storage mode is a single-level cell (SLC) mode, wherein a storage cell in the first group of storage blocks stores one bit of data. The second storage mode is a multi-level cell (MLC) mode, wherein the storage cells in the second group of storage blocks store two or more bits of data, and The parity data includes parity data from a Redundant Array of Independent Disks (RAID).

3. The storage system according to claim 2, wherein, The second storage mode is a four-level cell (QLC) mode. The parity data comprises N parity data portions, each generated by performing an XOR operation on M user data portions in the first set of storage blocks. Each of the M user data portions corresponds to one word line out of the M word lines, and N and M are positive integers. The M word lines are spaced three word lines apart from each other.

4. The storage system according to claim 2, wherein, The second storage mode is a five-level unit (PLC) mode. The parity data comprises N parity data portions, each generated by performing an XOR operation on M user data portions in the first set of storage blocks. Each of the M user data portions corresponds to one word line out of the M word lines, and N and M are positive integers. The M character lines are spaced four character lines apart from each other.

5. The storage system according to any one of claims 1 to 4, wherein, When the user data and the parity data are written to the second group of storage blocks, the independent redundant array of disks (RAID) encoder of the memory controller is disabled.

6. The storage system according to any one of claims 1 to 5, wherein, The data in the first set of storage blocks is associated with a first set of sequentially numbered pages, and the data in the second set of storage blocks is associated with a second set of sequentially numbered pages. The process of writing the user data and parity data read from the first set of storage blocks into the second set of storage blocks includes: Read data associated with one or more first pages in the first group of pages; and The data is written to one or more second pages in the second group of pages, wherein the page number of the one or more first pages and the page number of the one or more second pages are the same.

7. The storage system according to any one of claims 1 to 6, wherein, The first position of the parity data in the first group of storage blocks relative to the user data is the same as the second position of the parity data in the second group of storage blocks relative to the user data.

8. The storage system according to any one of claims 1 to 7, wherein, The memory controller is configured to perform the operation in response to receiving a write command from the host to write the user data.

9. The storage system according to any one of claims 1 to 8, wherein, The operation includes: In response to a write failure detected when writing the user data and the parity data to the second set of storage blocks, the user data and the parity data are read from the first set of storage blocks again.

10. The storage system according to any one of claims 1 to 9, wherein, The operation includes: In response to a read failure detected when reading the user data from the second set of storage blocks, the user data is recovered using the parity data from the second set of storage blocks.

11. A memory controller, comprising: A processor and an interface, wherein the processor is configured to perform operations including the following: Parity check data corresponding to user data is generated based on a second storage mode that has a higher storage density compared to the first storage mode. One or more first write commands are sent through the interface to write the user data and the parity data into the first group of storage blocks in the first storage mode; Send one or more read commands through the interface to read the user data and the parity data from the first set of storage blocks; and One or more second write commands are sent through the interface to write the user data and the parity data into the second set of storage blocks in the second storage mode.

12. The memory controller according to claim 11, wherein, When the user data and the parity data are written to the second group of storage blocks, the independent redundant array of disks (RAID) encoder of the memory controller is disabled.

13. The memory controller according to claim 11, wherein, The first storage mode is a single-level cell (SLC) mode, wherein a storage cell in the first group of storage blocks stores one bit of data. The second storage mode is a multi-level cell (MLC) mode, wherein the storage cells in the second group of storage blocks store two or more bits of data, and The parity data includes parity data from a Redundant Array of Independent Disks (RAID).

14. The memory controller according to claim 13, wherein, The second storage mode is a four-level cell (QLC) mode. The parity data comprises N parity data portions, each generated by performing an XOR operation on M user data portions in the first set of storage blocks. Each of the M user data portions corresponds to one word line out of the M word lines, and N and M are positive integers. The M word lines are spaced three word lines apart from each other.

15. The memory controller according to claim 13, wherein, The second storage mode is a five-level unit (PLC) mode, and The parity data comprises N parity data parts, each generated by performing an XOR operation on M user data parts in the first group of storage blocks. Each of the M user data parts corresponds to one word line out of the M word lines, and N and M are positive integers. The M character lines are spaced four character lines apart from each other.

16. The memory controller according to any one of claims 11 to 15, wherein, The operation includes: In response to a write failure detected when writing the user data and the parity data to the second set of storage blocks, the user data and the parity data are read from the first set of storage blocks again.

17. The memory controller according to any one of claims 11 to 16, wherein, The operation includes: In response to a read failure detected when reading the user data from the second set of storage blocks, the user data is recovered using the parity data from the second set of storage blocks.

18. A method of operating a storage system, comprising: Parity check data corresponding to user data is generated based on a second storage mode that has a higher storage density compared to the first storage mode. The user data and the parity data are written into the first group of storage blocks in the first storage mode; as well as The user data and the parity data read from the first set of storage blocks are written to the second set of storage blocks in the second storage mode.

19. The method of claim 18, comprising: In response to a write failure detected when writing the user data and the parity data to the second set of storage blocks, the user data and the parity data are read from the first set of storage blocks again.

20. The method according to claim 18 or 19, comprising: In response to a read failure detected when reading the user data from the second set of storage blocks, the user data is recovered using the parity data from the second set of storage blocks.

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