A high-speed multi-port shared cache management SRAM controller and control method

Abstract

This application relates to a high-speed multi-port shared cache management SRAM controller and control method, belonging to the field of data storage control technology. The SRAM controller includes a write data cache FIFO module, an SRAM chip select module, a memory address management module, an SRAM read / write control module, a priority queue management module, a scheduling module, and a CRC data encoding module. This invention achieves multi-port shared cache of 32 SRAM blocks through dynamic granular storage partitioning. It reduces head-of-chain congestion by combining a destination port-oriented SRAM_ID field allocation strategy, and employs a scheduling mode combining strict priority and weighted round-robin, along with CRC verification to achieve high-speed and reliable data read / write. The SRAM controller of this invention supports simultaneous read / write on 16 ports, with a single-port bandwidth of up to 1Gbps and a clock frequency higher than 250MHz. It can efficiently adapt to the high-speed data storage requirements of 40G / 100G network devices, significantly improving cache resource utilization and data processing efficiency.

Description

Technical Field

[0001] This application relates to the field of data storage control technology, and more specifically, to a high-speed multi-port shared cache management SRAM controller and control method. Background Technology

[0002] With the rapid development of network technology, internet traffic is exploding, and businesses and households are increasingly demanding higher network bandwidth. The arrival of the 40G and 100G network era has placed extremely high demands on the data storage capabilities of network devices. In the packet processing of network devices, storage management and scheduling account for a large portion of the processing time, and the low caching capacity of existing memory has become a core bottleneck limiting further improvements in network processor performance.

[0003] Existing SRAM cache management schemes in network devices mostly adopt a fixed capacity allocation method, that is, the total cache capacity is evenly distributed to each port. Although this method is simple to implement, the cache space cannot be shared between ports. If a port has a large amount of cache remaining, it cannot be allocated to other high-load ports, resulting in serious waste of cache resources and low cache efficiency. At the same time, during multi-port read and write, data packets from different destination ports are easily stored in the same SRAM block. Due to the single read channel characteristic of SRAM, chain head blocking occurs, which greatly reduces read and write efficiency. In addition, the fixed storage granularity of traditional cache management schemes cannot adapt to the storage needs of data packets of different lengths. Small data packets are prone to wasting space within the storage granularity, while large data packets require multiple allocations, increasing the complexity of control logic. Moreover, the multi-port scheduling mode is singular and cannot take into account the real-time performance of high-priority data packets and the fairness of low-priority data packets. There is a lack of effective error detection mechanisms during data transmission, and data reliability is difficult to guarantee. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of low resource utilization and low efficiency in existing SRAM cache management technology, and to provide a high-speed multi-port shared cache management SRAM controller and control method, which effectively improves resource utilization and data processing efficiency in SRAM cache management.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A high-speed, multi-port shared cache management SRAM controller is provided, comprising a write data cache FIFO module, an SRAM chip select module, and a memory address management module connected in sequence, as well as an SRAM read / write control module, a priority queue management module, and a scheduling module connected to the priority queue management module; the input terminal of the write data cache FIFO module and the output terminal of the scheduling module are both connected to a CRC data encoding module; wherein: The CRC data encoding module is used to encode the input data and decode and verify the output data. The write data buffer FIFO module is used to buffer input data and also buffer the destination port information of data packets; The SRAM chip select module is used to allocate SRAM_ID to data packets according to the SRAM idle / busy state, and to map 16 channels of write data to 32 SRAM channels; The memory address management module is used to manage storage granularities and determine the granularity of storage granularities based on the real-time packet length distribution. The priority queue management module is used to write SRAM_ID and unit_ID into the priority queue FIFO of the corresponding output port according to the field information of the corresponding destination port and the corresponding priority. The scheduling module is used to read SRAM_ID and unit_ID from the priority queue FIFO of the corresponding port according to the selected scheduling mode; The SRAM read / write control module is used to write and read data. During the write operation, the data is written to the specified address segment of the SRAM, and the SRAM_ID and unit_ID are written to the corresponding destination port and the corresponding priority queue FIFO according to the destination port and priority of the data packet.

[0006] This invention provides a high-speed multi-port shared cache management SRAM controller. It realizes multi-port shared cache of 32 SRAM blocks through dynamic granular storage granular partitioning. Combined with the destination port-oriented SRAM_ID field allocation strategy, it reduces chain head blocking. At the same time, it adopts a strict priority scheduling mode and cooperates with CRC check to achieve high-speed and reliable data reading and writing, which greatly improves cache resource utilization and data processing efficiency.

[0007] Furthermore, the write data buffer FIFO module is used to buffer 32-bit input data and sop, vld, and eop signals, and also buffers the destination port information of the data packet. After the SRAM_ID allocation is completed, the data is read out to realize the temporary storage and synchronization of data.

[0008] Furthermore, the SRAM chip select mode is used to allocate SRAM_IDs for 16 channels of write data. The allocation strategy includes classifying the packets output from each port according to the destination port. Packets from different destination ports are preferentially allocated to the specified SRAM_ID. When the specified SRAM_ID is busy or full, other SRAM_IDs are allocated. After each port outputs a packet, the current SRAM_ID is released and reallocated for a new packet.

[0009] Furthermore, the memory address management module uses a bitmap method to manage storage particles. A bit signal matching the number of storage particles represents the particle occupancy status; a signal value of 0 represents idle, and 1 represents occupied. This method allows for the occupation and release of storage particles, achieving high storage efficiency. The memory address management module also statistically analyzes the distribution characteristics of real-time write packet lengths, categorizing them into three scenarios: more large packets, more medium packets, and more small packets, and adjusts the division ratio of storage particles of these three granularities accordingly. The memory address management module also includes a counter to count the number of currently occupied storage particles. When the occupied number reaches a threshold, the almost_full signal is raised; when all storage particles are occupied, the full signal is raised.

[0010] Furthermore, the priority queue management module includes 16×8 priority queue FIFOs. After the data packet is written to the SRAM, the priority queue management module parses the data packet frame header and writes the SRAM_ID and unit_ID into the priority queue FIFO of the corresponding output port according to the field information of the corresponding destination port and the corresponding priority, thus simplifying the 32×128 switching network into a 32×16×8 hierarchical network.

[0011] Furthermore, the scheduling module includes a strict priority scheduling submodule and a weighted round-robin scheduling submodule, which can flexibly switch between scheduling modes. The strict priority scheduling submodule authorizes the eight priority queues in descending order of priority, and reads the data packets in the order they were written within the same priority to ensure the order of data packets. The weighted round-robin scheduling submodule configures weights decreasing from 8 to 1 for priorities 0-7. Within a round-robin cycle, if a single priority is continuously authorized up to the weight count or there is no request, it switches to the next priority, and the count is completed only after a complete data packet has been read.

[0012] Furthermore, during a write operation, the SRAM read / write control module writes data to a specified address segment of the SRAM according to the unit_ID. Simultaneously, during packet writing, it writes the destination port, priority, SRAM_ID, and unit_ID of the data packet into the corresponding priority queue FIFO of the destination port. During a read operation, it reads data from the specified address segment according to the SRAM_ID and unit_ID output by the scheduling module. When a termination signal is received or the data in the storage particle is read, the storage particle is released.

[0013] This invention also provides a control method for a high-speed multi-port shared cache management SRAM controller, employing the aforementioned high-speed multi-port shared cache management SRAM controller, comprising the following steps: S1. Data writing: After being encoded by the CRC data encoding module, the data packet is written to the data buffer FIFO module for buffering, and the destination port information of the data packet is also buffered; the SARM chip select module assigns SRAM_ID to the data packet according to the SARM's idle / busy state, and maps the 16 buffered write data to 32 SRAMs one by one; S2. Storage granularity allocation: The memory address management module determines the storage granularity based on the real-time packet length distribution and uses a bitmap method to allocate free storage granules to the data packets. If the data packet length is greater than a single storage granule, storage granules are allocated in multiple batches until the data packet is written. S3. Information Temporary Storage and Mapping: The SRAM read / write control module writes the unit_ID into the specified address segment of the SRAM, and writes the SRAM_ID and unit_ID into the corresponding destination port and the corresponding priority queue FIFO according to the destination port and priority of the data packet; S4. Data readout scheduling: The scheduling module reads the SRAM_ID and unit_ID from the priority queue FIFO of the corresponding port according to the selected scheduling mode, and sends them to the SRAM read / write control module. S5. Data Verification and Output: The SRAM read / write control module reads data from the SRAM according to the SRAM_ID and unit_ID. After the data is decoded and verified by the CRC data encoding module, if there is no error, it is output from the corresponding port; if there is an error, the error signal is pulled high. S6. Storage Particle Recycling: When the SRAM read / write control module receives a termination signal or when a single storage particle has finished reading data, it triggers the memory address management module to set the corresponding storage particle status to idle, thus completing the recycling.

[0014] Further, in step S2, the allocation rules for storage particles include: when the write enable signal is valid, and the data packet termination signal is read or the current storage particle is full, if the SRAM is not full, then unit_ID is allocated sequentially from the free storage particles according to the sequence number, and the bitmap signal of the corresponding full storage particle is set to 1; in step S6, the recycling rules for storage particles include: when the data is read and the signal is pulled high, the bitmap signal of the corresponding unit_ID is set to 0, and recycling is completed.

[0015] Compared with the prior art, the beneficial effects of the present invention are: This invention discloses a high-speed multi-port shared cache management SRAM controller and its control method. It realizes multi-port shared cache of 32 SRAM blocks through dynamic granular storage granular partitioning, reduces chain head blocking by combining a destination port-oriented SRAM_ID field allocation strategy, and adopts a strict priority scheduling mode and CRC check to achieve high-speed and reliable data reading and writing, which greatly improves cache resource utilization and data processing efficiency. Attached Figure Description

[0016] Figure 1 This is a schematic diagram showing the connections of the various modules of the SRAM controller in one embodiment; Figure 2 This is a block diagram of the overall architecture of the SRAM controller in one embodiment; Figure 3 This is a schematic diagram of the SRAM chip select module state machine in one embodiment; Figure 4 This is a block diagram of the memory address management module architecture in one embodiment; Figure 5 Here is a block diagram of dynamic granularity storage allocation in one embodiment; Figure 6 This is a block diagram of an SRAM controller packet forwarding speed test in one embodiment; Figure 7 This is a graph showing the test results of the SRAM controller packet forwarding speed in one embodiment; Figure 8 This is a block diagram of an SRAM controller packet delay test in one embodiment; Figure 9 This is a diagram showing the SRAM controller packet delay results in one embodiment; Figure 10 This is a schematic diagram of the control method flow in one embodiment. Detailed Implementation

[0017] The present invention will be further described below with reference to specific embodiments. The accompanying drawings are for illustrative purposes only, representing schematic diagrams rather than actual physical objects, and should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some components in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0018] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0019] Example 1 This embodiment is a first embodiment of a high-speed multi-port shared cache management SRAM controller, such as... Figure 1 As shown, the system includes a write data buffer FIFO module, an SRAM chip select module, and a memory address management module connected in sequence, as well as an SRAM read / write control module, a priority queue management module, and a scheduling module connected to the priority queue management module. Both the input of the write data buffer FIFO module and the output of the scheduling module are connected to a CRC data encoding module. The CRC data encoding module is used to encode the input data and decode and verify the output data. The write data buffer FIFO module buffers the input data and also buffers the destination port information of the data packets. The SRAM chip select module allocates SRAM_IDs to data packets according to the SRAM idle / busy state, mapping each of the 16 write data channels to an SRAM_ID. The system includes 32 SRAM channels; a memory address management module for managing storage granularities and determining granularity based on real-time packet length distribution; a priority queue management module for writing SRAM_ID and unit_ID into the priority queue FIFO of the corresponding output port according to the field information of the corresponding destination port and priority; a scheduling module for reading SRAM_ID and unit_ID from the priority queue FIFO of the corresponding port according to the selected scheduling mode; and an SRAM read / write control module for writing and reading data. During a write operation, data is written to the specified address segment of the SRAM, and SRAM_ID and unit_ID are written into the corresponding destination port and the corresponding priority queue FIFO according to the destination port and priority of the data packet.

[0020] In this embodiment, the SRAM controller manages 32 256K bit pseudo dual-port SRAMs with a total cache capacity of 8Mbit. It supports simultaneous read and write operations on 16 ports, with a data transmission bandwidth of up to 1Gbps per port. Each port is configured with 8 priority queues, and data is cached according to the queues. It is suitable for storing data packets of 64-1024 bytes and has a clock frequency higher than 250MHz to achieve high-speed caching.

[0021] In this embodiment, the write data buffer FIFO module is used to buffer 32-bit input data and sop, vld, and eop signals, and also buffers the destination port information of the data packet. After the SRAM_ID allocation is completed, the data is read out to realize the temporary storage and synchronization of data.

[0022] In this embodiment, the SRAM chip select mode is used to allocate SRAM_IDs for 16 channels of write data. The allocation strategy includes classifying the packets output from each port according to the destination port. Packets from different destination ports are preferentially allocated to the specified SRAM_ID. When the specified SRAM_ID is busy or full, other SRAM_IDs are allocated. After each port outputs a packet, the current SRAM_ID is released and reallocated for the new packet, avoiding chain head blocking caused by storing data packets from different destination ports in the same SRAM.

[0023] In this embodiment, the memory address management module divides a single SRAM into multi-granularity storage particles. These particles include three specifications: 8960 bits (corresponding to the maximum packet length), 4480 bits (corresponding to half of the maximum packet length), and 2240 bits (corresponding to 1 / 4 of the maximum packet length). The granularity allocation is dynamically adjusted based on the real-time packet length distribution. A bitmap approach is used to manage the storage particles. The particle occupancy status is represented by a bit signal matching the number of storage particles, with a signal value of 0 representing idle and 1 representing occupied, enabling rapid allocation and reclamation of storage particles. Simultaneously, a counter is set to count the number of currently occupied storage particles. When the number of occupied particles reaches a threshold, the almost_full signal is raised, and when all storage particles are occupied, the full signal is raised, enabling real-time monitoring of cache capacity.

[0024] In this embodiment, the SRAM read / write control module writes the unit_ID control data allocated by the memory address management module into the designated address segment of the SRAM. At the same time, when writing packets, the destination port, priority, SRAM_ID, and unit_ID of the data packet are written into the corresponding priority queue FIFO of the corresponding destination port. During the read operation, data is read from the designated address segment according to the SRAM_ID and unit_ID output by the scheduling module. When the termination signal is received or the data of the storage particle is read, the storage particle is released, thereby realizing precise read / write control of data.

[0025] In this embodiment, the priority queue management module includes 16×8 priority queue FIFOs. After parsing the SRAM_ID and unit_ID information in the frame header through message parsing, it writes them into the corresponding destination port and the corresponding priority queue FIFO, simplifying the 32×128 switching network into a 32×16×8 hierarchical network, reducing hardware implementation complexity and speeding up the read scheduling speed.

[0026] In this embodiment, the scheduling module includes a strict priority scheduling submodule and a weighted round-robin scheduling submodule, which can flexibly switch between scheduling modes. The strict priority scheduling submodule authorizes eight priority queues in descending order of priority, and reads data packets in the order they are written within the same priority, ensuring the order of data packets. It is suitable for scenarios with high real-time requirements for high-priority data packets. The weighted round-robin scheduling submodule configures weights decreasing from 8 to 1 for priorities 0-7. Within a round-robin cycle, if a single priority is continuously authorized up to the weight count or there is no request, it switches to the next priority. The count is completed only after a complete data packet is read, taking into account the fairness of low-priority data packets. It is suitable for scenarios where transmission efficiency must be guaranteed for multiple priority data packets.

[0027] In this embodiment, the CRC data encoding module includes a CRC encoding submodule and a CRC decoding submodule: the CRC encoding submodule performs a modulo-2 division operation on each frame of input data, with an initial value of FFFF_FFFF, generates a 32-bit CRC checksum, and adds the checksum to the last frame of the data packet for transmission with the packet; the CRC decoding submodule performs a modulo-2 division operation on each frame of output data, generates a checksum, and compares it with the checksum transmitted with the packet. If they do not match, the data_error signal is raised to indicate a data error, thereby realizing error detection during data transmission and improving data reliability.

[0028] This embodiment provides a high-speed, multi-port shared cache management SRAM controller. It achieves multi-port shared cache of 32 SRAM blocks through dynamic granular storage partitioning. Combined with a destination port-oriented SRAM_ID field allocation strategy, it reduces head-of-chain congestion. Furthermore, it employs a scheduling mode combining strict priority and weighted round-robin, along with CRC checksums, to achieve high-speed, reliable data read and write. This SRAM controller supports simultaneous read and write operations on 16 ports, with a single-port bandwidth of up to 1Gbps and a clock frequency exceeding 250MHz. It can efficiently adapt to the high-speed data storage requirements of 40G / 100G network devices, significantly improving cache resource utilization and data processing efficiency.

[0029] Example 2 This embodiment is a second embodiment of an SRAM controller for high-speed multi-port shared cache management. Similar to the first embodiment, this embodiment uses an SRAM controller applied to high-speed data storage in a 100G network switch. The controller references... Figure 2 It includes a write data buffer FIFO module, an SRAM chip select module, a memory address management module, an SRAM read / write control module, a priority queue management module, a scheduling module, and a CRC data encoding module. The hardware implementation of each module is based on the Verilog hardware description language, and can be synthesized and simulated on an FPGA platform.

[0030] In this embodiment, the SRAM controller manages 32 256K bit pseudo dual-port SRAMs with a total cache capacity of 8M bit. The clock frequency is set to 250MHz, supporting simultaneous read and write operations on 16 ports. The single-port data transmission bandwidth is 1Gbps. Each port is configured with 8 priority queues, adapting to the storage of Ethernet packets ranging from 64 to 1024 bytes. The packet frame format includes a control frame portion, which carries information about the destination port, priority, and packet length.

[0031] SRAM Chip Select Module Reference Figure 3 The 32 SRAMs are divided into 16 groups of 2, corresponding to 16 destination ports. Data packets from a destination port are preferentially allocated to the SRAM of the corresponding group. If all SRAMs in a group are busy or full, they are allocated to the idle SRAMs of other groups in turn. After each packet is transmitted, the current SRAM_ID is released and reallocated for the new packet, effectively avoiding chain head blocking.

[0032] Priority queue management module reference Figure 4 By setting up 128 priority queues FIFO with a depth of 256 (16 ports × 8 priorities), and writing the unit_ID of the data packet to the corresponding destination port and priority queue FIFO through read and write control, the complexity of the switching network is reduced from 32×128 to 32×16×8, reducing the FPGA resource consumption.

[0033] The scheduling module supports switching between strict priority and weighted round-robin modes: In strict priority mode, priority 0 is the highest priority and priority 7 is the lowest priority, and scheduling is carried out in descending order of priority; In weighted round-robin mode, the weights of priorities 0-7 are 8, 7, 6, 5, 4, 3, 2, 1 respectively, and the "AAABBC" authorization mode is adopted. The priority is switched when the authorization is continuously extended to the weighted number or when there are no requests.

[0034] Memory address management module reference Figure 4 and Figure 5 As shown, a single 256K bit SRAM is divided into 58 basic storage particles of 4480 bits. The granularity is dynamically adjusted according to the real-time packet length distribution: when there are more large packets (512-1024 bytes), every two 4480-bit particles are merged into an 8960-bit particle; when there are more small packets (64-256 bytes), every 4480-bit particle is split into two 2240-bit particles. A 64-bit bitmap signal is used to manage the storage particles (the lower 58 bits are valid), with a signal value of 0 representing idle and 1 representing occupied, to achieve fast allocation and reclamation of storage particles.

[0035] The CRC data encoding module uses a 32-bit CRC check algorithm with a generator polynomial of 0x04C11DB7 and an initial value of 0xFFFF_FFFF. It performs modulo-2 division on each 32-bit data packet frame by frame and adds the generated check code to the last frame of the data packet for transmission. When the output check is inconsistent, the data_error signal is pulled high by 1 bit to realize data error detection.

[0036] The SRAM controller in this embodiment was verified by co-simulation using UVM and Verilog tb_model. Using fixed priority (SP) and weighted round-robin (WRR) modes with an input bandwidth of 3Gbps and an input packet length of 64 bytes, ten tests were conducted. The SRAM controller's data packet processing speed was greater than 83Mpp in all ten tests. (Reference...) Figure 6 , Figure 7 Sixteen input ports receive a number of data packets with a bandwidth of 1Gbps. The latency of each data packet is recorded and statistically analyzed. Figure 8 and Figure 9 As shown, the lowest latency is 96ns, which is 24 clock cycles; statistically, the latency is distributed between 100ns and 10μs. The cache resource utilization rate is more than 60% higher than the traditional fixed allocation method, and there is no obvious chain head blocking phenomenon. It can stably adapt to the high-speed data storage requirements of 100G network switches.

[0037] Example 3 This embodiment is an example of a control method for a high-speed multi-port shared cache management SRAM controller. This embodiment uses the high-speed multi-port shared cache management SRAM controller provided in Embodiment 1, such as... Figure 10 As shown, the specific steps include: Step S1. Data writing: After the data packet is 32-bit CRC encoded by the CRC encoding submodule, it enters the write data buffer FIFO module for buffering, and at the same time buffers the destination port information of the data packet; the SRAM chip select module assigns a unique SRAM_ID to the data packet according to the destination port. If the specified SRAM is busy or full, other free SRAM_IDs are assigned.

[0038] Step S2. Storage Granule Allocation: The memory address management module first analyzes the distribution characteristics of the written packet length over a period of time, classifying them into three scenarios: more large packets, more medium packets, and more small packets. It then adjusts the allocation ratio of storage granularities of 8960bit, 4480bit, and 2240bit accordingly. A bitmap method is used to allocate idle unit_IDs to data packets. If the data packet length is less than a single storage granule, an idle unit_ID is directly allocated. If the data packet length is greater than a single storage granule, idle unit_IDs are allocated until the data packet is fully written and no eop signal is received. After allocating a unit_ID, the corresponding bitmap signal is set to 1, marking it as occupied.

[0039] Step S3. Information Temporary Storage and Mapping: The SRAM read / write control module writes the data packet to the specified address segment of the SRAM according to the SRAM_ID and unit_ID, and at the same time writes the SRAM_ID, unit_ID, destination port and priority information of the data packet to the corresponding SRAM temporary storage FIFO; the priority queue management module arbitrates according to the empty signal of each temporary storage FIFO, reads and parses the information in the temporary storage FIFO in sequence, and writes the unit_ID into the queue FIFO of the corresponding destination port and the corresponding priority.

[0040] Step S4. Data Readout Scheduling: Based on actual application requirements, select either strict priority or weighted round-robin scheduling mode. The scheduling module reads SRAM_ID and unit_ID sequentially from the priority queue FIFO of the corresponding output port according to the selected mode and sends them to the SRAM read / write control module. In weighted round-robin scheduling, weights decreasing from 8 to 1 are configured for priorities 0-7. Within a round-robin cycle, if a single priority is continuously authorized up to the weight count or there is no request, it switches to the next priority. The count is completed only after a complete data packet is read.

[0041] Step S5. Data Verification and Output: The SRAM read / write control module reads the data packet from the specified address segment of the SRAM according to the SRAM_ID and unit_ID output by the scheduling module. The data packet is transmitted to the CRC decoding submodule for verification. The CRC decoding submodule performs a modulo-2 division operation on each frame of the data packet to generate a check code and compares it with the 32-bit CRC check code transmitted with the packet. If the two match, it means that the data is error-free, and the data packet is output from the corresponding output port. If the two do not match, the data_error signal is pulled high, indicating that the data transmission has failed.

[0042] Step S6. Storage Particle Reclamation: When the SRAM read / write control module reads the eop signal (end of data packet) or when the data of a single storage particle is read, it triggers the read completion signal ram_rd_done to go high. After receiving this signal, the memory address management module sets the bitmap signal of the corresponding unit_ID to 0, marking it as idle, and completes the reclamation of the storage particle for subsequent data packet allocation.

[0043] This embodiment provides a control method for a high-speed multi-port shared cache management SRAM controller, which solves the technical problems of low resource utilization, easy blocking of multi-port read and write, fixed storage granularity, single scheduling mode and low data reliability in existing SRAM cache management, and realizes high-speed, efficient and reliable multi-port SRAM cache management.

[0044] In the specific implementation of the above embodiments, the technical features can be combined in any non-contradictory way. For the sake of brevity, not all possible combinations of the above technical features are described. However, as long as the combination of these technical features is not contradictory, it should be considered to be within the scope of this specification.

[0045] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A high-speed multi-port shared cache management SRAM controller, characterized in that, It includes a write data buffer FIFO module, an SRAM chip select module, and a memory address management module connected in sequence, as well as an SRAM read / write control module, a priority queue management module, and a scheduling module connected to the priority queue management module; the input of the write data buffer FIFO module and the output of the scheduling module are both connected to a CRC data encoding module; wherein: The CRC data encoding module is used to encode the input data and decode and verify the output data. The write data buffer FIFO module is used to buffer input data and also buffer the destination port information of data packets; The SRAM chip select module is used to allocate SRAM_ID to data packets according to the SRAM idle / busy state, and to map 16 write data channels to 32 SRAM channels one by one. The memory address management module is used to manage storage granularities and determine the granularity of storage granularities based on the real-time packet length distribution. The priority queue management module is used to write SRAM_ID and unit_ID into the priority queue FIFO of the corresponding output port according to the field information of the corresponding destination port and the corresponding priority. The scheduling module is used to read SRAM_ID and unit_ID from the priority queue FIFO of the corresponding port according to the selected scheduling mode; The SRAM read / write control module is used to write and read data. During the write operation, the data is written to the specified address segment of the SRAM, and the SRAM_ID and unit_ID are written to the corresponding destination port and the corresponding priority queue FIFO according to the destination port and priority of the data packet.

2. The SRAM controller for high-speed multi-port shared cache management according to claim 1, characterized in that, The write data buffer FIFO module is used to buffer 32-bit input data and sop, vld, and eop signals, and also buffers the destination port information of the data packet. After the SRAM_ID is allocated, the data is read out to realize the temporary storage and synchronization of data.

3. The SRAM controller for high-speed multi-port shared cache management according to claim 1, characterized in that, The SRAM chip select mode is used to allocate SRAM_IDs for 16 channels of write data. The allocation strategy includes classifying the packets output from each port according to the destination port. Packets from different destination ports are preferentially allocated to the specified SRAM_ID. When the specified SRAM_ID is busy or full, other SRAM_IDs are allocated. After each port outputs a packet, the current SRAM_ID is released and reallocated for a new packet.

4. The SRAM controller for high-speed multi-port shared cache management according to claim 1, characterized in that, The memory address management module uses a bitmap method to manage storage particles. The particle occupancy status is represented by a bit signal that matches the number of storage particles. A signal value of 0 represents idle and 1 represents occupied. The memory address management module also statistically analyzes the distribution characteristics of real-time write packet lengths, dividing them into three scenarios: more large packets, more medium packets, and more small packets, and adjusts the division ratio of storage particles of the three granularities accordingly. The memory address management module also has a counter to count the number of currently occupied storage particles. When the number of occupied particles reaches a threshold, the almost_full signal is raised, and when all storage particles are occupied, the full signal is raised.

5. The SRAM controller for high-speed multi-port shared cache management according to claim 1, characterized in that, The priority queue management module includes 16×8 priority queue FIFOs. After the data packet is written to the SRAM, the priority queue management module parses the data packet frame header and writes the SRAM_ID and unit_ID into the priority queue FIFO of the corresponding output port according to the field information of the corresponding destination port and the corresponding priority, thus simplifying the 32×128 switching network into a 32×16×8 hierarchical network.

6. The SRAM controller for high-speed multi-port shared cache management according to claim 1, characterized in that, The scheduling module includes a strict priority scheduling submodule and a weighted round-robin scheduling submodule, which can flexibly switch between scheduling modes. The strict priority scheduling submodule authorizes eight priority queues in descending order of priority, and reads data packets in the order they are written within the same priority to ensure the order of data packets. The weighted round-robin scheduling submodule configures weights decreasing from 8 to 1 for priorities 0-7. Within a round-robin cycle, if a single priority is continuously authorized up to the weight count or there is no request, it switches to the next priority, and the count is completed only after a complete data packet is read.

7. The SRAM controller for high-speed multi-port shared cache management according to claim 1, characterized in that, During a write operation, the SRAM read / write control module writes data to the specified address segment of the SRAM according to the unit_ID. Simultaneously, when writing a packet, it writes the destination port, priority, SRAM_ID, and unit_ID of the data packet into the corresponding priority queue FIFO of the destination port. During a read operation, it reads data from the specified address segment according to the SRAM_ID and unit_ID output by the scheduling module. When a termination signal is received or the data in the storage particle is read, the storage particle is released.

8. A control method for a high-speed multi-port shared cache management SRAM controller, characterized in that, The SRAM controller employing the high-speed multi-port shared cache management according to any one of claims 1 to 8 includes the following steps: S1. Data writing: After being encoded by the CRC data encoding module, the data packet is written to the data buffer FIFO module for buffering, and the destination port information of the data packet is also buffered; the SARM chip select module assigns SRAM_ID to the data packet according to the SARM's idle / busy state, and maps the 16 buffered write data to 32 SRAMs one by one; S2. Storage granularity allocation: The memory address management module determines the storage granularity based on the real-time packet length distribution and uses a bitmap method to allocate free storage granules to the data packets. If the data packet length is greater than a single storage granule, storage granules are allocated in multiple batches until the data packet is written. S3. Information Temporary Storage and Mapping: The SRAM read / write control module writes the unit_ID into the specified address segment of the SRAM, and writes the SRAM_ID and unit_ID into the corresponding destination port and the corresponding priority queue FIFO according to the destination port and priority of the data packet; S4. Data readout scheduling: The scheduling module reads the SRAM_ID and unit_ID from the priority queue FIFO of the corresponding port according to the selected scheduling mode, and sends them to the SRAM read / write control module. S5. Data Verification and Output: The SRAM read / write control module reads data from the SRAM according to the SRAM_ID and unit_ID. After the data is decoded and verified by the CRC data encoding module, if there is no error, it is output from the corresponding port; if there is an error, the error signal is pulled high. S6. Storage Particle Recycling: When the SRAM read / write control module receives a termination signal or when a single storage particle has finished reading data, it triggers the memory address management module to set the corresponding storage particle status to idle, thus completing the recycling.

9. The control method for the SRAM controller with high-speed multi-port shared cache management according to claim 8, characterized in that, In step S2, the allocation rules for storage particles include: when the write enable signal is valid and the data packet termination signal is read or the current storage particle is full, if the SRAM is not full, then unit_ID is allocated sequentially from the free storage particles according to the sequence number, and the bitmap signal of the corresponding full storage particle is set to 1.

10. The control method for the SRAM controller with high-speed multi-port shared cache management according to claim 8, characterized in that, In step S6, the recycling rules for storage particles include: when the data is read out and the signal is pulled high, the bitmap signal of the corresponding unit_ID is set to 0 to complete the recycling.

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