Method and apparatus for wireless communication

Abstract

Disclosed in the present application are a method and apparatus for wireless communication. The method comprises: a first node receiving first signaling, and receiving or sending a first signal. The first signaling indicates scheduling information of the first signal; a first bit block and a second bit block are used together to generate the first signal, the first bit block depends on an output of a first encoder, wherein an input of the first encoder comprises a first information bit block, and the second bit block depends on an output of a second encoder, wherein an input of the second encoder comprises a first check bit block, the first information bit block being used for generating the first check bit block; and the ratio between the size of the input of the first encoder and the size of the first bit block is not equal to the ratio between the size of the input of the second encoder and the size of the second bit block. The method improves encoding efficiency and / or encoding performance, thereby improving system transmission efficiency and performance.

Description

Method and apparatus for wireless communication TECHNICAL FIELD

[0001] The present application relates to methods and apparatuses in wireless communication system, and in particular, to AI(Artificial Intelligence) or ML(Machine Learning) schemes and apparatuses in wireless communication system. BACKGROUND

[0002] In conventional wireless communication, channel coding is used to improve the reliability of wireless communication, typical channel coding techniques include Turbo code, LDPC(Low Density Parity Check Code) code, polar code, etc.

[0003] With the popularization of AI(Artificial Intelligence) or ML(Machine Learning) technology, AI / ML-based encoding or decoding technology has become a research hotspot, such as joint source and channel coding technology, cross-layer coding technology, etc.

[0004] Since the specification of the AI model may be beyond the scope of 3GPP(3rd Generation Partner Project), except for the reference model used for performance calibration, the specific implementation of AI / ML training and AI / ML inference may be determined by the hardware device manufacturer, which can be based on, for example, classic models such as Transformer structure, RNN(Recurrent Neural Network), CNN(Conventional Neural Networks), or a hybrid model composed of multiple models. SUMMARY

[0005] The inventors have found through research that in AI / ML-based encoding and decoding technology, the special characteristics of data blocks can be utilized to improve encoding efficiency and / or encoding performance, such as but not limited to the correlation between multiple data blocks and the semantic characteristics of data blocks, etc. Since the CRC(Cyclic redundancy check) bit block does not have the characteristics of the data block, the AI / ML encoder trained for the data block may not be applicable to the CRC bit block. How to ensure the transmission performance of the CRC bit block is a problem to be solved.

[0006] In view of the above problems, the present application discloses a solution. It should be noted that although the motivation of the present application comes from AI / ML-based decoding; the present application is also applicable to traditional non-AI / ML decoding technology. Especially considering that the specific encoder / decoder algorithm is likely to be non-standardized or implemented by the hardware device manufacturer. Further, adopting a unified solution for different scenarios (including but not limited to AI / ML-based solutions and traditional non-AI / ML-based solutions) also helps to reduce signaling overhead / complexity, reduce hardware complexity and cost. In the case of no conflict, the embodiments in the first node and the features in the embodiments of the present application can be applied to the second node. In the case of no conflict, the embodiments of the present application and the features in the embodiments can be arbitrarily combined with each other.

[0007] In the case of need, the explanation of the terms in the present application can refer to the description of the specification agreement TS38 series of 3GPP, or refer to the description of the specification agreement TS28 series of 3GPP.

[0008] The present application discloses a method in a first node used for wireless communication, characterized in that, comprising:

[0009] receiving first signaling, the first signaling indicating scheduling information of a first signal;

[0010] receiving the first signal, or transmitting the first signal;

[0011] wherein the first bit block and the second bit block are collectively used to generate the first signal, the first bit block depends on the output of a first encoder, the input of the first encoder includes a first information bit block, the second bit block depends on the output of a second encoder, the input of the second encoder includes a first check bit block, the first information bit block is used to generate the first check bit block; the ratio between the size of the input of the first encoder and the size of the first bit block is not equal to the ratio between the size of the input of the second encoder and the size of the second bit block.

[0012] As an embodiment, the problem to be solved by the present application includes how to optimize the encoding of information bit blocks and check bit blocks according to their different needs; in the above method, the first information bit block and the first check bit block are respectively input into the first encoder and the second encoder, and correspond to different code rates, which solves this problem.

[0013] As an embodiment, the benefits of the above method include improving the encoding efficiency and encoding performance, thereby improving the system performance.

[0014] As an embodiment, the benefits of the above method include that the code rate of the information bit block and the check bit block is different, which improves the coding efficiency of the information bit, ensures the transmission performance of the check bit, and improves the overall system performance and transmission efficiency.

[0015] According to an aspect of the present application, the first signaling indicates the first MCS; the ratio between the size of the input of the first encoder and the size of the first bit block depends on the first MCS and the first factor, and the ratio between the size of the input of the second encoder and the size of the second bit block depends on only the first MCS of the first MCS and the first factor.

[0016] The benefits of the above method include that the code rate of the first information bit block can be flexibly selected or controlled to adapt to different service types, terminals, and application scenarios.

[0017] The benefits of the above method include that the existing MCS is fully utilized, the standard is slightly changed, and good backward compatibility is achieved.

[0018] The benefits of the above method include that the transmission efficiency of the information bit is improved, and the reliability of the transmission of the check bit is ensured.

[0019] According to an aspect of the present application, the first encoder is one of M encoders, and M is a positive integer greater than 1; the M encoders and M factors correspond to each other, and the first factor is the factor corresponding to the first encoder.

[0020] As an embodiment, the essence of the above method includes that the M encoders can be used for different service types, transmission environments, or application scenarios; the above method optimizes the data transmission performance in different services, environments, or scenarios, and further improves the overall system performance.

[0021] As an embodiment, the benefits of the above method include that the training of AI / ML is more targeted, and better performance can be obtained.

[0022] According to an aspect of the present application, the first signaling indicates the first factor.

[0023] The benefits of the above method include that it is applicable to the case where the first node receives the first signal.

[0024] The benefits of the above method include that the accuracy of decoding at the receiving end is ensured, and there is no ambiguity between the transmitting end and the receiving end about the size of the first information bit block.

[0025] The benefits of the above method include simple design and good backward compatibility.

[0026] According to an aspect of the present application, there is provided a method comprising:

[0027] transmitting first control information;

[0028] wherein the first control information indicates the first factor.

[0029] The method has the advantage of being applicable to the case where the first node transmits the first signal.

[0030] The method has the advantage of ensuring the accuracy of decoding at the receiving end and the absence of ambiguity between the transmitting and receiving parties regarding the size of the first block of information bits.

[0031] The method has the advantage of simple design and good backward compatibility.

[0032] According to an aspect of the present application, the first factor depends on the first MCS.

[0033] The method has the advantage of more flexible design and further optimization of the performance of the first block of information bits in different channel environments.

[0034] The method has the advantage of reducing the signaling overhead.

[0035] According to an aspect of the present application, K blocks of bits and the second block of bits are collectively used to generate the first signal, K being a positive integer greater than 1; the first block of bits is one of the K blocks of bits, the K blocks of bits being outputs respectively obtained by K encoders with K blocks of information bits as inputs, the first block of information bits being one of the K blocks of information bits; the second block of bits is an output obtained by the second encoder with a third block of bits as input, the third block of bits comprising K blocks of check bits, the K blocks of information bits being respectively used to generate the K blocks of check bits.

[0036] The method has the advantage of increasing the coding length of the blocks of check bits and improving the coding performance and transmission reliability of the blocks of check bits.

[0037] The method has the advantage of improving the overall performance of the system and improving the transmission efficiency.

[0038] According to an aspect of the present application, the ratio between the size of the input of the second encoder and the size of the second block of bits depends on K.

[0039] The method has the advantages that the code rate of the check bit block is adjusted according to the code length of the check bit block, the coding efficiency of the check bit block is improved without reducing the transmission performance of the check bit block, and the system performance is improved.

[0040] According to an aspect of the present application, there is provided a method in a first node for wireless communication, comprising:

[0041] performing decoding of a decoder corresponding to the first encoder;

[0042] performing decoding of a decoder corresponding to the second encoder;

[0043] The first node receives the first signal.

[0044] The method has the advantages that the AI / ML is used to improve the performance of the downlink transmission.

[0045] According to an aspect of the present application, there is provided a method in a first node for wireless communication, comprising:

[0046] performing encoding of the first encoder;

[0047] performing encoding of the second encoder;

[0048] The first node transmits the first signal.

[0049] The method has the advantages that the AI / ML is used to improve the performance of the uplink transmission.

[0050] The present application discloses a method in a second node for wireless communication, comprising:

[0051] transmitting first signaling, the first signaling indicating scheduling information of a first signal;

[0052] transmitting or receiving the first signal;

[0053] The first bit block and the second bit block are used together to generate the first signal, the first bit block depends on the output of a first encoder, the input of the first encoder includes a first information bit block, the second bit block depends on the output of a second encoder, the input of the second encoder includes a first check bit block, the first information bit block is used to generate the first check bit block, and the ratio between the size of the input of the first encoder and the size of the first bit block is not equal to the ratio between the size of the input of the second encoder and the size of the second bit block.

[0054] According to an aspect of the present application, the first signaling indicates a first MCS; the ratio between the size of the input of the first encoder and the size of the first bit block depends on the first MCS and a first factor, and the ratio between the size of the input of the second encoder and the size of the second bit block depends on only the first MCS of the first MCS and the first factor.

[0055] According to an aspect of the present application, the first encoder is one of M encoders, where M is a positive integer greater than 1; the M encoders and M factors are in one-to-one correspondence, and the first factor is a factor corresponding to the first encoder.

[0056] According to an aspect of the present application, the first signaling indicates the first factor.

[0057] According to an aspect of the present application, comprising:

[0058] receiving first control information;

[0059] The first control information indicates the first factor.

[0060] According to an aspect of the present application, the first factor depends on the first MCS.

[0061] According to an aspect of the present application, K bit blocks and the second bit block are collectively used to generate the first signal, where K is a positive integer greater than 1; the first bit block is one of the K bit blocks, the K bit blocks are respectively outputs obtained by K encoders respectively taking K information bit blocks as inputs, the first information bit block is one of the K information bit blocks; the second bit block is an output obtained by the second encoder taking a third bit block as input, the third bit block includes K check bit blocks, and the K information bit blocks are respectively used to generate the K check bit blocks.

[0062] According to an aspect of the present application, the ratio between the size of the input of the second encoder and the size of the second bit block depends on the K.

[0063] According to an aspect of the present application, comprising:

[0064] performing encoding of the first encoder;

[0065] performing encoding of the second encoder;

[0066] The second node transmits the first signal.

[0067] According to an aspect of the present application, there is provided a first node for wireless communication, comprising:

[0068] performing decoding of a decoder corresponding to the first encoder;

[0069] performing decoding of a decoder corresponding to the second encoder;

[0070] wherein the second node receives the first signal.

[0071] The present application discloses a first node for wireless communication, comprising:

[0072] a first receiver configured to receive first signaling, the first signaling indicating scheduling information of a first signal;

[0073] a first processor configured to receive the first signal, or transmit the first signal;

[0074] wherein a first bit block and a second bit block are jointly used to generate the first signal, the first bit block depending on an output of a first encoder, an input of the first encoder including a first information bit block, the second bit block depending on an output of a second encoder, an input of the second encoder including a first check bit block, the first information bit block being used to generate the first check bit block, a ratio between a size of the input of the first encoder and a size of the first bit block being different from a ratio between a size of the input of the second encoder and a size of the second bit block.

[0075] The present application discloses a second node for wireless communication, comprising:

[0076] a first transmitter configured to transmit first signaling, the first signaling indicating scheduling information of a first signal;

[0077] a second processor configured to transmit the first signal, or receive the first signal;

[0078] wherein a first bit block and a second bit block are jointly used to generate the first signal, the first bit block depending on an output of a first encoder, an input of the first encoder including a first information bit block, the second bit block depending on an output of a second encoder, an input of the second encoder including a first check bit block, the first information bit block being used to generate the first check bit block, a ratio between a size of the input of the first encoder and a size of the first bit block being different from a ratio between a size of the input of the second encoder and a size of the second bit block.

[0079] As an embodiment, compared with the conventional scheme, the present application has the following advantages:

[0080] The encoding efficiency and / or encoding performance of the data block is improved, while the transmission performance of the check bits is ensured;

[0081] The overall performance and transmission efficiency of the system are improved;

[0082] The design is flexible to adapt to different service types, terminals and application scenarios;

[0083] The design is simplified and the impact on the standard is fully utilized;

[0084] The signaling overhead is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0085] Other features, objects and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments, read in conjunction with the accompanying drawings:

[0086] Figure 1 shows a flowchart of a first message according to one embodiment of the application;

[0087] Figure 2 shows a schematic diagram of a network architecture according to one embodiment of the application;

[0088] Figure 3 shows a schematic diagram of an embodiment of a radio protocol architecture for the user plane and control plane according to one embodiment of the application;

[0089] Figure 4 shows a schematic diagram of a first communication device and a second communication device according to one embodiment of the application;

[0090] Figure 5 shows a transmission between a first node and a second node according to one embodiment of the application;

[0091] Figure 6 shows a transmission between a first node and a second node according to one embodiment of the application;

[0092] Figure 7 shows a schematic diagram of a first signal carrying a first block of bits and a second block of bits according to one embodiment of the application;

[0093] Figure 8 shows a schematic diagram of a first block of bits, a first information block of bits, a second block of bits and a first block of check bits according to one embodiment of the application;

[0094] Figure 9 shows a schematic diagram of a ratio between a size of an input of a first encoder and a size of a first block of bits depending on a first MCS and a first factor, and a ratio between a size of an input of a second encoder and a size of a second block of bits depending on only the first MCS of the first MCS and the first factor according to one embodiment of the application;

[0095] Figure 10 shows a schematic diagram of a size of a first information block of bits depending on a first factor according to one embodiment of the application;

[0096] FIG. 11 shows a diagram of M encoders and M factors according to one embodiment of the application;

[0097] FIG. 12 shows a diagram of a first signaling indicating a first factor according to one embodiment of the application;

[0098] FIG. 13 shows a diagram of a first control information indicating a first factor according to one embodiment of the application;

[0099] FIG. 14 shows a diagram of a first factor depending on a first MCS according to one embodiment of the application;

[0100] FIG. 15 shows a diagram of K information bit blocks and K check bit blocks according to one embodiment of the application;

[0101] FIG. 16 shows a diagram of a first signal carrying K bit blocks and a second bit block according to one embodiment of the application;

[0102] FIG. 17 shows a diagram of K bit blocks, K information bit blocks, a second bit block and a third bit block according to one embodiment of the application;

[0103] FIG. 18 shows a diagram of a ratio between a size of an input of a second encoder and a size of a second bit block depending on K according to one embodiment of the application;

[0104] FIG. 19 shows a diagram of deploying a decoder corresponding to a first encoder according to one embodiment of the application;

[0105] FIG. 20 shows a diagram of deploying a first encoder according to one embodiment of the application;

[0106] FIG. 21 shows a diagram of an artificial intelligence or machine learning based processing system according to one embodiment of the application;

[0107] FIG. 22 shows a diagram of an artificial intelligence or machine learning based according to one embodiment of the application;

[0108] FIG. 23 shows a diagram of AI function deployment according to one embodiment of the application;

[0109] FIG. 24 shows a diagram of AI function deployment according to one embodiment of the application;

[0110] FIG. 25 shows a diagram of AI function deployment according to one embodiment of the application;

[0111] FIG. 26 shows a diagram of AI function deployment according to one embodiment of the application;

[0112] Figure 27 shows a structural block diagram of a processing device in a first node according to an embodiment of the present application;

[0113] Figure 28 shows a structural block diagram of a processing device in a second node according to an embodiment of the present application. DETAILED DESCRIPTION

[0114] The technical solutions of the present application will be further described in detail below with reference to the accompanying drawings. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other arbitrarily without conflict. Based on performance, flexibility, complexity, overhead and compatibility, etc., the person skilled in the art has the motivation to combine the embodiments in different drawings flexibly without conflict, for example, but not limited to, the embodiments in Figure 1 and the embodiments in Figures 5-28, the embodiments in Figure 5 and the embodiments in Figures 6-28, etc.

[0115] Embodiment 1

[0116] Embodiment 1 illustrates a flowchart of a first message according to an embodiment of the present application, as shown in Figure 1. In 100 shown in Figure 1, each block represents a step. In particular, the order of the steps in the blocks does not represent a specific time sequence between the steps.

[0117] In embodiment 1, the first node receives a first signaling in step 101; receives or transmits a first signal in step 102. Wherein, the first signaling indicates scheduling information of the first signal; a first bit block and a second bit block are used together to generate the first signal, the first bit block depends on the output of a first encoder, the input of the first encoder includes a first information bit block, the second bit block depends on the output of a second encoder, the input of the second encoder includes a first check bit block, the first information bit block is used to generate the first check bit block; the ratio between the size of the input of the first encoder and the size of the first bit block is not equal to the ratio between the size of the input of the second encoder and the size of the second bit block.

[0118] As an embodiment, the first signaling includes DCI (Downlink Control Information).

[0119] As an embodiment, the first signaling is DCI.

[0120] As an example, the CRC (Cyclic redundancy check) of the first signaling is scrambled by C(Cell)-RNTI (Radio Network Temporary Identifier).

[0121] As an example, the first signaling includes RRC (Radio Resource Control) signaling.

[0122] As one embodiment, the first signaling includes the scheduling information of the first signal.

[0123] As an example, the scheduling information includes one or more of the following: time-domain resources, frequency-domain resources, MCS (Modulation and coding scheme), DMRS port, HARQ (Hybrid Automatic Repeat request) process number, RV (Redundancy Version), NDI (New Data Indicator), and BWP (Bandwidth Part) indication.

[0124] As one embodiment, the first node receives the first signal, and the scheduling information includes the TCI (Transmission Configuration Indicator) status.

[0125] As an example, the first node sends the first signal, and the scheduling information includes at least one of SRI (Sounding Reference Signal, resource indicator) and TPMI (Transmitted Precoding Matrix Indicator).

[0126] As an example, the first node receives the first signal on a PDSCH (Physical Downlink Shared Channel).

[0127] As one embodiment of the above embodiments, the first signal is received only on the one PDSCH.

[0128] As one embodiment of the above embodiments, the first signal is a signal received on the PDSCH.

[0129] As an example, the first node transmits the first signal on a PUSCH (Physical Uplink Shared Channel).

[0130] As one embodiment of the above embodiments, the first signal is transmitted only on the one PUSCH.

[0131] As one embodiment of the above embodiments, the first signal is a signal transmitted on the PUSCH.

[0132] As an example, the first signal occupies only one PDSCH or one PUSCH.

[0133] As one embodiment, the first signal includes a baseband signal.

[0134] As one embodiment, the first signal includes a wireless signal.

[0135] As one embodiment, the first signal includes a radio frequency signal.

[0136] As one embodiment, the first information bit block includes a TB (Transport Block).

[0137] As an example, the first information bit block is one TB.

[0138] As one embodiment, the first information bit block includes a CB (Code Block).

[0139] As an example, the first information bit block is a CB.

[0140] As one example, the first information bit block includes a CBG (Code Block Group).

[0141] As an example, the first information bit block is a CBG.

[0142] As an example, the first information bit block is a data block.

[0143] As an example, the first information bit block is an information block.

[0144] As an example, the size of the first information bit block is not less than 24.

[0145] As one embodiment, the first signal carries the first bit block and the second bit block.

[0146] As an example, the first signal depends on the output of the first bit block and the second bit block after being scrambled, modulated, layer mapped and resource block mapped in sequence.

[0147] As an example, the first signal is generated by sequentially scrambling, modulating, layer mapping, and resource block mapping of the first bit block and the second bit block.

[0148] As one example, after the first bit block and the second bit block are concatenated, they are sequentially subjected to scrambling, modulation, layer mapping, and resource block mapping.

[0149] As one embodiment, the first information bit block is transmitted on the first channel.

[0150] As an example, the first information bit block comes from the first channel.

[0151] As an example, the first channel corresponds to a logical channel.

[0152] As an example, the first channel corresponds to a logical channel group.

[0153] As one example, the first channel corresponds to a radio bearer.

[0154] As an example, the first channel corresponds to a type of service.

[0155] As an example, the first channel corresponds to a service type.

[0156] As an example, the first channel corresponds to a channel from the RLC (Radio Link Control) layer to the MAC (Medium Access Control) layer.

[0157] As an example, the first channel corresponds to a channel from the layer above the MAC layer to the MAC layer.

[0158] As an example, the first channel corresponds to a channel from the layer above the RLC layer to the MAC layer.

[0159] As an example, the first channel corresponds to one of the TM (Transparent Mode), UM (Unacknowledged Mode), or AM (Acknowledged Mode) of the RLC layer.

[0160] As an example, the first channel corresponds to one of TM, UM or AM of the layer above the RLC layer.

[0161] As one embodiment, any bit in the first check bit block depends on the sum of multiple bits in the first information bit block modulo 2.

[0162] As an example, any bit in the first check bit block is equal to the sum of multiple bits in the first information bit block modulo 2.

[0163] As an example, any bit in the first check bit block is equal to the sum of multiple bits in the first information bit block modulo 2, or equal to the sum of the sum of multiple bits in the first information bit block modulo 2 and the sum of the corresponding bits in the scrambling sequence modulo 2.

[0164] As an example, the first check bit block depends on the CRC (Cyclic redundancy check) bit block of the first information bit block.

[0165] As an example, the first check bit block is the CRC bit block of the first information bit block.

[0166] As an example, the first check bit block is obtained by scrambling the CRC bit block of the first information bit block.

[0167] As a sub-implementation of the above embodiment, the scrambling includes scrambling each bit in the CRC bit block.

[0168] As a sub-implementation of the above embodiments, the scrambling includes scrambling only a portion of the bits in the CRC bit block.

[0169] As an example, the CRC bit block of the first information bit block is the output of the first information bit block through a CRC cyclic generator polynomial.

[0170] As an example, the polynomial formed by the first information bit block and the CRC bit block of the first information bit block is divisible by the CRC cyclic generator polynomial over GF(2), that is, the remainder obtained by dividing the polynomial formed by the first information bit block and the CRC bit block of the first information bit block by the CRC cyclic generator polynomial is zero.

[0171] As an example, the size of the first check bit block is equal to 24.

[0172] As an example, the size of the first check bit block is equal to 16.

[0173] As an example, the size of the first check bit block is equal to 11.

[0174] As an example, the size of the first check bit block is equal to 6.

[0175] As an example, the size of the first check bit block is 32.

[0176] As an example, the size of the first parity bit block is one of 24, 16, 11, and 6.

[0177] As an example, the size of the first parity bit block is one of 32, 24, 16, 11, and 6.

[0178] As an example, the size of a bit block refers to the number of bits included in the bit block.

[0179] As an example, the size of a bit block refers to the payload size of the bit block.

[0180] As one embodiment, the first bit block depends on the output of the first encoder, including: the first bit block includes part or all of the output of the first encoder.

[0181] As one embodiment, the first bit block depending on the output of the first encoder includes: the first bit block is the output of the first encoder.

[0182] As a sub-implementation of the above embodiments, the first encoder includes rate matching.

[0183] As one embodiment, the first bit block depends on the output of the first encoder, which is used to generate the first bit block.

[0184] As one embodiment, the first bit block depending on the output of the first encoder includes: the first bit block is obtained by rate matching the output of the first encoder.

[0185] As a sub-implementation of the above embodiments, the first encoder does not include rate matching.

[0186] As one example, the first bit block depends on the output obtained by the first encoder with the first information bit block as input.

[0187] As one embodiment, the second bit block depends on the output of the second encoder and includes: the second bit block includes part or all of the output of the second encoder.

[0188] As one embodiment, the second bit block depends on the output of the second encoder, including: the second bit block is the output of the second encoder.

[0189] As a sub-implementation of the above embodiments, the second encoder includes rate matching.

[0190] As one embodiment, the second bit block depends on the output of the second encoder, which is used to generate the second bit block.

[0191] As one embodiment, the second bit block depends on the output of the second encoder, comprising: the second bit block is obtained by rate matching the output of the second encoder.

[0192] As a sub-implementation of the above embodiments, the second encoder does not include rate matching.

[0193] As one embodiment, the second bit block depends on the output obtained by the second encoder with the first check bit block as input.

[0194] In a preferred embodiment, the first encoder is based on AI or ML.

[0195] The problem that the above method aims to solve is that when the information bit block uses an AI / ML-based encoder, the different characteristics of the information bit block and the parity bit block make the AI / ML-based encoder trained for the information bit block unsuitable for encoding the parity bit block.

[0196] In the above method, the first information bit block and the first check bit block are encoded by different encoders and correspond to different code rates, thus solving this problem.

[0197] As one embodiment, the first encoder is based on AI or ML, and the encoding of the first encoder is inference.

[0198] As one embodiment, the first encoder, based on AI or ML, includes an encoding behavior of inference.

[0199] As an example, the inference refers to AI inference or ML inference.

[0200] As one embodiment, the first encoder, based on AI or ML, is obtained through training.

[0201] As one embodiment, the first encoder based on AI or ML includes: the first encoder includes at least one AI model or ML model.

[0202] As one embodiment, the first encoder based on AI or ML includes a model of the first encoder obtained through training.

[0203] As an example, the first node sends the first signal, and the model structure and model parameters of the first encoder are known to the first node, for example, by downloading from a network device, or by being specified in a standard, or by the first node through training, or various combinations thereof. For example, the model structure or model format of the first encoder is downloaded from a network device or is specified in a standard, and the model parameters of the first encoder are obtained by the first node through training.

[0204] As a sub-implementation of the above embodiments, the sender of the first signaling and the first node have a consensus on one or more of the model structure, model format and training dataset of the first encoder.

[0205] As an example, the first node receives the first signal, and the first node and the sender of the first signaling have a consensus on one or more of the model structure, model format and training dataset of the first encoder.

[0206] The typical structure of the first encoder includes Transformer structure, RNN (Recurrent Neural Network), CNN (Conventional Neural Network), etc., or a hybrid model composed of multiple models.

[0207] In a preferred embodiment, the first encoder is based on AI or ML, while the second encoder is neither based on AI nor ML.

[0208] In a preferred embodiment, the first encoder is based on AI or ML, and the second encoder is based on one of LDPC (Low Density Parity Check) codes, polar codes, turbo codes, or convolutional codes.

[0209] The advantages of the two embodiments described above include fully utilizing properties such as correlation or semantic characteristics between information bits, greatly improving the encoding efficiency and / or transmission performance of information bit blocks using AI / ML-based encoders, while avoiding performance loss due to the fact that check bit blocks do not possess the properties of information bit blocks.

[0210] The advantages of the two embodiments described above include that they simultaneously optimize the encoding efficiency and performance of the information bit block and the parity bit block.

[0211] The advantages of the two embodiments described above include that the parity bit block uses traditional channel coding, reducing the impact on the standard.

[0212] As an example, the sender of the first signaling and the first node have some consensus on the first encoder.

[0213] As an example, the sender of the first signaling and the first node have a consensus on the model structure or model format of the first encoder.

[0214] As an example, the sender of the first signaling and the first node have a consensus on the training dataset of the first encoder.

[0215] As an example, the model refers to an AI model or an ML model.

[0216] Example 2

[0217] Example 2 illustrates a schematic diagram of a network architecture according to an embodiment of this application, as shown in Figure 2.

[0218] Figure 2 illustrates network architecture 200. Network architecture 200 is a 5G NR (New Radio) / LTE (Long-Term Evolution) / LTE-A (Long-Term Evolution Advanced) system, or a 5G+ network architecture, or a 6G network architecture, or a network architecture adopted in future evolutions by 3GPP; network architecture 200 may be referred to as 5GS (5G System) / EPS (Evolved Packet System), or 6GS (6G System); network architecture 200 includes at least one of UE (User Equipment) 201, RAN (Radio Access Network) 202, core network 210, HSS (Home Subscriber Server) / UDM (Unified Data Management) 220, and Internet service 230. The network architecture 200 can interconnect with other access networks, but these entities / interfaces are not shown for simplicity. As shown, the network architecture 200 provides packet-switched services; however, those skilled in the art will readily understand that the various concepts presented throughout this application can be extended to networks providing circuit-switched services or other cellular networks. The RAN includes node 203. The RAN may also include other nodes 204. Node 203 provides user and control plane protocol termination toward UE 201. Node 203 may be connected to other nodes 204 via an Xn interface (e.g., backhaul) / X2 interface. Node 203 may also be referred to as a base station, base transceiver station, radio base station, radio transceiver, transceiver function, basic service set (BSS), extended service set (ESS), TRP (transmitter-receiver node), or some other suitable term. The core network 210 is a 5GC (5G Core Network) / EPC (Evolved Packet Core), or the core network 210 is a 6GC; node 203 provides UE 201 with an access point to the core network 210.Examples of UE201 include cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, personal digital assistants (PDAs), satellite radios, non-terrestrial base station communications, satellite mobile communications, global positioning systems, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, drones, aircraft, narrowband IoT devices, machine-type communication devices, land vehicles, automobiles, wearable devices, or any other similar functional devices. Those skilled in the art may also refer to UE201 as a mobile station, subscriber station, mobile unit, subscriber unit, radio unit, remote unit, mobile device, radio device, wireless communication device, remote device, mobile subscriber station, access terminal, mobile terminal, wireless terminal, remote terminal, handheld device, user agent, mobile client, client, or any other suitable term. Node 203 is connected to the core network 210 via an S1 / NG interface. The core network 210 includes an MME (Mobility Management Entity) / AMF (Authentication Management Field) / SMF (Session Management Function) 211, other MMEs / AMFs / SMFs 214, an S-GW (Service Gateway) / UPF (User Plane Function) 212, and a P-GW (Packet Data Network Gateway) / UPF 213. The MME / AMF / SMF 211 is the control node that handles signaling between the UE 201 and the core network 210. Generally, the MME / AMF / SMF 211 provides bearer and connection management. All user IP (Internet Protocol) packets are transmitted through the S-GW / UPF 212, which is itself connected to the P-GW / UPF 213. The P-GW provides UE IP address allocation and other functions. The P-GW / UPF 213 is connected to the Internet service 230. Internet services 230 include operator-compliant Internet protocol services, which may specifically include Internet, intranet, IMS (IP Multimedia Subsystem), and packet switching services.

[0219] As an example, the first node includes the UE201.

[0220] As one embodiment, the second node includes the node 203.

[0221] As an example, the wireless link between the UE201 and the node203 includes a cellular link.

[0222] As an example, the sender of the first signaling includes the node 203.

[0223] As an example, the recipient of the first signaling includes the UE201.

[0224] As an example, the sender of the first signal includes the node 203.

[0225] As an example, the receiver of the first signal includes the UE201.

[0226] As an example, the sender of the first signal includes the UE201.

[0227] As an example, the receiver of the first signal includes the node 203.

[0228] As an example, the sender of the first control information includes the UE201.

[0229] As an example, the recipient of the first control information includes the node 203.

[0230] As an example, the UE201 supports AI- or ML-based operations.

[0231] As an example, node 203 supports AI- or ML-based operations.

[0232] Example 3

[0233] Example 3 illustrates a schematic diagram of an embodiment of a wireless protocol architecture for the user plane and control plane according to an embodiment of this application, as shown in Figure 3.

[0234] Example 3 illustrates a schematic diagram of an embodiment of a wireless protocol architecture for a user plane and control plane according to this application, as shown in Figure 3. Figure 3 is a schematic diagram illustrating an embodiment of a radio protocol architecture for a user plane 350 and a control plane 300. Figure 3 shows the radio protocol architecture for the control plane 300 between a first communication node device (UE, gNB, or RSU in V2X) and a second communication node device (gNB, UE, or RSU in V2X), or between two UEs, using three layers: Layer 1, Layer 2, and Layer 3. Layer 1 (L1 layer) is the lowest layer and implements various PHY (physical layer) signal processing functions. Layer 1 will be referred to herein as PHY 301. Layer 2 (L2 layer) 305 is above PHY 301 and is responsible for the link between the first communication node device and the second communication node device, or between two UEs. Layer L2 305 includes a MAC (Medium Access Control) sublayer 302, an RLC (Radio Link Control) sublayer 303, and a PDCP (Packet Data Convergence Protocol) sublayer 304, which terminate at the second communication node device. The PDCP sublayer 304 provides multiplexing between different radio bearers and logical channels. It also provides security through encrypted data packets and supports cross-cell mobility between the second communication node devices and the first communication node device. The RLC sublayer 303 provides upper-layer packet segmentation and reassembly, retransmission of lost packets, and packet reordering to compensate for out-of-order reception due to HARQ. The MAC sublayer 302 provides multiplexing between logical and transport channels. It is also responsible for allocating various radio resources (e.g., resource blocks) within a cell among the first communication node devices. Furthermore, the MAC sublayer 302 handles HARQ operations. In the control plane 300, the Radio Resource Control (RRC) sublayer 306 of Layer 3 (L3) is responsible for acquiring radio resources (i.e., radio bearers) and configuring the lower layers using RRC signaling between the second and first communication node devices. The user plane 350's radio protocol architecture includes Layer 1 (L1) and Layer 2 (L2). The radio protocol architecture for the first and second communication node devices in the user plane 350 is largely the same as the corresponding layers and sublayers in the control plane 300 for Physical Layer 351, PDCP sublayer 354 in L2 Layer 355, RLC sublayer 353 in L2 Layer 355, and MAC sublayer 352 in L2 Layer 355. However, PDCP sublayer 354 also provides header compression for upper layer data packets to reduce radio transmission overhead.The L2 layer 355 in the user plane 350 also includes an SDAP (Service Data Adaptation Protocol) sublayer 356, which is responsible for mapping between QoS streams and data radio bearers (DRBs) to support service diversity. Although not illustrated, the first communication node device may have several upper layers above the L2 layer 355, including a network layer (e.g., IP layer) terminating at the P-GW on the network side and an application layer terminating at the other end of the connection (e.g., a remote UE, server, etc.).

[0235] As an example, the wireless protocol architecture in Figure 3 is applicable to the first node.

[0236] As an example, the wireless protocol architecture in Figure 3 is applicable to the second node.

[0237] As an example, the higher layer mentioned in this application refers to the layer above the physical layer.

[0238] As an example, the first signaling is generated in the PHY301 or the PHY351.

[0239] As an example, the first signaling is generated in the RRC sublayer 306.

[0240] As an example, the first signal is generated in the PHY301 or the PHY351.

[0241] As an example, the first control information is generated in the RRC sublayer 306.

[0242] As an example, the first control information is generated in the MAC sublayer 302 or the MAC sublayer 352.

[0243] As an example, the first control information is generated in the PHY301 or the PHY351.

[0244] Example 4

[0245] Example 4 illustrates a schematic diagram of a first communication device and a second communication device according to an embodiment of this application, as shown in Figure 4. Figure 4 is a block diagram of a first communication device 410 and a second communication device 450 communicating with each other in an access network.

[0246] The first communication device 410 includes a controller / processor 475, a memory 476, a receiver processor 470, a transmitter processor 416, a multi-antenna receiver processor 472, a multi-antenna transmitter processor 471, a transmitter / receiver 418, and an antenna 420.

[0247] The second communication device 450 includes a controller / processor 459, a memory 460, a data source 467, a transmitting processor 468, a receiving processor 456, a multi-antenna transmitting processor 457, a multi-antenna receiving processor 458, a transmitter / receiver 454, and an antenna 452.

[0248] In the transmission from the first communication device 410 to the second communication device 450, at the first communication device 410, upper-layer data packets from the core network are provided to the controller / processor 475. The controller / processor 475 implements L2 layer functionality. In DL (Downlink), the controller / processor 475 provides header compression, encryption, packet segmentation and reordering, multiplexing between logical and transport channels, and radio resource allocation to the second communication device 450 based on various priority metrics. The controller / processor 475 is also responsible for HARQ operation, retransmission of lost packets, and signaling to the second communication device 450. The transmit processor 416 and the multi-antenna transmit processor 471 implement various signal processing functions for L1 layer (i.e., physical layer). Transmit processor 416 performs encoding and interleaving to facilitate forward error correction (FEC) at the second communication device 450, and constellation mapping based on various modulation schemes (e.g., binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), M-phase shift keying (M-PSK), and M-quadrature amplitude modulation (M-QAM). Multi-antenna transmit processor 471 performs digital spatial precoding on the encoded and modulated symbols, including codebook-based precoding and non-codebook-based precoding, and beamforming processing, generating one or more parallel... The transmit processor 416 then maps each parallel stream to a subcarrier, multiplexes the modulated symbols with a reference signal (e.g., a pilot) in the time and / or frequency domains, and then uses an inverse fast Fourier transform (IFFT) to generate a physical channel carrying the time-domain multicarrier symbol stream. The multi-antenna transmit processor 471 then performs transmit analog precoding / beamforming operations on the time-domain multicarrier symbol stream. Each transmitter 418 converts the baseband multicarrier symbol stream provided by the multi-antenna transmit processor 471 into an RF stream, which is then provided to a different antenna 420.

[0249] In the transmission from the first communication device 410 to the second communication device 450, at the second communication device 450, each receiver 454 receives a signal through its corresponding antenna 452. Each receiver 454 recovers the information modulated onto the radio frequency carrier and converts the radio frequency stream into a baseband multicarrier symbol stream, which is then provided to the receiver processor 456. The receiver processor 456 and the multi-antenna receiver processor 458 implement various signal processing functions of the L1 layer. The multi-antenna receiver processor 458 performs receive analog precoding / beamforming operations on the baseband multicarrier symbol stream from the receiver 454. The receiver processor 456 uses a Fast Fourier Transform (FFT) to convert the baseband multicarrier symbol stream after the receive analog precoding / beamforming operations from the time domain to the frequency domain. In the frequency domain, the physical layer data signal and the reference signal are demultiplexed by the receiver processor 456, where the reference signal is used for channel estimation, and the data signal is recovered in the multi-antenna receiver processor 458 after multi-antenna detection to recover any parallel stream destined for the second communication device 450. Symbols on each parallel stream are demodulated and recovered in the receive processor 456, generating soft decisions. The receive processor 456 then decodes and deinterleaves the soft decisions to recover the upper-layer data and control signals transmitted over the physical channel by the first communication device 410. The upper-layer data and control signals are then provided to the controller / processor 459. The controller / processor 459 implements the functions of Layer 2 (L2). The controller / processor 459 may be associated with a memory 460 storing program code and data. The memory 460 may be referred to as computer-readable media. In the DL (Layered Logic), the controller / processor 459 provides multiplexing, packet reassembly, decryption, header decompression, and control signal processing between the transmission and logical channels to recover upper-layer packets from the core network. The upper-layer packets are then provided to all protocol layers above Layer 2. Various control signals may also be provided to Layer 3 (L3) for L3 processing. The controller / processor 459 is also responsible for error detection using ACK and / or NACK protocols to support HARQ operation.

[0250] In the transmission from the second communication device 450 to the first communication device 410, at the second communication device 450, a data source 467 is used to provide upper-layer data packets to the controller / processor 459. The data source 467 represents all protocol layers above the L2 layer. Similar to the transmission functions at the first communication device 410 described in the DL, the controller / processor 459 implements header compression, encryption, packet segmentation and reordering, and multiplexing between logical and transport channels based on the radio resource allocation of the first communication device 410, implementing L2 layer functions for the user plane and control plane. The controller / processor 459 is also responsible for HARQ operations, retransmission of lost packets, and signaling to the first communication device 410. Transmit processor 468 performs modulation mapping and channel coding processing, while multi-antenna transmit processor 457 performs digital multi-antenna spatial precoding, including codebook-based and non-codebook-based precoding, and beamforming processing. Subsequently, transmit processor 468 modulates the generated parallel stream into a multi-carrier / single-carrier symbol stream. After analog precoding / beamforming operations in multi-antenna transmit processor 457, the stream is provided to different antennas 452 via transmitter 454. Each transmitter 454 first converts the baseband symbol stream provided by multi-antenna transmit processor 457 into a radio frequency symbol stream before providing it to antenna 452.

[0251] In the transmission from the second communication device 450 to the first communication device 410, the function at the first communication device 410 is similar to the receiving function at the second communication device 450 described in the transmission from the first communication device 410 to the second communication device 450. Each receiver 418 receives radio frequency signals through its corresponding antenna 420, converts the received radio frequency signals into baseband signals, and provides the baseband signals to the multi-antenna receiving processor 472 and the receiving processor 470. The receiving processor 470 and the multi-antenna receiving processor 472 jointly implement the L1 layer functions. The controller / processor 475 implements the L2 layer functions. The controller / processor 475 may be associated with a memory 476 that stores program code and data. The memory 476 may be referred to as computer-readable media. The controller / processor 475 provides multiplexing, packet reassembly, decryption, header decompression, and control signal processing between the transmission and logical channels to recover upper-layer data packets from the second communication device 450. The upper-layer data packets from the controller / processor 475 may be provided to the core network. The controller / processor 475 is also responsible for error detection using ACK and / or NACK protocols to support HARQ operation.

[0252] As one embodiment, the second communication device 450 includes: at least one processor and at least one memory, the at least one memory including computer program code; the at least one memory and the computer program code are configured to be used with the at least one processor. The second communication device 450 is equipped with at least: receiving the first signaling; receiving the first signal or transmitting the first signal. The first signaling indicates that scheduling information, a first bit block, and a second bit block are used together to generate the first signal, the first bit block depending on the output of a first encoder, the input of the first encoder including a first information bit block, the second bit block depending on the output of a second encoder, the input of the second encoder including a first check bit block, the first information bit block being used to generate the first check bit block; the ratio between the size of the input of the first encoder and the size of the first bit block is not equal to the ratio between the size of the input of the second encoder and the size of the second bit block.

[0253] As one embodiment, the second communication device 450 includes: a memory storing a computer-readable instruction program that produces actions when executed by at least one processor, the actions including: receiving the first signaling; receiving the first signal or sending the first signal.

[0254] As one embodiment, the first communication device 410 includes: at least one processor and at least one memory, the at least one memory including computer program code; the at least one memory and the computer program code are configured to be used with the at least one processor. The first communication device 410 is equipped with at least: transmitting a first signaling; transmitting the first signal or receiving the first signal. The first signaling indicates scheduling information for the first signal; a first bit block and a second bit block are jointly used to generate the first signal, the first bit block depending on the output of a first encoder, the input of the first encoder including a first information bit block, the second bit block depending on the output of a second encoder, the input of the second encoder including a first check bit block, the first information bit block being used to generate the first check bit block; the ratio between the size of the input of the first encoder and the size of the first bit block is not equal to the ratio between the size of the input of the second encoder and the size of the second bit block.

[0255] As one embodiment, the first communication device 410 includes: a memory storing a computer-readable instruction program that produces actions when executed by at least one processor, the actions including: sending a first signaling; sending a first signal or receiving the first signal.

[0256] As an example, the first node in this application includes the second communication device 450.

[0257] As an example, the second node in this application includes the first communication device 410.

[0258] As an example, at least one of {the antenna 452, the receiver 454, the receiving processor 456, the multi-antenna receiving processor 458, the controller / processor 459, the memory 460, and the data source 467} is used to receive the first signaling; at least one of {the antenna 420, the transmitter 418, the transmitting processor 416, the multi-antenna transmitting processor 471, the controller / processor 475, and the memory 476} is used to transmit the first signaling.

[0259] As an example, at least one of {the antenna 452, the receiver 454, the receiving processor 456, the multi-antenna receiving processor 458, the controller / processor 459, the memory 460, and the data source 467} is used to receive the first signal; at least one of {the antenna 420, the transmitter 418, the transmitting processor 416, the multi-antenna transmitting processor 471, the controller / processor 475, and the memory 476} is used to transmit the first signal.

[0260] As an example, at least one of {the antenna 420, the receiver 418, the receiving processor 470, the multi-antenna receiving processor 472, the controller / processor 475, and the memory 476} is used to receive the first signal; and at least one of {the antenna 452, the transmitter 454, the transmitting processor 468, the multi-antenna transmitting processor 457, the controller / processor 459, the memory 460, and the data source 467} is used to transmit the first signal.

[0261] As an example, at least one of {the antenna 420, the receiver 418, the receiving processor 470, the multi-antenna receiving processor 472, the controller / processor 475, and the memory 476} is used to receive the first control information; at least one of {the antenna 452, the transmitter 454, the transmitting processor 468, the multi-antenna transmitting processor 457, the controller / processor 459, the memory 460, and the data source 467} is used to transmit the first control information.

[0262] Example 5

[0263] Example 5 illustrates a flowchart of transmission between a first node and a second node according to an embodiment of this application, as shown in Figure 5. In Figure 5, the second node U1 and the first node U2 are communication nodes transmitting via an air interface. In Figure 5, the steps in blocks F51 to F54 are optional.

[0264] For the second node U1, in step S511, the first signaling is sent; in step S512, the encoding of the first encoder is performed; in step S513, the encoding of the second encoder is performed; in step S5101, the encoding of each of the K encoders except the first encoder is performed; and in step S514, the first signal is sent.

[0265] For the first node U2, in step S5201, the decoder corresponding to the first encoder is deployed; in step S5202, the decoder corresponding to at least one encoder other than the first encoder among the K encoders is deployed; in step S521, the first signaling is received; in step S522, the first signal is received; in step S523, the decoding of the decoder corresponding to the first encoder is performed; in step S524, the decoding of the decoder corresponding to the second encoder is performed; in step S5203, the decoding of the decoder corresponding to each encoder other than the first encoder among the K encoders is performed.

[0266] In embodiment 5, the first signaling indicates scheduling information for the first signal; a first bit block and a second bit block are used together to generate the first signal, the first bit block depends on the output of the first encoder, the input of the first encoder includes a first information bit block, the second bit block depends on the output of the second encoder, the input of the second encoder includes a first check bit block, the first information bit block is used to generate the first check bit block; the ratio between the size of the input of the first encoder and the size of the first bit block is not equal to the ratio between the size of the input of the second encoder and the size of the second bit block.

[0267] As an example, the first node U2 is the first node in this application.

[0268] As an example, the second node U1 is the second node in this application.

[0269] As one embodiment, the air interface between the second node U1 and the first node U2 includes a wireless interface between the base station equipment and the user equipment.

[0270] As one embodiment, the air interface between the second node U1 and the first node U2 includes a wireless interface between the relay node device and the user equipment.

[0271] As one embodiment, the air interface between the second node U1 and the first node U2 includes the interface between the core network equipment and the user equipment.

[0272] As one embodiment, the air interface between the second node U1 and the first node U2 includes the interface between the OTT server (Over-The-Top server) and the user equipment.

[0273] As one embodiment, the air interface between the second node U1 and the first node U2 includes the interface between the NAS (Network Access Server) device and the user equipment.

[0274] As one embodiment, the air interface between the second node U1 and the first node U2 includes a wireless interface between user equipment.

[0275] As one embodiment, the first node U2 includes a terminal.

[0276] As one embodiment, the first node U2 includes a user equipment.

[0277] As one embodiment, the second node U1 includes the serving cell sustaining base station of the first node U2.

[0278] As one embodiment, the second node U1 includes an OTT server (Over-The-Top server).

[0279] As an example, the second node U1 includes OAM (Operation Administration and Maintenance).

[0280] As one embodiment, the second node U1 includes a NAS device.

[0281] As one embodiment, the second node U1 includes core network equipment.

[0282] As an example, the first signaling is transmitted on the PDCCH (Physical Downlink Control Channel).

[0283] As an example, the first signaling is transmitted on the PDSCH.

[0284] As an example, the first node receives the first signal, which is transmitted on the PDSCH.

[0285] As an example, the output of the decoder corresponding to the first encoder is used to recover the first information bit block.

[0286] As an example, the output of the decoder corresponding to the first encoder is used by the first node U2 to recover the first information bit block.

[0287] As an example, the first signal is used to generate the input of the decoder corresponding to the first encoder.

[0288] In a preferred embodiment, the decoding behavior of the decoder corresponding to the first encoder is inference.

[0289] As an example, the decoding of the decoder corresponding to the first encoder is performed earlier than the decoding of the decoder corresponding to the second encoder.

[0290] As an example, the decoding of the decoder corresponding to the first encoder is performed later than the decoding of the decoder corresponding to the second encoder.

[0291] As an example, the decoding execution of the decoder corresponding to the first encoder and the decoding execution of the decoder corresponding to the second encoder occupy at least partially overlapping time-domain resources.

[0292] In a preferred embodiment, the decoder corresponding to the first encoder is based on AI or ML.

[0293] As an example, the decoder corresponding to the first encoder is obtained through training.

[0294] As an example, the decoder corresponding to the first encoder includes at least one AI model or ML model.

[0295] As an example, the model of the decoder corresponding to the first encoder is obtained through training.

[0296] As an example, the model structure and model parameters of the decoder corresponding to the first encoder are known to the first node, for example, by downloading from a network device, or by being specified in a standard, or by the first node through training, or various combinations thereof. For example, the model structure or model format of the decoder corresponding to the first encoder is downloaded from a network device or is specified in a standard, and the model parameters of the decoder corresponding to the first encoder are obtained by the first node through training.

[0297] As a sub-implementation of the above embodiments, the sender of the first signaling and the first node have a consensus on one or more of the model structure, model format and training dataset of the decoder corresponding to the first encoder.

[0298] The typical structure of the decoder corresponding to the first encoder includes Transformer structure, RNN, CNN, etc., or a hybrid model composed of multiple models.

[0299] In a preferred embodiment, the decoder corresponding to the second encoder is neither based on AI nor on ML.

[0300] In a preferred embodiment, the decoder corresponding to the second encoder is based on one of LDPC codes, polar codes, turbo codes, or convolutional codes.

[0301] As an example, the first encoder and the decoder corresponding to the first encoder are jointly trained.

[0302] As an example, the first encoder and the decoder corresponding to the first encoder are trained separately but share the same training dataset.

[0303] As an example, the first encoder and the decoder corresponding to the first encoder are trained separately, and the training dataset of the first encoder and the training dataset of the decoder corresponding to the first encoder at least partially overlap.

[0304] As an example, the training of the first encoder and the training of the decoder corresponding to the first encoder are performed on the same node.

[0305] As an example, the training of the first encoder and the training of the decoder corresponding to the first encoder are performed on different nodes.

[0306] As an example, the training executor of the first encoder and the training executor of the decoder corresponding to the first encoder are the same network device or core network device.

[0307] As one embodiment, the training executor of the first encoder and the training executor of the decoder corresponding to the first encoder are different network devices or core network devices.

[0308] As one embodiment, the training executor of the first encoder is the sender of the first signaling, and the training executor of the decoder corresponding to the first encoder is the first node or a network device different from the sender of the first signaling.

[0309] As an example, the training of an encoder refers to the training of the model of the encoder.

[0310] As an example, training a decoder corresponding to an encoder refers to training the model of the decoder corresponding to the encoder.

[0311] As an example, the decoding behavior of the decoder corresponding to the first encoder is the inverse operation of the encoding behavior of the first encoder.

[0312] As an example, the encoding behavior of the first encoder is reasoning.

[0313] As an example, the encoding behavior of the second encoder is not reasoning.

[0314] As an example, the decoding of the decoder corresponding to the first encoder is earlier than the decoding of the decoder corresponding to the second encoder.

[0315] As an example, the decoding of the decoder corresponding to the first encoder is later than the decoding of the decoder corresponding to the second encoder.

[0316] As one embodiment, the decoding of the decoder corresponding to the first encoder and the decoding of the decoder corresponding to the second encoder occupy at least partially overlapping time-domain resources.

[0317] As an example, the first signaling indicates a first MCS; the ratio between the size of the input of the first encoder and the size of the first bit block depends on the first MCS and a first factor, and the ratio between the size of the input of the second encoder and the size of the second bit block depends on only the first MCS of the first MCS and the first factor.

[0318] As a sub-implementation of the above embodiments, the size of the first information bit block depends on the first factor.

[0319] As an example, the first encoder is one of M encoders, where M is a positive integer greater than 1; the M encoders correspond one-to-one with the M factors, and the first factor is the factor corresponding to the first encoder.

[0320] As an example, the first signaling indicates the first factor.

[0321] As an example, the first factor depends on the first MCS.

[0322] As an example, K bit blocks and the second bit block are used together to generate the first signal, where K is a positive integer greater than 1; the first bit block is one of the K bit blocks, each of the K bit blocks depends on the outputs obtained by K encoders with K information bit blocks as input, and the first information bit block is one of the K information bit blocks; the second bit block depends on the output obtained by the second encoder with a third bit block as input, the third bit block includes K check bit blocks, and the K information bit blocks are used to generate the K check bit blocks.

[0323] As one embodiment, the first signal carries the K bit blocks and the second bit block.

[0324] As an example, the first signal depends on the output of the K bit blocks and the second bit block after sequential scrambling, modulation, layer mapping and resource block mapping.

[0325] As an example, the first signal is generated by sequentially scrambling, modulating, layer mapping, and resource block mapping of the K bit blocks and the second bit block.

[0326] As one embodiment, after the K bit blocks and the second bit block are concatenated, they are sequentially subjected to scrambling, modulation, layer mapping, and resource block mapping.

[0327] As an example, the step in block F54 of Figure 5 exists, and the method used in the first node for wireless communication includes performing decoding by the decoder corresponding to each of the K encoders except the first encoder.

[0328] As an example, the step in block F53 of Figure 5 exists, and the method described above for the second node used in wireless communication includes performing encoding of each of the K encoders except the first encoder.

[0329] As an example, the steps in blocks F53 and F54 of Figure 5 are both present.

[0330] As an example, the ratio between the size of the input to the second encoder and the size of the second bit block depends on K.

[0331] As an example, the steps in block F51 of Figure 5 are present, and the method described above for the first node used in wireless communication includes deploying the decoder corresponding to the first encoder.

[0332] As an example, the step in block F51 of Figure 5 is not present, and the decoder corresponding to the first encoder does not need to be deployed.

[0333] As a sub-implementation of the above embodiments, the training of the decoder corresponding to the first encoder is performed by the first node.

[0334] As an example, the steps in block F52 of Figure 5 are present, and the method described above for the first node used in wireless communication includes deploying a decoder corresponding to at least one of the K encoders other than the first encoder.

[0335] As an example, the step in block F52 of Figure 5 is not present, and the decoder corresponding to any of the K encoders other than the first encoder does not need to be deployed.

[0336] As a sub-implementation of the above embodiment, all K encoders are the first encoder.

[0337] As a sub-example of the above embodiment, the training of the decoder corresponding to any encoder among the K encoders other than the first encoder is performed by the first node.

[0338] Example 6

[0339] Example 6 illustrates a flowchart of transmission between a first node and a second node according to an embodiment of this application, as shown in Figure 6. In Figure 6, the second node U3 and the first node U4 are communication nodes transmitting via an air interface. In Figure 6, the steps in blocks F61 to F65 are optional.

[0340] For the second node U3, in step S631, a first signaling is sent; in step S6301, a first control information is received; in step S632, a first signal is received; in step S633, the decoding of the decoder corresponding to the first encoder is performed; in step S634, the decoding of the decoder corresponding to the second encoder is performed; in step S6302, the decoding of the decoder corresponding to each of the K encoders except the first encoder is performed.

[0341] For the first node U4, in step S6401, the first encoder is deployed; in step S6402, at least one encoder other than the first encoder is deployed from among the K encoders; in step S641, the first signaling is received; in step S6403, the first control information is sent; in step S642, the encoding of the first encoder is executed; in step S643, the encoding of the second encoder is executed; in step S6404, the encoding of each encoder other than the first encoder from among the K encoders is executed; and in step S644, the first signal is sent.

[0342] In embodiment 6, the first signaling indicates scheduling information for the first signal; a first bit block and a second bit block are used together to generate the first signal, the first bit block depends on the output of the first encoder, the input of the first encoder includes a first information bit block, the second bit block depends on the output of the second encoder, the input of the second encoder includes a first check bit block, the first information bit block is used to generate the first check bit block; the ratio between the size of the input of the first encoder and the size of the first bit block is not equal to the ratio between the size of the input of the second encoder and the size of the second bit block.

[0343] As an example, the first node U4 is the first node in this application.

[0344] As an example, the second node U3 is the second node in this application.

[0345] As an example, the first node sends the first signal, which is transmitted on the PUSCH.

[0346] As an example, the encoding of the first encoder is earlier than the encoding of the second encoder.

[0347] As an example, the encoding of the first encoder is later than the encoding of the second encoder.

[0348] As an example, the encoding of the first encoder and the encoding of the second encoder occupy at least partially overlapping temporal domain resources.

[0349] As an example, the first signaling indicates a first MCS; the ratio between the size of the input of the first encoder and the size of the first bit block depends on the first MCS and a first factor, and the ratio between the size of the input of the second encoder and the size of the second bit block depends on only the first MCS of the first MCS and the first factor.

[0350] As an example, the first encoder is one of M encoders, where M is a positive integer greater than 1; the M encoders correspond one-to-one with the M factors, and the first factor is the factor corresponding to the first encoder.

[0351] As an example, the first signaling indicates the first factor.

[0352] As an example, the step in block F63 of Figure 6 exists, where the first control information indicates the first factor.

[0353] As an example, the first control information is transmitted on the PUCCH (Physical Uplink Control Channel).

[0354] As an example, the first control information is transmitted on the PUSCH.

[0355] As one example, the transmission of the first control information is later than the reception of the first signaling.

[0356] As an example, the transmission of the first control information precedes the reception of the first signaling.

[0357] As an example, the first factor depends on the first MCS.

[0358] As an example, K bit blocks and the second bit block are used together to generate the first signal, where K is a positive integer greater than 1; the first bit block is one of the K bit blocks, each of the K bit blocks depends on the outputs obtained by K encoders with K information bit blocks as input, and the first information bit block is one of the K information bit blocks; the second bit block depends on the output obtained by the second encoder with a third bit block as input, the third bit block includes K check bit blocks, and the K information bit blocks are used to generate the K check bit blocks.

[0359] As an example, the step in block F64 of Figure 6 exists, and the method described above for the first node used in wireless communication includes performing encoding of each of the K encoders except the first encoder.

[0360] As an example, the step in block F65 of Figure 6 exists, and the method described above for the second node used in wireless communication includes performing decoding of the decoder corresponding to each of the K encoders except the first encoder.

[0361] As an example, the steps in blocks F64 and F65 of Figure 6 are both present.

[0362] As an example, the ratio between the size of the input to the second encoder and the size of the second bit block depends on K.

[0363] As an example, the step in block F61 of Figure 6 is present, and the method described above for the first node used in wireless communication includes deploying the first encoder.

[0364] As an example, the step in block F61 of Figure 6 is not present, and the first encoder does not need to be deployed.

[0365] As a sub-implementation of the above embodiments, the training of the first encoder is performed by the first node.

[0366] As an example, the step in block F62 of Figure 6 exists, and the method described above for the first node used in wireless communication includes deploying at least one encoder other than the first encoder among the K encoders.

[0367] As an example, the step in block F62 of Figure 6 is not present, and none of the K encoders other than the first encoder needs to be deployed.

[0368] As a sub-implementation of the above embodiment, all K encoders are the first encoder.

[0369] As a sub-example of the above embodiment, the training of any encoder among the K encoders other than the first encoder is performed by the first node.

[0370] Example 7

[0371] Example 7 illustrates a schematic diagram of a first signal carrying a first bit block and a second bit block according to an embodiment of this application, as shown in Figure 7. In Figure 7(a), the first signal is the output of the first bit block and the second bit block after undergoing some or all of the following processes sequentially: scrambling, modulation, layer mapping, transform precoding, precoding, resource block mapping, OFDM (Orthogonal Frequency Division Multiplex) symbol generation, modulation, and upconversion. In Figure 7(b), the first signal is the output of the first bit block and the second bit block after undergoing some or all of the following processes sequentially: scrambling, modulation, layer mapping, antenna port mapping, resource block mapping, OFDM symbol generation, modulation, and upconversion. In Figure 7(a), transform precoding is optional.

[0372] As one embodiment, after the first bit block and the second bit block are concatenated, they sequentially undergo some or all of the following processes: scrambling, modulation, layer mapping, conversion precoding, precoding, resource block mapping, OFDM symbol generation, modulation, and upconversion.

[0373] As one embodiment, after the first bit block and the second bit block are concatenated, they are sequentially subjected to scrambling, modulation, layer mapping, antenna port mapping, resource block mapping, OFDM symbol generation, modulation and upconversion, some or all of which are involved.

[0374] Example 8

[0375] Example 8 illustrates a schematic diagram of a first bit block, a first information bit block, a second bit block, and a first check bit block according to an embodiment of this application; as shown in Figure 8. In Example 8, the first bit block depends on the output obtained by the first encoder with the first information bit block as input, and the second bit block depends on the output obtained by the second encoder with the first check bit block as input.

[0376] In Figure 8(a), the first bit block is the output obtained by the first encoder with the first information bit block as input, and the second bit block is the output obtained by the second encoder with the first check bit block as input; in Figure 8(b), the first bit block is the output obtained by the first encoder with the first information bit block as input after rate matching, and the second bit block is the output obtained by the second encoder with the first check bit block as input after rate matching.

[0377] As one embodiment, the input of the first encoder is the first information bit block.

[0378] As an example, the size of the input to the first encoder refers to the size of the first information bit block.

[0379] As one embodiment, the first bit block depends on the output obtained by the first encoder with the first information bit block as input, and the size of the input of the first encoder refers to the size of the first information bit block.

[0380] As one embodiment, the first bit block depends on the output obtained by the first encoder with the first information bit block as input, and the ratio between the size of the input of the first encoder and the size of the first bit block refers to the ratio between the size of the first information bit block and the size of the first bit block.

[0381] As one embodiment, the input of the second encoder is the first check bit block.

[0382] As an example, the size of the input to the second encoder refers to the size of the first check bit block.

[0383] As one embodiment, the second bit block depends on the output obtained by the second encoder with the first check bit block as input, wherein the size of the input of the second encoder refers to the size of the first check bit block.

[0384] As one embodiment, the second bit block depends on the output obtained by the second encoder with the first check bit block as input, and the ratio between the size of the input of the second encoder and the size of the second bit block refers to the ratio between the size of the first check bit block and the size of the second bit block.

[0385] As an example, the ratio between the size of the input of the first encoder and the size of the first bit block is the bit rate of the first information bit block.

[0386] As one embodiment, the first bit block depends on the output obtained by the first encoder with the first information bit block as input, and the ratio between the size of the input of the first encoder and the size of the first bit block is the bit rate of the first information bit block.

[0387] As an example, the ratio between the size of the input of the second encoder and the size of the second bit block is the bit rate of the first check bit block.

[0388] As one embodiment, the second bit block depends on the output obtained by the second encoder with the first parity bit block as input, and the ratio between the size of the input of the second encoder and the size of the second bit block is the bit rate of the first parity bit block.

[0389] As an example, the ratio between the size of the input of the first encoder and the size of the first bit block is less than the ratio between the size of the input of the second encoder and the size of the second bit block.

[0390] The advantages of the above method include improving the coding efficiency of information bit blocks by utilizing the characteristics of information bits (such as correlation, semantics, etc.) while ensuring the performance of parity bit blocks.

[0391] As an example, the ratio between the size of the input of the first encoder and the size of the first bit block is a positive real number less than 1.

[0392] As an example, the ratio between the size of the input of the second encoder and the size of the second bit block is a positive real number less than 1.

[0393] Example 9

[0394] Example 9 illustrates a schematic diagram of a first encoder according to an embodiment of the present application, where the ratio between the size of the input and the size of the first bit block depends on a first MCS and a first factor, and the ratio between the size of the input and the size of the second bit block depends on only the first MCS and the first factor; as shown in Figure 9.

[0395] As an example, the scheduling information of the first signal includes the first MCS.

[0396] As an example, the first factor is generated based on inference.

[0397] As an example, the first factor is generated based on AI or ML.

[0398] As an example, the first factor is a positive rational number.

[0399] As an example, the first factor is a positive real number.

[0400] As an example, the first factor is not less than 1.

[0401] As an example, the first factor is no greater than 3.

[0402] As an example, the first factor is not less than 1 and is less than 3.

[0403] As an example, the first MCS indicates a first code rate, and the product of the first code rate and the first factor is less than 1.

[0404] As an example, the first factor is configurable.

[0405] As an example, the first factor is a higher-layer signaling configuration.

[0406] As an example, the first factor is configured for the first node.

[0407] As an example, the first factor depends on the UE (User Equipment) capabilities of the first node.

[0408] As an example, the first factor is reported by the first node.

[0409] As an example, the first encoder corresponds to the first factor.

[0410] As an example, the first encoder corresponds only to the first factor.

[0411] As an example, the first encoder corresponds to multiple factors, and the first factor is one of the multiple factors.

[0412] As an example, the first factor is configured to the first encoder.

[0413] As one embodiment, the configuration information of the first encoder includes the first factor.

[0414] As an example, the parameters of the first encoder include the first factor.

[0415] As an example, the model parameters of the first encoder include the first factor.

[0416] As an example, the first factor is used to adjust the bit rate of a bit block using the first encoder.

[0417] As an example, the first factor is used only to adjust the bit rate of bit blocks using the first encoder.

[0418] As an example, the calculation of the TBS (Transport Block Size) of the TB using the first encoder depends on the first factor.

[0419] As an example, the calculation of TBS using only the TB of the first encoder depends on the first factor.

[0420] As an example, the first factor depends on the training of the first encoder.

[0421] As an example, the training result of the first encoder includes the first factor.

[0422] As an example, the first factor is indicated to the first node by the training executor of the first encoder.

[0423] The advantages of the above method include that the first factor and the first encoder are matched, which optimizes the efficiency and performance of AI-based coding.

[0424] As a sub-implementation of the above embodiment, the first node sends the first signal.

[0425] As one embodiment, the first factor is indicated by the training executor of the first encoder to the sender of the first signaling.

[0426] The advantages of the above method include that the first factor and the first encoder are matched, which optimizes the efficiency and performance of AI-based coding.

[0427] As a sub-implementation of the above embodiment, the first node receives the first signal.

[0428] As an example, the model refers to an AI model or an ML model.

[0429] As an example, the decoder corresponding to the first encoder corresponds to the first factor.

[0430] As an example, the decoder corresponding to the first encoder corresponds only to the first factor.

[0431] As an example, the decoder corresponding to the first encoder corresponds to multiple factors, and the first factor is one of the multiple factors.

[0432] As an example, the first factor is configured to the decoder corresponding to the first encoder.

[0433] As an example, the configuration information of the decoder corresponding to the first encoder includes the first factor.

[0434] As an example, the parameters of the decoder corresponding to the first encoder include the first factor.

[0435] As an example, the model parameters of the decoder corresponding to the first encoder include the first factor.

[0436] As an example, the first factor is used to adjust the bit rate of the bit block using the decoder corresponding to the first encoder.

[0437] As an example, the first factor is used only to adjust the bit rate of the bit block using the decoder corresponding to the first encoder.

[0438] As an example, the calculation of the TBS of the TB of the decoder corresponding to the first encoder depends on the first factor.

[0439] As an example, the calculation of the TBS of the decoder corresponding to the first encoder only depends on the first factor.

[0440] As an example, the first factor depends on the training of the decoder corresponding to the first encoder.

[0441] As an example, the training result of the decoder corresponding to the first encoder includes the first factor.

[0442] As an example, the first channel corresponds to the first factor.

[0443] As an example, the first channel corresponds only to the first factor.

[0444] As an example, the first channel corresponds to multiple factors, and the first factor is one of the multiple factors.

[0445] As an example, the first factor is used to adjust the code rate of the bit block from the first channel.

[0446] As an example, the first factor is used only to adjust the code rate of the bit blocks from the first channel.

[0447] As an example, the calculation of TBS of TB from the first channel depends on the first factor.

[0448] As an example, the calculation of TBS for TB from only the first channel depends on the first factor.

[0449] As one example, the first factor depends on the training of an encoder, which is used for bit blocks from the first channel.

[0450] As one example, the first factor depends on the training of an encoder, the training dataset of which includes bit blocks from the first channel.

[0451] As an example, the training result of an encoder includes the first factor, and the training dataset of the encoder includes bit blocks from the first channel.

[0452] As an example, the first MCS indicates a first bit rate, and the ratio between the size of the input of the first encoder and the size of the first bit block depends on the first bit rate and the first factor.

[0453] As an example, the ratio between the size of the input of the first encoder and the size of the first bit block depends on the product of the first bit rate and the first factor.

[0454] As an example, the ratio between the size of the input of the first encoder and the size of the first bit block is equal to the product of the first code rate and the first factor.

[0455] As an example, the ratio between the size of the input of the first encoder and the size of the first bit block increases with the increase of the first bit rate.

[0456] As an example, the ratio between the size of the input of the first encoder and the size of the first bit block increases as the first factor increases.

[0457] As an example, the ratio between the size of the input of the first encoder and the size of the first bit block increases as the product of the first code rate and the first factor increases.

[0458] As an example, when the product of the first code rate and the first factor is equal to C1, the ratio between the size of the input of the first encoder and the size of the first bit block is equal to D1; when the product of the first code rate and the first factor is equal to C2, the ratio between the size of the input of the first encoder and the size of the first bit block is equal to D2; C1 is greater than C2, and D1 is not less than D2.

[0459] As an example, the ratio between the size of the input of the second encoder and the size of the second bit block does not depend on the first factor.

[0460] As an example, the first MCS indicates a first bit rate, and the ratio between the size of the input of the second encoder and the size of the second bit block depends on the first bit rate.

[0461] As an example, the first MCS indicates a first bit rate, and the ratio between the size of the input of the second encoder and the size of the second bit block is equal to the first bit rate.

[0462] As an example, the first MCS indicates a first bit rate, and the ratio between the size of the input of the second encoder and the size of the second bit block increases as the first bit rate increases.

[0463] As an example, when the first bit rate is equal to C3, the ratio between the size of the input of the second encoder and the size of the second bit block is equal to D3; when the first bit rate is equal to C4, the ratio between the size of the input of the second encoder and the size of the second bit block is equal to D4; C3 is greater than C4, and D3 is not less than D4.

[0464] As one example, the size of the second bit block depends on the first MCS.

[0465] As one embodiment, the size of the second bit block depends only on the first MCS and the first factor.

[0466] As an example, the first MCS indicates a first code rate, and the size of the second bit block depends on the first code rate.

[0467] As an example, the size of the second bit block decreases as the first code rate increases.

[0468] As an example, when the first code rate is equal to C3, the size of the second bit block is equal to B3; when the first code rate is equal to C4, the size of the second bit block is equal to B4; C3 is greater than C4, and B3 is not greater than B4.

[0469] Example 10

[0470] Example 10 illustrates a schematic diagram of the size dependence of a first information bit block on a first factor according to an embodiment of the present application; as shown in Figure 10.

[0471] As an example, the size of the first information bit block increases with the increase of the first factor.

[0472] As an example, when the first factor is equal to A1, the size of the first information bit block is equal to B1; when the first factor is equal to A2, the size of the first information bit block is equal to B2; A1 is greater than A2, and B1 is not less than B2.

[0473] As an example, the size of the first information bit block depends on the first factor, the first MCS, the first number of symbols, and the first number of RBs (Resource Blocks); the first signaling indicates the first number of symbols and the first number of RBs.

[0474] As an example, the first symbol number is the number of symbols allocated to the PDSCH or PUSCH carrying the first signal.

[0475] As a sub-implementation of the above embodiments, the symbols include OFDM symbols.

[0476] As a sub-implementation of the above embodiments, the symbols include symbols obtained after the output of the transformation precoding is processed by OFDM symbol generation.

[0477] As a sub-implementation of the above embodiments, the symbol refers to the OFDM symbol.

[0478] As an example, the first RB number is the total number of RBs allocated to the first node.

[0479] As one embodiment, the RB includes a PRB (Physical Resource Block).

[0480] As an example, RB refers to PRB.

[0481] Example 11

[0482] Example 11 illustrates a schematic diagram of M encoders and M factors according to an embodiment of this application, as shown in Figure 11. In Example 11, the first encoder is one of the M encoders, and the M encoders and M factors correspond one-to-one, with the first factor being the factor corresponding to the first encoder. In Figure 11, the M encoders are represented as encoder #0, ..., encoder #(M-1); and the M factors are represented as factor #0, ..., factor #(M-1).

[0483] As a preferred embodiment, any one of the M encoders is based on AI or ML.

[0484] As an example, the encoding of any one of the M encoders is inference.

[0485] As an example, the encoding behavior of any one of the M encoders is inference.

[0486] As an example, any one of the M encoders is obtained through training.

[0487] As an example, any one of the M encoders includes at least one AI model or ML model.

[0488] As an example, the first node sends the first signal, and the model structure and model parameters of any of the M encoders are known to the first node, for example, by downloading from a network device, or by being specified in a standard, or by the first node through training, or a combination of the above.

[0489] As a sub-implementation of the above embodiments, the sender of the first signaling and the first node have consensus on one or more of the model structure, model format and training dataset of any of the M encoders.

[0490] As an example, the first node receives the first signal, and the first node and the sender of the first signaling have a consensus on one or more of the model structure, model format and training dataset of any of the M encoders.

[0491] As an example, each of the M encoders corresponds to a logical channel.

[0492] As an example, any one of the M encoders corresponds to a logical channel group.

[0493] As an example, any one of the M encoders corresponds to a radio bearer.

[0494] As an example, any one of the M encoders corresponds to a type of service.

[0495] As an example, any one of the M encoders corresponds to a service type.

[0496] As an example, among the M encoders, two encoders correspond to different logical channels.

[0497] As an example, among the M encoders, two encoders correspond to different logical channel groups.

[0498] As an example, among the M encoders, two encoders correspond to different wireless bearers.

[0499] As an example, among the M encoders, two encoders correspond to different service types.

[0500] As an example, any two of the M encoders correspond to different logical channels.

[0501] As an example, any two encoders among the M encoders correspond to different logical channel groups.

[0502] As an example, any two of the M encoders correspond to different wireless bearers.

[0503] As an example, any two of the M encoders correspond to different service types.

[0504] As an example, the M encoders correspond to the same function.

[0505] As an example, all M encoders are used for PDSCH or all are used for PUSCH.

[0506] As an example, all M encoders are used for encoding PDSCH or all are used for encoding PUSCH.

[0507] As an example, the M encoders are all different from each other.

[0508] As an example, any two of the M encoders include different models.

[0509] As an example, the M encoders are trained independently.

[0510] As an example, the M encoders are trained using different training datasets.

[0511] As an example, any one of the M encoders corresponds to one channel, and there are two encoders among the M encoders that correspond to different channels.

[0512] As an example, the M encoders each correspond to M channels.

[0513] As an example, the M channels are all different from each other.

[0514] As an example, the first channel is one of the M channels.

[0515] As an example, one channel corresponds to one logical channel.

[0516] As an example, one channel corresponds to one logical channel group.

[0517] As an example, one channel corresponds to one radio bearer.

[0518] As an example, one channel corresponds to one type of service.

[0519] As an example, one channel corresponds to one type of service.

[0520] As an example, one channel corresponds to one channel from the RLC layer to the MAC layer.

[0521] As an example, one channel corresponds to a channel from the layer above the MAC layer to the MAC layer.

[0522] As an example, one channel corresponds to a channel from the layer above the RLC layer to the MAC layer.

[0523] As an example, a channel corresponds to one of the TM, UM, or AM of the RLC layer.

[0524] As an example, a channel corresponds to one of the TM, UM, or AM layers above the RLC layer.

[0525] As an example, one encoder corresponding to one channel means that the encoder is used to transmit a block of bits on the channel.

[0526] As an example, one encoder corresponding to one channel means that the encoder is only used for the bit blocks transmitted on the one channel.

[0527] As a sub-example of the above embodiment, the encoder is not used for bit blocks transmitted on a different channel than the one described above.

[0528] As one example, the transmission of a bit block on a channel includes the bit block originating from the channel.

[0529] As an example, the first encoder corresponds to the first channel.

[0530] As an example, among the M encoders, only the first encoder corresponds to the first channel.

[0531] As an example, any two encoders among the M encoders correspond to different channels and have different models.

[0532] As an example, the first factor is the factor among the M factors that corresponds to the first encoder.

[0533] As an example, the M factors are configured separately.

[0534] As an example, the M factors are determined separately.

[0535] As an example, the M factors are trained or optimized separately.

[0536] As an example, the M factors are respectively configured to the M encoders.

[0537] As an example, the configuration information of the M encoders includes the M factors respectively.

[0538] As an example, the parameters of the M encoders each include the M factors.

[0539] As an example, the model parameters of the M encoders each include the M factors.

[0540] As an example, for any of the M encoders, the calculation of the TBS of the TB carried by the PDSCH or PUSCH of any encoder depends on the factor corresponding to any of the M factors.

[0541] As an example, for any one of the M factors, the calculation of the TBS of the TB carried by the PDSCH or PUSCH of the encoder corresponding to that factor depends only on that factor.

[0542] As an example, the M factors each depend on the training of the M encoders.

[0543] As an example, the training results of the M encoders each include the M factors.

[0544] As an example, the M factors are respectively instructed to the first node by the training executors of the M encoders.

[0545] As a sub-implementation of the above embodiment, the first node sends the first signal.

[0546] As one embodiment, the M factors are respectively instructed by the training executors of the M encoders to the sender of the first signaling.

[0547] As a sub-implementation of the above embodiment, the first node receives the first signal.

[0548] As an example, the model refers to an AI model or an ML model.

[0549] As an example, the first node determines the first encoder itself from the M encoders.

[0550] As a sub-implementation of the above embodiment, the first node sends the first signal.

[0551] As an example, the sender of the first signaling determines the first encoder from the M encoders itself.

[0552] As a sub-implementation of the above embodiment, the first node receives the first signal.

[0553] As one embodiment, the first node or the sender of the first signaling selects the encoder corresponding to the first channel from the M encoders as the first encoder.

[0554] Example 12

[0555] Example 12 illustrates a schematic diagram of a first signaling instruction for a first factor according to an embodiment of this application; as shown in Figure 12.

[0556] As one embodiment, the first node receives the first signal, and the first signaling indicates the first factor.

[0557] As an example, the first signaling explicitly indicates the first factor.

[0558] As an example, the first signaling indicates the value of the first factor.

[0559] As an example, the first signaling indicates the first factor from the M factors.

[0560] As one embodiment, the first encoder corresponds to a plurality of factors, the first factor being one of the plurality of factors, and the first signaling indicating the first factor from the plurality of factors.

[0561] As an example, the first signaling implicitly indicates the first factor.

[0562] As an example, the first signaling indicates the first factor by indicating other information.

[0563] As an example, the other information includes one or more of the following: the first encoder, the decoder corresponding to the first encoder, the training dataset of the first encoder, the training dataset of the decoder corresponding to the first encoder, the first channel, and the first MCS.

[0564] As an example, the first signaling indicates that the first channel corresponds to the first factor.

[0565] As an example, the first signaling indicates that the first encoder corresponds to the first factor.

[0566] As one embodiment, the first signaling indicates that the decoder corresponding to the first encoder corresponds to the first factor.

[0567] Example 13

[0568] Example 13 illustrates a schematic diagram of a first control information indicating a first factor according to an embodiment of this application; as shown in Figure 13.

[0569] As an example, the first node sends the first signal, and the first control information indicates the first factor.

[0570] As one example, the first control information includes UCI (Uplink Control Information).

[0571] As an example, the first control information includes MAC CE (Medium Access Control layer Control Element).

[0572] As one example, the first control information includes a MAC subheader.

[0573] As one embodiment, the logical channel occupied by the first control information includes UL-SCH (Uplink Shared Channel).

[0574] As an example, the first signal carries the first control information.

[0575] As one embodiment, the first signal includes the first control information.

[0576] As one embodiment, the first signal and the first control information are transmitted on different physical layer channels.

[0577] As an example, the first signal is transmitted on the PUSCH, and the first control information is transmitted on the PUCCH.

[0578] As an example, the first signal and the first control information are transmitted on different PUSCHs.

[0579] As an example, the first control information explicitly indicates the first factor.

[0580] As an example, the first control information indicates the value of the first factor.

[0581] As an example, the first control information indicates the first factor from the M factors.

[0582] As one embodiment, the first encoder corresponds to multiple factors, the first factor is one of the multiple factors, and the first control information indicates the first factor from the multiple factors.

[0583] As an example, the first control information implicitly indicates the first factor.

[0584] As an example, the first control information indicates the first factor by indicating other information.

[0585] As an example, the other information includes one or more of the following: the first encoder, the decoder corresponding to the first encoder, the training dataset of the first encoder, the training dataset of the decoder corresponding to the first encoder, and the first channel.

[0586] As an example, the first control information indicates that the first channel corresponds to the first factor.

[0587] As an example, the first control information indicates that the first encoder corresponds to the first factor.

[0588] As an example, the first control information indicates that the decoder corresponding to the first encoder corresponds to the first factor.

[0589] As an example, the first node determines the first factor itself.

[0590] As one embodiment, the first node sends the first signal, and the first node determines the first factor itself.

[0591] As one example, how the first node determines the first factor is determined by the hardware equipment manufacturer. Some non-limiting implementation methods are described below:

[0592] As one embodiment, the first encoder corresponds to the first factor, and the first node determines the first factor by determining the first encoder.

[0593] As an example, the first channel corresponds to the first factor, and the first node determines the first factor by determining the first channel.

[0594] As an example, the first node performs training on the first encoder, and the first node determines the first factor during the training process.

[0595] As an example, the first node performs training on the first encoder, and the result of the training includes the first factor.

[0596] As an example, the first node jointly trains the first encoder and the first factor so that bit blocks from the first channel can be transmitted at a higher bit rate when using the first encoder than when using a conventional encoder. The first factor is the maximum bit rate increase that can be obtained by using the first encoder without reducing the probability of accurate reception.

[0597] As an example, the first node jointly trains the first encoder and the first factor so that when the output of the bit block from the first channel is encoded by the first encoder at a first adjusted code rate and transmitted in the modulation scheme indicated by the first MCS, it can be correctly received with a probability not less than a first threshold, wherein the first adjusted code rate depends on the first MCS and the first factor.

[0598] As an example, the first factor is the largest real number that enables the output of a bit block from the first channel, encoded by the first encoder at a first adjusted code rate, to be correctly received with a probability not less than a first threshold when transmitted in the modulation scheme indicated by the first MCS, wherein the first adjusted code rate depends on the first MCS and the first factor.

[0599] As an example, the first MCS indicates a first bit rate, and the first adjusted bit rate increases as the product of the first bit rate and the first factor increases.

[0600] As an example, the first MCS indicates a first bitrate, and the first adjusted bitrate is equal to the product of the first bitrate and the first factor.

[0601] As an example, when the output of the bit block from the first channel, after being encoded by a conventional encoder at a first code rate, is transmitted in the modulation scheme indicated by the first MCS, it can be correctly received with a probability not less than the first threshold, where the first MCS indicates the first code rate.

[0602] As a sub-example of the above embodiments, the conventional encoder encoding is based on LDPC codes.

[0603] As a sub-example of the above embodiments, the conventional encoder encoding is based on polar codes.

[0604] As a sub-example of the above embodiments, the conventional encoder encoding is based on turbo codes or convolutional codes.

[0605] Example 14

[0606] Example 14 illustrates a schematic diagram of a first factor-dependent first MCS according to an embodiment of this application; as shown in Figure 14.

[0607] As an example, the first factor changes with the first MCS.

[0608] As an example, the first factor varies with the bit rate indicated by the first MCS.

[0609] As an example, the first factor decreases as the bit rate indicated by the first MCS increases.

[0610] As an example, when the code rate indicated by the first MCS is equal to C5, the first factor is equal to E1; when the code rate indicated by the first MCS is equal to C6, the first factor is equal to E2; C5 is greater than C6, and E1 is not greater than E2.

[0611] As an example, the first factor is one of a plurality of factors, and the first node determines the first factor from the plurality of factors based on the first MCS.

[0612] As an example, the first MCS indicates a first code rate, and the first node determines the first factor from the plurality of factors based on the first code rate.

[0613] As an example, the first node determines the first factor such that the product of the first code rate and the first factor is less than 1.

[0614] As an example, the plurality of factors correspond to a plurality of bitrate thresholds, the first bitrate threshold being the largest bitrate threshold among the plurality of bitrate thresholds that is not greater than the first bitrate, and the first factor being the factor corresponding to the first bitrate threshold.

[0615] As an example, the plurality of factors correspond to a plurality of bitrate thresholds, the first bitrate threshold being the smallest bitrate threshold among the plurality of bitrate thresholds that is not less than the first bitrate, and the first factor being the factor corresponding to the first bitrate threshold.

[0616] As an example, the first factor is the largest factor among the plurality of factors whose product with the first code rate is less than 1.

[0617] As an example, all of the multiple factors correspond to the first encoder.

[0618] As an example, the plurality of factors all correspond to the decoder corresponding to the first encoder.

[0619] As an example, all of the multiple factors correspond to the first channel.

[0620] As one embodiment, a factor and an encoder or decoder correspondence include the factor being configured to the encoder or decoder.

[0621] As one example, a factor and an encoder or decoder correspondence include the configuration information or model parameters of the encoder or decoder including the factor.

[0622] As one embodiment, a factor and an encoder or decoder correspondence include the factor being used to adjust the code rate of a bit block employing the encoder or decoder.

[0623] As one embodiment, a factor and an encoder or decoder correspondence include the factor being used only to adjust the code rate of a bit block employing the encoder or decoder.

[0624] As one example, a factor and an encoder or decoder correspondence include the calculation of the TBS of the TB using the encoder or decoder depending on the factor.

[0625] As an example, a factor and an encoder or decoder correspond to the calculation of the TBS of the TB using only the one encoder or decoder, which depends on the one factor.

[0626] As one embodiment, a factor and a channel correspondence include the factor being used to adjust the code rate of a bit block from the channel.

[0627] As one example, a factor and a channel correspondence include the factor being used only to adjust the bit rate of bit blocks from the channel.

[0628] As an example, a factor and a channel correspondence include the calculation of the TBS of the TB from the one channel depending on the one factor.

[0629] As an example, a factor and a channel correspondence include the calculation of TBS of TB from only the one channel depending on the one factor.

[0630] As one example, a factor and a channel correspondence includes the factor depending on the training of an encoder, which is used for bit blocks from the channel.

[0631] As one example, a factor and a channel correspondence includes the factor depending on the training of an encoder, the training dataset of which includes bit blocks from the channel.

[0632] As one example, a factor and a channel correspondence includes the training result of an encoder including the factor, and the training dataset of the encoder including bit blocks from the channel.

[0633] As one embodiment, the first signaling indicates the plurality of factors, and the first node indicates the first factor from the plurality of factors according to the first MCS.

[0634] As a sub-implementation of the above embodiments, the first signaling indicates the plurality of factors by instructing the first encoder, the decoder corresponding to the first encoder, or the first channel.

[0635] As one embodiment, the first signaling instruction is transmitted through the first MCS and instructs one of the following three: the first encoder, the decoder corresponding to the first encoder, or the first channel, to indicate the first factor.

[0636] As an example, the first signaling indicates one of the following: the first encoder, the decoder corresponding to the first encoder, or the first channel. The first encoder, the decoder corresponding to the first encoder, or the first channel corresponds to multiple factors. The first factor is one of the multiple factors. The first node determines the first factor from the multiple factors based on the first MCS.

[0637] As a sub-implementation of the above embodiment, the first node receives the first signal.

[0638] As an example, the first control information indicates the first factor, which is one of a plurality of factors, and the first node determines the first factor from the plurality of factors according to the first MCS.

[0639] As a sub-implementation of the above embodiment, the first node sends the first signal.

[0640] Example 15

[0641] Example 15 illustrates a schematic diagram of K information bit blocks and K parity bit blocks according to an embodiment of this application; as shown in Figure 15. In Example 15, the K information bit blocks are used to generate K parity bit blocks. In Figure 15, the K information bit blocks are represented as information bit blocks #0, ..., information bit blocks #(K-1); the K parity bit blocks are represented as parity bit blocks #0, ..., parity bit blocks #(K-1); information bit block #j is used to generate parity bit block #j, where j is any non-negative integer less than K.

[0642] As an example, any one of the K information bit blocks includes a TB.

[0643] As an example, any one of the K information bit blocks is a TB.

[0644] As an example, any one of the K information bit blocks includes a CB.

[0645] As an example, any one of the K information bit blocks is a CB.

[0646] As an example, any one of the K information bit blocks includes a CBG.

[0647] As an example, any one of the K information bit blocks is a CBG.

[0648] As an example, any one of the K information bit blocks is a data block.

[0649] As an example, any one of the K information bit blocks is an information block.

[0650] As an example, the size of any one of the K information bit blocks is not less than 24.

[0651] As an example, all K information bit blocks are transmitted on the first channel.

[0652] As an example, the K information bit blocks all come from the first channel.

[0653] As an example, at least two of the K information bit blocks are transmitted on different channels.

[0654] As an example, at least two of the K information bit blocks come from different channels.

[0655] In a preferred embodiment, all K information bit blocks are transmitted on the same physical layer channel.

[0656] In a preferred embodiment, the K information bit blocks and the K parity bit blocks are transmitted on the same physical layer channel.

[0657] As an example, for any given check bit block among the K check bit blocks, each bit in the given check bit block depends on the sum of multiple bits in the information bit block corresponding to the given check bit block modulo 2.

[0658] As an example, for any given check bit block among the K check bit blocks, any bit in the given check bit block is equal to the sum of multiple bits in the information bit block corresponding to the given check bit block modulo 2.

[0659] As an example, for any given parity bit block among the K parity bit blocks, any bit in the given parity bit block is equal to the sum of multiple bits in the information bit block corresponding to the given parity bit block modulo 2, or equal to the sum of multiple bits in the information bit block corresponding to the given parity bit block modulo 2 and the sum of the corresponding bits in the scrambling sequence modulo 2.

[0660] As an example, the K check bit blocks each depend on the CRC bit blocks of the K information bit blocks.

[0661] As an example, the K check bit blocks are the CRC bit blocks of the K information bit blocks.

[0662] As an example, the K check bit blocks are obtained by scrambling the CRC bit blocks of the K information bit blocks.

[0663] As a sub-implementation of the above embodiment, the scrambling includes scrambling each bit in the CRC bit block.

[0664] As a sub-implementation of the above embodiments, the scrambling includes scrambling only a portion of the bits in the CRC bit block.

[0665] As an example, the CRC bit block of any given information bit block among the K information bit blocks is the output of the given information bit block through the CRC cyclic generator polynomial.

[0666] As an example, for any given information bit block among the K information bit blocks, the polynomial formed by the given information bit block and the CRC bit block of the given information bit block is divisible by the CRC cyclic generator polynomial over GF(2), that is, the remainder obtained by dividing the polynomial formed by the given information bit block and the CRC bit block of the given information bit block by the CRC cyclic generator polynomial is zero.

[0667] As an example, the size of any of the K parity bit blocks is one of 24, 16, 11, and 6.

[0668] As an example, the size of any of the K parity bit blocks is one of 32, 24, 16, 11, and 6.

[0669] As an example, two of the K parity bit blocks have different sizes.

[0670] As an example, the K parity bit blocks have the same size.

[0671] Example 16

[0672] Example 16 illustrates a schematic diagram of a first signal carrying K bit blocks and a second bit block according to an embodiment of this application, as shown in Figure 16. In Figure 16(a), the first signal is the output after the K bit blocks and the second bit block have undergone some or all of the following processes sequentially: scrambling, modulation, layer mapping, conversion precoding, precoding, resource block mapping, OFDM symbol generation, modulation, and upconversion; in Figure 16(b), the first signal is the output after the K bit blocks and the second bit block have undergone some or all of the following processes sequentially: scrambling, modulation, layer mapping, antenna port mapping, resource block mapping, OFDM symbol generation, modulation, and upconversion. In Figure 16(a), conversion precoding is optional.

[0673] As an example, the first signal is the output of the K bit blocks and the second bit block after being subjected to some or all of the following processes: scrambling, modulation, layer mapping, conversion precoding, precoding, resource block mapping, OFDM symbol generation, modulation, and upconversion.

[0674] As an example, the first signal is the output after the K bit blocks and the second bit block have undergone some or all of the following processes in sequence: scrambling, modulation, layer mapping, antenna port mapping, resource block mapping, OFDM symbol generation, modulation, and upconversion.

[0675] As one embodiment, after the K bit blocks and the second bit block are concatenated, they are sequentially subjected to some or all of the following processes: scrambling, modulation, layer mapping, conversion precoding, precoding, resource block mapping, OFDM symbol generation, modulation, and upconversion.

[0676] As one embodiment, after the K bit blocks and the second bit block are concatenated, they are sequentially subjected to scrambling, modulation, layer mapping, antenna port mapping, resource block mapping, OFDM symbol generation, modulation and upconversion, some or all of which are involved.

[0677] Example 17

[0678] Example 17 illustrates a schematic diagram of K bit blocks, K information bit blocks, a second bit block, and a third bit block according to an embodiment of this application; as shown in Figure 17. In Figure 17, the K bit blocks are represented as bit block #0, ..., bit block (K-1); the K information bit blocks are represented as information bit block #0, ..., information bit block (K-1); and the K encoders are represented as encoder #0, ..., encoder (K-1). In Example 17, bit block #i depends on the output obtained by encoder #i with information bit block #i as input, where i is any non-negative integer less than K; the second bit block depends on the output obtained by the second encoder with the third bit block as input.

[0679] In Figure 17(a), bit block #i is the output obtained by encoder #i with information bit block #i as input, and the second bit block is the output obtained by the second encoder with the third bit block as input; in Figure 17(b), bit block #i is the output obtained by encoder #i with information bit block #i as input after rate matching, and the second bit block is the output obtained by the second encoder with the third bit block as input after rate matching.

[0680] As an example, for any given bit block among the K bit blocks, the output of the encoder corresponding to the given bit block, with the information bit block corresponding to the given bit block as input, is used to generate the given bit block.

[0681] As an example, for any given bit block among the K bit blocks, the given bit block includes all or part of the output obtained by the encoder corresponding to the given bit block with the information bit block corresponding to the given bit block as input.

[0682] As an example, for any given bit block among the K bit blocks, the given bit block is the output obtained by the encoder corresponding to the given bit block with the information bit block corresponding to the given bit block as input.

[0683] As a sub-implementation of the above embodiments, the corresponding encoder includes rate matching.

[0684] As an example, for any given bit block among the K bit blocks, the given bit block is obtained by rate matching after the output of the encoder corresponding to the given bit block is taken as input by the information bit block corresponding to the given bit block.

[0685] As a sub-example of the above embodiments, the corresponding encoder does not include rate matching.

[0686] As an example, the first encoder is one of the K encoders, and the first bit block is one of the K bit blocks.

[0687] As an example, the first encoder is one of the K encoders that takes the first information bit block as input, and the first bit block is one of the K bit blocks that depends on the output of the first encoder.

[0688] As an example, the inputs to the K encoders are the K information bit blocks, respectively.

[0689] As an example, the third bit block consists of the K parity bit blocks.

[0690] As an example, the K parity bit blocks are arranged sequentially to form the third bit block.

[0691] As an example, the third bit block includes the K parity bit blocks and at least one information bit block.

[0692] As an example, the third bit block includes the K parity bit blocks and at least one data block or information block.

[0693] As one embodiment, the second bit block includes all or part of the output obtained by the second encoder with the third bit block as input.

[0694] As an example, the second bit block is the output obtained by the second encoder with the third bit block as input.

[0695] As a sub-implementation of the above embodiments, the second encoder includes rate matching.

[0696] As an example, the output obtained by the second encoder with the third bit block as input is used to generate the second bit block.

[0697] As an example, the second bit block is obtained by rate matching the output of the second encoder with the third bit block as input.

[0698] As a sub-implementation of the above embodiments, the second encoder does not include rate matching.

[0699] As an example, the size of the input to the second encoder refers to the size of the third bit block.

[0700] As one embodiment, the second bit block depends on the output obtained by the second encoder with the third bit block as input, wherein the size of the input of the second encoder refers to the size of the third bit block.

[0701] As one embodiment, the second bit block depends on the output obtained by the second encoder with the third bit block as input, and the ratio between the size of the input of the second encoder and the size of the second bit block refers to the ratio between the size of the third bit block and the size of the second bit block.

[0702] As an example, the second bit block depends on the output obtained by the second encoder with the third bit block as input, and the ratio between the size of the input of the second encoder and the size of the second bit block refers to the bit rate of the third bit block.

[0703] As an example, the bit rate of any of the K parity bit blocks is equal to the ratio between the size of the input of the second encoder and the size of the second bit block.

[0704] As an example, the code rate of any parity bit block among the K parity bit blocks is equal to the ratio between the size of the third bit block and the size of the second bit block.

[0705] As an example, all K encoders are the first encoder.

[0706] As an example, all K encoders are the first encoder, and the K information bit blocks are K CBGs respectively.

[0707] As a sub-example of the above embodiment, the K information bit blocks are K CBGs of the same TB.

[0708] As an example, all K encoders are the first encoder, and the K information bit blocks are K CBs respectively.

[0709] As a sub-example of the above embodiment, the K information bit blocks are K CBs of the same TB.

[0710] The advantages of the above method include that the parity bit blocks of different CBs in the same TB are uniformly encoded, which increases the encoding length of the parity bit blocks and thus improves the transmission performance of the parity bit blocks.

[0711] As an example, the K encoders are all the first encoder, and the K bit blocks are the outputs obtained by the first encoder when different information bit blocks are used as inputs.

[0712] As a sub-example of the above embodiment, the K information bit blocks are transmitted on the same channel.

[0713] As an example, at least two of the K encoders are the same encoder.

[0714] As a sub-implementation of the above embodiment, the bit blocks corresponding to the at least two encoders are the outputs obtained by the same encoder when different information bit blocks are used as inputs.

[0715] As a sub-example of the above embodiment, at least two of the K information bit blocks are transmitted on the same channel.

[0716] As an example, at least one of the K encoders is different from the first encoder.

[0717] As a sub-implementation of the above embodiment, the first information bit block is transmitted on the first channel, and at least one of the K information bit blocks is transmitted on a channel different from the first channel.

[0718] As an example, any two of the K encoders are different.

[0719] As a sub-example of the above embodiment, any two information bit blocks among the K information bit blocks are transmitted on different channels.

[0720] The advantages of the above method include that parity bit blocks from different channels are uniformly encoded, increasing the encoding length of the parity bit blocks and thus improving the transmission performance of the parity bit blocks.

[0721] As a preferred embodiment, any one of the K encoders is based on AI or ML.

[0722] The advantages of the above method include improving the transmission efficiency of information bit blocks by using AI / ML, while ensuring the transmission quality of parity bit blocks.

[0723] As an example, the encodings of the K encoders are inference.

[0724] As an example, the encoding behavior of the K encoders is inference.

[0725] As an example, the K encoders are obtained through training.

[0726] As an example, the K encoders each include at least one AI model or ML model.

[0727] As an example, the first node sends the first signal, and the model structure and model parameters of any of the K encoders are known to the first node, for example, by downloading from a network device, or by being specified in a standard, or by the first node through training, or a combination of the above.

[0728] As a sub-example of the above embodiment, the sender of the first signaling and the first node have a consensus on one or more of the model structure, model format and training dataset of any of the K encoders.

[0729] As an example, the first node receives the first signal, and the first node and the sender of the first signaling have a consensus on one or more of the model structure, model format and training dataset of any of the K encoders.

[0730] In a preferred embodiment, any one of the K encoders is based on AI or ML, while the second encoder is neither based on AI nor ML.

[0731] In a preferred embodiment, any one of the K encoders is based on AI or ML, and the second encoder is based on one of LDPC (Low Density Parity Check) code, polar code, turbo code, or convolutional code.

[0732] As an example, all K information bit blocks are transmitted in the first channel, and any one of the K encoders is the first encoder.

[0733] As an example, K is greater than or equal to M, and the K encoders include the M encoders.

[0734] As an example, K is greater than or equal to M, and any one of the K encoders is one of the M encoders.

[0735] As an example, K is equal to M, and the K encoders are the M encoders respectively.

[0736] As an example, any one of the K information bit blocks is transmitted in one of the M channels, the M encoders correspond to the M channels respectively, and any one of the K encoders is one of the M encoders.

[0737] As a sub-example of the above embodiment, K is greater than M, and two information bit blocks are transmitted in the same channel among the K information bit blocks, and the encoders corresponding to the two information bit blocks are the same encoder among the M encoders.

[0738] In one embodiment, the first given information bit block and the second given information bit block are two information bit blocks among the K information bit blocks. The first given bit block depends on the output obtained by the first given encoder with the first given information bit block as input, and the second given bit block depends on the output obtained by the second given encoder with the second given information bit block as input. The ratio between the size of the first given information bit block and the size of the first given bit block is not equal to the ratio between the size of the second given information bit block and the size of the second given bit block.

[0739] As an example, the first given bit block and the second given bit block are two bit blocks out of the K bit blocks, and the first given encoder and the second given encoder are two encoders out of the K encoders.

[0740] As an example, the ratio between the size of the first given information bit block and the size of the first given bit block is the code rate of the first given information bit block, and the ratio between the size of the second given information bit block and the size of the second given bit block is the code rate of the second given information bit block.

[0741] As an example, the first given information bit block and the second given information bit block are any two information bit blocks among the K information bit blocks.

[0742] As a sub-example of the above embodiment, the K information bit blocks come from K different channels respectively.

[0743] As an example, the first given information bit block and the second given information bit block are any two information bit blocks from different channels among the K information bit blocks.

[0744] As an example, at least two of the K information bit blocks have different code rates.

[0745] As an example, at least two of the K information bit blocks from different channels have different code rates.

[0746] As an example, any two information bit blocks from different channels in the K information bit blocks have different code rates.

[0747] As an example, the first given encoder and the second given encoder are different encoders.

[0748] As an example, the third given information bit block and the fourth given information bit block are two information bit blocks among the K information bit blocks. The third given bit block depends on the output obtained by the third given encoder with the third given information bit block as input, and the fourth given bit block depends on the output obtained by the fourth given encoder with the fourth given information bit block as input. The ratio between the size of the third given information bit block and the size of the fourth given information bit block is equal to the ratio between the size of the fourth given information bit block and the size of the fourth given bit block.

[0749] As an example, the third given bit block and the fourth given bit block are two bit blocks out of the K bit blocks, and the third given encoder and the fourth given encoder are two encoders out of the K encoders.

[0750] As an example, the ratio between the size of the third given information bit block and the size of the third given bit block is the code rate of the third given information bit block, and the ratio between the size of the fourth given information bit block and the size of the fourth given bit block is the code rate of the fourth given information bit block.

[0751] As an example, the third given information bit block and the fourth given information bit block are any two information bit blocks among the K information bit blocks.

[0752] As a sub-example of the above embodiment, the K information bit blocks come from the same channel.

[0753] As a sub-implementation of the above embodiment, all K encoders are the first encoder.

[0754] As an example, the first given information bit block and the second given information bit block are any two information bit blocks from the same channel among the K information bit blocks.

[0755] As an example, at least two of the K information bit blocks have the same code rate.

[0756] As an example, at least two of the K information bit blocks from the same channel have the same code rate.

[0757] As an example, any two information bit blocks from the same channel among the K information bit blocks have the same code rate.

[0758] As an example, the third given encoder and the fourth given encoder are the same encoder.

[0759] As a sub-example of the above embodiment, the third given bit block and the fourth given bit block depend on the output obtained by the same encoder when different information bit blocks are input.

[0760] Example 18

[0761] Example 18 illustrates a schematic diagram of the ratio between the size of the input of the second encoder and the size of the second bit block according to an embodiment of this application, which depends on K; as shown in Figure 18.

[0762] As an example, the second bit block depends on the output obtained by the second encoder with the third bit block as input, and the ratio between the size of the input of the second encoder and the size of the second bit block depends on K.

[0763] As an example, the ratio between the size of the input of the second encoder and the size of the second bit block varies with the change of K.

[0764] As an example, the ratio between the size of the input of the second encoder and the size of the second bit block increases as K increases.

[0765] As an example, the ratio between the size of the input of the second encoder and the size of the second bit block depends on the first MCS and the K.

[0766] As one embodiment, the ratio between the size of the input of the second encoder and the size of the second bit block depends on the first MCS and a first adjustment factor, the first adjustment factor depending on K.

[0767] As an example, the first adjustment factor is a positive real number less than 1.

[0768] As an example, the ratio between the size of the input of the second encoder and the size of the second bit block is equal to the product of the first bit rate and the first adjustment factor, wherein the first MCS indicates the first bit rate.

[0769] As an example, the ratio between the size of the input of the second encoder and the size of the second bit block increases as the product of the first code rate and the first adjustment factor increases, wherein the first MCS indicates the first code rate.

[0770] As an example, when the product of the first bit rate and the first adjustment factor is equal to C7, the ratio between the size of the input of the second encoder and the size of the second bit block is equal to D5; when the product of the first bit rate and the first adjustment factor is equal to C8, the ratio between the size of the input of the second encoder and the size of the second bit block is equal to D6; C7 is greater than C8, and D5 is not less than D6.

[0771] As an example, the larger K is, the larger the first adjustment factor is.

[0772] As an example, the first adjustment factor is one of a plurality of adjustment factors, and which of the plurality of adjustment factors the first adjustment factor is depends on K.

[0773] As an example, the first node determines the first adjustment factor from the plurality of adjustment factors based on the K.

[0774] As an example, any one of the plurality of adjustment factors is a positive real number less than 1.

[0775] As an example, any one of the plurality of adjustment factors is a positive real number not greater than 1.

[0776] As an example, the plurality of adjustment factors correspond to K integers respectively, and the first adjustment factor is the smallest adjustment factor among the plurality of adjustment factors whose corresponding integer is not less than K.

[0777] As an example, the plurality of adjustment factors correspond to K integers respectively, and the first adjustment factor is the largest adjustment factor among the plurality of adjustment factors whose corresponding integer is not greater than K.

[0778] As one embodiment, the first signaling indicates the first adjustment factor.

[0779] As an example, the first control information indicates the first adjustment factor.

[0780] As an example, the plurality of adjustment factors are configured for the first node.

[0781] As an example, the plurality of adjustment factors are configured to the first node by higher-level signaling.

[0782] As an example, the plurality of adjustment factors are reported by the first node.

[0783] As an example, the first adjustment factor does not require explicit indication.

[0784] As an example, given the first MCS and the K, the first adjustment factor does not require explicit indication.

[0785] As an example, given the first MCS, the K, and the plurality of adjustment factors, the first adjustment factor does not need to be explicitly indicated.

[0786] As one example, the ratio between the size of the third bit block and the size of the second bit block depends on K.

[0787] Example 19

[0788] Example 19 illustrates a schematic diagram of deploying a decoder corresponding to a first encoder according to an embodiment of this application; as shown in Figure 19. In Example 19, a decoder corresponding to the first encoder is deployed in the first node.

[0789] As an example, the decoder corresponding to the first encoder needs to be deployed.

[0790] As an example, deploying the decoder corresponding to the first encoder means deploying the model of the decoder corresponding to the first encoder.

[0791] As an example, the deployment includes obtaining the decoder corresponding to the first encoder.

[0792] As an example, the deployment includes obtaining a model of the decoder corresponding to the first encoder.

[0793] As one embodiment, the deployment includes obtaining an AI entity that performs the decoding of the decoder corresponding to the first encoder.

[0794] As one embodiment, the deployment includes obtaining an AI entity that includes AI functionality to perform decoding on the decoder corresponding to the first encoder.

[0795] As one example, the deployment includes obtaining AI functionality to perform decoding on the decoder corresponding to the first encoder.

[0796] As one embodiment, the deployment includes loading the decoder corresponding to the first encoder.

[0797] As one embodiment, the deployment includes loading a model of the decoder corresponding to the first encoder.

[0798] As one embodiment, the deployment includes submitting a request to load the decoder corresponding to the first encoder.

[0799] As an example, the request in Figure 19 is a request from the first node to load the decoder corresponding to the first encoder.

[0800] As an example, the response in Figure 19 is a response to a request from the first node to load the decoder corresponding to the first encoder.

[0801] As an example, the first node obtains the decoder corresponding to the first encoder through the response shown in Figure 19.

[0802] As an example, the first node obtains the model of the decoder corresponding to the first encoder through the response shown in Figure 19.

[0803] As an example, the first producer provides the decoder corresponding to the first encoder to the first node via the response shown in Figure 19.

[0804] As an example, the first producer provides the first node with a model of the decoder corresponding to the first encoder via the response shown in Figure 19.

[0805] As an example, the deployment is accomplished by an AI function.

[0806] As an example, the deployment is accomplished by an AI deployment function.

[0807] As an example, the deployment is performed by an AI entity.

[0808] As an example, the deployment is performed by an AI entity with a deployment function.

[0809] As an example, the first producer generates and provides the decoder corresponding to the first encoder.

[0810] As an example, the first producer generates and provides a model of the decoder corresponding to the first encoder.

[0811] As an example, the training of the decoder corresponding to the first encoder is performed by the first producer.

[0812] As an example, the first producer is the producer of training the decoder corresponding to the first encoder.

[0813] As one example, the first producer includes an AI entity producer.

[0814] As one example, the first producer includes an AI function producer.

[0815] As one example, the first producer includes an AI deployment producer.

[0816] As one example, the first producer includes an AI training producer.

[0817] As an example, the first producer includes the producer of the AI ​​model training.

[0818] As one example, the first producer includes an MnS (Management Service) producer.

[0819] As an example, the first producer is the serving cell of the first node.

[0820] As an example, the first producer is the maintenance base station of the serving cell of the first node.

[0821] As an example, the first producer is a core network device.

[0822] As an example, the first producer is a NAS device.

[0823] As an example, the first producer is an OTT server.

[0824] Example 20

[0825] Example 20 illustrates a schematic diagram of deploying a first encoder according to one embodiment of this application; as shown in Figure 20. In Example 20, the first encoder is deployed on the first node.

[0826] As an example, the first encoder needs to be deployed.

[0827] As an example, deploying the first encoder means deploying the model of the first encoder.

[0828] As one embodiment, the deployment includes obtaining the first encoder.

[0829] As one example, the deployment includes obtaining the model of the first encoder.

[0830] As one example, the deployment includes obtaining an AI entity that performs the encoding of the first encoder.

[0831] As one example, the deployment includes obtaining an AI entity that includes AI functions that perform the encoding of the first encoder.

[0832] As one example, the deployment includes obtaining AI capabilities to perform the encoding of the first encoder.

[0833] As one embodiment, the deployment includes loading the first encoder.

[0834] As one example, the deployment includes loading the model of the first encoder.

[0835] As one embodiment, the deployment includes making a request to load the first encoder.

[0836] As an example, the request in Figure 20 is a request from the first node to load the first encoder.

[0837] As an example, the response in Figure 20 is a response to a request made by the first node to load the first encoder.

[0838] As an example, the second node obtains the first encoder through the response shown in Figure 20.

[0839] As an example, the second node obtains the model of the first encoder through the response shown in Figure 20.

[0840] As an example, the second producer provides the first encoder to the first node via the response shown in Figure 20.

[0841] As an example, the second producer provides the first encoder model to the first node via the response shown in Figure 20.

[0842] As an example, the deployment is accomplished by an AI function.

[0843] As an example, the deployment is accomplished by an AI deployment function.

[0844] As an example, the deployment is performed by an AI entity.

[0845] As an example, the deployment is performed by an AI entity with a deployment function.

[0846] As one example, the second producer generates and provides the first encoder.

[0847] As an example, the second producer generates and provides the model of the first encoder.

[0848] As an example, the training of the first encoder is performed by the second producer.

[0849] As an example, the second producer is the producer of the training of the first encoder.

[0850] As one example, the second producer includes an AI entity producer.

[0851] As one example, the second producer includes an AI function producer.

[0852] As one example, the second producer includes an AI deployment producer.

[0853] As one example, the second producer includes an AI training producer.

[0854] As an example, the second producer includes the producer of the AI ​​model training.

[0855] As one example, the second producer includes an MnS (Management Service) producer.

[0856] As one example, the second producer is the serving cell of the first node.

[0857] As one example, the second producer is the maintenance base station of the serving cell of the first node.

[0858] As one example, the second producer is a core network device.

[0859] As one example, the second producer is a NAS device.

[0860] As one example, the second producer is an OTT server.

[0861] Example 21

[0862] Example 21 illustrates a schematic diagram of an artificial intelligence or machine learning-based processing system according to an embodiment of this application, as shown in Figure 21. In Example 21, the third processor sends a first dataset to the fourth processor and a second dataset to the fifth processor; the fourth processor generates a target first-class parameter set based on the first dataset, and sends the generated target first-class parameter set to the fifth processor; the fifth processor processes the second dataset using the target first-class parameter set to obtain a first-class output, and sends the first-class output to the sixth processor. In Figure 21, the first-class feedback and the second-class feedback are optional; the fourth processor includes ML training functionality; the fifth processor includes ML inference functionality.

[0863] As one embodiment, the sixth processor includes ML testing functionality.

[0864] As one example, the sixth processor includes performance monitoring / evaluation of the ML model.

[0865] As one embodiment, the sixth processor includes the inverse operation of the fifth processor.

[0866] As one embodiment, the fifth processor includes the first encoder, and the sixth processor includes a decoder corresponding to the first encoder.

[0867] As an example, the fifth processor sends a first type of feedback to the fourth processor. The first type of feedback is used to trigger the recalculation or update of the target first type of parameter set, that is, to trigger ML initial training or ML retraining.

[0868] As one embodiment, the sixth processor sends a second type of feedback to the third processor, the second type of feedback being used to generate the first dataset or the second dataset, or the second type of feedback being used to trigger the sending of the first dataset or the second dataset.

[0869] As one embodiment, the third processor generates the first dataset and the second dataset based on the measurement of the reference signal.

[0870] As an example, the third processor generates the first dataset and the second dataset based on measurements of the physical layer channel.

[0871] As one embodiment, the third processor generates the first dataset and the second dataset based on data from the MAC layer or a layer higher than the MAC layer.

[0872] As one embodiment, the fifth processor is located at the first node, and the sixth processor is located at the second node.

[0873] As one embodiment, the fifth processor is located at the second node, and the sixth processor is located at the first node.

[0874] As an example, the second dataset includes inference data.

[0875] As an example, the second dataset is an inference dataset.

[0876] As an example, the input to an inference belongs to an inference dataset.

[0877] As an example, the first dataset includes training data.

[0878] As an example, the first dataset is a training dataset.

[0879] As an example, the fourth processor is used to train an ML model, and the trained model is described by the target first class of parameter sets.

[0880] As one embodiment, the fourth processor is located at the first node.

[0881] The above embodiments avoid passing the first dataset to the second node.

[0882] As one embodiment, the fourth processor is located at the second node.

[0883] The above embodiments support joint training and optimize system performance.

[0884] As one embodiment, the fourth processor is located in the core network.

[0885] The above embodiments support network-wide joint training, further optimizing system performance.

[0886] As an example, the fifth processor constructs a model based on the target first type of parameter group, and then inputs the second dataset into the constructed model to obtain the first type of output.

[0887] As an example, the fifth processor compares the real data with the first type of output, and the resulting error is used to generate the first type of feedback.

[0888] As an example, the fifth processor generates the first type of feedback through performance monitoring.

[0889] As an example, the first type of feedback is used to reflect the performance of the trained model; when the performance of the trained model fails to meet the requirements, the fourth processing opportunity recalculates the target first type of parameter set.

[0890] As an example, the sixth processor compares the real data with the first type of output, and the resulting error is used to generate the second type of feedback.

[0891] As an example, the sixth processor generates the second type of feedback through performance monitoring.

[0892] As an example, the second type of feedback is used to reflect the performance of the trained model; when the performance of the trained model fails to meet the requirements, the third processor sends the first dataset to trigger or assist the fourth processor in recalculating the target first type of parameter set.

[0893] As an example, when the error is too large or the update has not been performed for too long, the performance of the trained model is considered to be unsatisfactory.

[0894] As an example, the target first type of parameter group includes one or more of the following: convolution kernel size, number of convolution layers, convolution stride, pooling kernel size, pooling kernel stride, pooling function, activation function, or number of feature maps.

[0895] As an example, the target first type of parameter group includes one or more of the following: convolution kernel, pooling kernel, pooling function, activation function, parameters of pooling function, or parameters of activation function.

[0896] As one example, the ML includes AI.

[0897] As an example, the ML includes ML and AI.

[0898] Example 22

[0899] Example 22 illustrates a schematic diagram based on artificial intelligence or machine learning according to an embodiment of this application; as shown in Figure 22. Figure 22 includes a first operation, a second operation, a third operation, a fourth operation, and a fifth operation. In Example 22, the first and second operations belong to a first stage, the third operation belongs to a second stage, the fourth operation belongs to a third stage, and the fifth operation belongs to a fourth stage. In Figure 22, the lines with arrows indicate the sequence of processes.

[0900] As an example, the first operation includes ML training, the second operation includes ML testing, the third operation includes ML emulation, the fourth operation includes ML entity loading, and the fifth operation includes AI inference.

[0901] As one embodiment, the first stage includes a training phase, the second stage includes an emulation phase, the third stage includes a deployment phase, and the fourth stage includes an emulation phase.

[0902] As an example, the first stage includes ML model training.

[0903] As an example, the first stage includes ML model training and ML testing.

[0904] As an example, the ML model training includes initial training and re-training of one or a group of ML models.

[0905] As an example, the training of the ML model depends on training data.

[0906] As an example, the ML model training includes ML entity validation.

[0907] As an example, the ML entity verification is used to evaluate the performance of the ML entity.

[0908] As an example, the ML entity verification depends on verification data.

[0909] As an example, if the results of ML entity verification do not meet expectations, the ML model will be retrained.

[0910] As an example, the ML testing includes testing the validated ML entities to estimate the performance of the trained ML model.

[0911] As an example, if the ML test results meet expectations, the ML entity proceeds to the next stage; otherwise, the ML model will be retrained.

[0912] As an example, the ML test relies on test data.

[0913] As one embodiment, the second stage includes ML simulation, which performs inference of ML entities in a simulation environment.

[0914] As an example, the ML simulation estimates the performance of ML entity reasoning in a simulation environment before using ML entities.

[0915] As one embodiment, the second stage is optional.

[0916] As an example, the third stage includes ML entity loading, which is to obtain trained ML entities to obtain the desired AI inference capabilities.

[0917] As an example, the third stage is optional.

[0918] As an example, the third stage is no longer needed when the training and inference functions are co-located.

[0919] As an example, the fourth stage includes AI inference.

[0920] As an example, the AI ​​inference relies on inference data.

[0921] As an example, the input to an AI inference belongs to the inference dataset of the AI ​​inference model.

[0922] As one example, the ML includes AI.

[0923] As one example, the AI ​​includes ML.

[0924] Example 23

[0925] Example 23 illustrates a schematic diagram of AI function deployment according to one embodiment of this application; as shown in Figure 23.

[0926] In Example 23, the AI ​​training function of the RAN (Radio Access Network) domain is located in the 3GPP RAN domain-specific management function, while the AI ​​inference function is located in the UE.

[0927] In Example 23, RAN domain-specific management functions provide AI training function management capabilities and AI inference function management capabilities.

[0928] Example 24

[0929] Example 24 illustrates a schematic diagram of AI function deployment according to one embodiment of this application; as shown in Figure 24.

[0930] In Example 24, the AI ​​training function is a RAN domain-specific management function, while the AI ​​inference function is located locally on the UE.

[0931] In Example 24, the management capability of the AI ​​training function is provided by the RAN domain-specific management function, while the management capability of the AI ​​inference function is provided locally by the UE.

[0932] In Figure 24, MnF refers to Management Function.

[0933] Example 25

[0934] Example 25 illustrates a schematic diagram of AI function deployment according to one embodiment of this application; as shown in Figure 25.

[0935] In Example 25, both the AI ​​training function and the AI ​​inference function are located in the UE, wherein the UE provides the ability to train and infer.

[0936] In Example 25, RAN domain-specific management functions provide management capabilities for AI training and AI inference functions.

[0937] Example 26

[0938] Example 26 illustrates a schematic diagram of AI function deployment according to one embodiment of this application; as shown in Figure 26.

[0939] In Example 26, both the AI ​​training function and the AI ​​inference function are located in the UE.

[0940] In Example 26, the management capabilities of both the AI ​​training function and the AI ​​inference function are provided locally by the UE.

[0941] In Figure 26, MnF refers to Management Function.

[0942] Example 27

[0943] Example 27 illustrates a structural block diagram of a processing apparatus for a first node according to an embodiment of this application; as shown in Figure 27. In Figure 27, the processing apparatus 2700 in the first node includes a first receiver 2701 and a first processor 2702.

[0944] In embodiment 27, the first receiver 2701 receives the first signaling; the first processor 2702 receives the first signal or sends the first signal.

[0945] In embodiment 27, the first signaling indicates scheduling information for the first signal; a first bit block and a second bit block are used together to generate the first signal, the first bit block depends on the output of the first encoder, the input of the first encoder includes a first information bit block, the second bit block depends on the output of the second encoder, the input of the second encoder includes a first check bit block, the first information bit block is used to generate the first check bit block; the ratio between the size of the input of the first encoder and the size of the first bit block is not equal to the ratio between the size of the input of the second encoder and the size of the second bit block.

[0946] As one embodiment, the first node receives the first signal on a PDSCH, or the first node transmits the first signal on a PUSCH.

[0947] As one embodiment, the first information bit block includes a TB or a CB.

[0948] As one example, the first encoder is based on AI or ML, while the second encoder is neither based on AI nor ML.

[0949] As a sub-implementation of the above embodiments, the second encoder is based on one of LDPC codes, polar codes, turbo codes, or convolutional codes.

[0950] As a sub-example of the above embodiments, the decoder corresponding to the first encoder is based on AI or ML.

[0951] As an example, the first signaling indicates a first MCS; the ratio between the size of the input of the first encoder and the size of the first bit block depends on the first MCS and a first factor, and the ratio between the size of the input of the second encoder and the size of the second bit block depends on only the first MCS of the first MCS and the first factor.

[0952] As a sub-implementation of the above embodiments, the size of the first information bit block depends on the first factor.

[0953] As an example, the first encoder is one of M encoders, where M is a positive integer greater than 1; the M encoders correspond one-to-one with the M factors, and the first factor is the factor corresponding to the first encoder.

[0954] As a sub-example of the above embodiments, any one of the M encoders is based on AI or ML.

[0955] As an example, the first signaling indicates the first factor.

[0956] As one embodiment, the first processor 2702 sends first control information; wherein the first control information indicates the first factor.

[0957] As an example, the first factor depends on the first MCS.

[0958] As a sub-implementation of the above embodiments, the first MCS indicates the first code rate, and the product of the first code rate and the first factor is less than 1.

[0959] As an example, K bit blocks and the second bit block are used together to generate the first signal, where K is a positive integer greater than 1; the first bit block is one of the K bit blocks, each of the K bit blocks depends on the outputs obtained by K encoders with K information bit blocks as input, and the first information bit block is one of the K information bit blocks; the second bit block depends on the output obtained by the second encoder with a third bit block as input, the third bit block includes K check bit blocks, and the K information bit blocks are used to generate the K check bit blocks.

[0960] As a sub-example of the above embodiment, any one of the K encoders is based on AI or ML, and the K information bit blocks are all transmitted on the same physical layer channel.

[0961] As a reference embodiment of the above sub-example, the K parity bit blocks are all transmitted on the same physical layer channel.

[0962] As an example, the ratio between the size of the input to the second encoder and the size of the second bit block depends on K.

[0963] As one embodiment, the first processor 2702 performs decoding by the decoder corresponding to the first encoder and decoding by the decoder corresponding to the second encoder; wherein, the first node receives the first signal.

[0964] As one embodiment, the first processor 2702 executes the encoding of the first encoder and the encoding of the second encoder; wherein, the first node sends the first signal.

[0965] As one embodiment, the first bit block depends on the output obtained by the first encoder with the first information bit block as input, and the ratio between the size of the input of the first encoder and the size of the first bit block refers to the ratio between the size of the first information bit block and the size of the first bit block.

[0966] As a sub-implementation of the above embodiment, the second bit block depends on the output obtained by the second encoder with the first check bit block as input, and the ratio between the size of the input of the second encoder and the size of the second bit block refers to the ratio between the size of the first check bit block and the size of the second bit block.

[0967] As a sub-implementation of the above embodiment, the second bit block depends on the output obtained by the second encoder with the third bit block as input, and the ratio between the size of the input of the second encoder and the size of the second bit block refers to the ratio between the size of the third bit block and the size of the second bit block.

[0968] As one embodiment, the first node includes a terminal.

[0969] As one embodiment, the first node includes a user equipment.

[0970] As one embodiment, the first node includes a relay node device.

[0971] As an example, the first receiver 2701 includes at least one of the following in embodiment 4: {antenna 452, receiver 454, receiver processor 456, multi-antenna receiver processor 458, controller / processor 459, memory 460, data source 467}.

[0972] As an example, the first processor 2702 includes at least one of the following in embodiment 4: {antenna 452, receiver / transmitter 454, receiving processor 456, transmitting processor 468, multi-antenna receiving processor 458, multi-antenna transmitting processor 457, controller / processor 459, memory 460, data source 467}.

[0973] Example 28

[0974] Example 28 illustrates a structural block diagram of a processing apparatus for a second node according to an embodiment of this application; as shown in Figure 28. In Figure 28, the processing apparatus 2800 in the second node includes a first transmitter 2801 and a second processor 2802.

[0975] In embodiment 28, the first transmitter 2801 sends a first signaling; the second processor 2802 sends the first signal or receives the first signal.

[0976] In embodiment 28, the first signaling indicates scheduling information for the first signal; a first bit block and a second bit block are used together to generate the first signal, the first bit block depends on the output of the first encoder, the input of the first encoder includes a first information bit block, the second bit block depends on the output of the second encoder, the input of the second encoder includes a first check bit block, the first information bit block is used to generate the first check bit block; the ratio between the size of the input of the first encoder and the size of the first bit block is not equal to the ratio between the size of the input of the second encoder and the size of the second bit block.

[0977] As one embodiment, the first node receives the first signal on a PDSCH, or the first node transmits the first signal on a PUSCH.

[0978] As one embodiment, the first information bit block includes a TB or a CB.

[0979] As one example, the first encoder is based on AI or ML, while the second encoder is neither based on AI nor ML.

[0980] As a sub-implementation of the above embodiments, the second encoder is based on one of LDPC codes, polar codes, turbo codes, or convolutional codes.

[0981] As a sub-example of the above embodiments, the decoder corresponding to the first encoder is based on AI or ML.

[0982] As an example, the first signaling indicates a first MCS; the ratio between the size of the input of the first encoder and the size of the first bit block depends on the first MCS and a first factor, and the ratio between the size of the input of the second encoder and the size of the second bit block depends on only the first MCS of the first MCS and the first factor.

[0983] As a sub-implementation of the above embodiments, the size of the first information bit block depends on the first factor.

[0984] As an example, the first encoder is one of M encoders, where M is a positive integer greater than 1; the M encoders correspond one-to-one with the M factors, and the first factor is the factor corresponding to the first encoder.

[0985] As a sub-example of the above embodiments, any one of the M encoders is based on AI or ML.

[0986] As an example, the first signaling indicates the first factor.

[0987] As one embodiment, the second processor 2802 receives first control information; wherein the first control information indicates the first factor.

[0988] As an example, the first factor depends on the first MCS.

[0989] As a sub-implementation of the above embodiments, the first MCS indicates the first code rate, and the product of the first code rate and the first factor is less than 1.

[0990] As an example, K bit blocks and the second bit block are used together to generate the first signal, where K is a positive integer greater than 1; the first bit block is one of the K bit blocks, each of the K bit blocks depends on the outputs obtained by K encoders with K information bit blocks as input, and the first information bit block is one of the K information bit blocks; the second bit block depends on the output obtained by the second encoder with a third bit block as input, the third bit block includes K check bit blocks, and the K information bit blocks are used to generate the K check bit blocks.

[0991] As a sub-example of the above embodiment, any one of the K encoders is based on AI or ML, and the K information bit blocks are all transmitted on the same physical layer channel.

[0992] As a reference embodiment of the above sub-example, the K parity bit blocks are all transmitted on the same physical layer channel.

[0993] As an example, the ratio between the size of the input to the second encoder and the size of the second bit block depends on K.

[0994] As one embodiment, the second processor 2802 executes the encoding of the first encoder and the encoding of the second encoder; wherein the second node sends the first signal.

[0995] As one embodiment, the second processor 2802 performs decoding by the decoder corresponding to the first encoder and decoding by the decoder corresponding to the second encoder; wherein, the second node receives the first signal.

[0996] As one embodiment, the first bit block depends on the output obtained by the first encoder with the first information bit block as input, and the ratio between the size of the input of the first encoder and the size of the first bit block refers to the ratio between the size of the first information bit block and the size of the first bit block.

[0997] As a sub-implementation of the above embodiment, the second bit block depends on the output obtained by the second encoder with the first check bit block as input, and the ratio between the size of the input of the second encoder and the size of the second bit block refers to the ratio between the size of the first check bit block and the size of the second bit block.

[0998] As a sub-implementation of the above embodiment, the second bit block depends on the output obtained by the second encoder with the third bit block as input, and the ratio between the size of the input of the second encoder and the size of the second bit block refers to the ratio between the size of the third bit block and the size of the second bit block.

[0999] As one embodiment, the second node includes a base station.

[1000] As one embodiment, the second node includes a base station device.

[1001] As one embodiment, the second node includes a relay node device.

[1002] As one embodiment, the second node includes the sustaining base station of the serving cell of the first node.

[1003] As one embodiment, the second node includes an OTT (Over-The-Top) server.

[1004] As an example, the second node provides OAM (Operation Administration and Maintenance).

[1005] As one embodiment, the second node includes a NAS (Network Access Server).

[1006] As one embodiment, the second node includes a NAS device.

[1007] As one example, the second node provides network access services.

[1008] As one embodiment, the second node includes core network equipment.

[1009] As one embodiment, the second node includes base station equipment and core network equipment.

[1010] As one embodiment, the second node includes a base station device and a NAS device.

[1011] As one embodiment, the first transmitter 2801 includes at least one of the following in embodiment 4: {antenna 420, transmitter 418, transmission processor 416, multi-antenna transmission processor 471, controller / processor 475, memory 476}.

[1012] As one embodiment, the second processor 2802 includes at least one of the following in embodiment 4: {antenna 420, transmitter / receiver 418, transmitter processor 416, receiver processor 470, multi-antenna transmitter processor 471, multi-antenna receiver processor 472, controller / processor 475, memory 476}.

[1013] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory, hard disk, or optical disk. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module unit in the above embodiments can be implemented in hardware or in the form of software functional modules. This application is not limited to any specific combination of software and hardware. The user equipment, terminal, and UE in this application include, but are not limited to, drones, communication modules on drones, remote-controlled aircraft, aircraft, small aircraft, mobile phones, tablets, laptops, vehicle-mounted communication equipment, vehicles, RSUs, wireless sensors, internet access cards, IoT terminals, RFID terminals, NB-IoT terminals, MTC (Machine Type Communication) terminals, eMTC (enhanced MTC) terminals, data cards, internet access cards, vehicle-mounted communication equipment, low-cost mobile phones, low-cost tablets, and other wireless communication devices. The base stations or system equipment in this application include, but are not limited to, macrocell base stations, microcell base stations, small cell base stations, home base stations, relay base stations, eNBs, gNBs, TRPs (Transmitter Receiver Points), GNSS, relay satellites, satellite base stations, airborne base stations, RSUs (Road Side Units), drones, and testing equipment, such as transceivers or signaling testers that simulate some functions of a base station, and other wireless communication equipment.

[1014] Those skilled in the art will understand that the present invention can be practiced in other specified forms without departing from its core or essential characteristics. Therefore, the embodiments disclosed herein should in any way be considered descriptive rather than restrictive. The scope of the invention is defined by the appended claims rather than the foregoing description, and all modifications within their equivalent meaning and scope are considered to be included therein.

Claims

1. A first node used for wireless communication, characterized in that, include: A first receiver receives a first signaling instruction, which indicates scheduling information for a first signal. A first processor receives the first signal, or sends the first signal; In this process, a first bit block and a second bit block are used together to generate the first signal. The first bit block depends on the output of the first encoder, and the input of the first encoder includes a first information bit block. The second bit block depends on the output of the second encoder, and the input of the second encoder includes a first check bit block. The first information bit block is used to generate the first check bit block. The ratio between the size of the input of the first encoder and the size of the first bit block is not equal to the ratio between the size of the input of the second encoder and the size of the second bit block.

2. The first node according to claim 1, characterized in that, The first signaling indicates the first MCS; the ratio between the size of the input of the first encoder and the size of the first bit block depends on the first MCS and the first factor, and the ratio between the size of the input of the second encoder and the size of the second bit block depends on only the first MCS of the first MCS and the first factor.

3. The first node according to claim 2, characterized in that, The first encoder is one of M encoders, where M is a positive integer greater than 1; the M encoders correspond one-to-one with the M factors, and the first factor is the factor corresponding to the first encoder.

4. The first node according to claim 2 or 3, characterized in that, The first signaling indicates the first factor.

5. The first node according to claim 2 or 3, characterized in that, The first processor sends first control information; wherein the first control information indicates the first factor.

6. The first node according to any one of claims 2 to 5, characterized in that, The first factor depends on the first MCS.

7. The first node according to any one of claims 1 to 6, characterized in that, K bit blocks and the second bit block are used together to generate the first signal, where K is a positive integer greater than 1; the first bit block is one of the K bit blocks, each of the K bit blocks depends on the output of K encoders with K information bit blocks as input, and the first information bit block is one of the K information bit blocks; the second bit block depends on the output of the second encoder with a third bit block as input, the third bit block includes K check bit blocks, and the K information bit blocks are used to generate the K check bit blocks.

8. The first node according to claim 7, characterized in that, The ratio between the size of the input to the second encoder and the size of the second bit block depends on K.

9. The first node according to any one of claims 1 to 8, characterized in that, The first processor executes the decoding of the decoder corresponding to the first encoder and the decoding of the decoder corresponding to the second encoder; wherein, the first node receives the first signal.

10. The first node according to any one of claims 1 to 8, characterized in that, The first processor executes the encoding of the first encoder and the encoding of the second encoder; wherein the first node sends the first signal.

11. A second node used for wireless communication, characterized in that, include: The first transmitter sends a first signaling instruction, which indicates the scheduling information of the first signal. The second processor sends the first signal or receives the first signal; In this process, a first bit block and a second bit block are used together to generate the first signal. The first bit block depends on the output of the first encoder, and the input of the first encoder includes a first information bit block. The second bit block depends on the output of the second encoder, and the input of the second encoder includes a first check bit block. The first information bit block is used to generate the first check bit block. The ratio between the size of the input of the first encoder and the size of the first bit block is not equal to the ratio between the size of the input of the second encoder and the size of the second bit block.

12. The second node according to claim 11, characterized in that, The first signaling indicates the first MCS; the ratio between the size of the input of the first encoder and the size of the first bit block depends on the first MCS and the first factor, and the ratio between the size of the input of the second encoder and the size of the second bit block depends on only the first MCS of the first MCS and the first factor.

13. The second node according to claim 12, characterized in that, The first encoder is one of M encoders, where M is a positive integer greater than 1; the M encoders correspond one-to-one with the M factors, and the first factor is the factor corresponding to the first encoder.

14. The second node according to claim 2 or 13, characterized in that, The first signaling indicates the first factor.

15. The second node according to claim 12 or 13, characterized in that, The second processor receives first control information; wherein the first control information indicates the first factor.

16. The second node according to any one of claims 12 to 15, characterized in that, The first factor depends on the first MCS.

17. The second node according to any one of claims 11 to 16, characterized in that, K bit blocks and the second bit block are used together to generate the first signal, where K is a positive integer greater than 1; the first bit block is one of the K bit blocks, each of the K bit blocks depends on the output of K encoders with K information bit blocks as input, and the first information bit block is one of the K information bit blocks; the second bit block depends on the output of the second encoder with a third bit block as input, the third bit block includes K check bit blocks, and the K information bit blocks are used to generate the K check bit blocks.

18. The second node according to claim 17, characterized in that, The ratio between the size of the input to the second encoder and the size of the second bit block depends on K.

19. The second node according to any one of claims 11 to 18, characterized in that, The second processor executes the encoding of the first encoder and the encoding of the second encoder; wherein the second node sends the first signal.

20. The second node according to any one of claims 11 to 18, characterized in that, The second processor executes the decoding of the decoder corresponding to the first encoder and the decoding of the decoder corresponding to the second encoder; wherein, the second node receives the first signal.

21. A method used in a first node of wireless communication, characterized in that, include: Receive the first signaling, which indicates the scheduling information of the first signal; Receive the first signal, or send the first signal; In this process, a first bit block and a second bit block are used together to generate the first signal. The first bit block depends on the output of the first encoder, and the input of the first encoder includes a first information bit block. The second bit block depends on the output of the second encoder, and the input of the second encoder includes a first check bit block. The first information bit block is used to generate the first check bit block. The ratio between the size of the input of the first encoder and the size of the first bit block is not equal to the ratio between the size of the input of the second encoder and the size of the second bit block.

22. The method in the first node according to claim 21, characterized in that, The first signaling indicates the first MCS; the ratio between the size of the input of the first encoder and the size of the first bit block depends on the first MCS and the first factor, and the ratio between the size of the input of the second encoder and the size of the second bit block depends on only the first MCS of the first MCS and the first factor.

23. The method in the first node according to claim 22, characterized in that, The first encoder is one of M encoders, where M is a positive integer greater than 1; the M encoders correspond one-to-one with the M factors, and the first factor is the factor corresponding to the first encoder.

24. The method in the first node according to claim 22 or 23, characterized in that, The first signaling indicates the first factor.

25. The method in the first node according to claim 22 or 23, characterized in that, include: Send the first control message; The first control information indicates the first factor.

26. The method in the first node according to any one of claims 22 to 25, characterized in that, The first factor depends on the first MCS.

27. The method in the first node according to any one of claims 21 to 26, characterized in that, K bit blocks and the second bit block are used together to generate the first signal, where K is a positive integer greater than 1; the first bit block is one of the K bit blocks, each of the K bit blocks depends on the output of K encoders with K information bit blocks as input, and the first information bit block is one of the K information bit blocks; the second bit block depends on the output of the second encoder with a third bit block as input, the third bit block includes K check bit blocks, and the K information bit blocks are used to generate the K check bit blocks.

28. The method in the first node according to claim 27, characterized in that, The ratio between the size of the input to the second encoder and the size of the second bit block depends on K.

29. The method in the first node according to any one of claims 21 to 28, characterized in that, include: Perform the decoding of the decoder corresponding to the first encoder; Perform the decoding of the decoder corresponding to the second encoder; The first node receives the first signal.

30. The method in the first node according to any one of claims 21 to 28, characterized in that, include: Execute the encoding of the first encoder; Perform the encoding using the second encoder; The first node sends the first signal.

31. A method used in a second node of wireless communication, characterized in that, include: Send a first signaling instruction, which indicates the scheduling information of the first signal; Send the first signal, or receive the first signal; In this process, a first bit block and a second bit block are used together to generate the first signal. The first bit block depends on the output of the first encoder, and the input of the first encoder includes a first information bit block. The second bit block depends on the output of the second encoder, and the input of the second encoder includes a first check bit block. The first information bit block is used to generate the first check bit block. The ratio between the size of the input of the first encoder and the size of the first bit block is not equal to the ratio between the size of the input of the second encoder and the size of the second bit block.

32. The method in the second node according to claim 31, characterized in that, The first signaling indicates the first MCS; the ratio between the size of the input of the first encoder and the size of the first bit block depends on the first MCS and the first factor, and the ratio between the size of the input of the second encoder and the size of the second bit block depends on only the first MCS of the first MCS and the first factor.

33. The method in the second node according to claim 32, characterized in that, The first encoder is one of M encoders, where M is a positive integer greater than 1; the M encoders correspond one-to-one with the M factors, and the first factor is the factor corresponding to the first encoder.

34. The method in the second node according to claim 32 or 33, characterized in that, The first signaling indicates the first factor.

35. The method in the second node according to claim 32 or 33, characterized in that, include: Receive first control information; The first control information indicates the first factor.

36. The method in the second node according to any one of claims 32 to 35, characterized in that, The first factor depends on the first MCS.

37. The method in the second node according to any one of claims 31 to 36, characterized in that, K bit blocks and the second bit block are used together to generate the first signal, where K is a positive integer greater than 1; the first bit block is one of the K bit blocks, each of the K bit blocks depends on the output of K encoders with K information bit blocks as input, and the first information bit block is one of the K information bit blocks; the second bit block depends on the output of the second encoder with a third bit block as input, the third bit block includes K check bit blocks, and the K information bit blocks are used to generate the K check bit blocks.

38. The method in the second node according to claim 37, characterized in that, The ratio between the size of the input to the second encoder and the size of the second bit block depends on K.

39. The method in the second node according to any one of claims 31 to 38, characterized in that, include: Execute the encoding of the first encoder; Perform the encoding using the second encoder; The second node sends the first signal.

40. The method in the second node according to any one of claims 31 to 38, characterized in that, include: Perform the decoding of the decoder corresponding to the first encoder; Perform the decoding of the decoder corresponding to the second encoder; The second node receives the first signal.

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