A memory access request transmitting circuit and an artificial intelligence accelerator

By dynamically selecting the target memory access path and sending order through the conflict-aware memory access request unit, the memory access conflict problem in the AI ​​accelerator is solved, and the storage bandwidth utilization and memory access efficiency are improved.

CN122240533APending Publication Date: 2026-06-19YUAN LI (BEI JING) BAN DAO TI JI SHU YOU XIAN GONG SI
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
YUAN LI (BEI JING) BAN DAO TI JI SHU YOU XIAN GONG SI
Filing Date
2026-02-09
Publication Date
2026-06-19

AI Technical Summary

Technical Problem

Current mainstream AI accelerators, under multi-processor parallel architecture, struggle to achieve efficient data path utilization under different AI network structures, leading to memory access conflicts, increased latency, and decreased bandwidth utilization.

Method used

By using conflict-aware memory access request units, historical access path information and memory access path costs are utilized to dynamically select the target memory access path and sending order, avoiding concurrent access to the same memory bank or shared interconnect resources, thereby improving storage bandwidth utilization.

Benefits of technology

It effectively alleviates network congestion, reduces average memory access latency, improves storage bandwidth utilization and memory access efficiency, and adapts to the current network conditions to reduce resource conflicts.

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Abstract

This invention discloses a memory access request transmitting circuit and an artificial intelligence accelerator, including a processing unit for generating multiple memory access requests; and a conflict-aware memory access request unit for, upon receiving the multiple memory access requests sent by the processing unit, determining the target memory access path and target sending order corresponding to the multiple memory access requests based on historical access path information and memory access path costs, and sending the memory access requests and their corresponding target memory access paths to the storage access network according to the target sending order. By dynamically selecting target memory access paths that are adapted to the current network state and have lower expected overhead and fewer resource conflicts for each memory access request, and generating a matching target sending order, network congestion and resource contention problems caused by concurrent access to the same storage unit or shared interconnect resources are avoided, thereby improving storage bandwidth utilization and memory access efficiency.
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