Memory management method and memory controller

Abstract

A memory management method and memory controller are disclosed. The method includes: receiving a write instruction, the write instruction including data to be written and a corresponding first data tag, and temporarily storing the data to be written; counting the number of accesses to the data to be written within a preset period; determining a second data tag for the data to be written based on a comparison of the number of accesses with the preset threshold; if the first data tag and the second data tag are different, determining a target threshold based on the first data tag, and comparing the number of accesses with the target threshold to determine the data attribute of the data to be written; and writing the data to be written to a storage area corresponding to the data attribute. This disclosure can improve the accuracy of data classification.

Description

Technical Field

[0001] This disclosure relates to the field of data storage technology, and in particular to a memory management method and memory controller for optimizing hierarchical data storage. Background Technology

[0002] In the field of data storage, "hot data" refers to data that is frequently accessed and requires a fast response time, and is typically placed on high-performance storage media; "cold data," on the other hand, refers to data that is accessed less frequently but needs to be retained for a long time, and is typically placed on high-density storage media. Effectively distinguishing between hot and cold data and storing it in appropriate storage areas is of great significance for improving the overall performance of the storage system.

[0003] Currently, to achieve hot and cold data separation, host systems typically determine the hot / cold attribute of data based on file attributes and write the data streams with corresponding tags to the storage device. While host systems can respond quickly to hot / cold data determination based on file attributes, file attributes only represent the intended use of the data and cannot predict the actual user access behavior. When there is a discrepancy between the host system's prediction and the actual access behavior, it may lead to inaccurate hot / cold data classification, resulting in incorrect data placement. For example, actual cold data that is predicted as hot data may occupy space in high-performance storage areas, while actual hot data that is predicted as cold data may be stored in low-speed storage areas, ultimately leading to increased write amplification of the storage device and a decrease in overall performance.

[0004] Therefore, how to verify and correct the hot and cold data attributes by combining the host system's predictive information with the actual access behavior inside the storage device is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] In view of this, the present disclosure provides a memory management method and a storage device, which establishes a verification and correction mechanism between the pre-judgment information on the host system side and the actual access behavior inside the storage device through a two-stage data attribute determination mechanism and a differentiated threshold adjustment based on the first data tag, thereby improving the accuracy of hot and cold data classification and reducing write amplification and performance loss caused by data placement errors.

[0006] According to one or more embodiments of this disclosure, this disclosure provides a memory management method, including: receiving a write instruction, the write instruction including data to be written and a corresponding first data tag, and temporarily storing the data to be written; counting the number of accesses to the data to be written within a preset period; determining a second data tag for the data to be written based on a comparison result of the number of accesses and a preset threshold; if the first data tag and the second data tag are the same, determining the data attribute of the data to be written as the second data tag; if the first data tag and the second data tag are different, determining a target threshold based on the first data tag, and comparing the number of accesses with the target threshold to determine the data attribute of the data to be written; and writing the data to be written to a storage area corresponding to the data attribute.

[0007] According to one or more embodiments of the present disclosure, a storage device is provided, including: a memory controller; a buffer memory coupled to the memory controller; and a memory module coupled to the memory controller, the memory module including a plurality of storage regions; wherein the memory controller is configured to perform the above-described memory management method.

[0008] Based on the above, the memory management method and storage device provided in this disclosure receive a write instruction containing data to be written and a first data tag, temporarily store the data to be written, count the number of accesses to the data to be written within a preset period, and determine a second data tag based on the comparison result of the access count and a preset threshold. When the first data tag and the second data tag are the same, the memory controller uses the second data tag as a data attribute; when the first data tag and the second data tag are different, the memory controller determines a target threshold based on the first data tag and compares the access count with the target threshold to determine the data attribute. Finally, the memory controller writes the data to be written to the corresponding storage area according to the data attribute. Through the above-mentioned two-stage determination mechanism and differentiated threshold adjustment, this disclosure can combine the host system's predictive information with the actual access behavior inside the storage device for verification and correction, thereby improving the accuracy of hot and cold data classification. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a host system and storage device according to an embodiment of the present disclosure;

[0010] Figure 2 This is a flowchart illustrating a memory management method according to an embodiment of the present disclosure;

[0011] Figure 3 This is a detailed flowchart illustrating the data attribute determination according to an embodiment of the present disclosure;

[0012] Figure 4A This is a schematic diagram illustrating the principle of differentiated threshold adjustment according to an embodiment of the present disclosure;

[0013] Figure 4B This is a schematic diagram illustrating a target threshold determination method according to an embodiment of the present disclosure;

[0014] Figure 5 This is a schematic diagram of a storage region structure according to an embodiment of the present disclosure;

[0015] Figure 6 This is a schematic diagram illustrating an overview of the dynamic adjustment of a target threshold according to an embodiment of the present disclosure;

[0016] Figure 7 This is a flowchart illustrating the system load perception target threshold adjustment according to an embodiment of the present disclosure;

[0017] Figure 8 This is a flowchart illustrating the adjustment of the storage space-aware target threshold according to an embodiment of the present disclosure;

[0018] Figure 9 A flowchart illustrating an untrusted data type tag according to an embodiment of this disclosure;

[0019] Figure 10 This is a schematic diagram illustrating a three-level hot / cold classification according to an embodiment of the present disclosure;

[0020] Figure 11 This is a schematic diagram illustrating a two-stage decision calculation example according to an embodiment of the present disclosure;

[0021] Figure 12 This is a timing diagram of a memory management method according to an embodiment of the present disclosure. Detailed Implementation

[0022] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0023] Figure 1 This is a block diagram illustrating a host system and storage device according to embodiments of the present disclosure. Please refer to... Figure 1The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also called a second processor), host memory 120 (also called host RAM), and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also called electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be disposed on the motherboard of the host system 10.

[0024] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214.

[0025] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0026] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0027] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, the data transmission interface circuit 130 and the connection interface circuit 230 transmit data using the Non-Volatile Memory Express (NVMe) communication protocol.

[0028] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0029] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0030] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the memory module 220 according to the instructions of the host system 10, and to execute the memory management method provided in this disclosure.

[0031] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / codes, and these control instructions / codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data.

[0032] Furthermore, the processor 211 is configured to execute the memory management method provided in this disclosure. Specifically, the processor 211 receives a write instruction from the host system 10, the write instruction including data to be written and a corresponding first data tag, and temporarily stores the data to be written in the buffer memory 214; the processor 211 counts the number of accesses to the data to be written within a preset period, and determines a second data tag of the data to be written based on the comparison result of the number of accesses and a preset threshold; when the first data tag and the second data tag are the same, the processor 211 determines that the data attribute of the data to be written is the second data tag; when the first data tag and the second data tag are different, the processor 211 determines a target threshold based on the first data tag, and compares the number of accesses with the target threshold to determine the data attribute of the data to be written; finally, the processor 211 instructs the memory interface control circuit 213 to write the data to be written to the corresponding storage area in the memory module 220 according to the data attribute.

[0033] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuit (ASIC), programmable logic device (PLD), or other similar circuit components, and this disclosure is not limited thereto.

[0034] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0035] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to perform data transmission. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the memory module 220 via the memory interface control circuit 213. Alternatively, it performs a read operation according to a read instruction from the host system 10, reads data from one or more physical units of the memory module 220 via the memory interface control circuit 213, and writes the read data to the host system 10 via the connection interface circuit 230. In one embodiment, the data management circuit 212 cooperates with the processor 211 to parse the write instruction to obtain a first data tag and temporarily stores the data to be written in the buffer memory 214. Furthermore, the data management circuit 212 is also used to monitor access requests for the data to be written temporarily stored in the buffer memory 214 and notify the processor 211 of access events so that the processor 211 can count the number of accesses.

[0036] In another embodiment, the data management circuit 212 may also be integrated into the processor 211. The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform write (also known as programming), read, or erase operations on the memory module 220.

[0037] Furthermore, data to be written to memory module 220 is converted into a format acceptable to memory module 220 via memory interface control circuit 213. Specifically, if processor 211 needs to access memory module 220, processor 211 transmits a corresponding instruction sequence to memory interface control circuit 213 to instruct memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0038] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses of physical units (e.g., physical erase units / physical blocks, physical pages) configured for the memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also called the logical-to-physical mapping table) to find the physical unit mapped to a logical unit (e.g., finding the physical page mapped to a logical page; finding the physical address mapped to a logical address), and the memory controller 210 can use the physical-to-logical address mapping table (also called the physical-to-logical mapping table) to find the logical unit mapped to a physical unit (e.g., finding the logical page mapped to a physical page; finding the logical address mapped to a physical address).

[0039] Buffer memory 214 is electrically connected to processor 211 and is used to temporarily store data and instructions from host system 10, data from memory module 220, and various system data for managing storage device 20. In this embodiment, buffer memory 214 is also used to store data to be written, access count statistics for each piece of data to be written, a threshold configuration table, and the cumulative number of conflict events for each data type. The threshold configuration table records the mapping relationship between multiple data tags and multiple target thresholds, which processor 211 queries when the first data tag and the second data tag are different to determine the target threshold.

[0040] The memory module 220 is electrically connected to the memory controller 210 (specifically, electrically connected to the memory interface control circuit 213) and is used to store user data sent by the host system 10. In this disclosure, the memory module 220 includes multiple storage areas, including at least a hot data storage area and a cold data storage area, used to store data determined to be hot and cold attributes, respectively; the processor 211 writes the data to be written to the corresponding storage area according to the data attributes of the data to be written. In one embodiment, the hot data storage area consists of memory blocks with a first write endurance, and the cold data storage area consists of memory blocks with a second write endurance, wherein the first write endurance is higher than the second write endurance.

[0041] In one embodiment, the memory cell structure of the memory module 220 can be understood as a multi-layered physical organization architecture. Specifically, the memory module 220 includes multiple chips, each chip has multiple planes, and each plane contains multiple physical blocks, each physical block consisting of multiple physical pages. It should be noted that this disclosure is not limited to the specific size of each physical page and logical page.

[0042] Reference Figure 2 , Figure 2 This is a flowchart illustrating a memory management method according to an embodiment of the present disclosure. In one embodiment, the memory management method provided by the present disclosure is applied to the memory controller 210 of the storage device 20 to determine the data attributes of the data to be written, and to store the data to be written into the corresponding storage area according to the determination result. Specifically, the memory management method provided by the present disclosure includes steps S210 to S270.

[0043] In step S210, the memory controller 210 (e.g., processor 211) receives a write instruction, which includes the data to be written and a corresponding first data tag, and temporarily stores the data to be written. Specifically, in one embodiment, when the host system 10 sends the write instruction, it pre-determines the hot / cold data attributes of the data to be written based on information such as file attributes, application type, or historical access characteristics, and transmits the determination result as the first data tag along with the write instruction to the processor 211. After receiving the write instruction through the connection interface circuit 230, the processor 211 parses the write instruction to obtain the data to be written and the corresponding first data tag, and temporarily stores the data to be written in the buffer memory 214. In this embodiment, the first data tag may include a hot tag and a cold tag, where a hot tag indicates that the host system 10 predicts that the data will be accessed frequently, and a cold tag indicates that the host system 10 predicts that the data will be accessed less frequently.

[0044] In this embodiment, the first data tag may include a hot tag and a cold tag, where a hot tag indicates that the host system 10 predicts the data will be accessed frequently, and a cold tag indicates that the host system 10 predicts the data will be accessed less frequently. It should be noted that the term "tag" in this disclosure refers to a classification label assigned by the host system 10 or processor 211 based on prediction or preliminary judgment before the data attributes are finally determined; while "attribute" refers to the hot / cold characteristics of the data finally determined through a two-stage determination mechanism. Both tags and attributes can be numerically represented as hot or cold, but they are at different stages in the determination process.

[0045] In step S220, the processor 211 counts the number of accesses to the data to be written within a preset period. Specifically, in one embodiment, after the data to be written is temporarily stored in the buffer memory 214, the processor 211 initiates an access statistics mechanism to monitor and record the access requests of the host system 10 to the data to be written within the preset period. Access requests may include read requests and write requests. The processor 211 counts the sum of the number of read requests and the number of write requests for the data to be written within the preset period as the number of accesses to the data to be written. In one embodiment, the preset period may be configured as a fixed time length, such as 30 seconds, 1 minute, or 5 minutes, and this disclosure does not limit it.

[0046] In step S230, the processor 211 determines the second data tag of the data to be written based on the comparison result between the access count and a preset threshold. Specifically, in one embodiment, the processor 211 compares the access count obtained in step S220 with a preset threshold. When the access count is greater than the preset threshold, the processor 211 determines that the second data tag of the data to be written is a hot tag; when the access count is less than or equal to the preset threshold, the processor 211 determines that the second data tag of the data to be written is a cold tag. The second data tag reflects the actual access behavior of the data to be written during its temporary storage in the buffer memory 214 and can serve as an independent determination result of the processor 211 regarding the hot and cold characteristics of the data.

[0047] In step S240, the processor 211 determines whether the first data tag and the second data tag are the same. Specifically, in one embodiment, the processor 211 compares the first data tag provided by the host system 10 with the second data tag determined in step S230 to determine whether the host system's prediction and the storage device's internal determination are consistent. When the first data tag and the second data tag are the same, step S250 is executed; when the first data tag and the second data tag are different, step S260 is executed.

[0048] In step S250, if the first data tag and the second data tag are the same, the processor 211 determines that the data attribute of the data to be written is the second data tag. Specifically, in one embodiment, when the prediction result of the host system 10 is consistent with the judgment result of the processor 211 based on the actual access behavior, it indicates that the prediction on the host system side is accurate. At this time, the processor 211 directly accepts the consistent judgment result and uses the second data tag as the data attribute. In this way, the processor 211 can skip the subsequent differential threshold adjustment step when the prediction on the host system side is accurate, thereby reducing unnecessary computational overhead.

[0049] In step S260, if the first data tag is different from the second data tag, the processor 211 determines a target threshold based on the first data tag and compares the number of accesses with the target threshold to determine the data attribute of the data to be written. Specifically, in one embodiment, when the prediction result of the host system 10 differs from the internal determination result of the processor 211, the processor 211 uses a differentiated threshold adjustment mechanism to correct the determination. The processor 211 queries the pre-configured threshold configuration information based on the first data tag to obtain the target threshold corresponding to the first data tag. The processor 211 compares the number of accesses with the target threshold. When the number of accesses is greater than the target threshold, the data attribute is determined to be a hot attribute; when the number of accesses is less than or equal to the target threshold, the data attribute is determined to be a cold attribute.

[0050] In one embodiment, the target threshold configuration follows a differentiated trust principle. When the first data tag indicates a hot tag, the target threshold determined by the processor 211 is lower than a preset threshold, making it easier for the data to be written to be identified as a hot attribute even with relatively few accesses, thus reducing the difficulty of being identified as a hot attribute. When the first data tag indicates a cold tag, the target threshold determined by the processor 211 is higher than the preset threshold, requiring more accesses for the data to be written to be identified as a hot attribute, thus increasing the difficulty of being identified as a hot attribute. Through differentiated target threshold configuration, the processor 211 can provide a moderate trust adjustment to the host system's prediction when there is a discrepancy between the host system's prediction and the internal judgment result, thereby providing a preset correction mechanism.

[0051] In step S270, the processor 211 writes the data to be written to the storage area corresponding to the data attribute. Specifically, in one embodiment, the processor 211 instructs the memory interface control circuit 213 to write the data to be written from the buffer memory 214 to the corresponding storage area in the memory module 220 according to the data attribute determined in step S250 or step S260. When the data attribute is a hot attribute, the processor 211 writes the data to be written to the hot data storage area in the memory module 220; when the data attribute is a cold attribute, the processor 211 writes the data to be written to the cold data storage area in the memory module 220.

[0052] For example, suppose the preset threshold is configured as 30, the target threshold is configured as 18 when the first data tag is a hot tag, and as 45 when the first data tag is a cold tag. There are two data entries, data A and data B, to be written. Data A is pre-determined as a hot tag by the host system 10, and data B is pre-determined as a cold tag by the host system 10. Both data entries are accessed 35 times within a preset period. For data A, the processor 211 compares the access count of 35 with the preset threshold 30. Since 35 is greater than 30, the processor 211 determines that the second data tag is a hot tag. The processor 211 determines that the first data tag (hot tag) and the second data tag (hot tag) are the same, and therefore directly determines that the data attribute of data A is a hot attribute. For data B, the processor 211 compares the access count of 35 with the preset threshold 30. Since 35 is greater than 30, the processor 211 determines that the second data tag is a hot tag. The processor 211 determines that the first data tag (cold tag) and the second data tag (hot tag) are different, and therefore enters the differential threshold adjustment stage. Processor 211 obtains the corresponding target threshold 45 based on the first data tag (cold tag) and compares the access count 35 with the target threshold 45. Since 35 is less than 45, processor 211 determines that the data attribute of data B is a cold attribute.

[0053] In the example above, although data A and data B have the same access count of 35, the final data attribute determination results differ due to the different predictions made by the host system 10. For data A, both the host system and internal system determine it to be a hot tag, and the processor 211 directly accepts this result. For data B, the host system determines it to be a cold tag, but the internal system determines it to be a hot tag, and the two are inconsistent. The processor 211 corrects this through a differentiated threshold adjustment mechanism. Since the host system 10 determines data B to be a cold tag, the processor 211 configures a higher target threshold 45, requiring data B to have a higher access count to be determined as a hot attribute. Ultimately, the access count of 35 fails to exceed the target threshold 45, and data B is determined to be a cold attribute. Through this mechanism, when there is a discrepancy between the host system's prediction and internal determination, the processor 211 gives the host system's prediction a certain degree of trust, allowing the final determination result to comprehensively consider both the host system's intended use and the storage device's actual access behavior.

[0054] Reference Figure 3 , Figure 3 This is a detailed flowchart illustrating the data attribute determination according to an embodiment of the present disclosure. Figure 3 The process shown corresponds to Figure 2The specific implementation of steps S230 to S260 divides the data attribute determination process into a first stage S310 and a second stage S320. The first stage S310 is the second data tag determination stage, and the second stage S320 is the consistency verification and differentiation adjustment stage. Through the two-stage determination mechanism, the processor 211 can quickly complete the determination when the prediction on the host system is accurate, and perform differentiation correction when the prediction on the host system is inconsistent with the internal determination result.

[0055] In the first stage S310, the processor 211 performs the second data tag determination. First, in step S311, the processor 211 obtains the access count and a preset threshold. The access count is... Figure 2 In step S220, the number of accesses to the data to be written within a preset period is statistically calculated. The preset threshold is a judgment standard pre-configured by the processor 211 to distinguish between hot and cold tags. Next, in step S312, the processor 211 determines whether the number of accesses is greater than the preset threshold. When the number of accesses is greater than the preset threshold, in step S314, the processor 211 determines that the second data tag is a hot tag; when the number of accesses is less than or equal to the preset threshold, in step S313, the processor 211 determines that the second data tag is a cold tag. In step S315, the processor 211 determines the second data tag, completing the first stage of judgment.

[0056] In the second stage S320, the processor 211 performs consistency verification and differential adjustment. First, in step S321, the processor 211 determines whether the first data tag and the second data tag are the same. The first data tag is the prediction result provided by the host system 10 with the write instruction, and the second data tag is the second data tag determined in the first stage S310. When the first data tag and the second data tag are the same, it indicates that the prediction on the host system side is consistent with the internal judgment result on the storage device side, and the processor 211 directly uses the second data tag as a data attribute and proceeds to step S326 to complete the judgment. When the first data tag and the second data tag are different, it indicates that there is a discrepancy between the prediction on the host system side and the internal judgment result on the storage device side, and the processor 211 enters the differential adjustment process.

[0057] In step S322, the processor 211 determines the target threshold based on the first data tag. Specifically, the processor 211 queries pre-configured threshold configuration information according to the first data tag to obtain the target threshold corresponding to the first data tag. The configuration of the target threshold follows the principle of differentiated trust: when the first data tag indicates a hot tag, the target threshold is configured as a value lower than the preset threshold; when the first data tag indicates a cold tag, the target threshold is configured as a value higher than the preset threshold.

[0058] In step S323, processor 211 determines whether the number of accesses is greater than the target threshold. If the number of accesses is greater than the target threshold, in step S325, processor 211 determines the data attribute as a "hot" attribute; if the number of accesses is less than or equal to the target threshold, in step S324, processor 211 determines the data attribute as a "cold" attribute. In step S326, processor 211 determines the data attribute, completing the two-stage determination process.

[0059] For example, suppose the preset threshold is configured as 30, the target threshold is configured as 18 when the first data tag is a hot tag, and as 45 when the first data tag is a cold tag. Existing data A is pre-determined as a hot tag by the host system 10 and is accessed 20 times within a preset period. In the first stage S310, the processor 211 obtains the access count 20 and the preset threshold 30. Since 20 is less than or equal to 30, the processor 211 determines that the second data tag is a cold tag. In the second stage S320, the processor 211 determines that the first data tag (hot tag) and the second data tag (cold tag) are different, and thus enters the differentiation adjustment process. The processor 211 determines the target threshold as 18 based on the first data tag (hot tag) and determines whether the access count 20 is greater than the target threshold 18. Since 20 is greater than 18, the processor 211 determines that the data attribute of data A is a hot attribute.

[0060] In the example above, although the number of accesses to data A (20) did not exceed the preset threshold (30), because the host system 10 predicted that the data was a hot tag, the processor 211 used a lower target threshold (18) for correction in the second stage. Ultimately, the number of accesses (20) exceeded the target threshold (18), and data A was determined to be a hot attribute. This reflects the differentiated trust mechanism of this disclosure: when the host system predicts that a data is a hot tag, the processor 211 reduces the difficulty of determining that the data is a hot attribute by configuring a lower target threshold, thereby giving the host system a certain degree of trust in its prediction.

[0061] In another example, suppose data B is pre-determined as a cold tag by host system 10 and is accessed 35 times within a preset period. In the first stage S310, processor 211 obtains the access count 35 and the preset threshold 30. Since 35 is greater than 30, processor 211 determines that the second data tag is a hot tag. In the second stage S320, processor 211 determines that the first data tag (cold tag) and the second data tag (hot tag) are different, and thus enters the differentiation adjustment process. Processor 211 determines the target threshold to be 45 based on the first data tag (cold tag) and determines whether the access count 35 is greater than the target threshold 45. Since 35 is less than or equal to 45, processor 211 determines that the data attribute of data B is a cold attribute.

[0062] In the example above, although the number of accesses to data B (35) exceeded the preset threshold (30), because the host system 10 predicted that the data was a "cold" label, the processor 211 used a higher target threshold (45) for correction in the second stage. Ultimately, the number of accesses (35) failed to exceed the target threshold (45), and data B was determined to be a "cold" attribute. This also reflects the differentiated trust mechanism: when the host system predicts that the data is a "cold" label, the processor 211 increases the difficulty of determining that the data is a "hot" attribute by configuring a higher target threshold, making it more inclined to maintain the determination of a "cold" attribute.

[0063] pass Figure 3 The illustrated two-stage determination mechanism integrates host system-side pre-judgment and storage device-side internal judgment. In the first stage, processor 211 independently determines the data based on actual access behavior, obtaining a second data tag reflecting the data access frequency. In the second stage, processor 211 verifies the accuracy of the host system-side pre-judgment through consistency verification, and corrects it using a differentiated threshold adjustment mechanism when the two are inconsistent. This two-stage determination mechanism allows processor 211 to utilize host system-side pre-judgment information while simultaneously verifying and correcting it based on actual access behavior from the storage device, thereby improving the accuracy of data attribute determination.

[0064] Reference Figure 4A , Figure 4A This is a schematic diagram illustrating the principle of differentiated threshold adjustment according to an embodiment of the present disclosure. Figure 4A This demonstrates the adjustment direction of the target threshold relative to the preset threshold and its impact on the judgment result when the first data label is different.

[0065] like Figure 4A As shown in the upper part, when the first data tag indicates a hot tag, the processor 211 configures the target threshold to a value lower than the preset threshold. In the figure, GF41 represents the scenario where the first data tag indicates a hot tag, and arrow A41 indicates the direction of threshold reduction. Under this configuration, the target threshold is located to the left of the preset threshold, causing the area determined as hot to expand to the left on the number axis. Specifically, when the target threshold is lower than the preset threshold, even if the number of accesses to the data to be written does not reach the preset threshold, it can still be determined as hot as long as it exceeds the target threshold. This configuration reduces the difficulty of determining it as hot, reflecting the processor 211's trust in the host system's hot tag prediction: since the host system 10 predicts that the data is hot based on file attributes or application characteristics, the processor 211 provides a certain degree of positive support for this prediction, making it easier for the data to maintain its hot attribute determination result even with relatively few accesses.

[0066] like Figure 4AAs shown in the lower half, when the first data tag indicates a cold tag, the processor 211 configures the target threshold to a value higher than the preset threshold. In the figure, GF42 represents the scenario where the first data tag indicates a cold tag, and arrow A42 indicates the direction of threshold increase. Under this configuration, the target threshold is located to the right of the preset threshold, causing the area judged as hot data to shrink to the right on the number axis. Specifically, when the target threshold is higher than the preset threshold, the number of accesses to the data to be written must exceed the higher target threshold to be judged as hot data. This configuration increases the difficulty of being judged as hot data, reflecting the processor 211's trust in the host system's cold tag prediction: since the host system 10 predicts that the data is cold data, the processor 211 raises the judgment standard, requiring a higher number of accesses to overturn the host system's prediction.

[0067] Through the aforementioned differentiated threshold adjustment mechanism, the processor 211 achieves "conditional trust" in the host system's prediction. Conditional trust means that the processor 211 neither completely relies on nor completely ignores the host system's prediction. Instead, when a discrepancy arises between the internal judgment (second data tag) at the storage device and the host system's prediction (first data tag), the processor adjusts the judgment criteria (target threshold) to exert a moderate influence on the host system's prediction. When the host system predicts a "hot" tag, the processor 211 lowers the target threshold, making the judgment result more inclined towards a "hot" attribute; when the host system predicts a "cold" tag, the processor 211 raises the target threshold, making the judgment result more inclined towards a "cold" attribute.

[0068] For example, suppose the preset threshold is 30. When the first data tag is a hot tag, the target threshold is configured to be 18, and when the first data tag is a cold tag, the target threshold is configured to be 45. There are two data entries, data A and data B, to be written. Data A is pre-determined as a hot tag by the host system 10 and is accessed 25 times within a preset period. Since 25 is less than the preset threshold of 30, the second data tag is determined to be a cold tag. At this point, the first data tag (hot tag) and the second data tag (cold tag) are different, and the processor 211 enters the differentiation adjustment stage, obtaining the target threshold of 18 based on the hot tag. Since the number of accesses 25 is greater than the target threshold of 18, the processor 211 ultimately determines that the data attribute of data A is a hot attribute.

[0069] For data B, suppose it is pre-judged as a cold tag by host system 10 and accessed 35 times within a preset period. Since 35 is greater than the preset threshold 30, the second data tag is determined to be a hot tag. At this time, the first data tag (cold tag) and the second data tag (hot tag) are different, and processor 211 enters the differentiation adjustment stage, obtaining the target threshold 45 based on the cold tag. Since the number of accesses 35 is less than the target threshold 45, processor 211 finally determines that the data attribute of data B is a cold attribute. In the above example, although data A has fewer accesses (25 times), it is ultimately judged as a hot attribute because the host pre-judged it as a hot tag; although data B has more accesses (35 times), it is ultimately judged as a cold attribute because the host pre-judged it as a cold tag. This fully demonstrates how the differentiation threshold adjustment mechanism combines the host pre-judgment to correct the internal judgment result.

[0070] Reference Figure 4B , Figure 4B This is a schematic diagram illustrating a target threshold determination method according to an embodiment of the present disclosure. Figure 4B As shown, this disclosure provides three methods for determining the target threshold: Method A (table lookup method, T41), Method B (offset calculation method, T42), and Method C (scaling factor calculation method, T43). All three methods can be implemented. Figure 4A The differentiated threshold adjustment principle shown is that when the first data label indicates a hot label, the target threshold is lower than the preset threshold, and when the first data label indicates a cold label, the target threshold is higher than the preset threshold.

[0071] like Figure 4B As shown in T41 on the left, Method A is the lookup table method. In this method, the processor 211 pre-establishes a threshold configuration table, which records the mapping relationship between multiple data labels and multiple target thresholds. When the processor 211 needs to determine a target threshold, it queries the threshold configuration table based on the first data label to find the target threshold that matches the first data label. Figure 4B The example threshold configuration table shown has the following characteristics: when the first data label is a hot label, the corresponding target threshold is 18; when the first data label is a warm label, the corresponding target threshold is 30; and when the first data label is a cold label, the corresponding target threshold is 45. The advantage of the lookup table method is that it can directly obtain the corresponding target threshold without performing any calculations.

[0072] like Figure 4BAs shown in T42, Method B is the offset calculation method. In this method, the processor 211 presets a threshold value and configures a corresponding threshold offset for each first data tag. The processor 211 calculates the sum of the preset threshold value and the threshold offset to obtain the target threshold value. When the first data tag indicates a hot tag, the threshold offset is configured as a negative value, making the target threshold value lower than the preset threshold value; when the first data tag indicates a cold tag, the threshold offset is configured as a positive value, making the target threshold value higher than the preset threshold value. Figure 4B The calculation example shown assumes a preset threshold of 30, a threshold offset of -12 for hot tags, and a target threshold of 30 plus -12 equaling 18; a threshold offset of +15 for cold tags, and a target threshold of 30 plus +15 equaling 45. The offset calculation method is characterized by a smaller number of parameters and easier adjustment. The processor 211 only needs to maintain the preset threshold and the threshold offset for each data tag, without needing to maintain a complete threshold configuration table.

[0073] like Figure 4B As shown in T43 on the right, Method C is the scaling factor calculation method. In this method, the processor 211 presets a threshold and configures a corresponding threshold scaling factor for each first data tag. The processor 211 calculates the product of the preset threshold and the threshold scaling factor to obtain the target threshold. When the first data tag indicates a hot tag, the threshold scaling factor is configured to a positive value less than 1, making the target threshold lower than the preset threshold; when the first data tag indicates a cold tag, the threshold scaling factor is configured to a value greater than 1, making the target threshold higher than the preset threshold. Figure 4B The calculation example shown assumes a preset threshold of 30 and a threshold scaling factor of 0.6 for hot tags. Therefore, the target threshold is 30 multiplied by 0.6, which equals 18. For cold tags, the threshold scaling factor is 1.5, so the target threshold is 30 multiplied by 1.5, which equals 45. The scaling factor calculation method is characterized by its proportional adjustment; the target threshold and the preset threshold have a linear relationship. When the preset threshold is adjusted, the target threshold also changes proportionally.

[0074] In one embodiment, the processor 211 can select any one of the three methods described above to determine the target threshold according to system design requirements. The three methods are technically equivalent and can all achieve the principle of differentiated threshold adjustment: when the first data tag indicates a hot tag, the target threshold is lower than the preset threshold; when the first data tag indicates a cold tag, the target threshold is higher than the preset threshold. For example, the lookup table method is suitable for application scenarios that require independent and fine-grained configuration of each data tag; the offset calculation method is suitable for application scenarios that require rapid adjustment and have a limited number of parameters; and the scaling factor calculation method is suitable for application scenarios that require the target threshold to be adjusted proportionally with the preset threshold.

[0075] It should be noted that, Figure 4B The target threshold, threshold offset, and threshold scaling factor are merely exemplary and not limited thereto. These parameters can be set according to the manufacturer's requirements. In some embodiments, the scaling factor can be adjusted to a corresponding degree based on the temperature level of the data set by the host system 10. For example, the threshold scaling factor corresponding to "extremely hot data" can be set to be smaller than the threshold scaling factor for "hot data".

[0076] Reference Figure 5 , Figure 5 This is a schematic diagram illustrating a storage region structure according to an embodiment of the present disclosure. Figure 5 As shown, the memory module 220 includes a hot data storage area 221 and a cold data storage area 222 with different erase and write durability, which are used to store data to be written that are determined to be hot and cold, respectively.

[0077] In one embodiment, the hot data storage area 221 consists of storage blocks with a first write endurance, and the cold data storage area 222 consists of storage blocks with a second write endurance, wherein the first write endurance is higher than the second write endurance. Write endurance refers to the number of write / erase cycles a storage block can withstand during its lifetime; a storage block with higher write endurance can withstand more data write and erase operations. Since hot data is accessed more frequently, its write and update frequency is correspondingly higher. Therefore, storing hot data in the hot data storage area 221 with higher write endurance allows this storage area to withstand frequent write operations without prematurely exhausting its lifetime. Conversely, cold data is accessed less frequently, and its write and update frequency is correspondingly lower. Therefore, storing cold data in the cold data storage area 222 with lower write endurance can meet the cold data storage requirements while saving high-endurance storage resources.

[0078] In one embodiment, the hot data storage area 221 includes single-level cell (SLC) storage blocks, and the cold data storage area 222 includes triple-level cell (TLC) storage blocks or quad-level cell (QLC) storage blocks. Each storage cell of an SLC storage block stores 1 bit of data, offering high write endurance and fast read / write speeds; each storage cell of a TLC storage block stores 3 bits of data, offering high storage density but relatively low write endurance; each storage cell of a QLC storage block stores 4 bits of data, offering even higher storage density but even lower write endurance. By storing hot data in SLC storage blocks and cold data in TLC or QLC storage blocks, the processor 211 can achieve a match between storage medium characteristics and data access characteristics, enabling hot data to achieve faster access speeds and higher write endurance, while simultaneously achieving higher storage density for cold data.

[0079] like Figure 5 As shown, processor 211 monitors the number of free blocks in hot data storage area 221 via arrow A51 and monitors the number of free blocks in cold data storage area 222 via arrow A52. A free block refers to a storage block in a storage area that has not yet been written with valid data or has been erased and is available for writing new data. Processor 211 continuously monitors the number of free blocks in hot data storage area 221 and cold data storage area 222 to understand the available storage space status of each storage area. When the number of free blocks in a storage area falls below a preset threshold, it indicates that the available storage space in that storage area is insufficient. Processor 211 can then trigger a corresponding threshold adjustment strategy to control the amount of data written to that storage area.

[0080] For example, in one embodiment, assuming the total number of storage blocks in the hot data storage area 221 is 100, the processor 211 sets a threshold value of 20% of the total number of storage blocks, i.e., 20 blocks. When the processor 211 detects that the number of free blocks in the hot data storage area 221 is less than 20, it indicates that the available storage space in the hot data storage area 221 is tight. To prevent the hot data storage area 221 from being unable to accept new hot data due to insufficient space, the processor 211 can increase the target threshold value, so that subsequent data to be written requires more accesses to be determined as hot data, thereby reducing the amount of data determined as hot data and written to the hot data storage area 221. Similarly, when the processor 211 detects that the number of free blocks in the cold data storage area 222 is less than the threshold value, the processor 211 can decrease the target threshold value, so that subsequent data to be written is more easily determined as hot data, thereby reducing the amount of data determined as cold data and written to the cold data storage area 222. By combining the monitoring of the number of free blocks with dynamic adjustment of thresholds, the processor 211 can dynamically adjust the distribution ratio of hot and cold data according to the actual available space status of each storage area, so as to maintain the balance of space usage in each storage area.

[0081] It is worth mentioning that, in another embodiment, the memory module 220 may include more than two storage areas to correspond to three or more levels of hot and cold data classification. Specifically, when the first data tag includes a hot tag, a warm tag, and a cold tag, and the data attributes include hot attributes, warm attributes, and cold attributes, the memory module 220 may include a hot data storage area 221 corresponding to the hot attribute, a cold data storage area 222 corresponding to the cold attribute, and a warm data storage area (not shown) corresponding to the warm attribute. The hot data storage area 221 consists of storage blocks with a first write endurance, the warm data storage area consists of storage blocks with a third write endurance, and the cold data storage area 222 consists of storage blocks with a second write endurance, wherein the first write endurance is higher than the third write endurance, and the third write endurance is higher than the second write endurance. In one embodiment, the hot data storage area 221 may include SLC storage blocks, the warm data storage area may include multi-level cell (MLC) storage blocks or TLC storage blocks, and the cold data storage area 222 may include TLC storage blocks or QLC storage blocks. By setting up multiple storage areas and assigning them to different data attribute levels, the processor 211 can achieve more refined data routing, allowing data with different access characteristics to be stored in storage areas that match those characteristics, thereby achieving a balance between storage performance and storage capacity.

[0082] It should be noted that, in another embodiment, write endurance can be characterized or determined by various technical indicators. Besides the method of differentiating write endurance by storage cell type (SLC, MLC, TLC, QLC) as described above, the processor 211 can also determine the write endurance level of each storage block based on the number of program / erase cycles (P / E Cycle). Specifically, the processor 211 can maintain the P / E Cycle count information for each storage block and classify the storage blocks into different write endurance levels based on the P / E Cycle count value. Storage blocks with lower P / E Cycle count values ​​indicate a longer remaining write endurance, can be classified as having a higher write endurance level, and are allocated to the hot data storage area 221; storage blocks with higher P / E Cycle count values ​​indicate a shorter remaining write endurance, can be classified as having a lower write endurance level, and are allocated to the cold data storage area 222. In this way, the processor 211 can perform dynamic hierarchical management of each storage block in the same type of storage unit according to the actual usage status of each storage block, so that the storage blocks with longer remaining lifespans can be given priority to carry hot data with higher writing frequency, thereby extending the overall lifespan of the memory module 220.

[0083] Reference Figure 6 , Figure 6 This is a schematic diagram illustrating an overview of dynamic adjustment of a target threshold according to an embodiment of this disclosure. Figure 6 As shown, the processor 211 can dynamically adjust the target threshold based on two factors: system workload (S611) and hot data storage area status (S612) (S620), and use the adjusted target threshold as a comparison benchmark for data attribute determination (S630).

[0084] In one embodiment, such as Figure 6 As shown in S611 on the left, the processor 211 counts the system workload within a preset monitoring period. The system workload is the total number of read and write requests issued by the host system 10 to the storage device 20. The system workload reflects the overall intensity of access activity experienced by the storage device 20 within the preset monitoring period. When the system workload exceeds the upper limit threshold, it indicates that the storage device 20 is operating under high load. In this case, even if a piece of data to be written is accessed frequently, it may only reflect a general increase in overall access activity, rather than that the data itself has high access frequency. Accordingly, the processor 211 raises the target threshold to make the data attribute judgment criteria more adaptable to the system workload, thereby filtering out data that truly has high access frequency. Conversely, when the system workload is below the lower limit threshold, it indicates that the storage device 20 is operating under low load. In this case, the processor 211 can lower the target threshold to make the data attribute judgment criteria relatively lenient, thereby identifying data that is relatively active under low load conditions.

[0085] In one embodiment, such as Figure 6 As shown in S612 on the right, the processor 211 detects the number of free blocks in the hot data storage area to understand the available storage space status of the hot data storage area. When the number of free blocks in the hot data storage area is lower than the threshold, it indicates that the available storage space in the hot data storage area is tight. To prevent the hot data storage area from being unable to accept new hot data due to insufficient space, the processor 211 increases the target threshold, so that subsequent data to be written requires more accesses to be determined as hot data, thereby reducing the amount of data determined as hot data and written to the hot data storage area.

[0086] In one embodiment, such as Figure 6 As shown in S620, the processor 211 dynamically adjusts the target threshold by comprehensively considering the system workload and the status of the hot data storage area. The dynamically adjusted target threshold will serve as the comparison benchmark for data attribute determination in step S630, enabling the processor 211 to adopt appropriate determination criteria based on the current system operating status and storage space status when determining the data attributes of the data to be written.

[0087] In one embodiment, the processor 211 can independently apply the system workload awareness mechanism and the storage space awareness mechanism, or it can combine the two mechanisms. When both mechanisms simultaneously trigger target threshold adjustment, the processor 211 can adopt a higher adjustment range, or determine the final target threshold according to a preset priority rule. Through the target threshold dynamic adjustment mechanism, the processor 211 can dynamically adjust the judgment criteria of data attributes according to the actual operating state of the storage device 20, so that the judgment results can adapt to different system load conditions and storage space conditions, thereby improving the adaptability and accuracy of hot and cold data classification.

[0088] Reference Figure 7 , Figure 7 This is a flowchart illustrating the adjustment of the system load perception target threshold according to an embodiment of the present disclosure. Figure 7 The process shown corresponds to Figure 6 The specific implementation steps for dynamically adjusting the target threshold in the system workload (S611).

[0089] In step S710, the processor 211 counts the system workload within a preset monitoring period. Specifically, in one embodiment, the processor 211 maintains a system access counter in a buffer memory 214 to count the total number of read and write requests issued by the host system 10 to the storage device 20 within the preset monitoring period. The preset monitoring period can be configured to a fixed time length, such as 1 minute, 5 minutes, or 10 minutes, and this disclosure does not limit it. After the preset monitoring period ends, the processor 211 obtains the value of the system access counter as a quantitative indicator of the system workload.

[0090] In step S720, the processor 211 determines whether the system workload exceeds the load limit threshold. The load limit threshold is a pre-set threshold value used by the processor 211 to determine a high-load state. When the system workload exceeds the load limit threshold, the processor 211 determines that the storage device 20 is currently in a high-load state and proceeds to step S721; when the system workload is less than or equal to the load limit threshold, the processor 211 proceeds to step S730 to continue the determination.

[0091] In step S721, the processor 211 increases the target threshold. Specifically, when the storage device 20 is under high load, the overall system access frequency is high. Even if a piece of data to be written is accessed frequently, it may only reflect a general increase in overall access activity, rather than the data itself having high access frequency. Therefore, the processor 211 adjusts the target threshold upwards to make the data attribute judgment criteria more stringent, in order to filter out data that truly has high access frequency and avoid misclassifying a large amount of data as hot data due to the increased overall access frequency.

[0092] In step S730, the processor 211 determines whether the system workload is less than the lower load threshold. The lower load threshold is a pre-set threshold value for determining a low load state, and it is less than the upper load threshold. When the system workload is less than the lower load threshold, the processor 211 determines that the storage device 20 is currently in a low load state and proceeds to step S731; when the system workload is greater than or equal to the lower load threshold, it indicates that the system workload is between the lower load threshold and the upper load threshold, and the processor 211 determines that the storage device 20 is currently in a medium load state and proceeds to step S732.

[0093] In step S731, the processor 211 lowers the target threshold. Specifically, in one embodiment, when the storage device 20 is under low load, the overall system access frequency is low. Even if a piece of data to be written is accessed infrequently, it may still be considered relatively active data relative to the overall access activity. Accordingly, the processor 211 adjusts the target threshold downwards, making the criteria for determining data attributes more lenient, in order to identify relatively active data under low load conditions and avoid misjudging data with a certain level of access frequency as cold data due to the reduced overall access frequency.

[0094] In step S732, the processor 211 maintains the target threshold unchanged. Specifically, in one embodiment, when the storage device 20 is under medium load, the overall system access frequency is within the normal range, and the processor 211 does not need to adjust the target threshold, maintaining the original target threshold as the judgment criterion.

[0095] In step S740, processor 211 performs data attribute determination based on the adjusted target threshold. Specifically, in one embodiment, processor 211 compares the number of accesses to the data to be written with the target threshold determined in steps S721, S731, or S732 to determine the data attributes of the data to be written, and then... Figure 2 and Figure 3 The process shown continues with subsequent consistency verification and differentiation adjustment steps.

[0096] For example, suppose processor 211 is set to a preset monitoring period of 10 minutes, a lower load threshold of 500 access requests per minute, an upper load threshold of 2000 access requests per minute, and a baseline target threshold of 30. Within a certain preset monitoring period, processor 211 detects a system workload of 2500 access requests per minute, exceeding the upper load threshold of 2000, and determines that the system is currently under high load. Processor 211 calculates the adjusted target threshold based on a preset load adjustment coefficient (assumed to be 1.5), i.e., 30 multiplied by 1.5 equals 45. A piece of data to be written is accessed 35 times. Under the baseline target threshold of 30, it would be classified as a "hot" data item, but under the adjusted target threshold of 45 under high load conditions, it would be classified as a "cold" data item. Through the system load-aware target threshold adjustment mechanism, processor 211 can dynamically adjust the judgment criteria according to the current actual operating status of the system, making the data attribute judgment results more accurately reflect the access frequency of each piece of data relative to the overall system access activity.

[0097] Reference Figure 8 , Figure 8 This is a flowchart illustrating the adjustment of the target threshold for storage space awareness according to an embodiment of the present disclosure. Figure 8 The process shown corresponds to Figure 6The specific implementation steps for dynamically adjusting the target threshold in the state of the hot data storage area (S612) are further extended to the spatial perception of the cold data storage area.

[0098] In step S810, the processor 211 detects the number of free blocks in the storage area. Specifically, in one embodiment, the processor 211 detects the number of free blocks in the hot data storage area and the cold data storage area respectively. A free block refers to a storage block in the storage area that has not yet been written with valid data or has been erased and is available for writing new data. The processor 211 may perform the free block count detection periodically, or perform the free block count detection before each data attribute determination, to obtain the latest available space status of each storage area.

[0099] In step S820, processor 211 determines whether the number of free blocks in the hot data storage area is lower than a quantity threshold. The quantity threshold is a pre-set threshold value for processor 211 to determine the storage space shortage state, and can be configured as a fixed number or a fixed proportion of the total storage area capacity. When the number of free blocks in the hot data storage area is lower than the quantity threshold, processor 211 determines that the available storage space in the hot data storage area is scarce and proceeds to step S821; when the number of free blocks in the hot data storage area is greater than or equal to the quantity threshold, processor 211 proceeds to step S830 to continue the determination.

[0100] In step S821, the processor 211 increases the target threshold. Specifically, in one embodiment, when the available storage space in the hot data storage area is limited, to prevent the hot data storage area from being unable to accept new hot data due to insufficient space, the processor 211 adjusts the target threshold upwards. Increasing the target threshold requires a higher number of accesses for subsequent data to be determined as hot data in the second-stage differential adjustment. By increasing the target threshold, the processor 211 can reduce the amount of data determined as hot data and written to the hot data storage area, thereby alleviating the space pressure on the hot data storage area.

[0101] In step S830, processor 211 determines whether the number of free blocks in the cold data storage area is lower than a quantity threshold. When the number of free blocks in the cold data storage area is lower than the quantity threshold, processor 211 determines that the available storage space in the cold data storage area is tight and proceeds to step S831; when the number of free blocks in the cold data storage area is greater than or equal to the quantity threshold, it indicates that the available storage space in both the hot data storage area and the cold data storage area is within the normal range, and processor 211 proceeds to step S832.

[0102] In step S831, the processor 211 lowers the target threshold. Specifically, in one embodiment, when the available storage space in the cold data storage area is limited, to prevent the cold data storage area from being unable to accept new cold data due to insufficient space, the processor 211 adjusts the target threshold downwards. Lowering the target threshold makes it easier for subsequent data to be written to be determined as hot data in the second-stage differential adjustment. By lowering the target threshold, the processor 211 can reduce the amount of data determined as cold and written to the cold data storage area, thereby alleviating the space pressure on the cold data storage area.

[0103] In step S832, the processor 211 maintains the target threshold unchanged. Specifically, when the available storage space in both the hot data storage area and the cold data storage area is within the normal range, the processor 211 does not need to adjust the target threshold and maintains the original target threshold configuration as the judgment criterion.

[0104] In step S840, processor 211 performs data attribute determination based on the adjusted target threshold. Specifically, processor 211 compares the number of accesses to the data to be written with the target threshold determined in steps S821, S831, or S832, and determines the data attribute based on the adjusted target threshold. Figure 2 and Figure 3 The process shown executes the second data label determination, consistency verification, and differential adjustment steps.

[0105] For example, assuming the total number of storage blocks in the hot data storage area is 100, the processor 211 sets a threshold of 20% of the total number of storage blocks, i.e., 20 blocks, and a baseline target threshold of 30. When the processor 211 detects that the number of free blocks in the hot data storage area is 15, which is lower than the threshold of 20, the processor 211 determines that the available storage space in the hot data storage area is tight. The processor 211 calculates the adjusted target threshold based on a preset space adjustment coefficient (assuming it is 1.3), i.e., 30 multiplied by 1.3 equals 39. If a piece of data to be written has been accessed 35 times, it will be judged as hot under the baseline target threshold of 30, but under the adjusted target threshold of 39 under the tight space condition, it will be judged as cold, and thus written to the cold data storage area instead of the hot data storage area. Through the storage space-aware target threshold adjustment mechanism, the processor 211 can dynamically adjust the distribution ratio of hot and cold data according to the actual available space status of each storage area to maintain the balance of space usage in each storage area and avoid affecting the normal operation of the storage device 20 due to the exhaustion of space in a single storage area.

[0106] Reference Figure 9 , Figure 9 This is a flowchart illustrating the untrusted data type marking according to an embodiment of the present disclosure. Figure 9The process shown is used to identify the accuracy of the host system 10's prediction of specific data types, and to mark data types with low prediction accuracy in order to identify data types that are not trustworthy, thereby optimizing the subsequent data attribute determination process.

[0107] In step S910, the processor 211 detects that the first data tag is different from the data attribute. Specifically, when the processor 211 completes... Figure 2 and Figure 3 After the two-stage determination process shown, if the final determined data attribute differs from the first data tag provided by the host system 10, it indicates a discrepancy between the host system's prediction and the storage device's final determination. This discrepancy may stem from the host system 10's inaccurate prediction of the data's hot / cold characteristics, prompting the processor 211 to trigger a conflict event recording mechanism.

[0108] In step S920, the processor 211 records the conflict event and determines the data type. Specifically, the processor 211 records a conflict event as a case where the first data tag and data attribute are different, and determines the data type of the data to be written based on the metadata of the data to be written. The metadata may include information such as file type, file extension, application source, and directory path. The processor 211 classifies the data to be written into the corresponding data type according to the metadata. For example, the processor 211 may classify a file with the extension ".log" as a log file type, a file with the extension ".tmp" as a temporary file type, and data from a specific application as the data type corresponding to that application.

[0109] In step S930, the processor 211 counts the cumulative number of conflict events. Specifically, the processor 211 maintains a conflict event counter for each data type to count the cumulative number of conflict events corresponding to each data type within a preset statistical period. When a conflict event occurs in the data to be written of a certain data type, the processor 211 increments the conflict event counter corresponding to that data type. After the preset statistical period ends, the processor 211 can obtain the cumulative number of conflict events for each data type within that statistical period.

[0110] In step S940, processor 211 determines whether the cumulative number of conflict events exceeds the untrusted label threshold. The untrusted label threshold is a pre-set threshold value used by processor 211 to determine the credibility of data type predictions. When the cumulative number of conflict events for a certain data type exceeds the untrusted label threshold, it indicates that the host system 10 has low accuracy in predicting the hot and cold characteristics of that data type, and processor 211 proceeds to step S950; when the cumulative number of conflict events is less than or equal to the untrusted label threshold, processor 211 does not perform special labeling for that data type and maintains the original judgment process.

[0111] In step S950, the processor 211 marks the data type as an untrusted data type. Specifically, the processor 211 maintains a list of untrusted data types in the buffer memory 214, adding data types whose cumulative number of conflict events exceeds the untrusted marking threshold to this list. Data types marked as untrusted indicate that the host system 10 has a systematic bias in its prediction of the hot / cold characteristics of this type of data; in subsequent processing, the processor 211 will no longer rely on the host system's prediction result for this data type.

[0112] like Figure 9 As shown in step S960, for subsequent data to be written that belongs to an untrusted data type, the processor 211 directly determines the data attribute based on the second data tag in subsequent processing. Specifically, when the processor 211 receives data to be written that belongs to an untrusted data type, the processor 211 still performs the second data tag determination in the first stage to obtain the second data tag, but skips the differential adjustment step in the second stage that determines the target threshold based on the first data tag, and directly uses the second data tag as the data attribute. In this way, the processor 211 no longer adjusts the pre-judgment trust level for data types with low prediction accuracy, but makes the judgment entirely based on the actual access behavior inside the storage device.

[0113] For example, suppose processor 211 sets a preset statistical period of 1 hour and an untrusted labeling threshold of 10 times. Within a certain preset statistical period, the data type "temporary file" experiences 15 conflict events, meaning that 15 pieces of data to be written belonging to the temporary file type have different first data tags and data attributes. Since the cumulative number of conflict events (15) exceeds the untrusted labeling threshold of 10, processor 211 marks "temporary file" as an untrusted data type. In subsequent write operations, when processor 211 receives data to be written belonging to the temporary file type, even if the host system 10 predicts that the data is a hot tag, processor 211 will no longer configure a lower target threshold based on this hot tag prediction, but will directly determine the data attribute based on the comparison result between the access count and the preset threshold. Through the untrusted data type labeling mechanism, processor 211 can identify and adapt to the systematic prediction bias of the host system 10 for specific data types, avoiding errors in hot and cold data classification due to continuous reliance on inaccurate prediction information.

[0114] Reference Figure 10 , Figure 10 This is a schematic diagram illustrating a three-level hot / cold classification according to an embodiment of the present disclosure. Figure 10 It demonstrates the comparison rules between access counts and preset thresholds when data tags and data attributes are expanded to three-level classifications, as well as the correspondence between each attribute and storage area.

[0115] like Figure 10As shown in B100 above, in the embodiment of the three-level hot and cold classification, the preset thresholds include a first preset threshold and a second preset threshold. These two preset thresholds divide the access count axis into three intervals. The configuration of the first and second preset thresholds ensures that the first preset threshold is less than the second preset threshold. The processor 211 determines the second data tag for the data to be written based on the comparison result between the access count and the first and second preset thresholds. Specifically, when the access count is less than or equal to the first preset threshold, the processor 211 determines the second data tag as a cold tag; when the access count is greater than the first preset threshold and less than or equal to the second preset threshold, the processor 211 determines the second data tag as a warm tag; and when the access count is greater than the second preset threshold, the processor 211 determines the second data tag as a hot tag.

[0116] like Figure 10 As shown in B101 below, in the embodiment of the three-level cold and hot classification, the memory module 220 includes a cold data storage area 222 corresponding to the cold attribute, a warm data storage area 223 corresponding to the warm attribute, and a hot data storage area 221 corresponding to the hot attribute. The processor 211 writes the data to be written to the corresponding storage area according to the data attribute. When the data attribute is cold, the processor 211 writes the data to be written to the cold data storage area 222; when the data attribute is warm, the processor 211 writes the data to be written to the warm data storage area 223; and when the data attribute is hot, the processor 211 writes the data to be written to the hot data storage area 221.

[0117] In one embodiment, the three storage regions employ different types of storage units to match the access characteristics of the attribute data. For example... Figure 10 As shown, the hot data storage area 221 may include SLC (or MLC) storage blocks, which have high write endurance and fast read / write speeds, suitable for storing frequently accessed hot data; the warm data storage area 223 may include MLC (or TLC) storage blocks, which have medium write endurance and storage density, suitable for storing moderately accessed warm data; the cold data storage area 222 may include TLC (or QLC) storage blocks, which have high storage density but relatively low write endurance, suitable for storing infrequently accessed cold data. Through this three-tiered storage area configuration, the processor 211 can achieve more refined data routing, allowing data with different access characteristics to be stored in storage areas that match their characteristics.

[0118] For example, suppose processor 211 sets a first preset threshold of 15 and a second preset threshold of 40. There are three data entries to be written: data A, data B, and data C. These entries are accessed 10 times, 25 times, and 50 times respectively within a preset period. For data A, since the access count of 10 is less than or equal to the first preset threshold of 15, processor 211 determines that the second data tag of data A is a cold tag. For data B, since the access count of 25 is greater than the first preset threshold of 15 and less than or equal to the second preset threshold of 40, processor 211 determines that the second data tag of data B is a warm tag. For data C, since the access count of 50 is greater than the second preset threshold of 40, processor 211 determines that the second data tag of data C is a hot tag. In the three-level cold / hot classification embodiment, processor 211 also performs the second-stage consistency verification and differentiation adjustment process. When the first data tag and the second data tag are different, a target threshold is determined based on the first data tag for correction.

[0119] In another embodiment, when a three-level hot / cold classification is adopted, the configuration of the target threshold is also extended accordingly to include a first target threshold and a second target threshold. The processor 211 can configure corresponding combinations of the first and second target thresholds for hot, warm, and cold tags respectively to achieve differentiated threshold adjustment under the three-level classification. For example, when the first data tag is a hot tag, the processor 211 configures a lower first target threshold and a lower second target threshold, making it easier for the data to be written to be determined as warm or hot; when the first data tag is a cold tag, the processor 211 configures a higher first target threshold and a higher second target threshold, making it necessary for the data to be written to be accessed more times to be determined as warm or hot.

[0120] Reference Figure 11 , Figure 11 This is a schematic diagram illustrating a two-stage decision calculation example according to an embodiment of the present disclosure. Figure 11 The specific numerical examples demonstrate the determination process and results of the memory management method provided in this disclosure under different scenarios.

[0121] like Figure 11 As shown in B111 above, the scenario settings for this calculation example are as follows: the preset threshold is configured as 30, the target threshold is configured as 18 when the first data label is a hot label, and the target threshold is configured as 45 when the first data label is a cold label. Under this scenario setting, Figure 11 Table T111 below lists the determination process and results for four pieces of data to be written (data A, data B, data C, and data D).

[0122] For data A, the host system 10 predicts that the first data tag is a hot tag, having been accessed 35 times within a preset period. In the first stage, the processor 211 compares the access count of 35 with a preset threshold of 30. Since 35 is greater than 30, the processor 211 determines that the second data tag is a hot tag. The processor 211 determines that the first data tag (hot tag) and the second data tag (hot tag) are the same, indicating that the host system's prediction is consistent with the storage device's internal determination. The processor 211 directly uses the second data tag as a data attribute, determining that data A's data attribute is a hot attribute. The determination path for data A is "consistent → direct," without needing to enter the differentiation adjustment stage.

[0123] For data B, the host system 10 predicts that the first data tag is a hot tag, having been accessed 20 times within a preset period. In the first stage, the processor 211 compares the access count 20 with a preset threshold 30. Since 20 is less than 30, the processor 211 determines the second data tag to be a cold tag. The processor 211's determination that the first data tag (hot tag) and the second data tag (cold tag) are different indicates a discrepancy between the host system's prediction and the storage device's internal determination, prompting the processor 211 to enter a differentiation adjustment stage. The processor 211 determines a target threshold of 18 based on the first data tag (hot tag) and compares the access count 20 with the target threshold 18. Since 20 is greater than 18, the processor 211 determines that data B's data attribute is a hot attribute. The determination path for data B is "inconsistency → differentiation adjustment." Through the differentiation threshold adjustment mechanism, data B is ultimately determined to be a hot attribute, reflecting the processor 211's trust in the host system's hot tag prediction.

[0124] For data C, the host system 10 predicts that the first data tag is a cold tag, having been accessed 35 times within a preset period. In the first stage, the processor 211 compares the access count of 35 with a preset threshold of 30. Since 35 is greater than 30, the processor 211 determines that the second data tag is a hot tag. The processor 211 determines that the first data tag (cold tag) and the second data tag (hot tag) are different, indicating a discrepancy between the host system's prediction and the storage device's internal determination. The processor 211 then enters a differentiation adjustment stage. Based on the first data tag (cold tag), the processor 211 determines a target threshold of 45 and compares the access count of 35 with the target threshold 45. Since 35 is less than 45, the processor 211 determines that the data attribute of data C is a cold attribute. The determination path for data C is "inconsistency → differentiation adjustment." Through the differentiation threshold adjustment mechanism, data C is ultimately determined to be a cold attribute, reflecting the processor 211's trust in the host system's cold tag prediction.

[0125] For data D, the host system 10 predicts that the first data tag is a cold tag, accessed 50 times within a preset period. In the first stage, the processor 211 compares the access count 50 with a preset threshold 30. Since 50 is greater than 30, the processor 211 determines that the second data tag is a hot tag. The processor 211 determines that the first data tag (cold tag) and the second data tag (hot tag) are different, indicating a discrepancy between the host system's prediction and the storage device's internal determination. The processor 211 then enters a differentiation adjustment stage. Based on the first data tag (cold tag), the processor 211 determines a target threshold of 45 and compares the access count 50 with the target threshold 45. Since 50 is greater than 45, the processor 211 determines that the data attribute of data D is a hot attribute. The determination path for data D is "inconsistency → differential adjustment". Although the host system 10 predicts that data D is a cold label, the memory controller 210 still determines data D as a hot attribute because the number of accesses 50 exceeds the higher target threshold 45. This reflects that while the differential threshold adjustment mechanism gives the host system confidence in its prediction, it still uses the actual access behavior as the final determination basis.

[0126] pass Figure 11 The calculation example shown illustrates that data A and data C have the same number of visits (35), but due to different predictions from the host system, their final data attribute classifications differ. Data A, predicted as a "hot" tag by the host system and with its visit count exceeding the preset threshold of 30, is directly classified as a "hot" attribute. Data C, although also having 35 visits, is classified as a "cold" tag by the host system, which uses a higher target threshold of 45. Since its visit count does not exceed the target threshold of 45, it is ultimately classified as a "cold" attribute. This comparison demonstrates how the differentiated threshold adjustment mechanism incorporates host system prediction information into the final classification process, allowing data with the same visit frequency to receive different data attribute classifications due to different host system predictions.

[0127] Reference Figure 12 , Figure 12 This is a timing diagram of a memory management method according to an embodiment of the present disclosure. Figure 12 The interaction process between the host system 10, processor 211, buffer memory 214 and memory module 220 is shown in the form of a timing diagram. The memory management method is divided into three stages: write instruction reception and data temporary storage (stage one S1210), count of accesses within a preset period (stage two S1220), and two-stage data attribute determination (stage three S1230).

[0128] In stage one, S1210, the memory controller 210 performs write instruction reception and data temporary storage. First, in step S1211, the host system 10 sends a write instruction to the processor 211. The write instruction includes the data to be written and a corresponding first data tag. The first data tag is a data tag pre-determined by the host system 10 based on information such as file attributes, application type, or historical access characteristics. Next, in step S1212, the processor 211 instructs the buffer memory 214 to temporarily store the data to be written, temporarily storing the data to be written in the buffer memory 214 for subsequent processing. In step S1213, the processor 211 parses the write instruction to determine the first data tag and extracts the pre-determined information provided by the host system 10 from the metadata of the write instruction.

[0129] It should be noted that, in one embodiment, the write instruction is not limited to external instructions from the host system 10, but may also include internal write instructions generated within the storage device 20. Specifically, when the memory controller 210 performs background operations such as garbage collection, wear leveling, or read reclaim, the processor 211 generates an internal write instruction containing data to be written (such as valid data to be migrated), and pre-determines the hot / cold attribute of the data based on the type of background operation or the data source as a first data tag. For example, data migrated in wear leveling operations is usually static data that has not been accessed for a long time, and the processor 211 may pre-determine its first data tag as a cold tag; while data frequently moved in garbage collection operations may be pre-determined by the processor 211 as a hot tag. Such internal write instructions and their carried first data tags are also subject to the memory management method and two-stage determination process of this disclosure.

[0130] In stage two, S1220, the memory controller 210 performs a count of accesses within a preset period. Within this preset period, the host system 10 may issue an access request for data to be written, temporarily stored in the buffer memory 214. As shown in the cyclic process of steps S1221 to S1223, whenever the host system 10 issues a read or write access request for the data to be written, the processor 211 receives the access request in step S1221, accesses the temporarily stored data to be written in the buffer memory 214 in step S1222 to respond to the access request, and increments the access count counter corresponding to the data to be written by one in step S1223. This cyclic process continues to execute within the preset period until the preset period ends. After the preset period ends, the processor 211 obtains the cumulative access count of the data to be written within the preset period.

[0131] In stage three (S1230), the memory controller 210 performs a two-stage data attribute determination. First, in step S1231, the processor 211 compares the number of accesses with a preset threshold to determine the second data tag. When the number of accesses is greater than the preset threshold, the processor 211 determines the second data tag as a hot tag; when the number of accesses is less than or equal to the preset threshold, the processor 211 determines the second data tag as a cold tag. Next, the processor 211 determines whether the first data tag and the second data tag are the same, and executes different processing paths based on the determination result.

[0132] When the first data tag and the second data tag are different, the processor 211 enters the differentiation adjustment path. In step S1232, the processor 211 determines the target threshold based on the first data tag and queries the pre-configured threshold configuration information according to the first data tag to obtain the corresponding target threshold. In step S1233, the processor 211 compares the number of accesses with the target threshold to determine the data attribute. When the number of accesses is greater than the target threshold, the processor 211 determines the data attribute as a hot attribute; when the number of accesses is less than or equal to the target threshold, the processor 211 determines the data attribute as a cold attribute.

[0133] When the first data tag and the second data tag are the same, the processor 211 enters the direct determination path. In step S1234, the processor 211 directly determines the data attribute as the second data tag without needing to adjust the differentiation threshold.

[0134] Finally, in step S1235, the processor 211 writes the data to be written to the storage area corresponding to the data attribute. Specifically, the processor 211 instructs the memory interface control circuit 213 to write the data to be written from the buffer memory 214 to the corresponding storage area in the memory module 220 according to the data attribute. When the data attribute is a hot attribute, the processor 211 writes the data to be written to the hot data storage area; when the data attribute is a cold attribute, the processor 211 writes the data to be written to the cold data storage area.

[0135] pass Figure 12 As shown in the timing flow, the memory management method provided in this disclosure completes the determination of data attributes in the cache stage before the data is written to the memory module 220, so that the data to be written can be stored in the storage area of ​​the corresponding data attribute when it is written for the first time, avoiding the additional write operation and data migration overhead caused by writing first and then migrating.

[0136] It is worth noting that the parameters and strategies in the memory management method provided in this disclosure can be flexibly configured according to actual application scenarios. Regarding the preset period, in addition to a fixed duration (such as 1 minute), it can also be triggered to end based on conditions such as the cumulative number of accesses reaching a threshold or insufficient available space in the buffer memory 214, so as to balance the sufficiency of statistics and the system response speed. Regarding the access count statistics, only read or write requests can be counted, or different weights can be assigned to the two (for example, the write weight is higher than the read weight) to calculate the weighted access count.

[0137] Regarding the source of the first data tag, the host system 10 can make predictions based on multiple dimensions such as file type (e.g., system file / log file), application source (e.g., database / backup application), directory path, or explicit tags. Regarding threshold configuration (including preset threshold, target threshold, load / space threshold, etc.), in addition to static configuration, the processor 211 can also adopt a dynamic update or adaptive learning mechanism to automatically optimize each threshold parameter based on historical judgment accuracy.

[0138] Regarding the handling of untrusted data types, in addition to directly ignoring the first data tag, strategies such as reducing its influence weight or setting an expiration period for the untrusted tag (automatically reverting upon expiration) can also be adopted. Furthermore, the hot / cold classification levels disclosed in this invention are not limited to two levels (cold / hot), but can be extended to three levels (cold / warm / hot) or more levels. The corresponding number of preset thresholds and the number of storage areas are adjusted accordingly to adapt to different storage media combinations and fine-grained traffic distribution needs.

[0139] In another embodiment, the processor 211 may employ a data migration mechanism to reassess the hot / cold attributes of the data already written to the memory module 220 and migrate the data to a different storage area. Specifically, the hot / cold characteristics of the written data may change over time. Data initially classified as hot may gradually become colder due to decreased access frequency, and data initially classified as cold may gradually become hotter due to increased access frequency. The processor 211 may periodically count the access frequency of the written data. When the current access frequency of a piece of data does not match the hot / cold attribute of its storage area, the processor 211 may migrate the data to a storage area corresponding to its current hot / cold attribute.

[0140] More specifically, the processor 211 maintains an access frequency statistics table of written data in the buffer memory 214, recording the number of accesses to each logical address within a preset monitoring period. When the processor 211 detects that the number of accesses to a piece of data stored in the cold data storage area 222 exceeds the hot data threshold, the processor 211 determines that the data has changed from cold data to hot data and migrates the data from the cold data storage area 222 to the hot data storage area 221. Similarly, when the processor 211 detects that the number of accesses to a piece of data stored in the hot data storage area 221 is lower than the cold data threshold, the processor 211 determines that the data has changed from hot data to cold data and migrates the data from the hot data storage area 221 to the cold data storage area 222. In one embodiment, the processor 211 can perform the data migration operation during system idle periods to avoid affecting normal read and write performance. Through the data migration mechanism, the processor 211 can achieve data lifecycle management, ensuring that each piece of data is always stored in a storage area that matches its current access characteristics.

[0141] In other embodiments, the processor 211 may work in conjunction with a hot and cold data classification mechanism and a garbage collection (GC) mechanism. Specifically, garbage collection is a mechanism used by the processor 211 to reclaim space occupied by invalid data. The processor 211 reads pages containing valid data from the entity block to be reclaimed, rewrites them to a new entity block, and then performs an erase operation on the entity block to be reclaimed to free up storage space.

[0142] During garbage collection, processor 211 can optimize the rewriting strategy for valid data by combining hot and cold data classification information. Specifically, when processor 211 performs garbage collection, it reads the valid data in the entity block to be collected and queries the data attributes corresponding to each valid data or reassesses its access frequency. Based on the data attributes of each valid data, processor 211 rewrites hot data to the free blocks of hot data storage area 221 and cold data to the free blocks of cold data storage area 222. In this way, the garbage collection operation also has the effect of data classification correction, allowing data that may have been misclassified during the initial write to have the opportunity to be reclassified during the garbage collection stage.

[0143] In another embodiment, the processor 211 may prioritize garbage collection operations on the cold data storage area 222. Because cold data is updated less frequently, the proportion of valid data in the cold data storage area 222 is typically higher, resulting in relatively lower garbage collection efficiency. Conversely, the data in the hot data storage area 221 is updated more frequently, and invalid data is generated more quickly, leading to relatively higher garbage collection efficiency. The processor 211 can dynamically adjust the priority and execution frequency of garbage collection based on the number of free blocks and the proportion of valid data in each storage area to achieve a balance between storage space reclamation efficiency and system performance.

[0144] In one embodiment, the host system 10 can transmit the first data tag to the processor 211 via an extended field of the write instruction. Specifically, when the storage device 20 uses the Non-Volatile Memory Express (NVMe) communication protocol, the host system 10 can use a reserved field or a vendor-defined field in the CommandDword of the NVMe write instruction to encapsulate the first data tag.

[0145] More specifically, the NVMe specification defines multiple instruction double words for write commands, with some fields reserved for future use or for vendor customization. The host system 10 can encode the first data tag into a predefined value, such as 0 for a cold tag, 1 for a warm tag, and 2 for a hot tag, and fill this value into a specified field of the write command. Upon receiving the write command, the processor 211 parses the specified field to extract the encoded value of the first data tag and reconstructs the first data tag according to predefined encoding rules.

[0146] In another embodiment, the host system 10 can transmit data tag information to the processor 211 via a DatasetManagement Command in the NVMe instruction set. The DatasetManagement Command supports an attribute field, which the host system 10 can use to indicate the access characteristics of the data, and the processor 211 can then obtain the first data tag. In yet another embodiment, when the storage device 20 uses other communication protocols (such as SATA, SAS, or UFS), the host system 10 can transmit the first data tag via extended fields in the corresponding protocol specification or vendor-defined commands; this disclosure does not limit this method.

[0147] It should be noted that, in one embodiment, the processor 211 may employ a power-off recovery mechanism to ensure that the access statistics state can be saved and restored in the event of a power outage during the statistical process. Specifically, during the data attribute determination process, the processor 211 needs to continuously count the number of accesses for each piece of data to be written within a preset period. If an unexpected power outage occurs within the preset period, the access statistics information stored in the buffer memory 214 may be lost, making it impossible to continue the previous statistical process after the power outage is restored.

[0148] To address the aforementioned issues, the processor 211 can periodically persist access statistics to the system reserved area of ​​the memory module 220. Specifically, the processor 211 can set a persistence period, such as writing the access statistics from the buffer memory 214 to the system reserved area of ​​the memory module 220 every 5 seconds or whenever the cumulative number of accesses reaches a preset increment. The access statistics may include the logical address of each piece of data to be written, the current number of accesses, the start time of the preset period, and the elapsed time, etc.

[0149] When the storage device 20 recovers from a power outage, the processor 211 reads the most recently persisted access statistics from the system reserved area of ​​the memory module 220 during the initialization phase, and restores the statistical status of each piece of data to be written accordingly. The processor 211 can calculate the remaining statistical time based on the statistical time elapsed before the power outage and continue to complete the access statistics within the preset period. In another embodiment, if the statistical time elapsed before the power outage exceeds a predetermined proportion (e.g., 80%) of the preset period, the processor 211 can directly determine the data attributes based on the already counted accesses without waiting for the complete preset period to end. Through the power outage recovery mechanism, the processor 211 can ensure the continuity and reliability of the data attribute determination process and avoid affecting the classification accuracy due to the loss of statistical data caused by power outages.

[0150] It is worth mentioning that, in order to set the threshold more dynamically, in another embodiment, the processor 211 may employ a relative threshold determination mechanism to configure the preset threshold as a certain proportion of the total number of accesses within the statistical period. Specifically, within a preset period, the processor 211, in addition to counting the individual access counts of each piece of data to be written, also counts the total number of accesses of all data to be written temporarily stored in the buffer memory 214. After the preset period ends, the processor 211 calculates the preset threshold based on the total number of accesses and a preset proportion factor. The calculation formula is: the preset threshold equals the total number of accesses multiplied by the preset proportion factor. The processor 211 compares the individual access counts of each piece of data to be written with the calculated preset threshold to determine the second data tag.

[0151] More specifically, the processor 211 pre-sets a preset scaling factor, which represents the threshold of the proportion of accesses required to determine a data item as a hot tag relative to the total number of accesses. When the number of accesses to a data item to be written is greater than the preset threshold (i.e., the total number of accesses multiplied by the preset scaling factor), the processor 211 determines that the second data tag of the data item to be written is a hot tag; when the number of accesses to a data item to be written is less than or equal to the preset threshold, the processor 211 determines that the second data tag of the data item to be written is a cold tag.

[0152] For example, suppose processor 211 sets a preset scaling factor of 5%. Within a preset period, buffer memory 214 temporarily stores 50 pieces of data to be written, and the host system 10 accesses these 50 pieces of data a total of 1000 times. Processor 211 calculates a preset threshold as 1000 multiplied by 5%, which equals 50 times. If a piece of data to be written (data A) is accessed 60 times within the preset period, and since 60 is greater than the preset threshold of 50, processor 211 determines that the second data tag of data A is a hot tag; if another piece of data to be written (data B) is accessed 30 times within the preset period, and since 30 is less than the preset threshold of 50, processor 211 determines that the second data tag of data B is a cold tag.

[0153] The relative threshold determination mechanism has the following technical characteristics compared to the fixed threshold determination mechanism. Under the fixed threshold determination mechanism, the preset threshold is a pre-configured fixed value that does not change with the system's operating status. When the overall system access activity is high, multiple pieces of data to be written may simultaneously reach the hot tag determination criteria, leading to space shortage in the hot data storage area 221. When the overall system access activity is low, even relatively active data to be written may be determined as cold-tag because the number of accesses has not reached the fixed threshold. The relative threshold determination mechanism, by configuring the preset threshold as a proportion of the total number of accesses, allows the preset threshold to automatically adjust according to the intensity of the overall system access activity, ensuring that relatively active hot data can be filtered out under different load conditions.

[0154] In another embodiment, when a three-level cold / hot classification is adopted, the processor 211 can set a first preset scaling factor and a second preset scaling factor, wherein the first preset scaling factor is less than the second preset scaling factor. The processor 211 calculates the first preset threshold as the total number of accesses multiplied by the first preset scaling factor, and calculates the second preset threshold as the total number of accesses multiplied by the second preset scaling factor. When the number of accesses to a piece of data to be written is less than or equal to the first preset threshold, the second data tag is determined to be a cold tag; when the number of accesses is greater than the first preset threshold and less than or equal to the second preset threshold, the second data tag is determined to be a warm tag; when the number of accesses is greater than the second preset threshold, the second data tag is determined to be a hot tag.

[0155] For example, suppose processor 211 sets a first preset scaling factor of 2% and a second preset scaling factor of 10%. Within a preset period, the total number of accesses to the data to be written in buffer memory 214 is 2000. Processor 211 calculates the first preset threshold as 2000 multiplied by 2%, which equals 40 accesses, and the second preset threshold as 2000 multiplied by 10%, which equals 200 accesses. If a piece of data to be written is accessed 100 times, and since 100 is greater than the first preset threshold of 40 and less than the second preset threshold of 200, processor 211 determines that the second data tag of this piece of data to be written is a warm tag. Through the combination of a relative threshold determination mechanism and three-level classification, processor 211 can achieve stable and precise hot and cold data separation under different system load conditions.

[0156] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the various steps of the memory management method described above. The computer-readable storage medium can be a non-transitory computer-readable storage medium, such as a read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, hard disk, or solid-state drive. The computer program includes computer-readable instructions that, when executed by the processor 211, cause the processor 211 to perform the memory management method described in the above embodiments.

[0157] In summary, the memory management method and storage device provided in this disclosure perform statistical analysis of access behavior during the caching stage before data is written to the memory module. By combining the first data tag provided by the host based on data attribute information and the second data tag determined by the memory based on the actual number of accesses, a two-stage determination mechanism is adopted to re-determine the data attributes of the data to be written, and accordingly store the data to be written into the corresponding storage area in the memory module.

[0158] Compared with existing technologies that rely solely on host-side prediction or memory-side access frequency statistics, the technical solution disclosed herein has the following technical advantages.

[0159] First, this disclosure uses a consistency verification mechanism to determine whether the host-side prediction and the memory-side internal judgment are consistent. When they are consistent, the judgment result is directly accepted to reduce computational overhead. When they are inconsistent, a differentiated threshold adjustment mechanism is used to correct the judgment. The differentiated threshold adjustment mechanism configures a corresponding target threshold based on the first data tag. When the first data tag indicates a hot tag, a lower target threshold is configured to reduce the difficulty of being judged as a hot attribute; when the first data tag indicates a cold tag, a higher target threshold is configured to increase the difficulty of being judged as a hot attribute. Through this differentiated trust mechanism, this disclosure can give the host-side prediction an appropriate influence when there is a discrepancy between the host-side prediction and the memory-side internal judgment, achieving the fusion of host-side prediction information and actual memory-side access behavior.

[0160] Secondly, this disclosure provides three methods for determining the target threshold: table lookup, offset calculation, and scaling factor calculation. The appropriate method can be selected based on system design requirements. Table lookup is suitable for application scenarios requiring independent and fine-grained configuration of each data label; offset calculation is suitable for application scenarios requiring rapid adjustment and a limited number of parameters; and scaling factor calculation is suitable for application scenarios requiring the target threshold to be adjusted proportionally with a preset threshold.

[0161] Furthermore, this disclosure introduces a system load awareness target threshold adjustment mechanism and a storage space awareness target threshold adjustment mechanism. The system load awareness mechanism senses the overall system workload by statistically analyzing the total number of access requests issued by the host system within a preset monitoring period, and dynamically adjusts the target threshold under high or low load conditions to avoid misjudging the hotness or coldness of individual data due to fluctuations in overall system traffic. The storage space awareness mechanism monitors the available storage space status by detecting the number of free blocks in each storage area, and adjusts the target threshold when storage space is scarce to control the data distribution ratio and maintain a balance in space usage across storage areas.

[0162] Furthermore, this disclosure introduces an untrusted data type marking mechanism. When the cumulative number of conflict events between the first data tag and the data attribute of a certain data type exceeds the untrusted marking threshold, the memory controller marks the data type as untrusted. For subsequent data to be written that belongs to the untrusted data type, the memory controller directly determines the data attribute based on the second data tag, no longer relying on the host's pre-judgment result for the data type. Through this mechanism, the memory controller can identify and adapt to the host system's systematic pre-judgment bias for specific data types, avoiding errors in hot and cold data classification due to continuous reliance on inaccurate pre-judgment information.

[0163] Finally, this disclosure supports multiple cold and hot classification levels, including two-level classification (cold and hot attributes) or three-level classification (cold, warm, and hot attributes). When using three-level classification, the preset thresholds include a first preset threshold and a second preset threshold, and the memory module includes three storage areas corresponding to each attribute. By flexibly configuring the cold and hot classification levels, the memory controller can achieve different levels of data diversion based on the storage medium composition of the memory module and the application scenario requirements, allowing data with different access characteristics to be stored in storage areas that match their characteristics. This achieves a balance between storage performance and storage capacity, reduces write amplification of the storage device, and extends the lifespan of the storage device.

[0164] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A memory management method, characterized in that, include: Receive a write instruction, the write instruction including the data to be written and the corresponding first data tag, and temporarily store the data to be written; The number of times the data to be written is accessed is counted within a preset period; Based on the comparison result between the number of accesses and the preset threshold, the second data tag of the data to be written is determined; If the first data tag is different from the second data tag, a target threshold is determined based on the first data tag, and the number of accesses is compared with the target threshold to determine the data attributes of the data to be written. as well as The data to be written is written to the storage area corresponding to the data attribute.

2. The memory management method according to claim 1, characterized in that, If the first data tag is the same as the second data tag, the data attribute of the data to be written is determined to be the second data tag.

3. The memory management method according to claim 1, characterized in that, The step of determining the target threshold based on the first data label includes: When the first data tag indicates a hot tag, the target threshold is lower than the preset threshold; and When the first data tag indicates a cold tag, the target threshold is higher than the preset threshold.

4. The memory management method according to claim 3, characterized in that, The step of determining the target threshold based on the first data label includes: Access a pre-established threshold configuration table, which records the mapping relationships between multiple data labels and multiple target thresholds; and Find the target threshold that matches the first data label from the threshold configuration table.

5. The memory management method according to claim 4, characterized in that, The step of finding the target threshold that matches the first data label from the threshold configuration table includes: When the first data tag indicates a hot tag, the first target threshold is looked up from the threshold configuration table; When the first data tag indicates a cold tag, the second target threshold is looked up from the threshold configuration table.

6. The memory management method according to claim 3, characterized in that, The step of determining the target threshold based on the first data label includes: Obtain the threshold offset corresponding to the first data label; and The target threshold is obtained by calculating the sum of the preset threshold and the threshold offset. Specifically, when the first data tag indicates a hot tag, the threshold offset is negative; when the first data tag indicates a cold tag, the threshold offset is positive.

7. The memory management method according to claim 3, characterized in that, The step of determining the target threshold based on the first data label includes: Obtain the threshold scaling factor corresponding to the first data label; and The target threshold is obtained by calculating the product of the preset threshold and the threshold scaling factor; Specifically, when the first data tag indicates a hot tag, the threshold scaling factor is less than 1; when the first data tag indicates a cold tag, the threshold scaling factor is greater than 1.

8. The memory management method according to claim 1, characterized in that, Also includes: The system workload within a preset monitoring period is statistically analyzed, and the system workload includes the total number of read requests and write requests. The system workload is compared with load thresholds, which include an upper load threshold and a lower load threshold. When the system workload exceeds the upper limit threshold, the target threshold is increased; and When the system workload is lower than the lower load threshold, the target threshold is lowered.

9. The memory management method according to claim 1, characterized in that, The storage area includes a hot data storage area and a cold data storage area, and the method further includes: Detect the number of free blocks in the storage area; and When the number of free blocks in the hot data storage area is lower than a certain threshold, the target threshold is increased to reduce the amount of data identified as having hot attributes; or When the number of free blocks in the cold data storage area is lower than the number threshold, the target threshold is lowered to reduce the amount of data that is identified as cold.

10. The memory management method according to claim 9, characterized in that, The hot data storage area consists of storage blocks with a first erase / write endurance; The cold data storage area consists of storage blocks with a second erase / write endurance; The first erase / write durability is higher than the second erase / write durability.

11. The memory management method according to claim 1, characterized in that, Also includes: When the first data tag is different from the data attribute, a conflict event is recorded, and the corresponding data type is determined based on the metadata of the data to be written. The cumulative number of conflict events corresponding to each data type within a preset statistical period is calculated. When the cumulative number of conflict events corresponding to the data type exceeds the untrusted labeling threshold, the data type is labeled as an untrusted data type. as well as For subsequent data to be written that belongs to the untrusted data type, the data attributes are determined directly based on the second data tag.

12. The memory management method according to claim 1, characterized in that, The step of determining the second data tag of the data to be written based on the comparison result of the access count and the preset threshold includes: When the number of accesses exceeds the preset threshold, the second data tag is determined to be a hot tag.

13. The memory management method according to claim 1, characterized in that, The step of writing the data to be written to the storage area corresponding to the data attribute includes: The storage area includes a hot data storage area; If the data attribute of the data to be written is a hot attribute, the data to be written is written to the hot data storage area.

14. A memory controller suitable for a storage device configured with a memory module, characterized in that, include: A memory interface control circuit is used to electrically connect to the memory module; as well as A processor, electrically connected to the memory interface control circuit, wherein the processor is configured to: Receive a write instruction, the write instruction including the data to be written and the corresponding first data tag, and temporarily store the data to be written; The number of times the data to be written is accessed is counted within a preset period; Based on the comparison result between the number of accesses and the preset threshold, the second data tag of the data to be written is determined; If the first data tag is different from the second data tag, a target threshold is determined based on the first data tag, and the number of accesses is compared with the target threshold to determine the data attributes of the data to be written; and The data to be written is written to the storage area corresponding to the data attribute. The memory controller is further configured to perform the memory management method according to any one of claims 2 to 13.

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