Method for reporting interruption, method and apparatus for configuring interruption

Abstract

This application discloses a method for reporting interrupts, an interrupt configuration method, and an apparatus. The interrupt reporting method is applied to a node device communicating via a bus system, the node device including an interrupt vector table and an interrupt address table. The method includes: acquiring an interrupt event; generating an interrupt message for the interrupt event. The interrupt message includes an interrupt vector and an interrupt address, the interrupt vector being obtained from the interrupt vector table and the interrupt address being obtained from the interrupt address table; and sending the interrupt message to a network node via the bus system. This application can save the storage space required for interrupt data of interrupt events on the node device, enabling the node device to support more interrupts, thereby improving the operational efficiency of services.

Description

[0001] This application is a divisional application. The original application has the application number 202211706188.2 and the original application date is December 28, 2022. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of interrupt mechanism technology in computer systems, and in particular to a method for reporting interrupts, an interrupt configuration method, and an apparatus. Background Technology

[0003] In computer systems, the Peripheral Component Interconnect Express (PCIe) interface is the primary interface between external devices and System on Chip (SoC). For the production-consumer software model typically used by PCIe external devices, many services on these devices rely on interrupt events, and each service should have its own dedicated interrupt event to improve efficiency.

[0004] In the existing interrupt mechanism under the PCIe protocol, interrupt messages are reported on the node device by sending messages to the host's interrupt controller via memory write, and the message carries the interrupt vector number of the interrupt event. Under this interrupt mechanism, the interrupt data for each interrupt event needs to be pre-recorded in the node device. For example, under the current Message Signaled Interrupt eXtended (MSI-X) mechanism, the interrupt data for each interrupt event is stored in the memory-mapped input / output (MMIO) space on the node device, with a storage space size of 128 bits. Currently, to meet the increasing task demands of node devices, the requirement for the number of interrupt events on the node device is also increasing.

[0005] However, the current main chip on the node device has a limited capacity for storing interrupt data, which means it cannot store a large number of interrupt data events. This results in the aggregation of interrupt events when services on the node device are interrupted, thereby reducing service efficiency. Summary of the Invention

[0006] This application provides a method for reporting interrupts, an interrupt configuration method, and an apparatus, which can save the storage space required for interrupt data of interrupt events on node devices, enabling node devices to support more interrupts, thereby improving the operational efficiency of services.

[0007] In a first aspect, this application provides a method for reporting interrupts, applied to a node device communicating via a bus system, the node device including an interrupt vector table and an interrupt address table; the method includes: acquiring an interrupt event; generating an interrupt message for the interrupt event; wherein the interrupt message includes an interrupt vector and an interrupt address, the interrupt vector being obtained from the interrupt vector table and the interrupt address being obtained from the interrupt address table; and sending the interrupt message to a network node via the bus system.

[0008] From a technical perspective, the interrupt vector and interrupt address in the interrupt message of an interrupt event are stored separately in the interrupt vector table and the interrupt address table, meaning the interrupt address is stored independently. Since different interrupt events typically correspond to the same interrupt address, multiple interrupt events corresponding to the same interrupt address can share this common interrupt address. Compared to existing technologies where the interrupt address and interrupt vector are stored in the same table, and the interrupt address for each interrupt event is stored once in the corresponding entry, this application effectively saves storage space for interrupt event data. Given a fixed storage capacity on the node device, this allows the node device to support more interrupts, thereby improving operational efficiency.

[0009] In one feasible implementation, the interrupt vector table contains a plurality of first entries, each first entry containing an interrupt vector and each first entry corresponding to an interrupt event; the interrupt address table contains at least one second entry, each second entry containing an interrupt address; wherein, the plurality of first entries contains M first entries, the M first entries corresponding to M interrupt events, and the M interrupt events corresponding to the same second entry in the at least one second entry, where M is a positive integer greater than or equal to 2.

[0010] From a technical perspective, under the interrupt mechanism of this application, multiple interrupt events correspond to the same entry in the interrupt address table, meaning these multiple interrupt events share the interrupt address and other data in the same entry. In contrast, in existing technologies, interrupt vectors and interrupt addresses are jointly stored in the interrupt vector table, and each interrupt event corresponds to an entry in the interrupt vector table, containing both the interrupt vector and the interrupt address. That is, in existing technologies, even if multiple interrupt events correspond to the same interrupt address, the interrupt address for each interrupt event is stored once in its corresponding entry. Therefore, compared to existing technologies, this application requires less storage space to store the interrupt data for the same number of interrupt events, effectively saving storage space. Consequently, given a fixed storage capacity on the node device, the node device can support more interrupts, thereby improving operational efficiency.

[0011] In one feasible implementation, the interrupt vector table contains an address index corresponding to the interrupt vector, and the interrupt address is obtained from the interrupt address table based on the address index.

[0012] From a technical perspective, this application establishes a connection between the interrupt address table and the interrupt vector table through address indexing. This allows for rapid location of the required interrupt address during the generation of an interrupt message for an interrupt event, based on the address index contained in the Entry containing the interrupt vector. Furthermore, this application replaces the storage of the interrupt address corresponding to each interrupt event in the prior art by storing the address index of each interrupt address. Since the storage space required for storing the address index is much smaller than that required for storing the interrupt address, it effectively saves the storage space needed to store the interrupt data of the interrupt event.

[0013] In one feasible implementation, each of the second Entries further includes a Destination ID, which indicates the network node to which an interruption message containing the Destination ID is sent; the interruption message also includes the Destination ID.

[0014] From a technical perspective, by including a Dst ID indicating the network node to which the interrupt message is sent, the interrupt message can be sent to network nodes on the local server or other servers to execute the corresponding interrupt. Compared to existing technologies where interrupt messages can only be sent between nodes within the local server, this application extends the interrupt mechanism to a distributed system, improving the versatility and applicability of the interrupt mechanism.

[0015] In one feasible implementation, each of the second Entries further includes a Token ID, which is used by the network node to perform security verification on the interruption address; the interruption message also includes the Token ID.

[0016] From a technical perspective, the interruption message also includes a Token ID for address security verification, which enables the receiving network node to perform security verification after receiving the interruption address, effectively ensuring data security.

[0017] In one feasible implementation, the node device includes one or more of a graphics card, hard disk, network card, and sound card.

[0018] Secondly, this application provides an interrupt configuration method applied to a host communicating via a bus system; the method includes: generating an interrupt event configuration message; wherein the configuration message includes an interrupt vector and an interrupt address, the interrupt vector is configured in an interrupt vector table on a node device, the interrupt address is configured in an interrupt address table on the node device, the node device communicates with the host via the bus system; and sending the configuration message to the node device via the bus system.

[0019] In one feasible implementation, the interrupt vector table contains a plurality of first entries, each first entry containing an interrupt vector and each first entry corresponding to an interrupt event; the interrupt address table contains at least one second entry, each second entry containing an interrupt address; wherein, the plurality of first entries contains M first entries, the M first entries corresponding to M interrupt events, and the M interrupt events corresponding to the same second entry in the at least one second entry, where M is a positive integer greater than or equal to 2.

[0020] In one feasible implementation, the interrupt vector table further includes an address index corresponding to the interrupt vector, the address index pointing to the interrupt address in the interrupt address table.

[0021] In one feasible implementation, the configuration message further includes a Destination ID, which is configured in the interruption address table and is used to indicate the network node to which the interruption message containing the Destination ID is sent; each of the second Entries also includes one of the Destination IDs.

[0022] In one feasible implementation, the configuration message further includes a token ID, which is configured in the interrupt address table and is used by the Host to perform security verification on the interrupt address; each second Entry also includes one of the token IDs.

[0023] In one feasible implementation, the node device includes one or more of a graphics card, hard disk, network card, and sound card.

[0024] Thirdly, this application provides an interrupt reporting device, which communicates via a bus system and stores an interrupt vector table and an interrupt address table. The device includes: an acquisition unit for acquiring an interrupt event; a processing unit for generating an interrupt message for the interrupt event; wherein the interrupt message contains an interrupt vector and an interrupt address, the interrupt vector being obtained from the interrupt vector table and the interrupt address being obtained from the interrupt address table; and a transceiver unit for sending the interrupt message to a network node via the bus system.

[0025] In one feasible implementation, the interrupt vector table contains a plurality of first entries, each first entry containing an interrupt vector and each first entry corresponding to an interrupt event; the interrupt address table contains at least one second entry, each second entry containing an interrupt address; wherein, the plurality of first entries contains M first entries, the M first entries corresponding to M interrupt events, and the M interrupt events corresponding to the same second entry in the at least one second entry, where M is a positive integer greater than or equal to 2.

[0026] In one feasible implementation, the interrupt vector table contains an address index corresponding to the interrupt vector, and the interrupt address is obtained from the interrupt address table based on the address index.

[0027] In one feasible implementation, each of the second Entries further includes a Destination ID, which indicates the network node to which an interruption message containing the Destination ID is sent; the interruption message also includes the Destination ID.

[0028] In one feasible implementation, each of the second Entries further includes a Token ID, which is used by the network node to perform security verification on the interruption address; the interruption message also includes the Token ID.

[0029] Fourthly, this application provides an interrupt configuration apparatus, which communicates via a bus system; the apparatus includes: a processing unit, configured to generate a configuration message for an interrupt event; wherein the configuration message includes an interrupt vector and an interrupt address, the interrupt vector being configured in an interrupt vector table on a node device, the interrupt address being configured in an interrupt address table on the node device, and the node device communicating with the apparatus via the bus system; and a transceiver unit, configured to send the configuration message to the node device via the bus system.

[0030] In one feasible implementation, the interrupt vector table contains a plurality of first entries, each first entry containing an interrupt vector and each first entry corresponding to an interrupt event; the interrupt address table contains at least one second entry, each second entry containing an interrupt address; wherein, the plurality of first entries contains M first entries, the M first entries corresponding to M interrupt events, and the M interrupt events corresponding to the same second entry in the at least one second entry, where M is a positive integer greater than or equal to 2.

[0031] In one feasible implementation, the interrupt vector table further includes an address index corresponding to the interrupt vector, the address index pointing to the interrupt address in the interrupt address table.

[0032] In one feasible implementation, the configuration message further includes a Destination ID, which is configured in the interruption address table and is used to indicate the network node to which the interruption message containing the Destination ID is sent; each of the second Entries also includes one of the Destination IDs.

[0033] In one feasible implementation, the configuration message further includes a token ID, which is configured in the interrupt address table and is used by the Host to perform security verification on the interrupt address; each second Entry also includes one of the token IDs.

[0034] Fifthly, this application provides a network node, the network node including at least one processor, a memory and an interface circuit, the memory, the interface circuit and the at least one processor being interconnected by a line, the memory storing instructions, and when the instructions are executed by the processor, any of the methods described in the second aspect above can be implemented.

[0035] In a sixth aspect, this application provides a network node, which includes a processing circuit, a memory, and an interface circuit. The memory, the interface circuit, and the processing circuit are interconnected by a line. The memory stores instructions, and when the instructions are executed by the processing circuit, any of the methods described in the first aspect above can be implemented.

[0036] In a seventh aspect, embodiments of this application provide a chip system, the chip system including at least one processor, a memory, and an interface circuit, the memory, the interface circuit, and the at least one processor being interconnected via circuits, the at least one memory storing instructions; when the instructions are executed by the processor, any of the methods described in the second aspect above are implemented.

[0037] Eighthly, embodiments of this application provide a chip system, the chip system including a processing circuit, a memory, and an interface circuit, the memory, the interface circuit, and the processing circuit being interconnected via lines, the at least one memory storing instructions; when the instructions are executed by the processing circuit, any of the methods described in the first aspect above are implemented.

[0038] Ninthly, this application provides a server that includes at least one network node as described in the fifth aspect and at least one network node as described in the sixth aspect.

[0039] In a tenth aspect, this application provides a server comprising at least one chip system as described in the seventh aspect and at least one chip system as described in the eighth aspect.

[0040] In the eleventh aspect, this application provides a distributed system comprising at least two servers as described in the ninth or tenth aspect above.

[0041] In a twelfth aspect, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed, enables the implementation of the method described in any one of the first and / or second aspects described above.

[0042] In a thirteenth aspect, embodiments of this application provide a computer program product, the computer program including instructions that, when executed, enable the implementation of the method described in any one of the first and / or second aspects described above. Attached Figure Description

[0043] The accompanying drawings used in the embodiments of this application are described below.

[0044] Figure 1 A schematic diagram of the architecture of a distributed system provided in this application embodiment; Figure 2 A schematic diagram of the system architecture of a computer device provided in this application embodiment; Figure 3 A system architecture diagram of another computer device provided in this application embodiment; Figure 4 A flowchart illustrating an interrupt configuration method provided in this application embodiment; Figure 5 This is a schematic diagram illustrating a data organization format on a node device, as provided in an embodiment of this application. Figure 6 A schematic diagram of the logical structure of an interrupt vector table and an interrupt address table provided in an embodiment of this application; Figure 7 A flowchart illustrating a method for reporting an interruption is provided in this application embodiment; Figure 8 A schematic diagram of a device for reporting interruptions provided in an embodiment of this application; Figure 9 A schematic diagram of an interrupt configuration device provided in an embodiment of this application; Figure 10 A schematic diagram of the hardware structure of a network node provided in an embodiment of this application; Figure 11 This is a schematic diagram of the hardware structure of another network node provided in an embodiment of this application. Detailed Implementation

[0045] The embodiments of this application are described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " represents "or," for example, A / B can represent A or B; "and / or" in the text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0046] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a particular order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses. The reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0047] The following is a description of the technical terms used in this application: (1) Interrupt: When a network node (including the host and other node devices) is executing the current program, due to an emergency situation that needs to be handled, the network node suspends the program it is executing and instead executes another special program (usually called an interrupt service routine) to handle the emergency (this emergency is also the interrupt event reported by the node device to the network node in this application). After the interrupt event is handled, the network node automatically returns to the previously suspended program to continue execution. This situation where the execution process is interrupted due to external reasons is called an interrupt.

[0048] (2) Function Entity: The smallest granularity of the addressable functional component in the bus system, capable of initiating or responding to transaction operations and capable of being managed. Specifically, it is a hardware module on the node device that can independently report interrupts.

[0049] (3) Host: also known as System on Chip (SoC), is an integrated circuit that includes a processor, memory and on-chip logic.

[0050] (4) Interrupt Vector: The entry address of the interrupt service routine. When a node device reports an interrupt event to the network node, the network node can call the interrupt service routine through the interrupt vector, and then execute the task that needs to be handled urgently.

[0051] (5) Interrupt Address: The storage address used to store the above interrupt vector during the interrupt reporting process.

[0052] (6) Interrupt Vector Table: In this application, each functional entity corresponds to multiple interrupt events, and each functional entity also corresponds to an interrupt vector table. This interrupt vector table is used to store partial interrupt data for each of the multiple interrupt events. Specifically, this partial interrupt data includes the interrupt vector, the mask state, and the address index pointing to the interrupt address, etc.

[0053] (7) Interrupt Address Table: In this application, each functional entity corresponds to multiple interrupt events, and each functional entity also corresponds to an interrupt address table. This interrupt address table is used to store partial interrupt data for each of the multiple interrupt events. This partial interrupt data includes interrupt address, token ID, destination ID (Dst ID), valid ID, etc.

[0054] (8) Peripheral Component Interconnect Express (PCIe): This is a high-speed serial point-to-point dual-channel high-bandwidth transmission protocol. Devices connected via this protocol are allocated dedicated channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot-plugging, and Quality of Service (QoS) functions. PCIe devices are directly connected to the PCIe bus, bringing cache and data closer to the CPU, which can effectively reduce latency compared to traditional storage protocols.

[0055] (9) Network node: refers to a host or node device in a computer device. In this application, the computer device may be a mobile phone, computer, tablet, vehicle-mounted system, server, or wearable device, etc.

[0056] Please see Figure 1 , Figure 1 This is a schematic diagram of the architecture of a distributed system provided in an embodiment of this application. All or part of the computer devices in this architecture can be used to execute the interrupt reporting method and the interrupt configuration method in this application.

[0057] like Figure 1 As shown, this distributed system contains f computer devices (computer device 1...computer device f), where f is a positive integer greater than or equal to 2. These f computer devices communicate through network 110.

[0058] The system architecture of each of the f computer devices can be found in [reference]. Figure 2 .

[0059] like Figure 2 As shown, the system architecture of a computer device includes a host, multiple node devices (node ​​device 1...node device d), and a bus (also known as a Universal Bus (UB) system) connecting the host and the node devices, where d is a positive integer.

[0060] The host includes multiple processor cores, i.e., CPU-1…CPU-n, where n is a positive integer. Additionally, the host may contain memory. Figure 1 (Not shown).

[0061] like Figure 2 As shown, each node device contains an interrupt vector table and an interrupt address table. The interrupt vector table stores the interrupt vector corresponding to each interrupt event, and the interrupt address table stores the interrupt address corresponding to each interrupt event.

[0062] The following is combined Figure 1 and Figure 2 This application describes the interrupt mechanism implemented in this application, including two parts: interrupt data configuration and interrupt reporting.

[0063] (a) Configuration of interrupt data First, the host on the computer device generates interrupt data for the interrupt event, including the interrupt vector, interrupt address, mask state, Dst ID, Token ID, and Valid ID. Then, the driver on the host sends this interrupt data as configuration messages to the corresponding node devices via the bus system. The node devices then configure the received interrupt data into their onboard memory.

[0064] Each node device maintains two types of logical tables: an interrupt address table and an interrupt vector table. These two tables are used to store interrupt data for interrupt events. The interrupt address table stores interrupt address, Dst ID, Token ID, and Valid ID, among other data, from the interrupt data; the interrupt vector table stores interrupt vector, Mask status, and other data from the interrupt data. In addition, the interrupt vector table also stores address indexes pointing to interrupt addresses.

[0065] The configuration process for the aforementioned interrupt data is completed by the Host on each computer device instructing its node devices to perform the configuration.

[0066] (ii) Reporting of Interruptions When an interrupt event is generated on a node device, the node device first retrieves the interrupt vector, address index, mask status, and other data corresponding to the interrupt event from the interrupt vector table, and then retrieves the interrupt address, Dst ID, Token ID, and Valid ID, and other data corresponding to the interrupt event from the interrupt address table based on the address index.

[0067] Then, the interrupt vector, mask status, interrupt address, Dst ID, Token ID, and Valid ID are sent as an interrupt message to the network node (including the node device and host) indicated by the Dst ID, thus completing the reporting of the interrupt event.

[0068] The network node to which the interrupt message is sent can be a local network node or a network node on another computer device connected to the local computer device via a network. When the interrupt message is sent to a local network node, the method in this embodiment can be applied to a single computer device; when the interrupt message is sent to a network node on another computer device, the method in this embodiment can be applied to a distributed system.

[0069] Please see Figure 3 , Figure 3 A system architecture diagram of another computer device provided in this application embodiment, used for... Figure 2 The system architecture of the computer equipment is further refined, specifically, each node device can support multiple functional entities.

[0070] like Figure 3 As shown, the computer device contains d node devices, where d is a positive integer. Each node device contains at least one functional entity. For example, node device 1 contains m functional entities and storage unit 1; node device d contains a functional entities and storage unit d. Here, m and a are positive integers.

[0071] Each functional entity corresponds to multiple interrupt events, and each functional entity also corresponds to an interrupt vector table and an interrupt address table. The interrupt vector table and interrupt address table are used to store part or all of the interrupt data for each of the multiple interrupt events. The interrupt address table and interrupt vector table corresponding to each functional entity are located in the storage unit of its node device.

[0072] The interrupt vector table and interrupt address table described in this application are the interrupt vector table and interrupt address table corresponding to any functional entity on the node device.

[0073] It should be understood that Figure 2 and Figure 3This application merely provides an example of the system architecture of the computer device and does not constitute a limitation on the number of modules or the connection method, etc. For example, Figure 3 Displaying only one storage unit on each node device does not constitute a limitation on the number of storage units on it.

[0074] Optionally, Figures 1-3 The computer device mentioned can be a mobile phone, computer, tablet, vehicle system, server or wearable device, etc., and this application does not limit it.

[0075] Optionally, Figure 2 and Figure 3 The processor on the host can be a single-core, multi-core, or heterogeneous processor, etc., and this application does not limit it.

[0076] Optionally, Figure 2 and Figure 3 The node devices can be graphics cards, network cards, sound cards, hard disk drives, solid-state drives, keyboards, or mice, etc.

[0077] Optionally, Figure 2 and Figure 3 The storage units on the node device can be registers, register sets, or other readable and writable memories.

[0078] Please see Figure 4 , Figure 4 A flowchart illustrating an interrupt configuration method provided in this application embodiment can be applied to... Figures 1-3 In the system architecture shown, the method includes steps S410 and S420.

[0079] Step S410: The Host generates a configuration message for an interrupt event; wherein the configuration message includes an interrupt vector and an interrupt address, the interrupt vector is configured in the interrupt vector table on the node device, the interrupt address is configured in the interrupt address table on the node device, and the node device communicates with the Host through the bus system.

[0080] Specifically, for each interrupt event, the host generates interrupt data for that event and then encapsulates the interrupt data into a configuration message. The configuration message corresponding to each interrupt event contains data such as the interrupt vector and interrupt address.

[0081] The following describes the distribution of interrupt data and a feasible configuration process, taking any two interrupt events (first interrupt event and second interrupt event) corresponding to any functional entity (hereinafter referred to as the first functional entity) as objects: The first functional entity corresponds to a first interrupt address table and a first interrupt vector table on the node device. The first interrupt address table and the first interrupt vector table are used to store some or all of the interrupt data of multiple interrupt events corresponding to the first functional entity.

[0082] First, the node device receives the first configuration message for the first interrupt event sent by the host. The first configuration message contains the first interrupt vector and the first interrupt address, and the first interrupt address is different from the interrupt address already existing in the first interrupt address table.

[0083] Since the first interrupt address does not exist in the first interrupt address table, the first interrupt address is stored in an initialized entry (Entry) in the first interrupt address table. Then, a first address index pointing to this Entry is generated, and this first address index and the corresponding first interrupt vector are stored in an initialized entry (Entry) in the first interrupt vector table.

[0084] Then, the node device receives a second configuration message for the second interrupt event sent by the host. The second configuration message contains a second interrupt vector and a second interrupt address, and the second interrupt address is the same as the first interrupt address.

[0085] Since the second interrupt address is the same as the first interrupt address, there is no need to store the interrupt address again in the first interrupt address table. Instead, the first address index and the second interrupt vector are stored directly in an entry Enrty in the first interrupt vector table. If the first interrupt vector table already contains an Entry that includes the first address index and the second interrupt vector, there is no need to store it again.

[0086] Optionally, the node device stores the starting storage address, interrupt vector table offset, and interrupt address table offset corresponding to the first functional entity.

[0087] The starting memory address indicates the starting memory address of the interrupt data for multiple interrupt events corresponding to the first functional entity. The interrupt vector table offset is the offset of the starting memory address of the interrupt vector table relative to the starting memory address of the first functional entity. The interrupt address table offset is the offset of the starting memory address of the interrupt address table relative to the starting memory address of the first functional entity.

[0088] In the above process of configuring interrupt data, each interrupt data is configured into the interrupt address table and the interrupt vector table based on the starting storage address, interrupt vector table offset and interrupt address table offset of the first functional entity.

[0089] Please see Figure 5 , Figure 5 This is a schematic diagram of a data organization format on a node device provided in an embodiment of this application, serving as an example of a data storage method.

[0090] like Figure 5 As shown, the node device contains m functional entities, and each functional entity corresponds to an interrupt address table and an interrupt vector table in the first storage unit.

[0091] The first storage unit stores the interrupt data for each interrupt event. The interrupt data for each of the multiple interrupt events corresponding to each functional entity is stored in the interrupt vector table and interrupt address table corresponding to that functional entity. The first storage unit can be the MMIO Space on the node device.

[0092] The second storage unit is used to store data such as interrupt vector table offset, interrupt address table offset, number of interrupts, and enable status (Enable).

[0093] The Enable state indicates whether the interrupt data stored in the first memory cell is used.

[0094] The second storage unit can be referred to as the Configuration Space.

[0095] The following details the data organization / logical structure of the interrupt vector table and interrupt address table after configuring the interrupt data for the interrupt event using the above method: (1) Interrupt vector table (each entry in the interrupt vector table is called the first entry) The interrupt vector table contains multiple first entries, each containing an interrupt vector and corresponding to an interrupt event.

[0096] Each first entry (Entry) corresponds to an interrupt event, and the partial interrupt data of each interrupt event is stored in a first entry (Entry).

[0097] (2) Interrupt address table (each entry in the interrupt address table is called the second entry) The interrupt address table contains at least one second entry, each second entry contains an interrupt address, and at least one second entry corresponds to multiple interrupt events.

[0098] If a second entry Entry corresponds to multiple interrupt events, then a portion of the interrupt data for each of the multiple interrupt events is stored in that second entry Entry.

[0099] (3) The correspondence between the interrupt vector table and the interrupt address table Multiple first entries contain M first entries, which correspond to M interrupt events. These M interrupt events correspond to the same second entry in at least one second entry, where M is a positive integer greater than or equal to 2.

[0100] That is, in the interrupt vector table, there exists at least one first entry Entry, and at least one interrupt event corresponding to it corresponds to the same second entry Entry in the interrupt address table.

[0101] As can be seen, by configuring interrupt data in the above manner (i.e., storing interrupt addresses and interrupt vectors in different tables), for different interrupt events, if the interrupt addresses in their interrupt data are the same, they can be merged and stored in the interrupt address table, i.e., stored only once. This method effectively saves the storage space required for interrupt data of interrupt events, thus supporting the configuration of more interrupts on the node device under the condition of limited storage space on the node device, thereby effectively improving service performance.

[0102] Optionally, the interrupt vector table also contains an address index corresponding to the interrupt vector, which points to the interrupt address in the interrupt address table.

[0103] Specifically, the interrupt vector of each interrupt event corresponds to an address index in the interrupt vector table, and the interrupt vector and the address index are stored in the same first entry, Entry.

[0104] Optionally, the configuration message may also include a Destination ID, which is configured in the interruption address table and is used to indicate the network node to which the interruption message containing the Destination ID is sent.

[0105] Specifically, the Host generates a target ID (Dst ID) for the interrupt event and encapsulates it into the configuration message for the interrupt event. After receiving the configuration message, the node device stores the Dst ID and the interrupt address in the same Entry in the interrupt address table; that is, each second entry in the table also contains a Dst ID.

[0106] During the subsequent interrupt reporting process by a node device, the Dst ID is encapsulated in the interrupt message generated by the node device and sent to the network node via the bus system. The Dst ID is used to indicate the network node from which the interrupt message was sent.

[0107] Optionally, the configuration message may also include a token ID, which is configured in the interrupt address table and is used by the Host to perform security verification on the interrupt address.

[0108] Specifically, the host generates a Token ID for the interrupt event and then encapsulates it into the interrupt event's configuration message. After receiving the configuration message, the node device stores the Token ID and the interrupt address in the same Entry in the interrupt address table; that is, each second entry in the table also contains a Token ID.

[0109] During the subsequent interrupt reporting process by a node device, the Token ID is encapsulated in the interrupt message generated by the node device and sent to the network node via the bus system. After receiving the interrupt message, the network node uses the Token ID to perform security verification and address translation on the interrupt address to ensure data security.

[0110] Please see Figure 6 , Figure 6 The present application provides a schematic diagram of the logical structure of an interrupt vector table and an interrupt address table, which constitutes an example of an interrupt address table, an interrupt address table and the relationship between them.

[0111] like Figure 6 As shown, the interrupt vector table contains k entries (i.e., at least one first entry in the aforementioned embodiment), and each of these k entries corresponds to an interrupt event. The data in each of these k entries includes an address index, interrupt vector, mask status, etc. k is a positive integer. The mask status (Mask) functions the same as the Mask in existing interrupt mechanisms, and will not be elaborated upon in this application.

[0112] The interrupt address table contains h entries (i.e., at least one second entry in the aforementioned embodiments). Among these h entries, at least one entry corresponds to multiple interrupt events. The data in each of the h entries includes the interrupt address, target number, token, validity, etc. h is a positive integer less than or equal to k. The validity ID (ValidID) functions the same as the ValidID in existing interrupt mechanisms, and will not be elaborated upon here.

[0113] exist Figure 6In the example shown, the interrupt data for interrupt event 1 is configured in Entry-1 of the interrupt vector table and Entry-1 of the interrupt address table. The interrupt data for interrupt event 2 is configured in Entry-2 of the interrupt vector table and Entry-1 of the interrupt address table. The interrupt data for interrupt event e is configured in Entry-k of the interrupt vector table and Entry-h of the interrupt address table.

[0114] That is, Entry-1 in the interrupt vector table corresponds to interrupt event 1, Entry-2 in the interrupt vector table corresponds to interrupt event 2, and Entry-k in the interrupt vector table corresponds to interrupt event e. Entry-1 in the interrupt address table corresponds to interrupt events 1 and 2, and Entry-h in the interrupt address table corresponds to interrupt event e.

[0115] Step S420: The Host sends the configuration message to the node device through the bus system.

[0116] Specifically, after the Host generates the configuration message for the interrupt event, it sends it to the corresponding node device through the bus system.

[0117] After configuring interrupt data of an interrupt event to the node device as described in the foregoing embodiments, the following embodiments mainly describe the process of the node device generating an interrupt message based on the configured interrupt data and reporting the interrupt.

[0118] Please see Figure 7 , Figure 7 A flowchart illustrating a method for reporting interruptions provided in this application. This method is applied to the aforementioned... Figures 2-3 On the node devices in the process. As can be seen from the interrupt data configuration process in the foregoing embodiments, each node device maintains an interrupt vector table and an interrupt address table. The method includes steps S710, S720, and S730.

[0119] Step S710: Obtain the interrupt event.

[0120] Specifically, during operation, a node device may generate an interrupt event. At this time, the interrupt event needs to be reported to the corresponding network node so that the network node can suspend the currently executing program and start executing an interrupt service routine corresponding to the interrupt event.

[0121] For example, a node device can be a hard drive. When the hard drive finishes storing a piece of data, it will generate an interrupt event and report this interrupt event to the host so that the host can know the progress of data storage on the hard drive and execute the corresponding interrupt service routine.

[0122] Step S720: Generate an interrupt message for the interrupt event; wherein the interrupt message contains an interrupt vector and an interrupt address, the interrupt vector being obtained from the interrupt vector table and the interrupt address being obtained from the interrupt address table.

[0123] Specifically, after an interrupt event occurs on a node device, the node device generates an interrupt message for the interrupt event. Since the interrupt data for the interrupt event that needs to be reported has already been configured in the interrupt vector table and interrupt address table on the node device, the corresponding data can be retrieved from the interrupt vector table and interrupt address table to generate the interrupt message for the interrupt event.

[0124] Based on the aforementioned example of the interrupt data configuration process, the data organization / logical structure of the interrupt vector table and the interrupt address table is as follows: The interrupt vector table contains multiple first entries, each containing an interrupt vector and corresponding to an interrupt event. The interrupt address table contains at least one second entry, each containing an interrupt address.

[0125] Among them, there are M first entries in the first table entry, M first entries correspond to M interrupt events, and M interrupt events correspond to the same second entry in at least one second entry, where M is a positive integer greater than or equal to 2.

[0126] Optionally, the interrupt vector table contains an address index corresponding to the interrupt vector, and the interrupt vector and the address index are stored in the same first entry, Entry, on the interrupt vector table.

[0127] Optionally, each second entry Entry also contains a target number, Dst ID.

[0128] Optionally, each second entry also contains a token ID.

[0129] After an interrupt event occurs, the node device retrieves the interrupt vector from the first entry (Entry) in the interrupt vector table, and then looks up the second entry (Entry) in the interrupt address table based on the address index contained in the first entry (Entry) to retrieve the interrupt address. The interrupt vector and interrupt address are then encapsulated to generate an interrupt message for the interrupt event, which is sent to the corresponding network node.

[0130] Optionally, the node device may also obtain the Dst ID from the second entry (Entry) where the interrupt address is located, and encapsulate the Dst ID into the interrupt message.

[0131] Dst ID is used to indicate the network node from which the interruption message was sent.

[0132] Optionally, the node device may also obtain the Token ID from the second entry (Entry) where the interrupt address is located, and encapsulate the Token ID into the interrupt message as well.

[0133] The Token ID is used by the network node receiving the interruption message to perform security verification and address translation on the interruption address contained in the interruption message.

[0134] Step S730: Send the interrupt message to the network node through the bus system.

[0135] After generating an interrupt message for an interrupt event, the node device sends the interrupt message to the network node indicated by the Dst ID. This network node can be a network node on the local computer device or a network node on another computer device that communicates with the local computer device over the network.

[0136] Network nodes include node devices on computer equipment and hosts.

[0137] Please see Figure 8 , Figure 8 This is a schematic diagram of a device for reporting interrupts, provided in an embodiment of this application. The device stores an interrupt vector table and an interrupt address table. Figure 8 As shown, the device includes an acquisition unit 810, a processing unit 820, and a transceiver unit 830. Among them, An acquisition unit 810 is used to acquire an interrupt event. A processing unit 820 is used to generate an interrupt message for the interrupt event. The interrupt message includes an interrupt vector and an interrupt address; the interrupt vector is obtained from the interrupt vector table, and the interrupt address is obtained from the interrupt address table. A transceiver unit 830 is used to send the interrupt message to a network node via the bus system.

[0138] In one feasible implementation, the interrupt vector table contains a plurality of first entries, each first entry containing an interrupt vector and each first entry corresponding to an interrupt event; the interrupt address table contains at least one second entry, each second entry containing an interrupt address; wherein, the plurality of first entries contains M first entries, the M first entries corresponding to M interrupt events, and the M interrupt events corresponding to the same second entry in the at least one second entry, where M is a positive integer greater than or equal to 2.

[0139] In one feasible implementation, the interrupt vector table contains an address index corresponding to the interrupt vector, and the interrupt address is obtained from the interrupt address table based on the address index.

[0140] In one feasible implementation, each of the second Entries further includes a Destination ID, which indicates the network node to which an interruption message containing the Destination ID is sent; the interruption message also includes the Destination ID.

[0141] In one feasible implementation, each of the second Entries further includes a Token ID, which is used by the network node to perform security verification on the interruption address; the interruption message also includes the Token ID.

[0142] Specifically, the specific execution process of this device can be found in the execution flow corresponding to the method embodiment in the foregoing embodiments, and will not be repeated here.

[0143] Please see Figure 9 , Figure 9 This is a schematic diagram of an interrupt configuration device provided in an embodiment of this application. Figure 9 As shown, the device includes a processing unit 910 and a transceiver unit 920. Among them, Processing unit 910 is used to generate a configuration message for an interrupt event. The configuration message includes an interrupt vector and an interrupt address. The interrupt vector is configured in an interrupt vector table on the node device, and the interrupt address is configured in an interrupt address table on the node device. The node device communicates with the device through the bus system. Transceiver unit 920 is used to send the configuration message to the node device through the bus system.

[0144] In one feasible implementation, the interrupt vector table contains a plurality of first entries, each first entry containing an interrupt vector and each first entry corresponding to an interrupt event; the interrupt address table contains at least one second entry, each second entry containing an interrupt address; wherein, the plurality of first entries contains M first entries, the M first entries corresponding to M interrupt events, and the M interrupt events corresponding to the same second entry in the at least one second entry, where M is a positive integer greater than or equal to 2.

[0145] In one feasible implementation, the interrupt vector table further includes an address index corresponding to the interrupt vector, the address index pointing to the interrupt address in the interrupt address table.

[0146] In one feasible implementation, the configuration message further includes a Destination ID, which is configured in the interruption address table and is used to indicate the network node to which the interruption message containing the Destination ID is sent; each of the second Entries also includes one of the Destination IDs.

[0147] In one feasible implementation, the configuration message further includes a token ID, which is configured in the interrupt address table and is used by the Host to perform security verification on the interrupt address; each second Entry also includes one of the token IDs.

[0148] Specifically, the specific execution process of this device can be found in the execution flow corresponding to the method embodiment in the foregoing embodiments, and will not be repeated here.

[0149] Please see Figure 10 , Figure 10 This schematic diagram of a network node's hardware structure, provided in an embodiment of this application, can serve as a reference for the aforementioned... Figure 9 One possible specific implementation of the network device (i.e., the host in the aforementioned method embodiments). The network node includes a processor 1001, a memory 1002, and an interface circuit 1003. The memory 1002, the interface circuit 1003, and the processor 1001 are interconnected via a line 1004. Processor 1001 is used to generate a configuration message for an interrupt event. The configuration message includes an interrupt vector and an interrupt address. The interrupt vector is configured in an interrupt vector table on the node device, and the interrupt address is configured in an interrupt address table on the node device. The node device communicates with the device through the bus system. Interface circuit 1003 is used to send the configuration message to the node device through the bus system.

[0150] Specifically, the execution process of the aforementioned network nodes can be found in the preceding text. Figure 4 The execution flow in the method embodiment will not be described again here.

[0151] Please see Figure 11 , Figure 11 The hardware structure diagram of another network node provided in the embodiments of this application can be used as the foregoing Figure 8 One possible specific implementation of the network node (i.e., the node device in the aforementioned method embodiments). The network node includes a processing circuit 1101, a memory 1102, and an interface circuit 1103. The memory 1102, the interface circuit 1103, and the processing circuit 1101 are interconnected via a line 1104. Memory 1102 stores an interrupt vector table and an interrupt address table; processing circuit 1101 acquires an interrupt event and generates an interrupt message for the interrupt event. The interrupt message contains an interrupt vector and an interrupt address; the interrupt vector is obtained from the interrupt vector table, and the interrupt address is obtained from the interrupt address table. Interface circuit 1103 sends the interrupt message to a network node via a bus system.

[0152] Specifically, the execution process of the aforementioned network nodes can be found in the preceding text. Figure 7 The execution flow in the method embodiment will not be described again here.

[0153] This application provides a chip system including at least one processor, a memory, and an interface circuit. The memory, the interface circuit, and the at least one processor are interconnected via circuits. The at least one memory stores instructions; when the instructions are executed by the processor... Figure 4 Any part or all of the steps described in the method embodiments can be implemented.

[0154] This application provides a chip system including a processing circuit, a memory, and an interface circuit. The memory, the interface circuit, and the processing circuit are interconnected via circuits. At least one memory stores instructions; when the instructions are executed by the processing circuit... Figure 7Any part or all of the steps described in the method embodiments can be implemented.

[0155] This application provides a server, the server including... Figure 10 and Figure 11 The network nodes described in the examples.

[0156] This application provides a server, the server including components for implementing... Figure 4 and Figure 7 Chip system of a method embodiment.

[0157] This application provides a computer device that includes at least one of the aforementioned components. Figure 10 The network node and at least one of the aforementioned Figure 11 Network nodes in the network.

[0158] This application provides a distributed system comprising at least two computer devices described in the foregoing embodiments.

[0159] This application provides a computer storage medium storing a computer program that, when executed, enables the implementation of some or all of the steps described in the above method embodiments.

[0160] This application provides a computer program product, which includes instructions that, when executed by a processor, enable the implementation of some or all of the steps described in the above method embodiments.

[0161] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a particular embodiment can be found in the relevant descriptions of other embodiments. It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0162] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0163] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0164] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for reporting interruptions, characterized in that, An application to a node device communicating via a bus system, the node device including an interrupt vector table and an interrupt address table, wherein the interrupt vector table contains interrupt vectors and the interrupt address table contains interrupt addresses; the method includes: Acquire interrupt events; An interrupt message for the interrupt event is generated; wherein the interrupt message contains an interrupt vector and an interrupt address and is sent to the network node through the bus system.

2. The method according to claim 1, characterized in that, The interrupt vector table contains a plurality of first entries, each first entry contains an interrupt vector, and each first entry corresponds to an interrupt event. The interrupt address table contains at least one second entry, and each second entry contains one interrupt address. Among them, the plurality of first Entries includes M first Entries, the M first Entries correspond to M interrupt events, and the M interrupt events correspond to the same second Entry in the at least one second Entry, where M is a positive integer greater than or equal to 2.

3. The method according to claim 1, characterized in that, The interrupt vector table contains an address index corresponding to the interrupt vector, and the interrupt address is obtained from the interrupt address table based on the address index.

4. The method according to claim 2 or 3, characterized in that, Each of the second Entries also contains a Destination ID, which indicates the network node from which the interruption message containing the Destination ID was sent; The interruption message also includes the Destination ID.

5. The method according to any one of claims 2 or 3, characterized in that, Each second Entry also contains a Token ID, which is used by the network node to perform security verification on the interrupted address; The interruption message also includes the Token ID.

6. The method according to any one of claims 1-3, characterized in that, The node device includes one or more of the following: graphics card, hard drive, network card, and sound card.

7. A method for configuring an interrupt, characterized in that, A method applied to node devices that communicate via a bus system, the node devices communicating with a host via the bus system; the method includes: Receive a configuration message for an interrupt event sent by the Host from the bus system; wherein the configuration message includes an interrupt vector and an interrupt address; The interrupt vector is stored in the interrupt vector table on the node device; The interrupt address is stored in the interrupt address table on the node device.

8. The method according to claim 7, characterized in that, The interrupt vector table contains a plurality of first entries, each first entry contains an interrupt vector, and each first entry corresponds to an interrupt event; The interrupt address table contains at least one second entry, and each second entry contains one interrupt address. Among them, the plurality of first Entries includes M first Entries, the M first Entries correspond to M interrupt events, and the M interrupt events correspond to the same second Entry in the at least one second Entry, where M is a positive integer greater than or equal to 2.

9. The method according to claim 7, characterized in that, The interrupt vector table also contains an address index corresponding to the interrupt vector, and the address index points to the interrupt address in the interrupt address table.

10. The method according to claim 8 or 9, characterized in that, The configuration message also includes a Destination ID, which is configured in the interruption address table and is used to indicate the network node to which the interruption message containing the Destination ID is sent. Each of the second Entries also contains one of the Destination IDs.

11. The method according to any one of claims 8 or 9, characterized in that, The configuration message also includes a token ID, which is configured in the interrupt address table and is used by the Host to perform security verification on the interrupt address. Each of the second Entries also contains one of the Token IDs.

12. The method according to any one of claims 7-9, characterized in that, The node device includes one or more of the following: graphics card, hard drive, network card, and sound card.

13. A device for reporting interruptions, characterized in that, The device communicates via a bus system. The device stores an interrupt vector table and an interrupt address table, wherein the interrupt vector table contains interrupt vectors and the interrupt address table contains interrupt addresses. The device includes: The acquisition unit is used to acquire interrupt events; A processing unit is configured to generate an interrupt message for the interrupt event; wherein the interrupt message includes an interrupt vector and an interrupt address; The transceiver unit is used to send the interrupt message to the network node through the bus system.

14. The apparatus according to claim 13, characterized in that, The interrupt vector table contains a plurality of first entries, each first entry contains an interrupt vector, and each first entry corresponds to an interrupt event; The interrupt address table contains at least one second entry, and each second entry contains one interrupt address. Among them, the plurality of first Entries includes M first Entries, the M first Entries correspond to M interrupt events, and the M interrupt events correspond to the same second Entry in the at least one second Entry, where M is a positive integer greater than or equal to 2.

15. The apparatus according to claim 13, characterized in that, The interrupt vector table contains an address index corresponding to the interrupt vector, and the interrupt address is obtained from the interrupt address table based on the address index.

16. The apparatus according to claim 14 or 15, characterized in that, Each of the second Entries also contains a Destination ID, which indicates the network node from which the interruption message containing the Destination ID was sent; The interruption message also includes the Destination ID.

17. The apparatus according to any one of claims 14 or 15, characterized in that, Each second Entry also contains a token ID, which is used by the network node to perform security verification on the interrupted address; The interruption message also includes the Token ID.

18. An interrupt configuration device, characterized in that, The device communicates via a bus system, and communicates with the host via the bus system; the device includes: A transceiver unit is configured to receive a configuration message for an interrupt event sent by the Host from the bus system; wherein the configuration message includes an interrupt vector and an interrupt address; The processing unit is configured to store the interrupt vector in an interrupt vector table on the device and to store the interrupt address in an interrupt address table on the device.

19. The apparatus according to claim 18, characterized in that, The interrupt vector table contains a plurality of first entries, each first entry contains an interrupt vector, and each first entry corresponds to an interrupt event; The interrupt address table contains at least one second entry, and each second entry contains one interrupt address. Among them, the plurality of first Entries includes M first Entries, the M first Entries correspond to M interrupt events, and the M interrupt events correspond to the same second Entry in the at least one second Entry, where M is a positive integer greater than or equal to 2.

20. The apparatus according to claim 18, characterized in that, The interrupt vector table also contains an address index corresponding to the interrupt vector, and the address index points to the interrupt address in the interrupt address table.

21. The apparatus according to claim 19 or 20, characterized in that, The configuration message also includes a Destination ID, which is configured in the interruption address table and is used to indicate the network node to which the interruption message containing the Destination ID is sent. Each of the second Entries also contains one of the Destination IDs.

22. The apparatus according to any one of claims 19 or 20, characterized in that, The configuration message also includes a token ID, which is configured in the interrupt address table and is used by the Host to perform security verification on the interrupt address. Each of the second Entries also contains one of the Token IDs.

23. A network node, characterized in that, The network node includes at least one processor, a memory, and an interface circuit. The memory, the interface circuit, and the at least one processor are interconnected via a line. The memory stores instructions, and when the instructions are executed by the processor, the method described in any one of claims 7-12 is implemented.

24. A network node, characterized in that, The network node includes a processing circuit, a memory, and an interface circuit. The memory, the interface circuit, and the processing circuit are interconnected by a line. The memory stores instructions, and when the instructions are executed by the processing circuit, the method described in any one of claims 1-6 is implemented.

25. A chip system, characterized in that, The chip system includes at least one processor, a memory, and an interface circuit. The memory, the interface circuit, and the at least one processor are interconnected via lines. The at least one memory stores instructions. When the instructions are executed by the at least one processor, the method described in any one of claims 7-12 is implemented.

26. A chip system, characterized in that, The chip system includes a processing circuit, a memory, and an interface circuit. The memory, the interface circuit, and the processing circuit are interconnected by lines. The at least one memory stores instructions. When the instructions are executed by the processing circuit, the method described in any one of claims 1-6 is implemented.

27. A server, characterized in that, The server includes the network node described in claims 23 and 24.

28. A server, characterized in that, The server includes the chip system described in claims 25 and 26.

29. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed, enables the implementation of the method according to any one of claims 1-6 or 7-12.

30. A computer program product, characterized in that, The computer program includes instructions that, when executed, implement the method according to any one of claims 1-6 or 7-12.

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