Topological subarray identification method and apparatus

Abstract

This application relates to the field of power technology, and in particular to a method and apparatus for identifying topology subarrays. The method includes: determining a first port of a device to be tested in a power plant; injecting a first disturbance signal into the first port; detecting a second disturbance signal in ports of other devices besides the device to be tested; and, when the second disturbance signal matches the first disturbance signal, determining that the target port containing the second disturbance signal matching the first disturbance signal is in the same subarray as the first port. This method can automatically identify and correct topology information, effectively improving system stability and power quality, and can also reduce operation and maintenance costs and system downtime.

Description

Technical Field

[0001] This application relates to the field of power technology, and in particular to a method and apparatus for identifying topological subarrays. Background Technology

[0002] In off-grid mode, inverters need to establish stable voltage and frequency references to provide reliable power supply to the load. Therefore, off-grid inverters are core equipment in independent power supply systems, and their normal operation usually depends on the accurate identification of the load subarray topology. At the same time, grid-connected inverters, when operating in scenarios with multiple grid connection points, also need to accurately identify the grid connection point subarray topology to achieve reasonable power distribution and stable system operation.

[0003] For scenarios with complex load / grid connection subarrays, customers typically need to manually configure the topology information. However, manual configuration is prone to errors, and the system cannot automatically identify and correct them, which can easily lead to power dispatching errors, affecting system stability and power quality. Furthermore, due to inaccurate topology information, troubleshooting system faults becomes extremely difficult, increasing operation and maintenance costs and system downtime. Summary of the Invention

[0004] In view of this, embodiments of this application provide a method and apparatus for identifying topology subarrays to solve the problem that in the prior art, topology subarray identification cannot achieve automatic identification and correction, which easily affects system stability and power quality, and increases operation and maintenance costs and system downtime.

[0005] A first aspect of this application provides a method for identifying a topological subarray, the method comprising: Determine the first port of the device to be tested in the power plant; Inject a first disturbance signal into the first port; Detect the second disturbance signal in the ports of devices other than the device under test; When the second disturbance signal matches the first disturbance signal, it is determined that the target port where the second disturbance signal that matches the first disturbance signal is located is in the same subarray as the first port.

[0006] In conjunction with the first aspect, in a first possible implementation of the first aspect, the first port is an active port or a passive port; the first disturbance signal is a first disturbance current or a first disturbance voltage; Injecting a first disturbance signal into the first port includes: A first disturbance signal is injected into the first port through the device under test or the disturbance signal injection device.

[0007] In conjunction with the first possible implementation of the first aspect, in the second possible implementation of the first aspect, the first port is a passive port, and the first disturbance signal is a first disturbance voltage; Injecting a first disturbance signal into the first port through the device under test or the disturbance signal injection device includes: The first disturbance voltage is generated by controlling the device under test, and then injected into the first port; or... By controlling the device under test, the output voltage of the power supply connected to the device under test is injected into the first port as the first disturbance voltage; or... The first disturbance voltage is generated by the disturbance signal injection device and injected into the first port.

[0008] In conjunction with the second possible implementation of the first aspect, in the third possible implementation of the first aspect, the power source is the power grid, the internal common connection point of the device under test is connected to the first port via a first switch, the internal common connection point of the device under test is also connected to the power grid port via a second switch, the first port is connected to the load, and the power grid port is connected to the grid connection point. By controlling the device under test, the output voltage of the power supply connected to the device under test is injected into the first port as the first disturbance voltage, including: The first switch and the second switch are controlled to close so that the voltage of the power grid connected to the device under test is injected into the first port through the grid connection point and the power grid port.

[0009] In conjunction with the first possible implementation of the first aspect, in the fourth possible implementation of the first aspect, the first port is an active port, the first port is controllably connected to the power supply, and the first disturbance signal is a first disturbance voltage. Injecting a first disturbance signal into the first port through the device under test or the disturbance signal injection device includes: Disconnect the device under test from the power supply; control the device under test to output the first disturbance voltage and inject the first disturbance voltage into the first port, or... A first disturbance voltage is generated by a disturbance signal injection device and injected into the first port.

[0010] In conjunction with the first possible implementation of the first aspect, in the fifth possible implementation of the first aspect, the first port is an active port, and the first disturbance signal is a first disturbance current; Injecting a first disturbance signal into the first port through the device under test or the disturbance signal injection device includes: Control the device under test to output the first disturbance current, and inject the first disturbance current into the first port; or... The first disturbance current is generated by a disturbance signal injection device and injected into the first port; wherein the current characteristics of the first disturbance current are different from the current characteristics of the output current of the power supply connected to the device under test through the first port.

[0011] In conjunction with the first aspect, in a sixth possible implementation of the first aspect, detecting the second disturbance signal in a port of a device other than the device under test includes: Determine whether the type of the first port is an active port or a passive port; When the first port is an active port, the second disturbance signal is detected in the active ports of other devices besides the device under test; When the first port is a passive port, the second disturbance signal is detected in the passive ports of other devices besides the device under test.

[0012] In conjunction with the first aspect, in the seventh possible implementation of the first aspect, in the power station where the device to be tested is located, different devices are connected through multi-phase lines, the first port is a phase line port of the multi-phase line, and the following is performed for each phase of the multi-phase line: Determine the first port of the device to be tested; Inject a first disturbance signal into the first port; Detect the second disturbance signal in the ports of devices other than the device under test; When the second disturbance signal matches the first disturbance signal, the target port where the second disturbance signal that matches the first disturbance signal is located is determined to be connected to the same phase line as the first port.

[0013] In an eighth possible implementation of the first aspect, in conjunction with any one of the first to seventh possible implementations of the first aspect, after determining that the target port of the second disturbance signal matching the first disturbance signal is located in the same subarray as the first port, the method further includes: If there are still ports of equipment in the power station that have not been identified, select any port among the unidentified ports to update it as the first port, and jump to the step of injecting the first disturbance signal into the first port until all ports have been identified.

[0014] A second aspect of this application provides a topological subarray identification device, the device comprising: The first port determination unit is used to determine the first port of the device to be tested in the power plant. A signal injection unit is used to inject a first disturbance signal into the first port; A signal detection unit is used to detect a second disturbance signal in the ports of devices other than the device under test; The subarray identification unit is used to determine that when the second disturbance signal matches the first disturbance signal, the target port where the second disturbance signal that matches the first disturbance signal is located is in the same subarray as the first port.

[0015] A third aspect of this application provides a topology subarray identification system, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the topology subarray identification system implements the method described in any of the first aspects.

[0016] A fourth aspect of this application provides a computer program product that, when run on a computer, causes the computer to execute the methods described in the first aspect or its various implementations.

[0017] A fifth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method as described in any of the first aspects.

[0018] A sixth aspect of this application provides a chip for implementing the methods in the various implementations of the first aspect described above. Specifically, the chip includes a processor for calling and running a computer program from a memory, causing a device equipped with the chip to perform the methods as described in the first aspect or its various implementations.

[0019] The beneficial effects of this application embodiment compared with the prior art are as follows: This application embodiment determines the first port of the device to be tested in the power plant, injects a first disturbance signal into the first port, detects a second disturbance signal in the ports of other devices in the power plant besides the device to be tested, and compares the second disturbance signal with the first disturbance signal. When the two match, it can efficiently determine that the target port of the second disturbance signal that matches the first disturbance signal is in the same subarray as the first port. This method can automatically identify and correct the topology subarray information, effectively improve system stability and power quality, and reduce operation and maintenance costs and system downtime. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram illustrating multiple devices connecting multiple active ports according to an embodiment of this application; Figure 2 This is a schematic diagram illustrating multiple devices connecting multiple passive ports according to an embodiment of this application; Figure 3 This is a schematic diagram illustrating multiple devices connected to multiple active ports and multiple passive ports, as provided in an embodiment of this application. Figure 4 This is a schematic diagram illustrating the implementation process of a topological subarray identification method provided in an embodiment of this application; Figure 5 This is a schematic diagram illustrating the introduction of a first disturbance signal via power supply, as provided in an embodiment of this application. Figure 6 This is a schematic diagram of a first disturbance current injection active port provided in an embodiment of this application; Figure 7 This is a schematic diagram of a three-phase grid-connected dot matrix topology provided in an embodiment of this application; Figure 8 This is a schematic diagram of a topological subarray identification device provided in an embodiment of this application; Figure 9 This is a schematic diagram of a topological subarray identification system provided in an embodiment of this application. Detailed Implementation

[0022] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0023] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0024] In off-grid mode, the inverter needs to establish a stable voltage and frequency reference to ensure a continuous and reliable supply of power to the load. Therefore, the off-grid inverter is the core of an independent power supply system, and its stable operation depends on the accurate identification of the load subarray topology. Similarly, when a grid-connected inverter operates in a multi-grid-connection system, it also needs to accurately identify the subarray topology of the grid-connection points to achieve reasonable power distribution and stable system operation.

[0025] In application scenarios with complex load or grid connection subarray structures, current methods typically rely on manual configuration of topology information. This manual configuration approach is not only prone to errors, but the system often cannot automatically identify and correct them, easily leading to power dispatch anomalies and consequently affecting system stability and power quality. Furthermore, inaccurate topology subarray information makes troubleshooting difficult, resulting in increased maintenance costs and prolonged system downtime.

[0026] To address the aforementioned issues, this application proposes a topological subarray identification method. In the implementation scenario of this method, multiple devices are included, each device comprising one or more ports. The one or more ports included in each device can be all active ports, passive ports, or a combination of both. The multiple devices can be connected together using active ports, passive ports, or a combination of active and passive ports.

[0027] like Figure 1 The diagram shows a series of active ports connected together. The active ports (or grid ports) of devices 1, 2, and 3 are connected in parallel to the first grid connection point PCC1, while the active ports of devices 4 and 5 are connected in parallel to the second grid connection point PCC2. In this configuration, the active ports of devices 1, 2, and 3 connected to the first grid connection point are in the same subarray, and the active ports of devices 4 and 5 connected to the second grid connection point are in the same subarray.

[0028] like Figure 2 The diagram shows a series of passive ports connected together. Devices 1, 2, and 3 have their passive ports connected to the first load; device 4 has its passive port connected to the second load; and devices 5 and 6 have their passive ports connected to the third load. In this configuration, the passive ports of devices 1, 2, and 3 connected to the first load are located in the same subarray. The passive ports of devices 5 and 6 connected to the third load are located in the same subarray, while the passive port of device 4 is located in its own subarray.

[0029] like Figure 3The diagram illustrates a configuration where the active ports of some devices are connected together, and the passive ports of others are connected together. Specifically, the active ports of devices 1, 2, 4, and 5 are all connected to the first grid connection point PCC1; the active ports of devices 3 and 6 are all connected to the second grid connection point PCC2; and the passive ports of devices 2, 3, 4, and 5 are all connected to the first load. The passive port of device 1 is connected to the second load. The passive port of device 6 is connected to the third load. In this configuration, the active ports of devices 1, 2, 4, and 5 are located in the same subarray; the active ports of devices 3 and 6 are located in the same subarray; the passive ports of devices 5, 2, 3, and 4 are located in the same subarray; the passive port of device 1 is located in a separate subarray; and the passive port of device 6 is located in a separate subarray.

[0030] Figure 4 A schematic diagram illustrating the implementation process of a topological subarray identification method provided in this application is described in detail below: In S401, the first port of the device to be tested in the power plant is determined.

[0031] The devices in this application embodiment include the device to be detected and other devices besides the device to be detected. When identifying the subarray of topological connections, one device can be designated as the device to be detected each time, and the devices in the system other than the device to be detected are the other devices.

[0032] The device in this application embodiment can be an inverter or a gateway, etc. A single device may include one or more ports. These ports may include active ports or passive ports, or both active and passive ports. Active ports can be connected to a power source, and passive ports can be connected to a load. The power source can be an energy storage battery, a generator, an inverter, or the power grid, etc.

[0033] The ports of the devices in this application embodiment can be single-phase, split-phase, three-phase, or multi-phase. All ports of multiple devices can be connected to the same load or the same power supply, or a single phase port of multiple devices can be connected to the same load or the same power supply.

[0034] In a topology where multiple devices connect to multiple power supplies and / or multiple loads, ports of devices connected to the same power supply or the same load are said to be in the same subarray. To identify subarrays in the topology of multiple device ports, a port can be arbitrarily selected as the first port from a first port set where subarray affiliation is not explicitly defined. Based on the subarray identification method in this application embodiment, the subarray to which the first port belongs is determined, and the first port set is updated by deleting the first port and other ports belonging to the same subarray as the first port from the first port set, resulting in an updated first port set. Then, any port can be selected as the first port from the updated first port set for subarray identification.

[0035] In S402, a first disturbance signal is injected into the first port.

[0036] After determining the first port, the ports of other devices in the same subarray as the first port can be determined by introducing a first disturbance signal.

[0037] For devices with active ports (power ports) connected in parallel to the same power source, when a first disturbance signal is injected into the active port of one of the devices, the devices corresponding to other active ports connected in parallel with that active port can sense the disturbance, while the devices corresponding to other active ports not connected in parallel with that active port cannot sense the disturbance.

[0038] For devices with passive ports (load ports) connected in parallel to the same load, when a first disturbance signal is injected into the passive port of one of the devices, the devices corresponding to other passive ports connected in parallel with that passive port can sense the disturbance, while the devices corresponding to other passive ports not connected in parallel with that passive port cannot sense the disturbance.

[0039] Therefore, ports that can sense disturbances can be grouped into the same subarray, meaning devices that can sense disturbances can be grouped into the same subarray. In the embodiments of this application, devices located in the same subarray may have active ports connected in parallel or passive ports connected in parallel.

[0040] The disturbance signal in this embodiment can be a disturbance voltage or a disturbance current. The first disturbance signal can be a first disturbance voltage or a first disturbance current. The disturbance voltage can include voltages with specific characteristics such as power frequency voltage, harmonic voltage, square wave voltage, or triangular wave voltage. The disturbance current can include currents with specific characteristics such as power frequency current, harmonic current, square wave current, or triangular wave current.

[0041] In this embodiment of the application, a first disturbance signal can be injected into the first port by the device under test, or a first disturbance signal can be injected into the first port by a disturbance signal injection device.

[0042] When the first port is a passive port, when the device under test (DUT) injects a first disturbance signal into the first port, the DUT can be controlled to generate a first disturbance voltage and inject it into the first port. For example, the first disturbance voltage can be generated by a signal modulation module inside the DUT and injected into the first port, thus efficiently introducing the first disturbance voltage without the need for other devices. Alternatively, the output voltage of the power supply connected to the DUT can be used as the first disturbance voltage and injected into the first port. When the first disturbance signal is injected into the first port through a disturbance signal injection device, the first disturbance voltage can be generated by the disturbance signal injection device and injected into the first port. For example, the first disturbance voltage can be generated by a hardware circuit and injected into the first port.

[0043] like Figure 5 The diagram illustrates a method for introducing a first disturbance signal via power supply, as provided in an embodiment of this application. The device under test (DUT) is a grid-connected inverter, including active and passive ports. The active ports connected to the grid connection point include GridA, GridB, GridC, and GridN, while the passive ports connected to the load include LoadA, LoadB, LoadC, and LoadN. The first port to be tested by the DUT is the passive port connected to the load, which can be any one of LoadA, LoadB, LoadC, and LoadN. The internal common connection point of the DUT is connected via a first switch (S1). A S1 B S1 C S1 N The device under test is connected to the first port, which is connected to the load. The internal common connection point of the device under test is also connected to the second switch (S2). A S2 B S2 C S2 N The internal common connection point is connected to the grid port (active port), which in turn is connected to the grid connection point. At this time, the internal common connection point can be reached via the third switch (S3). A S3 B S3 C S3 N Connect to the device under test, i.e., the output terminal of the on-grid inverter.

[0044] When the first disturbance signal introduced is a first disturbance voltage, the first switch (S1) can be controlled. A S1 B S1 C S1 N ) and the second switch (S2) A S2B S2 C S2 N When the circuit is closed, the voltage of the power grid connected to the device under test is used as the first disturbance voltage and injected into the first port through the grid connection point and the power grid port.

[0045] It should be noted that, Figure 5 This explanation uses the power grid as an example, but it is not a limitation. In addition to the power grid, the power source can also be an energy storage battery, a generator, an inverter, etc.

[0046] In possible implementations, the first port may be an active port, such as... Figure 1 The diagram shows a topology of a power station where the device under test is located, according to an embodiment of this application. In this topology diagram, the active ports of devices 1, 2, and 3 are connected in parallel to the first grid connection point PCC1 of the power grid, and the active ports of devices 4 and 5 are connected in parallel to the second grid connection point PCC2 of the power grid.

[0047] When the first disturbance voltage is injected into the active port of the device under test, the device under test can be controlled to be disconnected from the power supply. Figure 1 The connection between the power grid and the power source is disconnected, meaning the voltage of the power source will not be connected to the first port, thus avoiding a short circuit when the first disturbance voltage is injected. Then, the first disturbance voltage can be generated by the signal modulation module inside the device under test, and the generated first disturbance voltage is injected into the first port to detect other ports in the same subarray as the first port, that is, to detect other devices in the same subarray as the device under test. Thus, the first disturbance voltage can be efficiently introduced without the need for other tools.

[0048] In one possible implementation, a first disturbance voltage can be generated and injected into the first port using a disturbance signal injection device. For example, the first disturbance voltage can be generated and injected into the first port using hardware circuitry. When injecting the first disturbance voltage, the voltage injected can be different from the voltage that may exist in the system where the device under test is located, such as a voltage with different characteristics from the power supply (mains) voltage, including triangular wave voltage or harmonic voltage. This can help to perform subarray identification more efficiently and reliably.

[0049] In possible implementations, when the first port is an active port and the first disturbance signal is a first disturbance current, when the first disturbance signal is injected through the device under test or the disturbance signal injection device, the first disturbance current can be output by the device under test, or the first disturbance current can be generated by the disturbance signal injection device and injected into the first port. To facilitate the detection of the disturbance signal, the current characteristics of the first disturbance current are different from the current characteristics of the output current of the power supply connected to the device under test through the first port. For example, the first disturbance current can be a harmonic current or a triangular wave current with different current characteristics from the output current of the power supply connected to the first port.

[0050] for example Figure 1 As shown, the first port (grid port) connected to the grid connection point can generate a first disturbance current through modulation of the device under test and inject it into the first port, or generate a first disturbance current through another disturbance signal injection device and inject it into the first port, so that the port matching the first disturbance current can be detected in other devices, thereby determining other ports in the same subarray as the first port.

[0051] Taking the first port of the device under test as an active port, and the power supply connected to the first port as a transformer in the power grid as an example, when the first disturbance signal generated by the device under test is the first disturbance current, the theoretical voltage generated by the first disturbance current at other ports located in the same subarray as the first port can be calculated by combining the line impedance and the transformer leakage inductance impedance, thereby obtaining the theoretical second disturbance signal. For example Figure 6 The diagram shown is a schematic of a first disturbance current injection into a first port (active port) according to an embodiment of this application. e is the electromotive force in the secondary side of the transformer. The first disturbance current generated by the device under test is i, the line impedance is z1, and the transformer leakage inductance impedance is z2. The theoretical second disturbance signal is: u = e + i(z1 + z2). When the actual second disturbance signal of a port of a device other than the device under test matches u, it indicates that the port and the first port are located in the same subarray, meaning the device corresponding to that port and the device under test are located in the same active subarray.

[0052] In S403, a second disturbance signal is detected in the ports of devices other than the device under test.

[0053] After injecting a first disturbance signal into the first port, a second disturbance signal can be detected at the ports of other devices to determine whether a second disturbance signal exists. The second disturbance signal is a disturbance signal present in the ports of other devices, and can be a second disturbance voltage or a second disturbance current.

[0054] To improve detection efficiency, embodiments of this application can determine the port to be detected based on the type of the first port.

[0055] For example, if the first port is an active port, it is only necessary to detect whether the active ports of other devices have a second disturbance signal. If the first port is a passive port, it is only necessary to detect whether the passive ports of other devices have a second disturbance signal. By distinguishing the port types, the number of ports to be detected can be effectively reduced, thus improving the subarray identification efficiency.

[0056] In S404, when the second disturbance signal matches the first disturbance signal, it is determined that the target port where the second disturbance signal that matches the first disturbance signal is located is in the same subarray as the first port.

[0057] When detecting the second disturbance signal, the second disturbance signal may be a signal unrelated to the first disturbance signal or a signal related to the first disturbance signal. Further matching processing is required to determine whether the second disturbance signal matches the first disturbance signal, that is, whether the second disturbance signal and the first disturbance signal satisfy a preset correspondence or a theoretical correspondence. For example, when the disturbance signal is a disturbance current, it is possible to detect whether the current characteristics of the second disturbance current match the current characteristics of the first disturbance current, or it is possible to detect whether the voltage characteristics of the second disturbance voltage match the current characteristics of the first disturbance current. The current and voltage characteristics can be harmonic orders, frequencies, waveforms, etc. If they match, it indicates that the device under test and the device containing the target port where the second disturbance signal is detected are located in the same subarray; that is, the first port and the target port where the second disturbance signal is detected are in the same subarray.

[0058] After detecting the target port associated with the first port and determining other ports located in the same subarray as the first port, if there are still unidentified ports of devices in the system, then select any port among the unidentified ports to update it as the first port, and jump to S402 to inject the first disturbance signal into the first port, until all ports are identified and all subarrays included in the system are obtained.

[0059] For example, in recognition Figure 3When defining a subarray in the multi-device topology diagram, we can first identify any device, such as the active port of device 1, as the first port. A first disturbance signal is injected into the first port using a disturbance signal injection device or the device under test. If a second disturbance signal matching the first disturbance signal is detected at the active ports of devices 2, 4, and 5, then devices 1, 2, 4, and 5 are determined to be located in the same active subarray (the subarray determined by the active ports of the devices). From the remaining unidentified active ports, the active port of one of devices 3 and 6 is identified as the first port. After injecting the first disturbance signal, if a second disturbance signal matching the first disturbance signal is detected at the active port of the other device, then devices 3 and 6 are determined to be located in the same active subarray.

[0060] After all active ports have been identified, any one device, such as the passive port of device 1, is designated as the first port. A first disturbance signal is injected into the first port. If no second disturbance signal matching the first disturbance signal is detected in the passive ports of other devices, device 1 is determined to be located in a passive subarray (the subarray determined by the passive ports of the devices). From the unidentified passive ports, any one device, such as the passive port of device 2, is selected and updated as the first port. The first disturbance signal is injected into the first port. If a second disturbance signal matching the first disturbance signal is detected in the passive ports of devices 3, 4, and 5, then devices 2, 3, 4, and 5 are identified as being located in the same passive subarray. From the remaining unidentified ports (the passive ports of device 6), any one of the passive ports (the passive ports of device 6) is selected and updated as the first port. The first disturbance signal is injected into the first port. If no second disturbance signal matching the first disturbance signal is detected in the passive ports of other devices, device 6 is determined to be located in a passive subarray.

[0061] In some possible implementations, each phase port of the device may be connected to different phase lines. In this case, subarray identification is required for each phase port to determine which ports are connected to the same phase line. For example... Figure 7 The diagram shown is a schematic of a three-phase grid-connected subarray topology provided in an embodiment of this application. Each phase port (phase A, phase B, and phase C) of the device is connected to a different phase line. Each phase port of the device is connected to the secondary side of a transformer, and the primary sides of the two transformers are connected in parallel. The device is a three-phase four-wire system, with each phase port connected to a different phase of the transformer secondary side. Subarray identification is performed on each phase port of the device to determine the subarray corresponding to each phase port.

[0062] It can be determined that any one phase port of the device under test is the first port, a first disturbance signal is injected into the first port, and a second disturbance signal is detected in the ports of other devices besides the device under test. When the second disturbance signal matches the first disturbance signal, it is determined that the target port of the second disturbance signal that matches the first disturbance signal is connected to the same phase line as the first port.

[0063] For example, we can first identify device 1 as the device to be tested, and determine port 1 of device 1 (the port where device 1 is connected to the A-phase line of the transformer corresponding to PCC1) as the first port. A first disturbance signal is injected into the first port, and a second disturbance signal matching the first disturbance signal is detected at port 1 of device 2 (the port where device 2 is connected to the A-phase line of the transformer corresponding to PCC1). This indicates that port 1 of device 2 is connected to port 1 of device 1 on the same phase line. After updating the first port, we continue with the topology subarray identification step, which can determine that port 2 of device 1 is connected to port 2 of device 3 on the same phase line. Furthermore, after updating the first port, we can identify that port 3 of device 2 is connected to port 3 of device 3 on the same phase line. This process can be repeated to identify all subarrays in the system, thereby determining which ports are connected to the same phase line.

[0064] As can be seen from the above analysis, the topology subarray identification method in this application embodiment realizes automatic identification and correction of the system's topology subarray information, thereby effectively reducing system power scheduling errors, improving system stability and power quality, and improving system troubleshooting efficiency due to more accurate topology subarray information, thereby reducing operation and maintenance costs and reducing system downtime.

[0065] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0066] Figure 8 This is a schematic diagram of a topological subarray identification device provided in an embodiment of this application. The device includes: First port determination unit 801 is used to determine the first port of the device to be tested in the power plant; The signal injection unit 802 is used to inject a first disturbance signal into the first port; The signal detection unit 803 is used to detect a second disturbance signal in the port of a device other than the device under test; The subarray identification unit 804 is used to determine that the target port where the second disturbance signal that matches the first disturbance signal is located is in the same subarray as the first port when the second disturbance signal matches the first disturbance signal.

[0067] Figure 8 The topological subarray identification device shown is, and Figure 4 The topological subarray identification method shown corresponds to this.

[0068] Figure 9 This is a schematic diagram of a topological subarray identification system provided in an embodiment of this application. For example... Figure 9 As shown, the topology subarray identification system 9 of this embodiment includes: a processor 90, a memory 91, and a computer program 92 stored in the memory 91 and executable on the processor 90, such as a topology subarray identification program. When the processor 90 executes the computer program 92, it implements the steps in the various topology subarray identification method embodiments described above. Alternatively, when the processor 90 executes the computer program 92, it implements the functions of each module / unit in the various device embodiments described above.

[0069] For example, the computer program 92 can be divided into one or more modules / units, which are stored in the memory 91 and executed by the processor 90 to complete this application. The one or more modules / units can be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program 92 in the topology subarray identification system 9.

[0070] The topological subarray identification system may include, but is not limited to, a processor 90 and a memory 91. Those skilled in the art will understand that... Figure 9 This is merely an example of a topology subarray identification system 9 and does not constitute a limitation on the topology subarray identification system 9. It may include more or fewer components than shown, or combine certain components, or different components. For example, the topology subarray identification system may also include input / output devices, network access devices, buses, etc.

[0071] The processor 90 may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0072] The memory 91 can be an internal storage unit of the topology subarray identification system 9, such as a hard disk or memory of the topology subarray identification system 9. The memory 91 can also be an external storage device of the topology subarray identification system 9, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the topology subarray identification system 9. Furthermore, the memory 91 can include both internal storage units and external storage devices of the topology subarray identification system 9. The memory 91 is used to store the computer program and other programs and data required by the topology subarray identification system. The memory 91 can also be used to temporarily store data that has been output or will be output.

[0073] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0074] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0075] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0076] In the embodiments provided in this application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0077] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0078] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0079] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by hardware related to computer program instructions. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0080] In addition, this application also provides a computer program product that, when run on a computer, causes the computer to execute the methods in the above-described implementations.

[0081] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for identifying topological subarrays, characterized in that, The method includes: Determine the first port of the device to be tested in the power plant; Inject a first disturbance signal into the first port; Detect the second disturbance signal in the ports of devices other than the device under test; When the second disturbance signal matches the first disturbance signal, it is determined that the target port where the second disturbance signal that matches the first disturbance signal is located is in the same subarray as the first port.

2. The method according to claim 1, characterized in that, The first port is an active port or a passive port; the first disturbance signal is a first disturbance current or a first disturbance voltage; Injecting a first disturbance signal into the first port includes: A first disturbance signal is injected into the first port through the device under test or the disturbance signal injection device.

3. The method according to claim 2, characterized in that, The first port is a passive port, and the first disturbance signal is the first disturbance voltage; Injecting a first disturbance signal into the first port through the device under test or the disturbance signal injection device includes: The first disturbance voltage is generated by controlling the device under test, and the first disturbance voltage is injected into the first port; or, By controlling the device under test, the output voltage of the power supply connected to the device under test is injected into the first port as the first disturbance voltage; or... The first disturbance voltage is generated by the disturbance signal injection device and injected into the first port.

4. The method according to claim 3, characterized in that, The power source is the power grid. The internal common connection point of the device under test is connected to the first port via a first switch. The internal common connection point of the device under test is also connected to the power grid port via a second switch. The first port is connected to the load, and the power grid port is connected to the grid connection point. By controlling the device under test, the output voltage of the power supply connected to the device under test is injected into the first port as the first disturbance voltage, including: The first switch and the second switch are controlled to close so that the voltage of the power grid connected to the device under test is injected into the first port through the grid connection point and the power grid port.

5. The method according to claim 2, characterized in that, The first port is an active port, and the first port is controllably connected to the power supply. The first disturbance signal is the first disturbance voltage. Injecting a first disturbance signal into the first port through the device under test or the disturbance signal injection device includes: Disconnect the device under test from the power supply; By controlling the device under test to output the first disturbance voltage and injecting the first disturbance voltage into the first port, or... A first disturbance voltage is generated by a disturbance signal injection device and injected into the first port.

6. The method according to claim 2, characterized in that, The first port is an active port, and the first disturbance signal is a first disturbance current; Injecting a first disturbance signal into the first port through the device under test or the disturbance signal injection device includes: Control the device under test to output the first disturbance current, and inject the first disturbance current into the first port; or... The first disturbance current is generated by a disturbance signal injection device and injected into the first port; wherein the current characteristics of the first disturbance current are different from the current characteristics of the output current of the power supply connected to the device under test through the first port.

7. The method according to claim 1, characterized in that, Detecting a second disturbance signal in the ports of devices other than the device under test, including: Determine whether the type of the first port is an active port or a passive port; When the first port is an active port, the second disturbance signal is detected in the active ports of other devices besides the device under test; When the first port is a passive port, the second disturbance signal is detected in the passive ports of other devices besides the device under test.

8. The method according to claim 1, characterized in that, In the power station where the device under test is located, different devices are connected through multi-phase lines. The first port is a phase line port in the multi-phase line, and the following is performed for each phase of the multi-phase line: Determine the first port of the device to be tested; Inject a first disturbance signal into the first port; Detect the second disturbance signal in the ports of devices other than the device under test; When the second disturbance signal matches the first disturbance signal, the target port where the second disturbance signal that matches the first disturbance signal is located is determined to be connected to the same phase line as the first port.

9. The method according to any one of claims 1-8, characterized in that, After determining that the target port of the second disturbance signal matching the first disturbance signal is located in the same subarray as the first port, the method further includes: If there are still ports of equipment in the power station that have not been identified, select any port among the unidentified ports to update it as the first port, and jump to the step of injecting the first disturbance signal into the first port until all ports have been identified.

10. A topological subarray identification device, characterized in that, The device includes: The first port determination unit is used to determine the first port of the device to be tested in the power plant. A signal injection unit is used to inject a first disturbance signal into the first port; A signal detection unit is used to detect a second disturbance signal in the ports of devices other than the device under test; The subarray identification unit is used to determine that when the second disturbance signal matches the first disturbance signal, the target port where the second disturbance signal that matches the first disturbance signal is located is in the same subarray as the first port.

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