Display device and electronic device

Abstract

A display device and an electronic device are disclosed. The display device includes a semiconductor substrate and a plurality of pixels disposed on the semiconductor substrate. Each pixel includes a light-emitting element, a first transistor, a second transistor, a first capacitor, and a second capacitor. The first capacitor includes a first-first capacitor electrode and a first-second capacitor electrode spaced apart from the first-first capacitor electrode in a horizontal direction. The second capacitor includes a second-first capacitor electrode and a second-second capacitor electrode, the second-second capacitor electrode being spaced apart from the second-first capacitor electrode in a vertical direction and superimposed on the second-first capacitor electrode in a horizontal direction.

Description

Technical Field

[0001] The embodiments of this disclosure described herein relate to a display device and an electronic device, and more specifically, to a display device and an electronic device including a semiconductor substrate. Background Technology

[0002] Electronic devices that provide images to users, such as smartphones, laptops, car navigation units, and smart TVs, include display devices for displaying images. Augmented reality devices, virtual reality devices, or video projection devices may include microdisplay devices. To display high-brightness images while operating at low power, microdisplay devices may include a silicon wafer and light-emitting elements disposed on the silicon wafer. Summary of the Invention

[0003] Embodiments of this disclosure provide a display device and an electronic device including a semiconductor substrate.

[0004] According to an embodiment, the display device includes a semiconductor substrate and a plurality of pixels disposed on the semiconductor substrate.

[0005] Each of the plurality of pixels includes: a light-emitting element; a first transistor disposed between a first power line and the light-emitting element and operating according to the potential of a control node; a second transistor disposed between a data line and the control node; a first capacitor connected between a first electrode of the first transistor and the control node; and a second capacitor connected between the control node and a second electrode of the first transistor.

[0006] The first capacitor includes a first capacitor electrode and a first second capacitor electrode spaced apart from the first capacitor electrode in a horizontal direction. The second capacitor includes a second first capacitor electrode and a second second capacitor electrode, the second second capacitor electrode being spaced apart from the second first capacitor electrode in a vertical direction and stacked on top of the second first capacitor electrode in a horizontal direction.

[0007] According to an embodiment, the electronic device includes a display panel, a frame housing the display panel, and a structure on which the frame is mounted, and the display panel includes a semiconductor substrate and a plurality of pixels disposed on the semiconductor substrate.

[0008] Each of the plurality of pixels includes: a light-emitting element; a first transistor disposed between the power line and the light-emitting element and operating according to the potential of the control node; a second transistor disposed between the data line and the control node; a first capacitor connected between the first electrode of the first transistor and the control node; and a second capacitor connected between the control node and the second electrode of the first transistor.

[0009] The first capacitor includes a first capacitor electrode and a second capacitor electrode disposed on the same layer as the first capacitor electrode. The second capacitor includes a second capacitor electrode and a second capacitor electrode, the second capacitor electrode being stacked with the second capacitor electrode and disposed on a different layer than the layer on which the second capacitor electrode is disposed. Attached Figure Description

[0010] The above and other objects and features of this disclosure will become clear from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0011] Figure 1 This is a perspective view of a display device according to an embodiment of the present disclosure.

[0012] Figure 2 This is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0013] Figure 3 It is a plan view of a unit pixel region according to an embodiment of the present disclosure.

[0014] Figure 4 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0015] Figure 5A This is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0016] Figure 5B This is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0017] Figure 6 This is a cross-sectional view showing a portion of a display device according to an embodiment of the present disclosure.

[0018] Figures 7A to 7G This is a plan view illustrating the stacking process of circuit layers according to an embodiment of the present disclosure.

[0019] Figure 8 This is a cross-sectional view showing a portion of a display device according to an embodiment of the present disclosure.

[0020] Figure 9 This is a cross-sectional view showing a portion of a display device according to an embodiment of the present disclosure.

[0021] Figure 10 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0022] Figure 11 This is an exploded perspective view of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0023] In this specification, when a component (or region, layer, part, etc.) is referred to as being "on" another component, "connected to" or "integrated into" another component, this means that the component may be directly on, directly connected to or directly integrated into the other component, or that a third component may be present between them.

[0024] The same reference numerals refer to the same components. Furthermore, in the accompanying drawings, the thickness, scale, and dimensions of the components are exaggerated for effective description. As used herein, the term "and / or" includes all of one or more combinations defined by the relevant components.

[0025] Terms such as "first," "second," etc., may be used to describe various components, but components should not be limited by the terms. These terms may be used only to distinguish one component, part, region, layer, or portion from other components, parts, regions, layers, or portions. For example, without departing from the scope of this disclosure, a first component, first part, first region, first layer, or first portion may be referred to as a second component, second part, second region, second layer, or second portion, and similarly, a second component, second part, second region, second layer, or second portion may also be referred to as a first component, first part, first region, first layer, or first portion. Unless otherwise stated, singular terms may include plural forms.

[0026] Furthermore, terms such as "below," "under," "above," and "on top of" are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0027] It should be understood that when terms such as “comprising,” “including,” and “having” are used herein, the presence of the stated features, quantities, steps, operations, components, parts, or combinations thereof is specified, but the presence or addition of one or more other features, quantities, steps, operations, components, parts, or combinations thereof is not excluded.

[0028] Unless otherwise defined, all terms used herein (including technical or scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as in the context of the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning unless expressly defined in this application as having such a meaning.

[0029] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings.

[0030] Figure 1 This is a perspective view of a display device according to an embodiment of the present disclosure.

[0031] Reference Figure 1 The display device DD may have a rectangular shape, comprising a long side parallel to the first direction DR1 and a short side parallel to the second direction DR2 intersecting the first direction DR1. However, the embodiments are not limited thereto, and the display device DD may have various shapes such as a circular shape and polygonal shapes other than a rectangular shape. In the following, the direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. The expression "when viewed from above the plane" as used herein may refer to viewing from the third direction DR3.

[0032] The display device DD can be a device activated in response to an electrical signal. The display device DD can be a display device used in televisions, monitors, billboards, tablet computers, car navigation units, personal computers, laptop computers, personal digital terminals, game consoles, smartphones, cameras, and wearable devices. For example, wearable devices can include virtual reality devices, augmented reality devices, and smartwatches. Virtual reality devices and augmented reality devices can be devices in the form of glasses that can be worn by a user. These devices are merely illustrative, and in the concept of this disclosure, the display device DD can display images through a display area DA. A non-display area NDA can surround the display area DA. Figure 1 As shown in the diagram, the non-display area NDA can be set to be adjacent only to one side of the display area DA, or it can be omitted.

[0033] Multiple pixels (PXs) can be arranged in a display area (DA). The pixels (PXs) can be arranged in a matrix. Each pixel (PX) may include pixel circuitry and a light-emitting diode (LED). All pixels (PXs) can generate light of the same color. Optionally, multiple pixels (PXs) that generate light of different colors can be arranged in the display area (DA). For example, a first pixel that outputs light of a first color (or red light), a second pixel that outputs light of a second color (or green light), and a third pixel that outputs light of a third color (or blue light) can be arranged in the display area (DA).

[0034] Figure 2 This is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0035] Reference Figure 2 The display device DD may include a circuit layer CL, a light-emitting element layer EDL, a packaging layer TFE, a color filter layer CFL, a lens layer LEL, an outer coating layer OCL, a window WD, and a polarizing layer POL.

[0036] Pixel circuit PXC (refer to) Figure 5ATransistors can be formed in a circuit layer CL. The circuit layer CL may include at least one insulating layer, conductive patterns, and signal lines. The insulating and conductive layers can be formed by processes such as coating or deposition, and then selectively patterned by performing photolithography processes multiple times.

[0037] The light-emitting element layer (EDL) can be disposed on the circuit layer (CL). The EDL may include a first electrode (AE), an emitting layer (EL), and a second electrode (CE). In this embodiment, the first electrode (AE) may be an anode, and the second electrode (CE) may be a cathode.

[0038] The first electrode AE ​​may include a transparent conductive oxide pattern. The first electrode AE ​​may be formed individually in each of the pixels PX. The transparent conductive oxide pattern may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or zinc oxide (ZnO) to facilitate hole injection. x The first electrode AE ​​can have a single-layer or multi-layer structure. It can be indium oxide (In₂O₃) or aluminum-doped zinc oxide (AZO).

[0039] An emitting layer (EL) can be disposed on a first electrode (AE). The emitting layer (EL) can have a monolithic shape and can be commonly disposed in a pixel (PX). When the emitting layer (EL) has a monolithic shape, it can provide blue light or white light. However, it is not limited thereto; the emitting layer (EL) can be formed individually in each of the pixels (PX). When the emitting layer (EL) is formed individually in each of the pixels (PX), it can emit at least one of a first color, a second color, and a third color. The emitting layer (EL) can include organic light-emitting materials, quantum dots, quantum rods, microLEDs, or nanoLEDs.

[0040] The second electrode CE can be disposed on the emitter layer EL. The second electrode CE can have a monolithic shape and can be commonly disposed in multiple pixels PX. A common voltage can be provided to the second electrode CE, and the second electrode CE can be referred to as the common electrode.

[0041] A TFE (Transmission Equipment Layer) is disposed on the EDL (Emitting Diode Layer). The TFE protects the EDL from foreign matter such as moisture, oxygen, and dust particles. The TFE may include at least one inorganic film (hereinafter referred to as the inorganic encapsulation film). Additionally, the TFE may include at least one organic film (hereinafter referred to as the organic encapsulation film). The TFE may comprise inorganic, organic, and inorganic encapsulation layers stacked sequentially on top of each other. However, the layers constituting the TFE are not limited to these.

[0042] A color filter layer (CFL) can be disposed on the encapsulation layer (TFE). The CFL can include multiple color filters CF1, CF2, and CF3. These multiple color filters CF1, CF2, and CF3 can include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1 can convert colored light (e.g., blue light or a third color light) generated from the emitter layer (EL) into light of a first color and can output light of the first color. The second color filter CF2 can convert colored light generated from the emitter layer (EL) into light of a second color and can output light of the second color. The third color filter CF3 can transmit colored light generated from the emitter layer (EL) without converting the color light and can output light of the third color. Although not shown, the CFL can also include a light-blocking pattern.

[0043] The lens layer (LEL) can be disposed on the color filter layer (CFL). The lens layer (LEL) can include multiple lens patterns. The lens patterns can be configured to correspond to the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3), respectively, and can be spaced apart from each other.

[0044] The outer coating layer (OCL) can be disposed on the lens layer (LEL). The outer coating layer (OCL) may include an optically transparent material. The outer coating layer (OCL) may be a planarization layer and may include a flat upper surface.

[0045] The window WD can be mounted on the outer coating OCL. The window WD provides the outer surface of the display device DD.

[0046] A polarizing layer (POL) can be disposed on the window WD. The polarizing layer POL can function to block external light incident on the display device DD from the outside. The polarizing layer POL can block a portion of the external light. Furthermore, the polarizing layer POL can prevent reflected light generated by components included in the light-emitting element layer EDL and the circuit layer CL from being output to the outside. In other words, the polarizing layer POL can be an anti-reflective layer.

[0047] Figure 3 It is a plan view of a unit pixel region according to an embodiment of the present disclosure.

[0048] exist Figure 3 The image shows a repeated setting. Figure 1 The unit pixel area LU in the display area DA.

[0049] Reference Figure 3 The unit pixel region LU may include a first emission region LA1, a second emission region LA2, and a third emission region LA3. The first light-emitting element of the first pixel, the second light-emitting element of the second pixel, and the third light-emitting element of the third pixel may be respectively disposed in the first emission region LA1, the second emission region LA2, and the third emission region LA3.

[0050] Light of the first color, light of the second color, and light of the third color can be output through the first emission region LA1, the second emission region LA2, and the third emission region LA3, respectively. When the emission layer EL from the first light-emitting element to the third light-emitting element... Figure 2 When integrally formed as shown, the first to third light-emitting elements can generate light of the same color (e.g., blue light). In this case, Figure 2 The first color filter CF1, the second color filter CF2, and the third color filter CF3 shown are configured to correspond to the first light-emitting element, the second light-emitting element, and the third light-emitting element, respectively. Therefore, light of the same color output from the first, second, and third light-emitting elements can be converted into light of the first color, the second color, and the third color, respectively, through the first color filter CF1, the second color filter CF2, and the third color filter CF3. Optionally, when the emitting layers of the first to third light-emitting elements are independently configured, the first, second, and third light-emitting elements can output light of the first color, the second color, and the third color, respectively.

[0051] like Figure 3 As shown, the first emitting region LA1, the second emitting region LA2, and the third emitting region LA3 can have different sizes. For example, the third emitting region LA3 can be larger than the first emitting region LA1, and the first emitting region LA1 can be larger than the second emitting region LA2. In this case, the first emitting region LA1 can output red light as the first color, the second emitting region LA2 can output green light as the second color, and the third emitting region LA3 can output blue light as the third color. That is, the size of the emitting region can vary depending on the efficiency of the light-emitting element.

[0052] Although the structures of the first launch region LA1, the second launch region LA2, and the third launch region LA3 can have the following characteristics... Figure 3 The quadrilateral shape shown is not limited thereto. The shape, arrangement, and area ratio of the first emission region LA1, the second emission region LA2, and the third emission region LA3 may be similar to those shown. Figure 3 The shapes, arrangements, and area ratios shown are different.

[0053] Figure 4 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0054] Reference Figure 4The display device DD may include a display panel DP and a panel driver. In embodiments of this disclosure, the panel driver may include a control circuit 100, a data driver circuit 200, a scan driver circuit 310, a transmission control circuit 350, and a voltage generator 400.

[0055] The display panel DP may include a display area DA and a non-display area NDA surrounding at least a portion of the display area DA. The display panel DP may include a plurality of pixels PX disposed within the display area DA. Each of the plurality of pixels PX includes a light-emitting element ED (see reference). Figure 5A ) and the pixel circuit PXC (refer to) that controls the light emission of the light-emitting element ED. Figure 5A The pixel circuit (PXC) may include at least one transistor and at least one capacitor.

[0056] The display panel DP may also include data lines DL1 to DLm, write scan lines GWL1 to GWLn, reset scan lines GRL1 to GRLn, and transmit control lines EL1 to ELn. Here, m and n can be integers (or natural numbers) of 1 or greater.

[0057] The control circuit 100 receives the image signal RGB and the control signal CTRL. According to the interface specification with the data driver circuit 200, the control circuit 100 generates image data DAT by converting the data format of the image signal RGB. The control circuit 100 outputs a first drive control signal DCS, a second drive control signal GCS, and a third drive control signal ECS.

[0058] The data driver circuit 200 receives a first drive control signal DCS and image data DAT from the control circuit 100. The data driver circuit 200 converts the image data DAT into a data signal and outputs the data signal to data lines DL1 to DLm. The data signal is an analog voltage corresponding to the grayscale value of the image data DAT.

[0059] The scan driver circuit 310 can be located in the non-display area NDA of the display panel DP. The scan driver circuit 310 receives a second drive control signal GCS from the control circuit 100. The scan driver circuit 310 can be connected to write scan lines GWL1 to GWLn and reset scan lines GRL1 to GRLn. In response to the second drive control signal GCS, the scan driver circuit 310 can output write scan signals to the write scan lines GWL1 to GWLn. In response to the second drive control signal GCS, the scan driver circuit 310 can also output reset scan signals to the reset scan lines GRL1 to GRLn.

[0060] The transmission control circuit 350 can be located in the non-display area NDA of the display panel DP. The transmission control circuit 350 receives a third drive control signal ECS from the control circuit 100. The transmission control circuit 350 can be connected to the transmission control lines EL1 to ELn. The transmission control circuit 350 can output transmission control signals to the transmission control lines EL1 to ELn in response to the third drive control signal ECS.

[0061] The scan driver circuit 310 and the emission control circuit 350 can be integrated into the non-display area (NDA) of the display panel (DP) using the same process as the pixel circuit (PXC). Each of the scan driver circuit 310 and the emission control circuit 350 may include a transistor formed using the same process as the pixel circuit (PXC).

[0062] Voltage generator 400 (or power supply circuit) generates the voltages required for the operation of the display panel DP. In this embodiment, voltage generator 400 may generate a first drive voltage ELVDD, a second drive voltage ELVSS, an initialization voltage VINT, and a reference voltage VREF.

[0063] Each of the multiple pixels PX can be electrically connected to a corresponding data line DL1 to DLm, a corresponding write scan line GWL1 to GWLn, a corresponding reset scan line GRL1 to GRLn, and a corresponding transmit control line EL1 to ELn. However, the number of signal lines connected to each of the multiple pixels PX can vary.

[0064] Each of the multiple pixels PX can receive a first driving voltage ELVDD, a second driving voltage ELVSS, an initialization voltage VINT, and a reference voltage VREF from the voltage generator 400. However, the reference voltage VREF can be omitted.

[0065] Figure 5A This is a circuit diagram of a pixel according to an embodiment of the present disclosure. Figure 5B This is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0066] exist Figure 5A In, it is shown Figure 4 The diagram shows the equivalent circuit diagram of one of the multiple pixels PX, PXij. Since the multiple pixels PX have the same circuit structure, the description of the circuit structure of pixel PXij can be applied to the remaining pixels, and the specific descriptions of the remaining pixels will be omitted.

[0067] Reference Figure 5APixel PXij is connected to the j-th data line DLj among data lines DL1 to DLm, the i-th write scan line GWLi among write scan lines GWL1 to GWLn, the i-th reset scan line GRLi among reset scan lines GRL1 to GRLn, and the i-th transmit control line ELi among transmit control lines EL1 to ELn.

[0068] Pixel PXij includes pixel circuit PXC and light-emitting element ED electrically connected to pixel circuit PXC. In embodiments of this disclosure, light-emitting element ED may be a light-emitting diode.

[0069] In this embodiment, the pixel circuit PXC may include four transistors (first transistor T1, second transistor T2, third transistor T3, and fourth transistor T4) and three capacitors (first capacitor C1, second capacitor C2, and third capacitor C3). Each of the first transistors T1 to the fourth transistor T4 may be a transistor having an LTPS semiconductor layer. In embodiments of this disclosure, the first transistors T1 to the fourth transistor T4 may be P-type transistors. However, this disclosure is not limited thereto. Optionally, the first transistors T1 to the fourth transistor T4 may be N-type transistors. In another case, some of the first transistors T1 to the fourth transistor T4 may be P-type transistors, while the others may be N-type transistors. For example, among the first transistors T1 to the fourth transistor T4, the first transistors T1 to the third transistor T3 may be P-type transistors, while the fourth transistor T4 may be an N-type transistor having an oxide semiconductor as its semiconductor layer.

[0070] The i-th write scan line GWLi, the i-th reset scan line GRLi, and the i-th transmit control line ELi can supply the i-th write scan signal GWi, the i-th reset scan signal GRi, and the i-th transmit control signal EMi to pixel PXij. The j-th data line DLj supplies the j-th data signal DSj to pixel PXij.

[0071] In embodiments of this disclosure, pixel PXij can be connected to a first power line PL1, a second power line PL2, a first voltage line VL1, and a second voltage line VL2. The first power line PL1 provides a first driving voltage ELVDD to pixel PXij, and the second power line PL2 provides a second driving voltage ELVSS to pixel PXij. Furthermore, the first voltage line VL1 provides an initialization voltage VINT to pixel PXij, and the second voltage line VL2 provides a reference voltage VREF to pixel PXij. The first voltage line VL1 can be referred to as the initialization voltage line, and the second voltage line VL2 can be referred to as the reference voltage line.

[0072] A first transistor T1 is connected between a first power line PL1 receiving a first driving voltage ELVDD and the anode (or first electrode) of the light-emitting element ED. The first transistor T1 can be referred to as a driving transistor. The first transistor T1 may include a first electrode, a second electrode, and a gate electrode. The gate electrode of the first transistor T1 may be connected to a first node N1 (or a control node), the first electrode of the first transistor T1 may be connected to a second node N2, and the second electrode of the first transistor T1 may be connected to the anode of the light-emitting element ED. The first electrode may be referred to as the drain of the first transistor T1, and the second electrode may be referred to as the source of the first transistor T1. The first transistor T1 operates according to the potential of the first node N1 to supply a driving current Id to the light-emitting element ED.

[0073] A second transistor T2 is connected between the j-th data line DLj and the first node N1, and receives the i-th write scan signal GWi. The second transistor T2 can be referred to as a switching transistor. The second transistor T2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the first node N1, and a gate electrode connected to the i-th write scan line GWLi. The second transistor T2 can be turned on by the i-th write scan signal GWi received through the i-th write scan line GWLi, and can apply the j-th data signal DSj provided from the j-th data line DLj to the first node N1.

[0074] A third transistor T3 is connected between the first power line PL1 and the second node N2, and receives the i-th transmit control signal EMi. The third transistor T3 includes a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1 (i.e., the second node N2), and a gate electrode connected to the i-th transmit control line ELi. The third transistor T3 can be turned on or off in response to the i-th transmit control signal EMi provided through the i-th transmit control line ELi. A first drive voltage ELVDD can be applied to the first transistor T1 through the turned-on third transistor T3.

[0075] A fourth transistor T4 can be connected between a first voltage line VL1 providing the initialization voltage VINT and the anode of the light-emitting element ED, and can receive the i-th reset scan signal GRi. The fourth transistor T4 includes a first electrode connected to the first voltage line VL1, a second electrode connected to the second electrode of the first transistor T1 (i.e., the third node N3), and a gate electrode connected to the i-th reset scan line GRLi. The third node N3 can be the node where the second electrode of the first transistor T1, the second electrode of the fourth transistor T4, and the anode of the light-emitting element ED are connected. The fourth transistor T4 can be turned on by the i-th reset scan signal GRi provided through the i-th reset scan line GRLi, and can initialize (or reset) the third node N3 (i.e., the anode of the light-emitting element ED) to the initialization voltage VINT.

[0076] In embodiments of this disclosure, each of the first transistor T1 to the fourth transistor T4 may further include a third electrode. The third electrode of each of the first transistor T1 to the fourth transistor T4 is connected to a substrate (e.g., a semiconductor substrate SS (refer to...)). Figure 6 This allows the substrate to have a constant voltage. For example... Figure 5A As shown, the third electrode of the first transistor T1 to the third transistor T3 can receive the first driving voltage ELVDD, and the third electrode of the fourth transistor T4 can receive the ground voltage GND.

[0077] A first capacitor C1 can be connected between the gate electrode (i.e., the first node N1) of the first transistor T1 and the first electrode (i.e., the second node N2) of the first transistor T1. The first capacitor C1 includes a first-first capacitor electrode CE11 connected to the first node N1 and a first-second capacitor electrode CE12 connected to the second node N2. The first capacitor C1 can store the voltage difference between the first node N1 and the second node N2.

[0078] The second capacitor C2 can be connected between the first node N1 and the second electrode (i.e., the third node N3) of the first transistor T1. The second capacitor C2 includes a second-first capacitor electrode CE21 connected to the first node N1 and a second-second capacitor electrode CE22 connected to the third node N3. The second capacitor C2 can store the voltage difference between the first node N1 and the third node N3.

[0079] A third capacitor C3 can be connected between the first node N1 and the second voltage line VL2, which provides the reference voltage VREF. The third capacitor C3 includes a third-to-first capacitor electrode CE31 connected to the first node N1 and a third-to-second capacitor electrode CE32 connected to the second voltage line VL2. The third capacitor C3 can store the voltage difference between the first node N1 and the second voltage line VL2.

[0080] The anode of the light-emitting element ED is connected to the third node N3 (i.e., the second electrode of the first transistor T1), and the cathode (or second electrode) of the light-emitting element ED is connected to the second power line PL2, which provides the second driving voltage ELVSS. The second driving voltage ELVSS can have a voltage level lower than the initialization voltage VINT.

[0081] In embodiments of this disclosure, the maximum potential difference between the second-first capacitor electrode CE21 and the second-second capacitor electrode CE22 can be greater than the maximum potential difference between the first-first capacitor electrode CE11 and the first-second capacitor electrode CE12. Furthermore, the potential difference between the first driving voltage ELVDD and the initialization voltage VINT can be greater than the potential difference between the first driving voltage ELVDD and the reference voltage VREF. Therefore, the maximum potential difference between the second-first capacitor electrode CE21 and the second-second capacitor electrode CE22 can be greater than the maximum potential difference between the third-first capacitor electrode CE31 and the third-second capacitor electrode CE32.

[0082] Figure 5A The pixel circuit PXC is not limited to this. The number of transistors or capacitors included in the pixel circuit PXC can be varied in various ways depending on the design of the pixel circuit PXC.

[0083] like Figure 5B As shown, the pixel circuit PXCa may include four transistors (first transistor T1, second transistor T2, third transistor T3, and fourth transistor T4) and two capacitors (first capacitor C1 and second capacitor C2). That is, Figure 5B The pixel circuit PXCa can have a component from which Figure 5A The pixel circuit PXC omits the third capacitor C3. Alternatively, the pixel circuit PXCa may have a structure in which one of the four transistors T1 to T4 is omitted or at least one transistor is added.

[0084] Figure 6 This is a cross-sectional view showing a portion of a display device according to an embodiment of the present disclosure.

[0085] Reference Figure 6 The circuit layer CL may include a semiconductor substrate SS, at least one insulating layer IL1 to IL7, and at least one conductive pattern. Although seven insulating layers IL1 to IL7 are shown as an example in this embodiment, the present disclosure is not limited thereto.

[0086] The semiconductor substrate SS can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Multiple pixels PX (see reference) Figure 4The source regions SR1 and SR2 and the drain regions DDR1 and DDR2 can be formed on a semiconductor substrate SS. The semiconductor substrate SS may include source regions SR1 and SR2 and drain regions DDR1 and DDR2. Each of the source regions SR1 and SR2 and the drain regions DDR1 and DDR2 may be a region doped with impurities. The source regions SR1 and SR2 and the drain regions DDR1 and DDR2 may define transistors T1 and T2 together with gate electrodes GT1 and GT2, which will be described below. Depending on the signal flow, the source regions SR1 and SR2 and the drain regions DDR1 and DDR2 may be the source or drain of transistors T1 and T2.

[0087] A gate insulating pattern (GIL) and gate electrodes GT1 and GT2 are disposed on a semiconductor substrate SS. Gate electrodes GT1 and GT2 may comprise metal. Gate electrodes GT1 and GT2 are configured to correspond to the regions between source regions SR1 and SR2 and drain regions DDR1 and DDR2. The gate insulating pattern (GIL) may be configured to correspond to gate electrodes GT1 and GT2.

[0088] An insulating layer IL1 can be disposed on a semiconductor substrate SS. The insulating layer IL1 can be stacked together with multiple pixels PX and can cover the gate electrodes GT1 and GT2 of transistors T1 and T2. The insulating layer IL1 can be an inorganic layer and / or an organic layer, and can have a single-layer or multi-layer structure. The insulating layer IL1 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the insulating layer IL1 can be a single silicon oxide layer. The insulating layer IL1 can be referred to as the third insulating layer.

[0089] The second-first sub-electrode C2_C21 can be disposed on the insulating layer IL1. The second-first sub-electrode C2_C21 can face the gate electrode GT1 of the first transistor T1 and can form a second capacitor C2. The gate electrode GT1 of the first transistor T1 can be electrically connected to the second-first capacitor electrode CE21 (see reference). Figure 5A And, and can have an integral shape with the second-first capacitor electrode CE21. Here, integral shape means that a physical component can contain or act as both the gate electrode GT1 and the second-first capacitor electrode CE21. The second-first sub-electrode C2_C21 can be included in the second-second capacitor electrode CE22 (refer to...). Figure 5A The components in the first transistor T1. The second-first sub-electrode C2_C21 may be spaced apart from the gate electrode GT1 of the first transistor T1 in the vertical direction (e.g., third direction DR3), and may be partially superimposed on the gate electrode GT1 of the first transistor T1 in the horizontal direction (e.g., first direction DR1 or second direction DR2). That is, the second-first capacitor electrode CE21 and the second-second capacitor electrode CE22 may be disposed on different layers.

[0090] The contact hole exposing the drain region DDR2 of the second transistor T2 can be disposed in the insulating layer IL1. The first data connection electrode D_CNE1, which connects to the drain region DDR2 of the second transistor T2 through the contact hole, can be further disposed on the insulating layer IL1.

[0091] The second-first sub-electrode C2_C21 and the first data connection electrode D_CNE1 can be the first conductive pattern layer CPL1 (see reference). Figure 7B ( ) part.

[0092] An insulating layer IL2 covering the second-first sub-electrode C2_C21 and the first data connection electrode D_CNE1 is disposed on an insulating layer IL1. The insulating layer IL2 is stacked together with multiple pixels PX. The insulating layer IL2 can be an inorganic layer and / or an organic layer, and can have a single-layer or multi-layer structure. In this embodiment, the insulating layer IL2 can be a single-layer silicon oxide layer. The insulating layer IL2 can be referred to as the intermediate gate insulating layer.

[0093] The capacitor connection electrode C2_CNE is disposed on the second insulating layer IL2. The contact hole exposing the second-first sub-electrode C2_C21 can be disposed in the second insulating layer IL2. The capacitor connection electrode C2_CNE can be connected to the second-first sub-electrode C2_C21 through the contact hole in the second insulating layer IL2.

[0094] The contact hole exposing the first data connection electrode D_CNE1 can be further disposed in the second insulating layer IL2. The second data connection electrode D_CNE2, which is connected to the first data connection electrode D_CNE1 through the contact hole, can be further disposed on the second insulating layer IL2.

[0095] An insulating layer IL3 covering the capacitor connection electrode C2_CNE and the second data connection electrode D_CNE2 is disposed on the insulating layer IL2. The insulating layer IL3 is stacked together with multiple pixels PX. The insulating layer IL3 can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure. The insulating layer IL3 can be referred to as the fourth insulating layer.

[0096] The second sub-electrode C2_C22 is disposed on the insulating layer IL3. The contact hole for exposing the capacitor connection electrode C2_CNE can be disposed within the insulating layer IL3. The second sub-electrode C2_C22 can be connected to the capacitor connection electrode C2_CNE through the contact hole in the insulating layer IL3. That is, the second sub-electrode C2_C22 can be electrically connected to the second sub-electrode C2_C21 through the capacitor connection electrode C2_CNE.

[0097] The second horizontal voltage line H_VL2 can be further disposed on the insulating layer IL3. The second horizontal voltage line H_VL2 can be included in the initialization voltage VINT (refer to...) applied to it. Figure 5A The first voltage line VL1 (refer to) Figure 5A Components in ).

[0098] The contact hole exposing the second data connection electrode D_CNE2 can be further disposed in the insulating layer IL3. The third data connection electrode D_CNE3, which is connected to the second data connection electrode D_CNE2 through the contact hole, can be further disposed on the insulating layer IL3.

[0099] The second sub-electrode C2_C22, the second horizontal voltage line H_VL2, and the third data connection electrode D_CNE3 can be the second conductive pattern layer CPL2 (see reference). Figure 7C ( ) part.

[0100] An insulating layer 4 IL4 covering the second sub-electrode C2_C22, the second horizontal voltage line H_VL2, and the third data connection electrode D_CNE3 is disposed on the insulating layer 3 IL3. The insulating layer 4 IL4 is stacked together with multiple pixels PX. The insulating layer 4 IL4 can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure. The insulating layer 4 IL4 can be referred to as the first insulating layer.

[0101] The first-first sub-electrode C1_C11 and the first-third sub-electrode C1_C21 are disposed on the insulating layer IL4. The first-first sub-electrode C1_C11 may be included in the first-first capacitor electrode CE11 (refer to...). Figure 5A The components in the first-third sub-electrode C1_C21 may be included in the first-second capacitor electrode CE12 (refer to...). Figure 5A The components in the (). The first-first sub-electrode C1_C11 and the first-third sub-electrode C1_C21 can be spaced apart from each other in the horizontal direction (e.g., the first direction DR1 or the second direction DR2). Therefore, the first capacitor C1 can be formed between the first-first sub-electrode C1_C11 and the first-third sub-electrode C1_C21. ​​The first-first capacitor electrode CE11 and the first-second capacitor electrode CE12 can be disposed on the same layer (i.e., insulating layer 4 IL4).

[0102] When viewed from above the plane, the first sub-electrode C1_C11 may partially overlap with the second sub-electrode C2_C22, and may be spaced apart from the second sub-electrode C2_C22 in a vertical direction (e.g., third direction DR3). The first sub-electrode C1_C11 may face the second sub-electrode C2_C22 and may form a second capacitor C2. The first sub-electrode C1_C11 may be electrically connected to the second capacitor electrode CE21 (see reference). Figure 5A And, and can have an integral shape with the second-first capacitor electrode CE21. Here, integral shape means that a physical component can be used as or contain the first-first sub-electrode C1_C11 and the second-first capacitor electrode CE21. The second-second sub-electrode C2_C22 can be a component included in the second-second capacitor electrode CE22.

[0103] The contact hole exposing the third data connection electrode D_CNE3 can be further disposed in the insulating layer IL4. The fourth data connection electrode D_CNE4, which is connected to the third data connection electrode D_CNE3 through the contact hole, can be further disposed on the insulating layer IL4.

[0104] The first-first sub-electrode C1_C11, the first-third sub-electrode C1_C21, and the fourth data connection electrode D_CNE4 can be the third conductive pattern layer CPL3 (see reference). Figure 7D ( ) part.

[0105] An insulating layer IL5 covering the first-first sub-electrode C1_C11, the first-third sub-electrode C1_C21, and the fourth data connection electrode D_CNE4 is disposed on the insulating layer IL4. The insulating layer IL5 is stacked together with multiple pixels PX. The insulating layer IL5 can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure. The insulating layer IL5 can be referred to as the second insulating layer.

[0106] The first and second sub-electrodes C1_C12 and the first and fourth sub-electrodes C1_C22 are disposed on the insulating layer IL5. The first and second sub-electrodes C1_C12 may be included in the first capacitor electrode CE11 (refer to...). Figure 5A The components in the first-fourth sub-electrodes C1_C22 may be included in the first-second capacitor electrode CE12 (refer to...). Figure 5AThe components in the (e.g., first-second sub-electrode C1_C12 and first-fourth sub-electrode C1_C22) can be spaced apart from each other in the horizontal direction (e.g., first direction DR1 or second direction DR2). Therefore, the first capacitor C1 can be formed between the first-second sub-electrode C1_C12 and the first-fourth sub-electrode C1_C22. The first-first capacitor electrode CE11 and the first-second capacitor electrode CE12 can be disposed on the same layer (i.e., insulating layer IL5). The first-second sub-electrode C1_C12 can be stacked with the first-first sub-electrode C1_C11 in the vertical direction (e.g., third direction DR3), and the first-fourth sub-electrode C1_C22 can be stacked with the first-third sub-electrode C1_C21 in the vertical direction (e.g., third direction DR3).

[0107] The contact hole exposing the fourth data connection electrode D_CNE4 can be further disposed in the insulating layer IL5. The j-th data line DLj, which is connected to the fourth data connection electrode D_CNE4 through the contact hole, can be further disposed on the insulating layer IL5. The j-th data line DLj can be electrically connected to the drain region DDR2 of the second transistor T2 through the first data connection electrode D_CNE1 to the fourth data connection electrode D_CNE4.

[0108] The first and second sub-electrodes C1_C12, the first and fourth sub-electrodes C1_C22, and the j-th data line DLj can be the fourth conductive pattern layer CPL4 (see reference). Figure 7E ( ) part.

[0109] An insulating layer IL6 covering the first-second sub-electrodes C1_C12, the first-fourth sub-electrodes C1_C22, and the j-th data line DLj is disposed on insulating layer IL5. Insulating layer IL6 can be referred to as the third data insulating layer.

[0110] The first-fifth sub-electrodes C1_C13 and the first-sixth sub-electrodes C1_C23 are disposed on the insulating layer IL6. The first-fifth sub-electrodes C1_C13 may be included in the first capacitor electrode CE11 (refer to...). Figure 5A The components in the first-sixth sub-electrodes C1_C23 may be included in the first-second capacitor electrode CE12 (refer to...). Figure 5A The components in the () are as follows. The first-fifth sub-electrode C1_C13 and the first-sixth sub-electrode C1_C23 can be spaced apart from each other in the horizontal direction (e.g., the first direction DR1 or the second direction DR2). Therefore, the first capacitor C1 can be formed between the first-fifth sub-electrode C1_C13 and the first-sixth sub-electrode C1_C23. The first-first capacitor electrode CE11 and the first-second capacitor electrode CE12 can be disposed on the same layer (i.e., insulating layer IL6).

[0111] The first to fifth sub-electrodes C1_C13 and the first to sixth sub-electrodes C1_C23 can be the fifth conductive pattern layer CPL5 (see reference). Figure 7F ( ) part.

[0112] An insulating layer 7 IL7 covering the first to fifth sub-electrodes C1_C13 and the first to sixth sub-electrodes C1_C23 is disposed on the insulating layer 6 IL6. The insulating layer 7 IL7 can be referred to as the anode insulating layer.

[0113] The anode AE ​​and the grid power line V_PL1 are disposed on the insulating layer IL7. The anode AE ​​can be partially superimposed on the first-fifth sub-electrodes C1_C13 in the vertical direction (e.g., third-direction DR3). Therefore, the second capacitor C2 can be formed between the first-fifth sub-electrodes C1_C13 and the anode AE. The first-fifth sub-electrodes C1_C13 can be electrically connected to the second-first capacitor electrode CE21 (see reference). Figure 5A And, and can have an integral shape with the second-first capacitor electrode CE21, that is, a single physical component can contain or act as both the first-fifth sub-electrode C1_C13 and the second-first capacitor electrode CE21. The anode AE ​​can be electrically connected to the second-second capacitor electrode CE22 (see reference). Figure 5A ), and can have an integral shape with the second-second capacitor electrode CE22, that is, one physical component can contain or act as two components. Although Figure 6 An insulating layer 7 IL7 covering the first-fifth sub-electrodes C1_C13 and the first-sixth sub-electrodes C1_C23 is shown disposed on an insulating layer 6 IL6. However, this disclosure is not limited thereto. For example, the insulating layer 7 IL7 and the first-fifth sub-electrodes C1_C13 and the first-sixth sub-electrodes C1_C23 can be omitted. In this case, the anode AE ​​can be disposed on the insulating layer 6 IL6, and the anode AE ​​can be stacked with the first-second sub-electrodes C1_C12 in a vertical direction (e.g., a third direction DR3) to form a second capacitor C2.

[0114] The grid power line V_PL1 can be included in the first drive voltage ELVDD (refer to...) Figure 5A The first power line PL1 (refer to) Figure 5A Components in ).

[0115] The anode AE ​​and the grid electric field lines V_PL1 can be the sixth conductive pattern layer CPL6 (see reference). Figure 7G ( ) part.

[0116] A pixel-defining layer (PDL) covering the anode AE ​​and the grid power lines V_PL1 is disposed on the insulating layer IL7. A pixel opening (PDL_OP) exposing the anode AE ​​is disposed within the pixel-defining layer (PDL). An emission layer (EL) is disposed on the pixel-defining layer (PDL) and the anode AE ​​exposed through the pixel opening (PDL_OP). In this embodiment, the emission layer (EL) can be commonly disposed in multiple pixels (PX). In this case, the common emission layer (EL) can generate white light or blue light. A cathode (CE) is disposed on the emission layer (EL). The cathode (CE) is commonly disposed in multiple pixels (PX). The cathode (CE) can be sealed by an encapsulation layer (TFE).

[0117] The maximum potential difference between the second-first capacitor electrode CE21 and the second-second capacitor electrode CE22 can be greater than the maximum potential difference between the first-first capacitor electrode CE11 and the first-second capacitor electrode CE12, and the maximum potential difference between the third-first capacitor electrode CE31 and the third-second capacitor electrode CE32. That is, a first capacitor C1 and a third capacitor C3 with small internal pressures can be formed by separating the two capacitor electrodes horizontally, but a second capacitor C2 with large internal pressures can be formed by separating the two capacitor electrodes vertically. Therefore, short circuits between the two capacitor electrodes in the second capacitor C2 with its large internal pressure can be prevented.

[0118] Figures 7A to 7G This is a plan view illustrating the stacking process of circuit layers according to an embodiment of the present disclosure.

[0119] Reference Figure 6 and Figure 7A The semiconductor substrate SS can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SS can be a substrate doped with a first type of impurity. The semiconductor substrate SS can include source regions SR1 to SR4 and drain regions DDR1 to DDR4. Each of the source regions SR1 to SR4 and the drain regions DDR1 to DDR4 can be a region doped with a second type of impurity. The second type of impurity can be different from the first type of impurity described above. For example, when the first type of impurity is a P-type impurity, the second type of impurity can be an N-type impurity. Optionally, when the first type of impurity is an N-type impurity, the second type of impurity can be a P-type impurity. When viewed from above the plane, the source regions SR1 to SR4 and the drain regions DDR1 to DDR4 can be spaced apart from each other.

[0120] A gate insulating pattern (GIL) and gate electrodes GT1 to GT4 can be formed on a semiconductor substrate (SS). The gate insulating pattern (GIL) may include silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and titanium dioxide (TiO2). The gate electrodes GT1 to GT4 may include polycrystalline silicon, titanium nitride (TiN), tungsten (W), molybdenum (Mo), and aluminum (Al). The gate insulating pattern (GIL) may have a shape corresponding to the shape of the gate electrodes GT1 to GT4.

[0121] When viewed from above the plane, gate electrodes GT1 to GT4 may be partially stacked with the corresponding source regions SR1 to SR4 and the corresponding drain regions DDR1 to DDR4, respectively. However, this disclosure is not limited thereto, and when viewed from above the plane, gate electrodes GT1 to GT4 may not be stacked with the corresponding source regions SR1 to SR4 and the corresponding drain regions DDR1 to DDR4, respectively.

[0122] Reference Figure 6 , Figure 7A and Figure 7B An insulating layer IL1 covers the semiconductor substrate SS and gate electrodes GT1 to GT4. A first conductive pattern layer CPL1 is formed on the insulating layer IL1. The first conductive pattern layer CPL1 includes a second-first sub-electrode C2_C21 and a first data connection electrode D_CNE1. When viewed from above the plane, the second-first sub-electrode C2_C21 is superimposed on the gate electrode GT1 of the first transistor T1. Therefore, a second capacitor C2 can be formed between the second-first sub-electrode C2_C21 and the gate electrode GT1 of the first transistor T1.

[0123] The second-first sub-electrode C2_C21 is configured as multiple parts, for example, Figure 7B Three second-first sub-electrodes are shown. Multiple second-first sub-electrodes C2_C21 are spaced apart from each other at a specific interval. The first data connection electrode D_CNE1 is connected to the drain region DDR2 of the second transistor T2.

[0124] The first conductive pattern layer CPL1 may further include an i-th write scan line GWLi, an i-th reset scan line GRLi, a horizontal power line H_PL1, and a first horizontal voltage line H_VL1. The i-th write scan line GWLi can be connected to the gate electrode GT2 of the second transistor T2, and the i-th reset scan line GRLi can be connected to the gate electrode GT4 of the fourth transistor T4. The horizontal power line H_PL1 can receive a first drive voltage ELVDD and can form... Figure 5A The first power line PL1 is shown. The first horizontal voltage line H_VL1 can receive the initialization voltage VINT and can form... Figure 5A The first voltage line VL1 is shown in the figure.

[0125] The first conductive pattern layer CPL1 may further include a first connection pattern CNE1 and a second connection pattern CNE2. The first connection pattern CNE1 can connect the source region SR3 (or the second electrode) of the third transistor T3 and the drain region DDR1 (or the first electrode) of the first transistor T1, and the second connection pattern CNE2 can connect the source region SR2 (or the second electrode) of the second transistor T2 and the gate electrode GT1 of the first transistor T1.

[0126] Reference Figure 6 , Figure 7B and Figure 7C A second conductive pattern layer CPL2 is formed on the insulating layer IL3. The second conductive pattern layer CPL2 includes a second sub-electrode C2_C22 and a third data connection electrode D_CNE3. When viewed from above the plane, the second sub-electrode C2_C22 is superimposed on the gate electrode GT1 and the second sub-electrode C2_C21 of the first transistor T1. Therefore, a second capacitor C2 can be formed between the gate electrode GT1 and the second sub-electrode C2_C21 of the first transistor T1.

[0127] The third data connection electrode D_CNE3 is connected to the second data connection electrode D_CNE2 through a contact hole that penetrates the insulating layer IL3.

[0128] The second conductive pattern layer CPL2 also includes an i-th emitter control line ELi and a second horizontal voltage line H_VL2. The i-th emitter control line ELi can be connected to the gate electrode GT3 of the third transistor T3, and the second horizontal voltage line H_VL2 can be connected to the first horizontal voltage line H_VL1 and can receive the initialization voltage VINT. The second horizontal voltage line H_VL2 can form Figure 5A The first voltage line VL1 is shown in the figure.

[0129] Reference Figure 6 , Figure 7C and Figure 7D A third conductive pattern layer CPL3 is formed on the insulating layer IL4. The third conductive pattern layer CPL3 includes a first-first sub-electrode C1_C11, a first-third sub-electrode C1_C21, a third-first sub-electrode C3_C11, a third-third sub-electrode C3_C21, and a fourth data connection electrode D_CNE4. The first-first sub-electrode C1_C11 may be included in the first-first capacitor electrode CE11 (refer to...). Figure 5A The components in the first-third sub-electrode C1_C21 may be included in the first-second capacitor electrode CE12 (refer to...). Figure 5AThe components in the (). The first-first sub-electrode C1_C11 and the first-third sub-electrode C1_C21 can be spaced apart from each other in the horizontal direction (e.g., the first direction DR1 or the second direction DR2). Therefore, the first capacitor C1 can be formed between the first-first sub-electrode C1_C11 and the first-third sub-electrode C1_C21. ​​The first-first capacitor electrode CE11 and the first-second capacitor electrode CE12 can be disposed on the same layer (i.e., insulating layer 4 IL4).

[0130] When viewed from above the plane, the first sub-electrode C1_C11 can be partially superimposed on the second sub-electrode C2_C22. Therefore, the second capacitor C2 can be formed between the first sub-electrode C1_C11 and the second sub-electrode C2_C22.

[0131] The third-first sub-electrode C3_C11 may be included in the third-first capacitor electrode CE31 (refer to...). Figure 5A The third sub-electrode C3_C21 in the component of the third-second capacitor electrode CE32 (see reference) can be a component included in the third-second capacitor electrode CE32. Figure 5A The components in the () are as follows. The third-first sub-electrode C3_C11 and the third-third sub-electrode C3_C21 can be spaced apart from each other in the horizontal direction (e.g., the first direction DR1 or the second direction DR2). Therefore, the third capacitor C3 can be formed between the third-first sub-electrode C3_C11 and the third-third sub-electrode C3_C21. ​​The third-first capacitor electrode CE31 and the third-second capacitor electrode CE32 can be disposed on the same layer (i.e., insulating layer 4 IL4).

[0132] The fourth data connection electrode D_CNE4 is connected to the third data connection electrode D_CNE3 through a contact hole that penetrates the insulating layer IL4.

[0133] Reference Figure 6 , Figure 7D and Figure 7E A fourth conductive pattern layer CPL4 is formed on the insulating layer IL5. The fourth conductive pattern layer CPL4 includes first-second sub-electrodes C1_C12, first-fourth sub-electrodes C1_C22, third-second sub-electrodes C3_C12, third-fourth sub-electrodes C3_C22, and the j-th data line DLj. The first-second sub-electrodes C1_C12 may be included in the first-first capacitor electrode CE11 (refer to...). Figure 5A The components in the first-fourth sub-electrodes C1_C22 may be included in the first-second capacitor electrode CE12 (refer to...). Figure 5AThe components in the () are as follows. The first-second sub-electrode C1_C12 and the first-fourth sub-electrode C1_C22 can be spaced apart from each other in the horizontal direction (e.g., the first direction DR1 or the second direction DR2). Therefore, the first capacitor C1 can be formed between the first-second sub-electrode C1_C12 and the first-fourth sub-electrode C1_C22. The first-first capacitor electrode CE11 and the first-second capacitor electrode CE12 can be disposed on the same layer (i.e., insulating layer IL5).

[0134] The third-second sub-electrode C3_C12 may be included in the third-first capacitor electrode CE31 (refer to...). Figure 5A The components in the third-fourth sub-electrode C3_C22 may be included in the third-second capacitor electrode CE32 (refer to...). Figure 5A The components in the (). The third-second sub-electrode C3_C12 and the third-fourth sub-electrode C3_C22 can be spaced apart from each other in the horizontal direction (e.g., the first direction DR1 or the second direction DR2). Therefore, the third capacitor C3 can be formed between the third-second sub-electrode C3_C12 and the third-fourth sub-electrode C3_C22. The third-first capacitor electrode CE31 and the third-second capacitor electrode CE32 can be disposed on the same layer (i.e., insulating layer IL5).

[0135] The j-th data line DLj is connected to the fourth data connection electrode D_CNE4 through a contact hole that penetrates the insulating layer IL5.

[0136] Reference Figure 6 , Figure 7E and Figure 7F A fifth conductive pattern layer CPL5 is formed on the insulating layer IL6. The fifth conductive pattern layer CPL5 includes first-fifth sub-electrodes C1_C13, first-sixth sub-electrodes C1_C23, third-fifth sub-electrodes C3_C13, and third-sixth sub-electrodes C3_C23. The first-fifth sub-electrodes C1_C13 may be included in the first-first capacitor electrode CE11 (refer to...). Figure 5A The components in the first-sixth sub-electrodes C1_C23 may be included in the first-second capacitor electrode CE12 (refer to...). Figure 5A The components in the () are as follows. The first-fifth sub-electrode C1_C13 and the first-sixth sub-electrode C1_C23 can be spaced apart from each other in the horizontal direction (e.g., the first direction DR1 or the second direction DR2). Therefore, the first capacitor C1 can be formed between the first-fifth sub-electrode C1_C13 and the first-sixth sub-electrode C1_C23. The first-first capacitor electrode CE11 and the first-second capacitor electrode CE12 can be disposed on the same layer (i.e., insulating layer IL6).

[0137] The third-fifth sub-electrodes C3_C13 may be included in the third-first capacitor electrode CE31 (refer to...). Figure 5A The components in the third-sixth sub-electrode C3_C23 may be included in the third-second capacitor electrode CE32 (refer to...). Figure 5A The components in the ( ). The third-fifth sub-electrode C3_C13 and the third-sixth sub-electrode C3_C23 can be spaced apart from each other in the horizontal direction (e.g., the first direction DR1 or the second direction DR2). Therefore, the third capacitor C3 can be formed between the third-fifth sub-electrode C3_C13 and the third-sixth sub-electrode C3_C23. The third-first capacitor electrode CE31 and the third-second capacitor electrode CE32 can be disposed on the same layer (i.e., insulating layer IL6).

[0138] Reference Figure 6 , Figure 7F and Figure 7G A sixth conductive pattern layer CPL6 is formed on the insulating layer IL7. The sixth conductive pattern layer CPL6 includes an anode AE ​​and a grid of electric field lines V_PL1. The anode AE ​​can be partially superimposed on the first to fifth sub-electrodes C1_C13 in the vertical direction (e.g., the third direction DR3). Therefore, a second capacitor C2 can be formed between the first to fifth sub-electrodes C1_C13 and the anode AE.

[0139] The grid power line V_PL1 can be included in the first drive voltage ELVDD (refer to...) Figure 5A The first power line PL1 (refer to) Figure 5A Components in ).

[0140] Figure 8 This is a cross-sectional view showing a portion of a display device according to an embodiment of the present disclosure. Figure 8 Among the components shown, with Figure 6 Components shown will be assigned the same reference numerals and their specific descriptions will be omitted.

[0141] Reference Figure 8 The circuit layer CLa may include a semiconductor substrate SS, at least one insulating layer IL1 to IL6, and at least one conductive pattern. Although six insulating layers IL1 to IL6 are shown as an example in this embodiment, the present disclosure is not limited thereto.

[0142] An insulating layer IL6 covering the first-second sub-electrodes C1_C12 and the first-fourth sub-electrodes C1_C22 is disposed on the insulating layer IL5. The insulating layer IL6 can be referred to as the anode insulating layer.

[0143] The anode AE ​​and the grid power line V_PL1 are disposed on the insulating layer IL6. The anode AE ​​can be partially stacked with the first-second sub-electrodes C1_C12 in the vertical direction (e.g., third-direction DR3). Therefore, the second capacitor C2 can be formed between the first-second sub-electrodes C1_C12 and the anode AE. The first-second sub-electrodes C1_C12 can be electrically connected to the second-first capacitor electrode CE21 (see reference). Figure 5A And, and can have an integral shape with the second-first capacitor electrode CE21, that is, one physical component can contain or act as two components. The anode AE ​​can be electrically connected to the second-second capacitor electrode CE22 (see reference). Figure 5A And it can have an integral shape with the second-second capacitor electrode CE22, that is, one physical component can contain or act as two components.

[0144] The grid power line V_PL1 can be included in the first drive voltage ELVDD (refer to...) Figure 5A The first power line PL1 (refer to) Figure 5A Components in ).

[0145] A pixel-defining layer (PDL) covering the anode AE ​​and the grid power lines V_PL1 is disposed on the insulating layer IL6. A pixel opening (PDL_OP) exposing the anode AE ​​is disposed within the pixel-defining layer (PDL). An emission layer (EL) is disposed on the pixel-defining layer (PDL) and the anode AE ​​exposed through the pixel opening (PDL_OP). In this embodiment, the emission layer (EL) can be commonly disposed in multiple pixels (PX). In this case, the common emission layer (EL) can generate white light or blue light. A cathode (CE) is disposed on the emission layer (EL). The cathode (CE) is commonly disposed in multiple pixels (PX). The cathode (CE) can be sealed by an encapsulation layer (TFE).

[0146] Figure 9 This is a cross-sectional view showing a portion of a display device according to an embodiment of the present disclosure. Figure 9 Among the components shown, with Figure 6 Components shown will be assigned the same reference numerals and their specific descriptions will be omitted.

[0147] Reference Figure 9 The circuit layer CLb may include a semiconductor substrate SS, at least one insulating layer IL1 to IL7, and at least one conductive pattern. Although seven insulating layers IL1 to IL7 are shown as an example in this embodiment, the present disclosure is not limited thereto.

[0148] An insulating layer IL2 covering the second-first sub-electrode C2_C21 and the first data connection electrode D_CNE1 is disposed on an insulating layer IL1.

[0149] The second sub-electrode C2_C22 and the second data connection electrode D_CNE2 are disposed on the second insulating layer IL2. Contact holes exposing the second sub-electrode C2_C21 can be disposed in the second insulating layer IL2. The second sub-electrode C2_C22 can be connected to the second sub-electrode C2_C21 through the contact holes in the second insulating layer IL2.

[0150] An insulating layer IL3 covering the second sub-electrode C2_C22 and the second data connection electrode D_CNE2 is disposed on the insulating layer IL2. The first sub-electrode C1_C11, the first third sub-electrode C1_C21, and the third data connection electrode D_CNE3 are disposed on the insulating layer IL3. The insulating layer IL3 may be referred to as the first insulating layer.

[0151] The first sub-electrode C1_C11 may be included in the first capacitor electrode CE11 (refer to...). Figure 5A The components in the first-third sub-electrode C1_C21 may be included in the first-second capacitor electrode CE12 (refer to...). Figure 5A The components in the first-first sub-electrode C1_C11 and the first-third sub-electrode C1_C21 can be spaced apart from each other in the horizontal direction (e.g., the first direction DR1 or the second direction DR2). Therefore, the first capacitor C1 can be formed between the first-first sub-electrode C1_C11 and the first-third sub-electrode C1_C21.

[0152] When viewed from above the plane, the first sub-electrode C1_C11 may partially overlap with the second sub-electrode C2_C22, and may be spaced apart from the second sub-electrode C2_C22 in a vertical direction (e.g., third direction DR3). The first sub-electrode C1_C11 may face the second sub-electrode C2_C22 and may form a second capacitor C2. The first sub-electrode C1_C11 may be electrically connected to the second capacitor electrode CE21 (see reference). Figure 5A And, and can have an integral shape with the second-first capacitor electrode CE21, that is, one physical component can contain or act as two components. The second-second sub-electrode C2_C22 can be a component included in the second-second capacitor electrode CE22.

[0153] An insulating layer 4 IL4 covering the first-first sub-electrode C1_C11, the first-third sub-electrode C1_C21, and the third data connection electrode D_CNE3 is disposed on the insulating layer 3 IL3. The insulating layer 4 IL4 can be referred to as the second insulating layer.

[0154] The first and second sub-electrodes C1_C12, the first and fourth sub-electrodes C1_C22, and the fourth data connection electrode D_CNE4 are disposed on the insulating layer IL4. The first and second sub-electrodes C1_C12 may be included in the first capacitor electrode CE11 (refer to...). Figure 5A The components in the first-fourth sub-electrodes C1_C22 may be included in the first-second capacitor electrode CE12 (refer to...). Figure 5A The components in the first-second sub-electrode C1_C12 and the first-fourth sub-electrode C1_C22 can be spaced apart from each other in the horizontal direction (e.g., the first direction DR1 or the second direction DR2). Therefore, the first capacitor C1 can be formed between the first-second sub-electrode C1_C12 and the first-fourth sub-electrode C1_C22.

[0155] Insulating layer IL5 covers the first-second sub-electrodes C1_C12 and the first-fourth sub-electrodes C1_C22, and the fourth data connection electrode D_CNE4 is disposed on insulating layer IL4. Insulating layer IL5 can be referred to as the third data insulating layer.

[0156] The first to fifth sub-electrodes C1_C13, the first to sixth sub-electrodes C1_C23, and the j-th data line DLj are disposed on the insulating layer IL5. The first to fifth sub-electrodes C1_C13 may be included in the first capacitor electrode CE11 (refer to...). Figure 5A The components in the first-sixth sub-electrodes C1_C23 may be included in the first-second capacitor electrode CE12 (refer to...). Figure 5A The components in the (e.g., first-fifth sub-electrodes C1_C13 and first-sixth sub-electrodes C1_C23) can be spaced apart from each other in the horizontal direction (e.g., first direction DR1 or second direction DR2). Therefore, the first capacitor C1 can be formed between the first-fifth sub-electrodes C1_C13 and the first-sixth sub-electrodes C1_C23. The first-fifth sub-electrodes C1_C13 can be stacked with the first-second sub-electrodes C1_C12 in the vertical direction (e.g., third direction DR3), and the first-sixth sub-electrodes C1_C23 can be stacked with the first-fourth sub-electrodes C1_C22 in the vertical direction (e.g., third direction DR3).

[0157] An insulating layer IL6 covering the first to fifth sub-electrodes C1_C13 and the first to sixth sub-electrodes C1_C23 is disposed on the insulating layer IL5. The insulating layer IL6 can be referred to as the fourth data insulating layer.

[0158] The first-seventh sub-electrode C1_C14 and the first-eighth sub-electrode C1_C24 are disposed on the insulating layer IL6. The first-seventh sub-electrode C1_C14 may be included in the first capacitor electrode CE11 (refer to...). Figure 5A The components in the first-eighth sub-electrodes C1_C24 may be included in the first-second capacitor electrode CE12 (refer to...). Figure 5A The components in the (e.g., the first-seventh sub-electrode C1_C14 and the first-eighth sub-electrode C1_C24) can be spaced apart from each other in the horizontal direction (e.g., the first direction DR1 or the second direction DR2). Therefore, the first capacitor C1 can be formed between the first-seventh sub-electrode C1_C14 and the first-eighth sub-electrode C1_C24. The first-seventh sub-electrode C1_C14 can be stacked with the first-fifth sub-electrode C1_C13 in the vertical direction (e.g., the third direction DR3), and the first-eighth sub-electrode C1_C24 can be stacked with the first-sixth sub-electrode C1_C23 in the vertical direction (e.g., the third direction DR3).

[0159] An insulating layer 7 IL7 covering the first to seventh sub-electrodes C1_C14 and the first to eighth sub-electrodes C1_C24 is disposed on an insulating layer 6 IL6. The insulating layer 7 IL7 can be referred to as the anode insulating layer.

[0160] The anode AE ​​and the grid power line V_PL1 are disposed on the insulating layer IL7. The anode AE ​​can be partially superimposed on the first-seventh sub-electrode C1_C14 in the vertical direction (e.g., third-direction DR3). Therefore, the second capacitor C2 can be formed between the first-seventh sub-electrode C1_C14 and the anode AE. The first-seventh sub-electrode C1_C14 can be electrically connected to the second-first capacitor electrode CE21 (see reference). Figure 5A And, and can have an integral shape with the second-first capacitor electrode CE21, that is, one physical component can contain or act as two components. The anode AE ​​can be electrically connected to the second-second capacitor electrode CE22 (see reference). Figure 5A And it can have an integral shape with the second-second capacitor electrode CE22, that is, one physical component can contain or act as two components.

[0161] Figure 10 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0162] Reference Figure 10 The electronic device 601 outputs various information through the display module 640 in the operating system. When the processor 610 executes the application stored in the memory 620, the display module 640 provides application information to the user through the display panel 641.

[0163] The processor 610 receives external input via the input module 630 or the sensor module 661 and executes the application corresponding to the external input. For example, when a user selects the camera icon displayed on the display panel 641, the processor 610 receives user input via the input sensor 661-2 and activates the camera module 671. The processor 610 transmits the image data corresponding to the captured image obtained by the camera module 671 to the display module 640. The display module 640 can display the image corresponding to the captured image via the display panel 641.

[0164] In another example, when personal information authentication is performed in display module 640, fingerprint sensor 661-1 obtains the input fingerprint information as input data. Processor 610 compares the input data obtained by fingerprint sensor 661-1 with the authentication data stored in memory 620 and executes the application based on the comparison result. Display module 640 can display the information executed according to the application logic via display panel 641.

[0165] In another example, when a user selects a music stream icon displayed in display module 640, processor 610 receives user input via input sensor 661-2 and activates the music stream application stored in memory 620. When a music playback command is input to the music stream application, processor 610 activates sound output module 663 and provides the user with sound information corresponding to the music playback command.

[0166] The operation of electronic device 601 has been briefly described above. The construction of electronic device 601 will be described in detail below. Some of the components of electronic device 601, which will be described later, can be implemented as a single component, and a single component can be divided into two or more components.

[0167] Reference Figure 10 Electronic device 601 can communicate with external electronic device 602 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to embodiments, electronic device 601 may include a processor 610, a memory 620, an input module 630, a display module 640, a power module 650, an internal module 660, and an external module 670. According to embodiments, electronic device 601 may not include at least one of the above-described components, or may include one or more other components. According to embodiments, some of the above-described components (e.g., sensor module 661, antenna module 662, or voice output module 663) may be integrated into any other component (e.g., display module 640).

[0168] The processor 610 can execute software to control at least one component (e.g., a hardware or software component) of the electronic device 601 connected to the processor 610, and can perform various data processing or operations. According to an embodiment, as at least part of the data processing or operation, the processor 610 can store commands or data received from any other component (e.g., input module 630, sensor module 661, or communication module 673) in volatile memory 621, can process commands or data stored in volatile memory 621, and can store the processed data in non-volatile memory 622.

[0169] Processor 610 may include a main processor 611 and an auxiliary processor 612. Main processor 611 may include one or more of a central processing unit (CPU) 611-1 and an application processor (AP). Main processor 611 may also include one or more of a graphics processing unit (GPU) 611-2, a communication processor (CP), and an image signal processor (ISP). Main processor 611 may also include a neural processing unit (NPU) 611-3. Neural processing unit 611-3 may be a processor dedicated to processing artificial intelligence models and may create artificial intelligence models through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural networks may include one or more of deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), restricted Boltzmann machines (RBM), deep belief networks (DBN), bidirectional recurrent deep neural networks (BRDNN), and deep Q-networks, but this disclosure is not limited thereto. Additionally or optionally, in addition to hardware architecture, the artificial intelligence model may also include software architecture. At least two of the aforementioned processing units and processors can be implemented as a whole using a single component (e.g., a single chip), or each of the aforementioned processing units and processors can be implemented using independent components (e.g., multiple chips).

[0170] The auxiliary processor 612 may include a drive controller 612-1. The drive controller 612-1 may include interface conversion circuitry and timing control circuitry. The drive controller 612-1 receives image signals from the main processor 611 and outputs image data obtained by converting the data format of the image signals to suit the specifications of the interface with the display module 640. The drive controller 612-1 can output various control signals required to drive the display module 640. The construction of the drive controller 612-1 is basically similar to... Figure 4 The construction of the control circuit 100 shown is omitted here to avoid redundancy.

[0171] The auxiliary processor 612 may also include a data conversion circuit 612-2, a gamma correction circuit 612-3, a rendering circuit 612-4, etc. The data conversion circuit 612-2 can receive image data from the drive controller 612-1; the data conversion circuit 612-2 can compensate the image data to display the image at the desired brightness according to the characteristics of the electronic device 601 or user settings, or it can convert the image data to reduce power consumption or compensate for image retention. The gamma correction circuit 612-3 can convert the image data or gamma reference voltage so that the image displayed on the electronic device 601 has the desired gamma characteristics. The rendering circuit 612-4 can receive image data from the drive controller 612-1 and can render the image data taking into account the pixel arrangement of the display panel 641 applied to the electronic device 601. At least one of the data conversion circuit 612-2, the gamma correction circuit 612-3, and the rendering circuit 612-4 can be integrated into any other component (e.g., the main processor 611 or the drive controller 612-1). At least one of the data conversion circuit 612-2, the gamma correction circuit 612-3, and the rendering circuit 612-4 can be integrated into the data driver 643, which will be described later.

[0172] The memory 620 may store various data used by at least one component of the electronic device 601 (e.g., processor 610 or sensor module 661) and input or output data of commands associated therewith. The memory 620 may include at least one of volatile memory 621 and non-volatile memory 622.

[0173] The input module 630 can receive commands or data from outside the electronic device 601 (e.g., from a user or external electronic device 602) that will be used by components of the electronic device 601 (e.g., processor 610, sensor module 661, or voice output module 663).

[0174] Input module 630 may include a first input module 631 for inputting commands or data from a user and a second input module 632 for inputting commands or data from an external electronic device 602. The first input module 631 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 632 may support a specified protocol enabling wired or wireless connection to the external electronic device 602. According to embodiments, the second input module 632 may include an High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, or an audio interface. The second input module 632 may include a connector (e.g., an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector)) capable of physically connecting to the external electronic device 602.

[0175] Display module 640 visually provides information to the user. Display module 640 may include a display panel 641, a gate driver 642, and a data driver 643. Display module 640 may also include a window, a base, and a bracket for protecting the display panel 641. Display module 640 may also include a transmitter driver, a voltage generator, etc. The voltage generator can output various types of voltages required to drive the display panel 641 (e.g., a first drive voltage ELVDD (see reference)). Figure 4 ) and the second driving voltage ELVSS (refer to Figure 4 The display panel 641, gate driver 642, data driver 643, and voltage generator are constructed in a manner that is basically similar to that of the display panel 641, gate driver 642, data driver 643, and voltage generator. Figure 4 The construction of the display panel DP, scan driver circuit 310, data driver circuit 200 and voltage generator 400 shown will be omitted in detail to avoid redundancy.

[0176] Power module 650 supplies power to components of electronic device 601. Power module 650 may include a battery charged with a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power module 650 may include a power management integrated circuit (PMIC). The PMIC supplies optimized power for each of the modules described above and later. Power module 650 may include a wireless power transmitting / receiving component electrically connected to the battery. The wireless power transmitting / receiving component may include multiple antenna radiators in the form of coils.

[0177] The electronic device 601 may also include an internal module 660 and an external module 670. The internal module 660 may include a sensor module 661, an antenna module 662, and a sound output module 663. The external module 670 may include a camera module 671, an optical module 672, and a communication module 673.

[0178] Sensor module 661 can sense input through the user's body or through a pen in the first input module 631, and can generate an electrical signal or data value corresponding to the input. Sensor module 661 may include at least one of fingerprint sensor 661-1, input sensor 661-2, and digitizer 661-3.

[0179] The fingerprint sensor 661-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 661-1 may include one of an optical fingerprint sensor and a capacitive fingerprint sensor.

[0180] Input sensor 661-2 can generate data values ​​corresponding to the coordinate information of user's body input or pen input. Input sensor 661-2 generates capacitance changes caused by input as data values. Input sensor 661-2 can sense input from a passive pen or exchange data with an active pen.

[0181] Input sensor 661-2 can measure biometric signals such as blood pressure, water content, or body fat. For example, when a user touches a part of their body to the sensor layer or sensing panel and does not move it for a given period of time, input sensor 661-2 can detect biometric signals based on changes in the electric field caused by the body part and can output the information desired by the user to display module 640.

[0182] The digitizer 661-3 can generate data values ​​corresponding to the coordinate information input by the pen. The digitizer 661-3 generates electromagnetic changes as data values ​​based on the input. The digitizer 661-3 can sense input from a passive pen or exchange data with an active pen.

[0183] At least one of the fingerprint sensor 661-1, input sensor 661-2, and digitizer 661-3 can be implemented using a sensor layer formed on the display panel 641 by a continuous process. The fingerprint sensor 661-1, input sensor 661-2, and digitizer 661-3 can be disposed above / on the display panel 641, and at least one of the fingerprint sensor 661-1, input sensor 661-2, and digitizer 661-3 (e.g., digitizer 661-3) can be disposed below / under the display panel 641.

[0184] At least two of the fingerprint sensor 661-1, input sensor 661-2, and digitizer 661-3 can be integrally formed with a sensing panel using the same process. When they are integrally formed with a sensing panel, the sensing panel can be disposed between the display panel 641 and a window disposed above / on the display panel 641. According to an embodiment, the sensing panel can be disposed on the window, and the position of the sensing panel is not particularly limited.

[0185] At least one of the fingerprint sensor 661-1, the input sensor 661-2, and the digitizer 661-3 can be embedded in the display panel 641. That is, at least one of the fingerprint sensor 661-1, the input sensor 661-2, and the digitizer 661-3 can be formed simultaneously by a process for forming elements (e.g., light-emitting elements and transistors) included in the display panel 641.

[0186] Furthermore, sensor module 661 can generate electrical signals or data values ​​corresponding to the internal or external states of electronic device 601. Sensor module 661 may also include, for example, gesture sensors, gyroscope sensors, atmospheric pressure sensors, magnetic sensors, accelerometers, grip sensors, proximity sensors, color sensors, infrared (IR) sensors, biometric sensors, temperature sensors, humidity sensors, or illuminance sensors.

[0187] Antenna module 662 may include one or more antennas to transmit or receive signals or power from an external source. According to embodiments, antenna module 662 may transmit or receive signals from external electronic device 602 via an antenna suitable for a communication method. The antenna pattern of antenna module 662 may be integrated with a component of display module 640 (e.g., display panel 641) or input sensor 661-2.

[0188] The sound output module 663, as a means for outputting sound signals to the outside of the electronic device 601, may include, for example, a speaker for general purposes such as multimedia playback or recording playback, and a receiver specifically for receiving calls. According to embodiments, the receiver and speaker may be integrated or separate. The sound output pattern of the sound output module 663 may be integrated with the display module 640.

[0189] Camera module 671 can capture still images and moving images. According to embodiments, camera module 671 may include one or more lenses, image sensors, or image signal processors. Camera module 671 may also include an infrared camera capable of measuring the presence or absence of a user, the user's position, and the user's line of sight.

[0190] The optical module 672 can provide light. The optical module 672 may include a light-emitting diode or a xenon lamp. The optical module 672 can operate in conjunction with the camera module 671, or it can operate independently.

[0191] Communication module 673 can establish a wired or wireless communication channel between electronic device 601 and external electronic device 602, and can support communication execution through the established communication channel. Communication module 673 may include one or all of the following: a wireless communication module (such as a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module) and a wired communication module (such as a local area network (LAN) communication module or a power line communication module). Communication module 673 can communicate with external electronic device 602 through short-range communication networks (such as Bluetooth, Wi-Fi Direct, or Infrared Data Association (IrDA)) or long-range communication networks (such as cellular networks, the Internet, or computer networks (e.g., LAN or WAN)). The various types of communication modules described above can be implemented using a single chip or separate chips.

[0192] The input module 630, sensor module 661, camera module 671, etc., can be used in conjunction with the processor 610 to control the operation of the display module 640.

[0193] The processor 610 outputs commands or data to the display module 640, sound output module 663, camera module 671, or optical module 672 based on input data received from the input module 630. For example, the processor 610 can generate image data corresponding to input data applied via a mouse or active pen, and can output the image data to the display module 640; alternatively, the processor 610 can generate command data corresponding to the input data, and can output the command data to the camera module 671 or optical module 672. When no input data is received from the input module 630 during a given time period, the processor 610 can switch the operating mode of the electronic device 601 to a low-power mode or a sleep mode, thereby reducing the power consumption of the electronic device 601.

[0194] Processor 610 outputs commands or data to display module 640, sound output module 663, camera module 671, or optical module 672 based on sensing data received from sensor module 661. For example, processor 610 can compare authentication data obtained by fingerprint sensor 661-1 with authentication data stored in memory 620, and then execute an application based on the comparison result. Processor 610 can execute commands based on sensing data sensed by input sensor 661-2 or digitizer 661-3, or it can output image data corresponding to the sensing data to display module 640. When sensor module 661 includes a temperature sensor, processor 610 can receive temperature data associated with the measured temperature from sensor module 661, and can also perform brightness correction on image data based on the temperature data.

[0195] Processor 610 can receive measurement data from camera module 671 regarding the presence or absence of a user, the user's position, and the user's gaze. Processor 610 can also perform brightness correction on image data based on the measurement data. For example, processor 610, which determines the presence or absence of a user based on input from camera module 671, can output image data to display module 640 whose brightness has been corrected by data conversion circuit 612-2 or gamma correction circuit 612-3.

[0196] Some of the components described above can be connected to each other via communication schemes between peripheral devices (e.g., buses, general purpose input / output (GPIO), serial peripheral interfaces (SPI), mobile industrial processor interfaces (MIPI), or hyperpath interconnect (UPI) links) and can exchange signals (e.g., commands or data). Processor 610 can communicate with display module 640 via a given interface. For example, one of the communication methods described above can be used, and this disclosure is not limited thereto.

[0197] The electronic device 601 according to various embodiments of the present disclosure can be implemented as various types of devices. The electronic device 601 may include at least one of, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, and a home appliance. The electronic device 601 according to embodiments of the present disclosure is not limited to the devices described above.

[0198] Figure 11 This is an exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0199] exist Figure 11 In the diagram, augmented reality (AR) glasses are shown as an example of a wearable device. The electronic device ELD may include glasses GR and a frame FR mounted on the glasses GR. The frame FR may accommodate a reference... Figure 10 The described display panel 641, or one that can accommodate references Figure 10 Other modules described. The light guide LG that guides the image generated from the display panel 641 can be mounted on the frame FR.

[0200] The glasses GR can be worn on the user's head. Since augmented reality (AR) glasses are described as an example of a wearable device in this embodiment, the structure with the frame FR mounted on it is described as glasses. The structure can vary depending on the type of wearable device. Furthermore, the structure can be omitted depending on the type of electronic device ELD.

[0201] According to this disclosure, a first capacitor and a third capacitor with a small internal pressure applied thereto can be formed by separating the two capacitor electrodes in a horizontal direction, but a second capacitor with a large internal pressure applied thereto can be formed by separating the two capacitor electrodes in a vertical direction. Therefore, short circuits between the two capacitor electrodes in the second capacitor with a large internal pressure applied thereto can be prevented.

[0202] Although this disclosure has been described with reference to its embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the disclosure as set forth in the claims.

Claims

1. A display device, the display device comprising: Semiconductor substrate; as well as Multiple pixels are disposed on the semiconductor substrate. Each of the plurality of pixels includes: a light-emitting element; a first transistor electrically connected to a first power line and the light-emitting element, and configured to operate according to the potential of a control node; a second transistor electrically connected to a data line and the control node; a first capacitor electrically connected to a first electrode of the first transistor and the control node; and a second capacitor electrically connected to the control node and a second electrode of the first transistor. The first capacitor includes: a first capacitor electrode; and a first and second capacitor electrode, spaced apart from the first capacitor electrode in the horizontal direction. The second capacitor includes: a second-first capacitor electrode; and a second-second capacitor electrode, which is spaced apart from the second-first capacitor electrode in the vertical direction and positioned to overlap with the second-first capacitor electrode.

2. The display device according to claim 1, wherein The first-first capacitor electrode and the first-second capacitor electrode are disposed on the same insulating layer, and The second-first capacitor electrode and the second-second capacitor electrode are disposed on different insulating layers.

3. The display device according to claim 1, wherein The second-first capacitor electrode is electrically connected to the first-first capacitor electrode, and The second capacitor electrode is electrically connected to the anode of the light-emitting element.

4. The display device according to claim 1, wherein Each of the plurality of pixels also includes a third capacitor connected to the control node and the reference voltage line.

5. The display device of claim 4, wherein, The third capacitor includes: The third-first capacitor electrode is electrically connected to the first-first capacitor electrode; and The third-second capacitor electrode is spaced apart from the third-first capacitor electrode in the horizontal direction and is connected to the reference voltage line.

6. The display device of claim 5, wherein, The third-first capacitor electrode and the third-second capacitor electrode are disposed on the same insulating layer.

7. The display device according to claim 1, wherein The first capacitor electrode includes: First sub-electrodes are disposed on the first insulating layer; and First and second sub-electrodes are disposed on a second insulating layer, the second insulating layer covering the first and second sub-electrodes, and the first and second sub-electrodes are positioned to overlap with the first and second sub-electrodes. The first and second capacitor electrodes include: First-third sub-electrodes, disposed on the first insulating layer, and spaced apart from the first-first sub-electrodes in the horizontal direction; and The first to fourth sub-electrodes are disposed on the second insulating layer and positioned to overlap with the first to third sub-electrodes, wherein the first to fourth sub-electrodes are spaced apart from the first to second sub-electrodes in the horizontal direction.

8. The display device of claim 7, wherein, The second-second capacitor electrode includes: A second-first sub-electrode is disposed on a third insulating layer, the third insulating layer covering the gate electrode of the first transistor, and the second-first sub-electrode is positioned to partially overlap with the gate electrode; and The second sub-electrode is disposed on the fourth insulating layer and positioned to overlap with the first sub-electrode.

9. The display device of claim 8, wherein, The second-first sub-electrode is electrically connected to the second-second sub-electrode via a capacitor connection electrode disposed on an intermediate gate insulating layer positioned between the third insulating layer and the fourth insulating layer.

10. The display device of claim 9, wherein, The first-first capacitor electrode further includes first-fifth sub-electrodes disposed on a fifth insulating layer, the fifth insulating layer covering the first-second sub-electrode and the first-fourth sub-electrode, the first-fifth sub-electrode being positioned overlapping the first-second sub-electrode, and... The first-second capacitor electrode further includes a first-sixth sub-electrode, which is disposed on the fifth insulating layer and positioned to overlap with the first-fourth sub-electrode. The first-sixth sub-electrode is spaced apart from the first-fifth sub-electrode in the horizontal direction.

11. The display device according to claim 10, wherein, The first capacitor electrode further includes a first-seventh sub-electrode disposed on a sixth insulating layer, the sixth insulating layer covering the first-fifth sub-electrode and the first-sixth sub-electrode, the first-seventh sub-electrode being positioned superimposed on the first-fifth sub-electrode, and The first-second capacitor electrode further includes a first-eighth sub-electrode, which is disposed on the sixth insulating layer and positioned to overlap with the first-sixth sub-electrode. The first-eighth sub-electrode is spaced apart from the first-seventh sub-electrode in the horizontal direction.

12. The display device according to claim 10, wherein, The light-emitting element includes an anode disposed on a seventh insulating layer, the seventh insulating layer covering the first to fifth sub-electrodes and the first to sixth sub-electrodes, and the anode and the first to fifth sub-electrodes are partially stacked to form the second capacitor.

13. The display device according to claim 7, wherein, The light-emitting element includes an anode disposed on a sixth insulating layer, the sixth insulating layer covering the first-second sub-electrode and the first-fourth sub-electrode, and the anode and the first-second sub-electrode are stacked to form the second capacitor.

14. The display device according to claim 13, wherein, The second-second capacitor electrode includes: A second-first sub-electrode is disposed on a third insulating layer, the third insulating layer covering the gate electrode of the first transistor, and the second-first sub-electrode is positioned to partially overlap with the gate electrode; and The second sub-electrode is disposed on the fourth insulating layer and positioned to overlap with the first sub-electrode.

15. The display device according to claim 14, wherein, The second-first sub-electrode is electrically connected to the second-second sub-electrode via a capacitor connection electrode disposed on an intermediate gate insulating layer positioned between the third insulating layer and the fourth insulating layer.

16. The display device according to claim 1, wherein, The maximum potential difference between the second-first capacitor electrode and the second-second capacitor electrode is greater than the maximum potential difference between the first-first capacitor electrode and the first-second capacitor electrode.

17. The display device according to claim 1, wherein, Each of the plurality of pixels also includes: The third transistor is electrically connected to the first power line and the first electrode of the first transistor; A fourth transistor, electrically connected to the initialization voltage line and the second electrode of the first transistor; and The third capacitor is electrically connected to the control node and the reference voltage line.

18. The display device according to claim 17, wherein, A first driving voltage is applied to the first electric field line. The initialization voltage is applied to the initialization voltage line. Wherein, a reference voltage is applied to the reference voltage line, and Wherein, the potential difference between the first driving voltage and the initialization voltage is greater than the potential difference between the first driving voltage and the reference voltage.

19. The display device according to claim 18, wherein, The light-emitting element includes a cathode, which is connected to a second electric field line, and A second driving voltage with a voltage level lower than the initial voltage is applied to the second power line.

20. An electronic device, the electronic device comprising: Display panel; A frame is constructed to accommodate the display panel; as well as The frame is mounted on the structure thereon. The display panel includes: a semiconductor substrate; and a plurality of pixels disposed on the semiconductor substrate. Each of the plurality of pixels includes: a light-emitting element; a first transistor electrically connected to a power line and the light-emitting element, and configured to operate according to the potential of a control node; a second transistor electrically connected to a data line and the control node; a first capacitor electrically connected to a first electrode of the first transistor and the control node; and a second capacitor electrically connected to the control node and a second electrode of the first transistor. The first capacitor includes: a first capacitor electrode; and a second capacitor electrode, disposed on the same layer as the first capacitor electrode. The second capacitor includes: a second-first capacitor electrode; and a second-second capacitor electrode disposed on a different layer than the layer on which the second-first capacitor electrode is disposed, wherein the second-second capacitor electrode is positioned to overlap with the second-first capacitor electrode.

Images