Display device and driving method thereof

Abstract

This disclosure relates to a display device and a driving method thereof. The display device includes: a display panel including sub-pixels; a scan driver configured to apply at least one scan signal to the display panel; a data driver configured to apply a data voltage to the display panel; an initialization voltage line connected to the sub-pixels; and a control transistor configured to control whether an initialization voltage is applied through the initialization voltage line.

Description

Cross-reference to related applications

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0189466, filed on December 18, 2024, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0002] This invention relates to a display device and its driving method. Background Technology

[0003] With the advancement of information technology, the market for display devices, which serve as connection media linking users with information, is growing. Consequently, the use of display devices such as light-emitting diode (LED) displays, quantum dot (QDD) displays, and liquid crystal displays (LCDs) is increasing.

[0004] The aforementioned display device includes: a display panel comprising a plurality of sub-pixels; a driver outputting a drive signal for driving the display panel; and a power supply generating power to be supplied to the display panel or the driver.

[0005] In such a display device, when a drive signal (e.g., a scan signal and a data signal) is provided to each sub-pixel disposed in the display panel, the selected sub-pixel can transmit light or emit light on its own, thus displaying an image. Summary of the Invention

[0006] This disclosure provides a display device that can block the coupling effect between an initialization voltage applied through the anode electrode of a light-emitting device and a scan signal applied adjacent to it to prevent voltage ripple and to stably apply the initialization voltage. Furthermore, this disclosure provides a display device that allows for stable application of the initialization voltage and thus prevents the occurrence of horizontal mura (image quality defects of horizontal lines), thereby improving display quality.

[0007] To achieve these objectives and other advantages and for the purposes of this disclosure, as embodied and broadly described herein, a display device includes: a display panel including sub-pixels; a scan driver configured to apply at least one scan signal to the display panel; a data driver configured to apply a data voltage to the display panel; an initialization voltage line connected to the sub-pixels; and a control transistor configured to control whether an initialization voltage is applied through the initialization voltage line.

[0008] When the at least one scan signal is applied as a voltage to turn on the transistor, the control transistor can be turned off to cut off the supply of the initialization voltage.

[0009] The initialization voltage line may include a region that overlaps with at least one scan line.

[0010] The control transistor can be placed in the non-display area of ​​the display panel where no image is displayed.

[0011] The sub-pixel may include a p-type transistor and an n-type transistor, and at least one scan line may include a scan line A controlling the p-type transistor and a scan line B controlling the n-type transistor, and the control transistor may be turned on or off based on a scan signal applied through the scan line B.

[0012] The sub-pixel may include a first to a seventh transistor, and at least one scan line may include a first scan line controlling the first transistor, a second scan line controlling the second transistor, a third scan line controlling the sixth and seventh transistors, and a fourth scan line controlling the fifth transistor, and may turn the control transistors on or off based on a third scan signal applied through the third scan line.

[0013] The initialization voltage line may include a region that overlaps with the fourth scan line.

[0014] When a fourth scan signal with a high gate voltage is applied through the fourth scan line, the control transistor can be turned off to cut off the supply of the initialization voltage.

[0015] In another aspect of this disclosure, a method for driving a display device includes: applying a scan signal via at least one scan line connected to a display panel; applying a data voltage via a data line connected to the display panel; and applying an initialization voltage via an initialization voltage line connected to a sub-pixel, wherein applying the initialization voltage may include cutting off the supply of the initialization voltage when the scan signal is applied to a voltage for turning on a transistor included in the display panel.

[0016] The initialization voltage line may include a region that overlaps with at least one scan line. Attached Figure Description

[0017] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated into and forming part of this application, illustrate (multiple) embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure. In the drawings:

[0018] Figure 1 It is a schematic block diagram illustrating the display device, and Figure 2 This is a block diagram illustrating the configuration of the gate driver in a display device;

[0019] Figure 3It is a cross-sectional view illustrating the stacked structure of the display panels;

[0020] Figure 4 This is an exemplary schematic diagram illustrating a control transistor for controlling the output of the second initialization voltage according to the first embodiment and a portion of the elements included in the sub-pixel. Figure 5 yes Figure 4 The diagram shows an exemplary arrangement of the control transistors. Figure 6 This is a schematic diagram used to describe a comparison example that does not include a control transistor, and Figure 7 This is a schematic diagram illustrating a first embodiment including a control transistor;

[0021] Figure 8 This is an exemplary schematic diagram illustrating the control transistor controlling the output of the anode initialization voltage according to the second embodiment and the elements included in the sub-pixel. Figure 9 and Figure 10 Based on Figure 8 An exemplary driving waveform diagram of a display panel implemented with subpixels, and Figure 11 It is used to describe based on Figure 8 A schematic diagram of the driving characteristics of a display panel implemented by subpixels;

[0022] Figure 12 It shows based on Figure 8 A schematic diagram of a portion of the implemented sub-pixel. Figure 13 This is a schematic diagram used to describe a comparative example that does not include a control transistor. Figure 14 This is a schematic diagram illustrating a second embodiment including a control transistor;

[0023] Figure 15 This is a schematic diagram illustrating the problem that occurs when the second initialization voltage is increased, in a comparative example excluding the control transistor. Figure 16 This is a schematic diagram used to describe a comparative example that does not include a control transistor. Figure 17 This is a schematic diagram illustrating a second embodiment including a control transistor;

[0024] Figure 18 This is an exemplary schematic diagram illustrating the control transistor controlling the output of the anode initialization voltage according to the third embodiment and the elements included in the sub-pixel. Figure 19 and Figure 20 Based on Figure 18 An exemplary driving waveform diagram of a display panel implemented with subpixels; and

[0025] Figure 21 This is an exemplary schematic diagram illustrating the control transistor controlling the output of the anode initialization voltage according to the fourth embodiment and the elements included in the sub-pixel. Figure 22 and Figure 23 Based on Figure 21 An exemplary driving waveform diagram of a display panel implemented by subpixels. Detailed Implementation

[0026] The present disclosure will be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are illustrated. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the concepts of the disclosure to those skilled in the art.

[0027] The display device according to this disclosure can be implemented as a light-emitting display device or a quantum dot display (QDD) device. In the following description, for ease of description, a self-emissive light-emitting display device based on an inorganic or organic light-emitting diode will be described, for example.

[0028] Furthermore, the thin-film transistor (TFT) described below can be implemented using n-type TFTs, p-type TFTs, or a combination of n-type and p-type TFTs. A TFT can be a three-electrode device comprising a gate, a source, and a drain. The source can be the electrode that provides charge carriers to the transistor. In a TFT, charge carriers can begin to flow from the source. The drain can be the electrode from which charge carriers flow from the TFT to the outside. That is, in a TFT, charge carriers flow from the source to the drain.

[0029] In a p-type TFT, because the charge carriers are holes, the source voltage can be higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-type TFT, because holes flow from the source to the drain, current can flow from the source to the drain. On the other hand, in an n-type TFT, because the charge carriers are electrons, the source voltage can be lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-type TFT, because electrons flow from the source to the drain, current can flow from the drain to the source. However, the source and drain of a TFT can switch between the two based on the voltage applied to them. Therefore, in the following description, one of the source and drain will be described as the first electrode, and the other of the source and drain will be described as the second electrode.

[0030] Figure 1 This is a block diagram schematically illustrating the display device 10, and Figure 2 This is a block diagram illustrating the configuration of the gate driver in the display device 10.

[0031] like Figure 1As shown, the display device 10 may include: a display panel 100, which includes a plurality of sub-pixels SP; a controller 200; a gate driver 300, which supplies gate signals to the plurality of sub-pixels SP; a data driver 400, which supplies data signals (or data voltages) to the plurality of sub-pixels SP; and a power supply 500, which supplies power to the plurality of sub-pixels SP.

[0032] The display panel 100 may include a display area (see...) Figure 2 (AA) and non-display areas (see AA) Figure 2 The display area (AA) provides multiple sub-pixels P, the non-display area is set around the display area AA, and the gate driver 300 and the data driver 400 are set in the non-display area.

[0033] In the display panel 100, multiple gate lines GL and multiple data lines DL can intersect each other, and each of the multiple sub-pixels P can be connected to both the gate line GL and the data line DL. Specifically, a gate signal can be provided to a sub-pixel P from the gate driver 300 via the gate line GL, a data voltage (data signal) can be provided to a sub-pixel P from the data driver 400 via the data line DL, and a high-level voltage EVDD and a low-level voltage EVSS can be provided to a sub-pixel P from the power supply 500.

[0034] Gate line GL transmits scan signal Sc and emit control signal Em to multiple sub-pixels SP, and data line DL transmits data voltage Vdata to multiple sub-pixels SP. According to various embodiments, gate line GL may include multiple scan lines SCL for supplying scan signal Sc and multiple emit control lines EML for supplying emit control signal Em. Voltages Vini, Var, and Vobs can be provided to multiple sub-pixels P through multiple voltage lines VL. The voltages Vini, Var, and Vobs applied through multiple voltage lines VL will be described below.

[0035] Each of the multiple sub-pixels P may include a sub-pixel driving circuit. The sub-pixel driving circuit may include multiple switching elements, driving elements, and capacitors. The switching elements and driving elements may each be configured as TFTs. The switching transistors may be turned on based on a scan signal Sc provided via scan line SCL and an emission control signal Em provided via emission control line EML. The driving transistors may control the amount of current supplied to the OLED light-emitting device (controlling the amount of emitted light) based on the data voltage Vdata.

[0036] Display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device that displays images on its screen while allowing the real objects in the background to be seen. Display panel 100 can be implemented as a flexible display panel. A flexible display panel can use a plastic substrate. For color implementation, each of the plurality of sub-pixels P can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Each of the plurality of sub-pixels P can further include a white sub-pixel.

[0037] A touch sensor may be disposed in the display panel 100. Touch input may be sensed by using a separate touch sensor or by multiple subpixels SP. The touch sensor may be arranged as an on-cell type or an additional type in the screen of the display panel 100, or it may be implemented as an in-cell type touch sensor embedded in the display panel 100.

[0038] The controller 200 can process externally input image data (RGB) based on the size and resolution of the display panel 100 to provide it to the data driver 400. The controller 200 can generate a gate control signal GCS and a data control signal DCS using externally input synchronization signals (e.g., a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync). The controller 200 can supply the gate control signal GCS to the gate driver 300 to control the operating timing of the gate driver 300. The controller 200 can supply the data control signal DCS to the data driver 400 to control the operating timing of the data driver 400. The controller 200 can synchronize the operating timing of the gate driver 300 with the operating timing of the data driver 400 by using the gate control signal GCS and the data control signal DCS.

[0039] The controller 200 can be configured to be coupled to various processors (e.g., microprocessors, mobile processors, and application processors) based on devices mounted thereon. The host system located at the front end relative to the controller 200 can be one of a television (TV) system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, wearable device, or automotive system.

[0040] The controller 200 can multiply the input frame frequency by i (where i can be a positive integer greater than 0) to control the operating timing of the display panel driver based on a frame frequency of input frame frequency × i Hz. The input frame frequency can be approximately 60 Hz in the National Television Standards Committee (NTSC) scheme and approximately 50 Hz in the Phase Inverter (PAL) scheme.

[0041] The controller 200 can drive the display panel 100 at various refresh rates. The controller 200 can drive the display panel 100 in a switchable type in variable refresh rate (VRR) mode (i.e., between a first refresh rate and a second refresh rate).

[0042] For example, controller 200 can simply change the speed of the clock signal, or it can generate a synchronization signal to cause horizontal or vertical blanking, or it can drive gate driver 300 in mask mode to drive display panel 100 at various refresh rates. Vertical blanking can be defined as a period of time that allows the timing of the input of data signals to match the timing of the output (display) of the image to the display panel. Vertical blanking can repeat at one frame period, and various signals used for the operation of the display device during the corresponding period can be synchronized with each other.

[0043] The voltage level of the gate control signal GCS output from controller 200 can be converted into on-state and off-state voltages by a level shifter (not shown) and provided to gate driver 300. The level shifter can shift the low-level voltage of the gate control signal GCS to the gate low voltage VGL and the high-level voltage of the gate control signal GCS to the gate high voltage VGH. The gate control signal GCS may include a start pulse and a shift clock.

[0044] The gate driver 300 can provide a gate signal to the gate line GL based on the gate control signal GCS provided from the controller 200. The gate driver 300 can be disposed on one or both sides of the display panel 100 in the form of a gate in panel (GIP) type.

[0045] The gate driver 300 can sequentially output gate signals to multiple gate lines GL based on the control of the controller 200. The gate driver 300 can shift the gate signals by using a shift register, and therefore can sequentially supply signals to the gate lines GL.

[0046] In an organic light-emitting display device, the gate signals may include a scan signal Sc and an emission control signal Em. The scan signal Sc may include a scan pulse that oscillates between a gate low voltage VGL and a gate high voltage VGH. The emission control signal Em may include an emission control signal pulse that oscillates between a gate on voltage VEL and a gate off voltage VEH. The scan pulse can select the sub-pixel P of the line to which data voltage Vdata is to be written. The emission control signal Em can define the emission time of each sub-pixel SP.

[0047] The gate driver 300 may include a transmit control signal driver 310 and one or more scan drivers 320. The transmit control signal driver 310 may output transmit control signal pulses in response to a start pulse and a shift clock from the controller 200, and may shift the transmit control signal pulses sequentially according to the shift clock. The one or more scan drivers 320 may output scan pulses in response to a start pulse and a shift clock from the controller 200, and may shift the scan pulses based on the shift clock timing.

[0048] The data driver 400 can convert image data RGB into data voltage Vdata based on the data control signal DCS provided by the controller 200, and can output the data voltage Vdata through the data line DL.

[0049] exist Figure 1 The diagram shows a data driver 400 disposed on one side of the display panel 100, but the number and arrangement of the data drivers 400 are not limited thereto. That is, the data driver 400 can be configured with multiple integrated circuits (ICs) and can be provided in multiple forms, and the multiple data drivers 400 can be arranged separately on one side of the display panel 100.

[0050] Power supply 500 can generate the direct current (DC) power required to drive the display panel driver and the sub-pixel array of display panel 100 by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, and a boost converter. Power supply 500 can receive a DC input voltage applied from a host system (not shown) to generate DC voltages such as gate voltages VGL, VEL, VGH, and VEH, high-level voltage EVDD, and low-level voltage EVSS.

[0051] like Figure 1 and Figure 2 As shown, the gate driver 300 may include an emit control signal driver 310 and a scan driver 320. The scan driver 320 may include a first scan driver 321 to a fourth scan driver 324. In addition, the second scan driver 322 may include an odd-numbered second scan driver 322_O and an even-numbered second scan driver 322_E.

[0052] The shift registers configuring the gate driver 300 can be configured symmetrically on both sides of the display area AA. The shift registers on one side of the display area AA may include second scan drivers 322_O and 322_E, a fourth scan driver 324, and a transmit control signal driver 310, while the shift registers on the other side of the display area AA may include a first scan driver 321, second scan drivers 322_O and 322_E, and a third scan driver 323. Figure 2 The diagram illustrates an example of a structure where odd-numbered second scan drivers 322_O and even-numbered second scan drivers 322_E share a second scan driver 322. Therefore, the transmit control signal driver 310 and the first scan drivers 321 to the fourth scan drivers 324 can be arranged differently, but are not limited thereto.

[0053] The shift register stages STG1 to STGn may include first scan signal generators SC1(1) to SC1(n), second scan signal generators SC2_O(1) to SC2_O(n) and SC2_E(1) to SC2_E(n), third scan signal generators SC31(1) to SC3(n), fourth scan signal generators SC4(1) to SC4(n) and transmit control signal generators EM(1) to EM(n).

[0054] The first scan signal generators SC1(1) to SC1(n) can output the first scan signal through the first scan line SCL1 of the display panel 100, respectively. The second scan signal generators SC2(1) to SC2(n) can output the second scan signal through the second scan line SCL2 of the display panel 100, respectively. The third scan signal generators SC3(1) to SC3(n) can output the third scan signal through the third scan line SCL3 of the display panel 100, respectively. The fourth scan signal generators SC4(1) to SC4(n) can output the fourth scan signal through the fourth scan line SCL4 of the display panel 100, respectively. The transmit control signal generators EM(1) to EM(n) can output the transmit control signal through the transmit control line EML of the display panel 100, respectively.

[0055] The first scan signal can be used to drive the A-th transistor (e.g., a compensation transistor) included in the sub-pixel driving circuit. The second scan signal can be used to drive the B-th transistor (e.g., a data supply transistor) included in the sub-pixel driving circuit. The third scan signal can be used to drive the C-th transistor (e.g., a bias transistor) included in the sub-pixel driving circuit. The fourth scan signal can be used to drive the D-th transistor (e.g., an initialization transistor) included in the sub-pixel driving circuit. The emission control signal can be used to drive the E-th transistor (e.g., an emission control transistor) included in the sub-pixel driving circuit. For example, when the emission control transistor is controlled using the emission control signal, the emission time of the light-emitting device can be varied.

[0056] The bias voltage line VobsL for transmitting the bias voltage, the first initialization voltage line ViniL for transmitting the first initialization voltage Vini, and the second initialization voltage line VaralL for transmitting the second initialization voltage Var can be set between the gate driver 300 and the display area AA.

[0057] In the accompanying drawings, each of the bias voltage line VobsL, the first initialization voltage line ViniL, and the second initialization voltage line VaraL is shown as being positioned on one side of the display area AA, but not limited thereto, and may be positioned on both sides, or even when positioned on one side, the position is not limited to the left or right side.

[0058] Furthermore, one or more optical regions OA1 and OA2 can be set within the display area AA. Optical regions OA1 and OA2 can be configured to overlap with one or more optoelectronic devices, such as imaging devices (such as cameras (image sensors)) and sensing sensors (such as proximity sensors and illumination sensors).

[0059] Optical regions OA1 and OA2 can have light-transmitting structures for the operation of optoelectronic devices, and therefore can have a certain level or higher transmittance. In other words, the number of pixels P per unit area in optical regions OA1 and OA2 can be less than the number of pixels per unit area in the normal area of ​​display area AA excluding optical regions OA1 and OA2. That is, the resolution of each of optical regions OA1 and OA2 can be lower than the resolution of the normal area of ​​display area AA.

[0060] In optical regions OA1 and OA2, the light-transmitting structure can be configured by patterning a cathode electrode in the portion where no sub-pixels are set. In this case, the patterned cathode electrode can be removed by using a laser, or the cathode electrode can be selectively patterned by using a material such as a cathode deposition prevention layer.

[0061] Furthermore, in optical regions OA1 and OA2, the light-transmitting structure can be configured by forming a light-emitting device and a sub-pixel driving circuit included in the sub-pixel, respectively. In other words, the light-emitting device of the sub-pixel can be disposed in optical regions OA1 and OA2, and multiple transistors constituting the sub-pixel driving circuit can be disposed near optical regions OA1 and OA2. Therefore, the light-emitting device can be electrically connected to the sub-pixel driving circuit through a transparent metal layer.

[0062] Figure 3 This is a cross-sectional view illustrating the stacked structure of the display panel 100.

[0063] like Figure 3 As shown, the capacitor CST and transistors TFT1 and TFT2 used to drive the light-emitting device OLED disposed in the display area AA can be disposed on the substrate 111 of the display panel 100. Transistors TFT1 and TFT2 can include: a switching / driving thin-film transistor comprising a polycrystalline semiconductor material, and an oxide thin-film transistor comprising an oxide semiconductor material. In this case, the thin-film transistor comprising a polycrystalline semiconductor material can be referred to as polycrystalline thin-film transistor TFT1, and the thin-film transistor comprising an oxide semiconductor material can be referred to as oxide thin-film transistor TFT2. For example, polycrystalline thin-film transistor TFT1 can be a transistor connected to the light-emitting device OLED, and oxide thin-film transistor TFT2 can be a transistor connected to the capacitor CST.

[0064] The substrate 111 may include a first substrate layer 111a, a second substrate layer 111b, and a third substrate layer 111c. The first substrate layer 111a and the third substrate layer 111c may be selected as organic layers including polyimide, and the second substrate layer 111b disposed between the first substrate layer 111a and the third substrate layer 111c may be selected as an inorganic layer such as silicon oxide resin (SiO2).

[0065] A lower buffer layer 112a may be formed on the substrate 111. The lower buffer layer 112a can be used to prevent water from penetrating from the outside, and can be a SiO2 layer stacked in multiple layers. An auxiliary buffer layer 112b may be further disposed on the lower buffer layer 112a to protect the device from water penetration.

[0066] A polycrystalline thin-film transistor (TFT) 1 can be formed on a substrate 111. The TFT 1 can use a polycrystalline semiconductor as its active layer. The TFT 1 may include a first active layer ACT1, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2. The first active layer ACT1 includes a channel through which electrons or holes can move. A first gate insulating layer 113 can be disposed between the first gate electrode GE1 and the first active layer ACT1, and can be an inorganic layer such as silicon nitride (SiNx) or SiO2 layers, stacked as a single layer or multiple layers.

[0067] The first active layer ACT1 may include a first channel region, a first source region disposed on one side relative to the first channel region, and a first drain region disposed on the other side relative to the first channel region. The first source region and the first drain region may each be a region that conducts electricity by doping an intrinsic polycrystalline semiconductor material with a certain concentration of Group V or III impurity ions (e.g., phosphorus (P) or boron (B)). The first channel region may allow the polycrystalline semiconductor material to remain in its intrinsic state and may provide a path for the movement of electrons or holes.

[0068] According to an embodiment, the polycrystalline thin-film transistor TFT1 can be implemented in a top gate structure, wherein a first gate electrode GE1 is disposed on a first active layer ACT1. Therefore, the first electrode CST1 included in the capacitor CST and the light-blocking layer LS included in the oxide thin-film transistor TFT2 can be formed of the same material as the first gate electrode GE1. The first gate electrode GE1, the first electrode CST1, and the light-blocking layer LS can be formed using a single mask process, thereby reducing the number of mask processes.

[0069] The first gate electrode GE1 may include a metallic material. For example, the first gate electrode GE1 may be a single layer or multiple layers, including, but not limited to, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof. A first interlayer insulating layer 114 may be disposed on the first gate electrode GE1. The first interlayer insulating layer 114 may be implemented using SiO2 or SiNx.

[0070] The display panel 100 may further include an upper buffer layer 115, a second gate insulating layer 116, and a second interlayer insulating layer 117 sequentially disposed on the first interlayer insulating layer 114, and the polycrystalline thin-film transistor TFT1 may include a first source electrode SD1 and a first drain electrode SD2 formed on the second interlayer insulating layer 117 and respectively connected to the first source region and the first drain region.

[0071] The first source electrode SD1 and the first drain electrode SD2 may be a single layer or multiple layers of one or an alloy of Mo, Al, Cr, Au, Ti, Ni, Nd and Cu, but are not limited thereto.

[0072] The upper buffer layer 115 can separate the second active layer ACT2 of the oxide thin film transistor TFT2, which is made of oxide semiconductor material, from the first active layer ACT1, which is made of polycrystalline semiconductor material, and can provide a basis for forming the second active layer ACT2.

[0073] The second gate insulating layer 116 may cover the second active layer ACT2 of the oxide thin-film transistor TFT2. The second gate insulating layer 116 may be formed on the second active layer ACT2, which is implemented using an oxide semiconductor material, and therefore may be implemented as an inorganic layer. For example, the second interlayer insulating layer 116 may be SiO2 or SiNx.

[0074] The second gate electrode GE2 may be configured with a metallic material. For example, the second gate electrode GE2 may be a single layer or multiple layers of one or an alloy of Mo, Al, Cr, Au, Ti, Ni, Nd and Cu, or thereof, but is not limited thereto.

[0075] The oxide thin-film transistor TFT2 can be formed on the upper buffer layer 115. The oxide thin-film transistor TFT2 may include a second active layer ACT2 made of oxide semiconductor material, a second gate electrode GE2 disposed on the second gate insulating layer 116, and a second source electrode SD3 and a second drain electrode SD4 disposed on the second interlayer insulating layer 117. The second active layer ACT2 can be made of oxide semiconductor material and may include an intrinsic second channel region without impurities and a second source region and a second drain region that are conductive through impurities.

[0076] The oxide thin-film transistor TFT2 may further include a light-blocking layer LS disposed below the upper buffer layer 115 to overlap with the second active layer ACT2. The light-blocking layer LS prevents light from incident on the second active layer ACT2, thus ensuring the reliability of the oxide thin-film transistor TFT2. The light-blocking layer LS may be formed of the same material as the first gate electrode GE1 and may be disposed on the upper surface of the first gate insulating layer 113. The light-blocking layer LS may be electrically connected to the second gate electrode GE2 to configure a dual-gate configuration.

[0077] The second source electrode SD3 and the second drain electrode SD4 can be formed simultaneously on the second interlayer insulating layer 117 from the same material as the first source electrode SD1 and the first drain electrode SD2, and thus the number of mask processes can be reduced.

[0078] Furthermore, the second electrode CST2 can be disposed on the first interlayer insulating layer 114 to overlap with the first electrode CST1, and thus a capacitor CST can be realized. For example, the second electrode CST2 can be a single layer or multiple layers of one or an alloy of Mo, Al, Cr, Au, Ti, Ni, Nd and Cu.

[0079] The capacitor CST can store the data voltage applied via the data line DL during a specific time period. The capacitor CST may include two corresponding electrodes and a dielectric disposed therebetween. A first interlayer insulating layer 114 may be disposed between the first electrode CST1 and the second electrode CST2.

[0080] The first electrode CST1 or the second electrode CST2 of the capacitor CST can be electrically connected to the second source electrode SD3 or the second drain electrode SD4 of the oxide thin-film transistor TFT2. However, the embodiments are not limited to this, and the connection relationship of the capacitor CST can be changed based on the sub-pixel driving circuit.

[0081] A first planarization layer 118 and a second planarization layer 119 for planarizing the surface can be sequentially disposed on the sub-pixel driving circuit. The first planarization layer 118 and the second planarization layer 119 can each be an organic layer, such as polyimide or acrylic resin. An OLED light-emitting device can be formed on the second planarization layer 119.

[0082] An OLED (Optical Display Cell) device may include an anode electrode AND, a cathode electrode CAT, and an emitter layer EML disposed between the anode electrode AND and the cathode electrode CAT. When implementing a sub-pixel driving circuit that uses a common low-level voltage connected to the cathode electrode CAT, the anode electrode AND may be configured as a separate electrode for each sub-pixel. Conversely, when implementing a sub-pixel driving circuit that uses a common high-level voltage, the cathode electrode CAT may be configured as a separate electrode for each sub-pixel.

[0083] The light-emitting device OLED can be electrically connected to the driving element via the central electrode CNE disposed on the first planarization layer 118. For example, the anode electrode AND of the light-emitting device OLED and the first source electrode SD1 of the polycrystalline thin-film transistor TFT1 constituting the sub-pixel driving circuit can be connected to each other via the central electrode CNE.

[0084] The anode electrode AND can be connected to the center electrode CNE exposed through a contact hole passing through the second planarization layer 119. The center electrode CNE can be connected to the first source electrode SD1 exposed through a contact hole passing through the first planarization layer 118.

[0085] The center electrode CNE can be used as a medium to connect the first source electrode SD1 to the anode electrode AND. The center electrode CNE can include a conductive material such as Cu, Ag, Mo, or Ti.

[0086] The anode electrode AND can be formed as a multilayer structure comprising a transparent conductive layer and an opaque conductive layer with high reflectivity. The transparent conductive layer can include materials with relatively high work function values, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive layer can be formed as a single layer or multiple layers, including Al, Ag, Cu, lead (Pb), Mo, or Ti, or alloys thereof. For example, the anode electrode AND can be formed in a structure where transparent conductive layers, opaque conductive layers, and transparent conductive layers are stacked sequentially, or in a structure where transparent conductive layers and opaque conductive layers are stacked sequentially. The emitter layer EML can be formed by stacking a hole-correlated layer, an organic emitter layer, and an electron-correlated layer on the anode electrode AND in either a sequential or reverse order.

[0087] The dam layer (BNK) can be a subpixel definition layer that exposes the anode electrode AND of each subpixel. The dam layer (BNK) can be formed of an opaque material (e.g., black) to prevent light interference between adjacent subpixels. In this case, the dam layer (BNK) can include a light-blocking material, which includes at least one of colored pigments, organic black, and carbon.

[0088] The cathode electrode CAT can be formed on the upper and side surfaces of the emitting layer EML, so as to be opposite to the anode electrode AND and with the emitting layer EML located therebetween. The cathode electrode CAT can be formed into a body to cover the entire display area AA. In the case of the cathode electrode CAT being used in a top-emitting type organic light-emitting display device, the cathode electrode CAT may include a transparent conductive layer, such as ITO or IZO.

[0089] An encapsulation layer 120 for preventing water penetration may be further disposed on the cathode electrode CAT. The encapsulation layer 120 prevents external water or oxygen from penetrating into the emitter layer EML, which is susceptible to external water or oxygen. For this purpose, the encapsulation layer 120 may include, but is not limited to, at least one inorganic encapsulation layer and at least one organic encapsulation layer. The encapsulation layer 120 may include a first encapsulation layer 121, a second encapsulation layer 122, and a third encapsulation layer 123 stacked in sequence.

[0090] The first encapsulation layer 121 and the third encapsulation layer 123 may comprise inorganic insulating materials capable of low-temperature deposition, such as SiNx, SiOx, silicon oxynitride (SiON), or aluminum oxide (Al2O3). The first encapsulation layer 121 and the third encapsulation layer 123 can be deposited in a low-temperature atmosphere, and therefore, damage to the emitter layer (EML), which is susceptible to high-temperature atmospheres, can be prevented when performing the deposition process of the first encapsulation layer 121 and the third encapsulation layer 123.

[0091] The second encapsulation layer 122 can perform a buffering function to reduce the stress between layers caused by the bending of the display device 10, and can flatten the step height between layers. The second encapsulation layer 122 can be formed on the substrate 111 on which the first encapsulation layer 121 is formed, and can include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin and polyethylene, or a non-photosensitive organic insulating material such as silicon oxycarbide (SiOC), or a photosensitive organic insulating material such as photoacrylic acid, but the embodiments are not limited thereto.

[0092] When the second encapsulation layer 122 is formed by inkjet printing, a dam DAM can be provided to prevent the second encapsulation layer 122 from spreading to the edge of the substrate 111. The dam DAM can be set closer to the edge of the substrate 111 than the second encapsulation layer 122. The dam DAM can prevent the second encapsulation layer 122 from spreading to the pad area where conductive pads are provided at the outermost part of the substrate 111.

[0093] The dam DAM can be designed to prevent the diffusion of the second encapsulation layer 122. However, if the second encapsulation layer 122 is formed to flow above the height of the dam DAM during process execution, the second encapsulation layer 122, as an organic layer, can be exposed externally, and therefore, water can easily penetrate into the light-emitting device OLED. Therefore, to solve this problem, the dam DAM can be configured to have ten or more overlapping each other.

[0094] The dam DAM can be disposed on the second interlayer insulating layer 117 of the non-display area NA. Furthermore, the dam DAM can be formed simultaneously with the first planarization layer 118 and the second planarization layer 119. When the first planarization layer 118 is formed, the lower layer of the dam DAM can be formed together, and when the second planarization layer 119 is formed, the upper layer of the dam DAM can be formed together, and therefore, the dam DAM can be stacked and formed as a dual structure. Thus, the dam DAM can include the same insulating material as the first planarization layer 118 and the second planarization layer 119, but the embodiments are not limited to this.

[0095] The dam DAM can be formed to overlap with the low-level voltage line EVSS. For example, the low-level voltage line EVSS can be disposed in the lower layer of the area where the dam DAM is disposed in the non-display area NA. The low-level voltage line EVSS can be disposed further outward than the gate driver 300 and can surround the display area AA. For example, the low-level voltage line EVSS can include, but is not limited to, the same material as the first gate electrode GE1, and can include the same material as the second electrode CST2 or the first source electrode SD1 and the first drain electrode SD2. The low-level voltage line EVSS can be electrically connected to the cathode electrode CAT to apply the low-level voltage EVSS to the plurality of sub-pixels included in the display area AA.

[0096] The touch layer can be disposed on the encapsulation layer 120. In the touch layer, the touch buffer layer 151 can be disposed between the cathode electrode CAT of the light-emitting device OLED and the touch sensor metal layer including touch electrodes 155 and 156 and touch electrode connection lines 152 and 154.

[0097] The touch buffer layer 151 prevents external water or chemical solutions (e.g., developers or etchants) used in the manufacturing process of the touch sensor metal layer disposed on the touch buffer layer 151 from penetrating into the emitter layer EML, which includes organic materials. Therefore, the touch buffer layer 151 can prevent damage to the emitter layer EML, which is susceptible to chemical solutions or water.

[0098] The touch buffer layer 151 may comprise an organic insulating material having a low dielectric constant of 1 to 3 and capable of being formed at a temperature (e.g., 100°C) or lower to prevent damage to the emitter layer (EML) containing organic materials susceptible to high temperatures. For example, the touch buffer layer 151 may comprise acrylic, epoxy, or siloxane materials. The touch buffer layer 151, comprising an organic insulating material and possessing planarization properties, can prevent damage to the encapsulation layer 120 caused by device bending and breakage of the touch sensor metal layer formed on the touch buffer layer 151.

[0099] According to the mutual capacitance-based touch sensor structure, touch electrodes 155 and 156 can be disposed on the touch buffer layer 151, and touch electrodes 155 and 156 can be arranged to intersect each other. Touch electrode connecting lines 152 and 154 can electrically connect touch electrodes 155 and 156 to each other. Touch electrode connecting lines 152 and 154 and touch electrodes 155 and 156 can be disposed in different layers, with a touch insulating layer 153 in between. Touch electrode connecting lines 152 and 154 can be arranged to overlap with the embankment layer BNK and can prevent a decrease in aperture ratio.

[0100] In touch electrodes 155 and 156, a portion of touch electrode connection line 152 can pass through the upper and side surfaces of encapsulation layer 120 and the upper and side surfaces of dam DAM, and can be electrically connected to touch driving circuit (not shown) via touch panel PAD. A portion of touch electrode connection line 152 can be supplied with touch driving signals from the touch driving circuit, and can transmit touch driving signals to touch electrodes 155 and 156, or can transmit touch sensing signals from touch electrodes 155 and 156 to the touch driving circuit.

[0101] A touch protection layer 157 may be disposed on touch electrodes 155 and 156. In the figures, the touch protection layer 157 is shown as being disposed only on touch electrodes 155 and 156, but the embodiment is not limited thereto, and the touch protection layer 157 may extend to the front or rear portion relative to the dam DAM, and may be disposed on touch electrode connection line 152. Furthermore, a color filter (not shown) may be further disposed on encapsulation layer 120, and the color filter may be disposed on the touch layer or may be disposed between encapsulation layer 120 and the touch layer.

[0102] Figure 4 This is an exemplary schematic diagram illustrating a control transistor for controlling the output of the second initialization voltage according to the first embodiment and a portion of the elements included in the sub-pixel. Figure 5 yes Figure 4 The diagram shows an exemplary arrangement of the control transistors. Figure 6 This is a schematic diagram used to describe a comparison example that does not include a control transistor, and Figure 7 This is a schematic diagram illustrating a first embodiment including a control transistor.

[0103] like Figure 4 As shown, sub-pixel P may include a driving transistor DT, a first transistor T1, and a light-emitting device (OLED). The driving transistor DT can be implemented as p-type. The p-type driving transistor DT can operate based on a data voltage applied at a low voltage and can generate a driving current to be supplied to the OLED. The first transistor T1 can be implemented as n-type. The n-type first transistor T1 can operate based on a scan signal applied at a high voltage, and the driving transistor DT can be configured as a diode. The OLED emits light according to the driving current generated based on the operation of the first transistor T1 and the driving transistor DT.

[0104] As mentioned above, sub-pixel P can be implemented based on two types of transistors, but is not limited to these. Furthermore, sub-pixel P may also include circuitry for compensating the driving transistor DT or the light-emitting device OLED. Therefore, the circuitry included in sub-pixel P can be implemented differently, and reference should be made to... Figure 4 .

[0105] Sub-pixel P can be connected to a control transistor TR_VAR that controls the output of the second initialization voltage (controlling whether the initialization voltage is applied). The control transistor TR_VAR can be turned on or off to perform control, such that the second initialization voltage transmitted through the second initialization voltage line VaralL is applied or not applied to sub-pixel P. The control transistor TR_VAR is implemented as a p-type for example, but it can also be implemented as an n-type.

[0106] The control transistor TR_VAR may include a gate electrode connected to a first scan line SCA(n) to which the first scan signal A is applied, a first electrode connected to a second initialization voltage line VaralL to which a second initialization voltage is applied, and a second electrode connected to the sub-pixel P. For further description, the control transistor TR_VAR may include a gate electrode connected to the first scan line SCA(n), a first electrode connected to a second initialization voltage source, and a second electrode connected to the second initialization voltage line VaralL, which is connected to the sub-pixel P. For further description, the control transistor TR_VAR may include a gate electrode connected to the first scan line SCA(n), a first electrode connected to one side of the second initialization voltage line VaralL, and a second electrode connected to the other side of the second initialization voltage line VaralL. The second initialization voltage output from the control transistor TR_VAR can be applied to the anode electrode of the OLED. Furthermore, the second initialization voltage can be defined as an anode initialization voltage used to initialize the anode electrode of the OLED.

[0107] like Figure 4 and Figure 5 As shown, the control transistor TR_VAR can be located in the non-display area NA adjacent to the gate driver 300. The A-scan line SCA(n) for controlling the control transistor TR_VAR and the B-scan line SCB(n) for controlling the transistor included in the sub-pixel P can be located in the display area AA and the non-display area NA.

[0108] The B-th scan line SCB(n) can be positioned adjacent to or overlapping with the second initialization voltage line VaralL, which transmits the second initialization voltage. In this case, a parasitic capacitor CC can be formed between the second initialization voltage line VaralL and the B-th scan line SCB(n).

[0109] When the parasitic capacitor CC is formed between the second initialization voltage line VarL and the B-th scan line SCB(n), the second initialization voltage Var may be affected by the B-th scan signal Scb(n) transmitted through the B-th scan line SCB(n).

[0110] like Figure 5 and Figure 6 As shown, for example, when the B-th scan signal Scb(n) is applied as a gate low voltage Vgl (or the transistor's turn-off voltage) and then as a gate high voltage Vgh (or the transistor's turn-on voltage), the second initialization voltage Var can be placed in a coupling state affected by the B-th scan signal Scb(n) which is subject to the gate high voltage Vgh, thus increasing (see...) Figure 6 ΔV).

[0111] like Figure 5 and Figure 7 As shown, for example, when the control transistor TR_VAR is turned off (TR_VAR off), and the B-scan signal Scb(n) is applied as a gate low voltage Vgl and then as a gate high voltage Vgh, the second initialization voltage Var can be placed in a decoupled state (the supply of the second initialization voltage is cut off), which is not affected by the B-scan signal Scb(n) of the gate high voltage Vgh, and therefore does not need to be increased.

[0112] Furthermore, the control transistor TR_VAR can be in a turned-off state before the gate high voltage Vgh of the B-th scan signal Scb(n) occurs. Moreover, even after the B-th scan signal Scb(n) shifts from the gate high voltage Vgh to the gate low voltage Vgl, the control transistor TR_VAR can remain in a turned-off state for a period of time. Therefore, the coupling effect between the second initialization voltage Var and the B-th scan signal Scb(n) can be completely eliminated, and this should be interpreted as an example.

[0113] Therefore, the first embodiment can physically / electrically prevent coupling problems that increase as the anode initialization voltage used to initialize the anode electrode of the OLED light-emitting device via the control transistor TR_VAR is affected by adjacent scan signals. The first embodiment will be described in more detail below with its sub-pixel-based circuit configuration and driving method.

[0114] Figure 8 This is an exemplary schematic diagram illustrating the control transistor controlling the output of the anode initialization voltage according to the second embodiment and the elements included in the sub-pixel. Figure 9 and Figure 10 Based on Figure 8 An exemplary driving waveform diagram of a display panel implemented with subpixels, and Figure 11 It is used to describe based on Figure 8 A schematic diagram of the driving characteristics of the display panel implemented by subpixels.

[0115] like Figure 8As shown, sub-pixel P may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a driving transistor DT, a capacitor CST, and a light-emitting device OLED. Figure 8 In this example, the first transistor T1 and the fifth transistor T5 may be implemented as n-type based on oxide semiconductor, and the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the driving transistor DT may be implemented as p-type based on polycrystalline semiconductor, but the embodiments are not limited thereto.

[0116] The first transistor T1 may include a gate electrode connected to a first scan line SC1(n), a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first transistor T1 may be turned on in response to a first scan signal applied through the first scan line SC1(n). When the first transistor T1 is turned on, the threshold voltage of the driving transistor DT can be sampled. The first transistor T1 may be defined as a compensation transistor.

[0117] The second transistor T2 may include a gate electrode connected to the second scan line SC2(n), a first electrode connected to the data line DL, and a second electrode connected to the first node N1. The second transistor T2 can be turned on in response to a second scan signal applied through the second scan line SC2(n). When the second transistor T2 is turned on, the data voltage Vdata applied through the data line DL can be transmitted to the first node N1. The second transistor T2 can be defined as a data supply transistor.

[0118] The third transistor T3 may include a gate electrode connected to the emit control signal line EM(n), a first electrode connected to the high-level voltage line EVDD, and a second electrode connected to the first node N1. The third transistor T3 can be turned on in response to an emit control signal applied through the emit control signal line EM(n). When the third transistor T3 is turned on, the high-level voltage applied through the high-level voltage line EVDD can be transferred to the first node N1. The third transistor T3 can be defined as an emit control transistor.

[0119] The fourth transistor T4 may include a gate electrode connected to the emission control signal line EM(n), a first electrode connected to the third node N3, and a second electrode connected to the anode electrode of the light-emitting device OLED. The fourth transistor T4 can be turned on in response to an emission control signal applied via the emission control signal line EM(n). When the fourth transistor T4 is turned on, a drive current generated from the driving transistor DT can be delivered to the light-emitting device OLED. When the fourth transistor T4 is turned on, the light-emitting device OLED can emit light based on the drive current generated from the driving transistor DT. The fourth transistor T4 can be defined as an emission control transistor.

[0120] The fifth transistor T5 may include a gate electrode connected to the fourth scan line SC4(n), a first electrode connected to the first initialization voltage line ViniL, and a second electrode connected to the second node N2. The fifth transistor T5 can be turned on in response to a fourth scan signal applied through the fourth scan line SC4(n). When the fifth transistor T5 is turned on, the first initialization voltage applied through the first initialization voltage line ViniL can be transferred to the second node N2. When the fifth transistor T5 is turned on, the remaining charge in the gate electrode of the driving transistor DT, which is connected to the second electrode of the capacitor CST and the second node N2, can be initialized. The fifth transistor T5 can be defined as an initialization transistor.

[0121] The sixth transistor T6 may include a gate electrode connected to the third scan line SC3(n), a first electrode connected to the second electrode of the control transistor TR_VAR connected to the second initialization voltage line VaralL, and a second electrode connected to the anode electrode of the OLED. The sixth transistor T6 can be turned on in response to a third scan signal applied through the third scan line SC3(n). When the sixth transistor T6 is turned on, the second initialization voltage applied through the second initialization voltage line VaralL can be transferred to the anode electrode of the OLED. When the sixth transistor T6 is turned on, the remaining charge in the anode electrode of the OLED can be initialized. The sixth transistor T6 can be defined as an initialization transistor.

[0122] The seventh transistor T7 may include a gate electrode connected to the third scan line SC3(n), a first electrode connected to the bias voltage line VobsL, and a second electrode connected to the first node N1. The seventh transistor T7 can be turned on in response to a third scan signal applied through the third scan line SC3(n). When the seventh transistor T7 is turned on, the bias voltage applied through the bias voltage line VobsL can be transferred to the first node N1. When the seventh transistor T7 is turned on, the driving transistor DT connected to the first node N1 can maintain a stronger saturation state based on the bias voltage. Therefore, the phenomenon of reduced or delayed voltage charging time for charging the voltage applied to the anode electrode of the OLED light-emitting device during the emission period can be improved. The seventh transistor T7 can be defined as a bias transistor.

[0123] For example, as the bias voltage Vobs increases, the voltage of the third node N3, which serves as the drain electrode of the driving transistor DT, can increase, and the gate-source voltage or drain-source voltage of the driving transistor DT can decrease. Therefore, it is preferable that the bias voltage Vobs is at least higher than the data voltage Vdata. In this case, the magnitude of the drain-source current Id of the driving transistor DT can be reduced, and the stress on the driving transistor DT can be reduced, thereby preventing charge delay at the third node N3. In other words, when the conduction bias stress operation is performed before sampling the threshold voltage of the driving transistor DT, the hysteresis of the driving transistor DT can be mitigated.

[0124] The driving transistor DT may include a gate electrode connected to the second node N2, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The driving transistor DT can be driven to generate a drive current based on the data voltage Vdata stored in the capacitor CST.

[0125] The capacitor CST may include a first electrode connected to the high-level voltage line EVDD and a second electrode connected to the second node N2. The capacitor CST can store the data voltage Vdata for a period of time, and then transfer the data voltage Vdata to the gate electrode of the driving transistor DT.

[0126] An OLED (Optical Display Device) may include an anode electrode connected to a second electrode of a fourth transistor T4 and a cathode electrode connected to a low-level voltage line EVSS. The OLED emits light based on a drive current transmitted through the conducting fourth transistor T4.

[0127] According to the second embodiment, the control transistor TR_VAR may include a gate electrode connected to a third scan line SC3(n) to which a third scan signal is applied, a first electrode connected to a second initialization voltage line VaralL to which a second initialization voltage is applied, and a second electrode connected to a first electrode of a sixth transistor T6 included in the sub-pixel P.

[0128] based on Figure 8 The display panel implemented by the sub-pixel P can be based on Figure 9 The driving waveform shown is used to drive in the first driving mode, and furthermore, it can be based on... Figure 10 The driving waveform shown is driven in a second driving mode. The first driving mode may be included in the programming frame for high-speed driving of the display panel, and the second driving mode may be included in the anode reset frame for low-speed driving of the display panel.

[0129] like Figure 9 and Figure 10 As shown, a first scan signal Sc1(n), a second odd-numbered scan signal Sc2(n)_O, a second even-numbered scan signal Sc2(n)_E, a third scan signal Sc3(n), and a fourth scan signal Sc4(n) can be formed based on a high gate voltage Vgh and a low gate voltage Vgl, and the pulse form can be changed based on the driving mode. On the other hand, a transmit control signal Em(n) can be formed based on a gate on-voltage and a gate off-voltage, and the pulse form can be changed without considering the driving mode. However, Figure 9 and Figure 10 The driving waveform may be merely an example, and this disclosure is not limited thereto.

[0130] like Figure 1 and Figure 11 As shown, the display panel 100 can operate in a variable refresh rate (VRR) mode based on the aforementioned drive waveform. The VRR mode can be a drive mode in which the display panel 150 is driven at a specific drive frequency, and then the refresh rate required to update the data voltage Vdata is increased or decreased according to high-speed or low-speed drive conditions, thereby reducing power consumption. For example, the display panel 100 can drive one frame at 120 Hz (1 frame = 1 / 120 second), or at 60 Hz (1 frame = 1 / 60 second), or it can be diversified to drive one frame at 24 Hz (1 frame = 1 / 24 second).

[0131] Under high-speed drive conditions such as 120 Hz, refresh frames can be provided to refresh the data voltage Vdata at each frame (image refresh). On the other hand, under low-speed drive conditions such as 60 Hz or 24 Hz, anode reset frames can be provided between anode reset frames to refresh the data voltage Vdata every N frames (where N can be an integer of 1 or greater).

[0132] An anode reset frame can be included in a subframe, and the device can operate in the corresponding frame to enable the display panel 100 to display an image normally. Furthermore, the anode reset frame can be executed under low-speed drive conditions. Therefore, the anode reset frame can correspond to a level where there is almost no image motion or a static image is displayed, and can therefore be defined as executing only the output of the scan signal while the output of the data voltage Vdata is stopped; however, embodiments of this disclosure are not limited thereto.

[0133] Furthermore, according to the second embodiment, Figure 8 The control transistor TR_VAR can be turned off based on the third scan signal of the gate high voltage Vgh applied through the third scan line SC3(n) (TR_VAR turn-off) in order to prevent the coupling effect between the second initialization voltage and the scan signal, and the configuration associated with it will be described below.

[0134] Figure 12 It shows based on Figure 8 A schematic diagram of a portion of the implemented sub-pixel. Figure 13 This is a schematic diagram used to describe a comparative example that does not include a control transistor, and Figure 14 This is a schematic diagram illustrating a second embodiment including a control transistor.

[0135] like Figure 12 As shown, a portion of the second initialization voltage line VaralL, which transmits the second initialization voltage to sub-pixel P, can overlap with a portion of the fourth scan line SC4(n), which transmits the fourth scan signal. As described above, when the second initialization voltage line VaralL and the fourth scan line SC4(n), which are disposed in different layers, overlap each other, a parasitic capacitor can be formed.

[0136] In providing Figure 12 In the case of the structure shown, the comparative example does not include the control transistor, such as Figure 13 As shown, whenever the fourth scan signal Sc4(n) of the gate high voltage Vgh is applied, the second initialization voltage Var and the fourth scan signal Sc4(n) can be placed in a coupled state. Therefore, the second initialization voltage Var can be placed in a coupled state affected by the fourth scan signal Sc4(n) of the gate high voltage Vgh, and thus can increase (see...) Figure 6 ΔV).

[0137] In providing Figure 12 In the case of the structure shown, the second embodiment may include a control transistor, such as Figure 14 As shown, whenever the fourth scan signal Sc4(n) with a gate high voltage Vgh is applied, the control transistor can be turned off (TR_VAR turned off). Therefore, the second initialization voltage Var and the fourth scan signal Sc4(n) can be placed in a decoupled state unaffected by coupling effects. Thus, the second initialization voltage Var can be placed in a decoupled state affected by the fourth scan signal Sc4(n) with a gate high voltage Vgh, and therefore does not need to be increased.

[0138] Figure 15 This is a schematic diagram used to illustrate the problem that occurs when the second initialization voltage is increased in a comparative example excluding the control transistor. Figure 16 This is a schematic diagram used to describe a comparative example that does not include a control transistor. Figure 17 This is a schematic diagram illustrating a second embodiment including a control transistor.

[0139] like Figure 15 As shown, in a comparative example excluding the control transistor, whenever the fourth scan signal Sc4 with a high gate voltage is applied, a voltage ripple (Var ripple) may occur due to an increase in the second initialization voltage Var. This voltage ripple (Var ripple) can cause horizontal moiré patterns that affect the image quality of the horizontal lines.

[0140] Figure 15 The voltage ripple (Var ripple) shown may not appear in a single horizontal line direction, and may appear continuously in the horizontal line of the fourth scan signal Sc4 where a high gate voltage is applied. This can be referenced. Figure 16 The fourth scan signal Sc4(1) of the first horizontal line, the fourth scan signal Sc4(5) of the fifth horizontal line, and the fourth scan signal Sc4(9) of the ninth horizontal line are shown.

[0141] Therefore, the voltage ripple (Var ripple) shown in the comparative example can continuously appear in the horizontal line of the fourth scan signal Sc4, to which a high gate voltage is applied, and as a result, horizontal moiré patterns that affect the image quality of the horizontal line may occur (see Figure 16 "Var Ripple O -> Horizontal Mura O"

[0142] On the other hand, the second embodiment can use a control transistor to block the coupling effect of the increase in the second initialization voltage Var whenever the fourth scan signal Sc4 is applied, and thus can prevent the occurrence of voltage ripple (Var ripple) and horizontal moiré patterns (see [link]). Figure 17The process involves "Var Ripple X -> Horizontal Mura X". Therefore, a control transistor can be set for each horizontal line to prevent horizontal mura from occurring.

[0143] Furthermore, the period during which the second initialization voltage Var is applied can be defined as the initialization period. Therefore, it can be described that the control transistor has an off state during each initialization period when the second initialization voltage Var is applied.

[0144] In the following description of the third embodiment, the configuration that differs from the second embodiment will be described primarily. Therefore, refer to Figure 3 For configurations not described, please refer to the description of the second embodiment.

[0145] Figure 18 This is an exemplary schematic diagram illustrating the control transistor controlling the output of the anode initialization voltage according to the third embodiment and the elements included in the sub-pixel. Figure 19 and Figure 20 Based on Figure 18 An exemplary driving waveform diagram of a display panel implemented by subpixels.

[0146] According to the third embodiment, the control transistor TR_VAR may include a gate electrode connected to the N-1 scan line SC1(nx) to which the N-1 scan signal is applied, a first electrode connected to the second initialization voltage line VaralL to which the second initialization voltage is applied, and a second electrode connected to the first electrode of the sixth transistor T6 included in the sub-pixel P.

[0147] based on Figure 18 The display panel implemented by the sub-pixel P can be based on Figure 19 The driving waveform shown is used to drive in the first driving mode, and furthermore, it can be based on... Figure 20 The driving waveform shown is used to drive in the second driving mode.

[0148] like Figure 19 and Figure 20 As shown, the transmit control signal Em(n), the first scan signal Sc1(n), the second odd scan signal Sc2(n)_O, the second even scan signal Sc2(n)_E, the third scan signal Sc3(n) and the fourth scan signal Sc4(n) can be formed based on the gate high voltage Vgh and the gate low voltage Vgl, and can be changed based on the driving mode.

[0149] like Figure 18 and Figure 19As shown, based on the (N-1)th scan signal Sc1(nx), the control transistor TR_VAR can be in a turned-off (TR_VAR off) state during the period of the fourth scan signal Sc4(n) when a gate high voltage Vgh is applied. The (N-1)th scan signal Sc1(nx) can correspond to the first scan signal of the front-end horizontal line, which is generated with a gate high voltage before the first scan signal Sc1(n).

[0150] Figure 21 This is an exemplary schematic diagram illustrating the control transistor controlling the output of the anode initialization voltage according to the fourth embodiment and the elements included in the sub-pixel. Figure 22 and Figure 23 Based on Figure 21 An exemplary driving waveform diagram of a display panel implemented by subpixels.

[0151] According to the fourth embodiment, the control transistor TR_VAR may include a gate electrode connected to a control scan line SCV(n) to which a separate control scan signal Scv(n) is applied, a first electrode connected to a second initialization voltage line VaralL to which a second initialization voltage is applied, and a second electrode connected to the first electrode of a sixth transistor T6 included in the sub-pixel P.

[0152] based on Figure 21 The display panel implemented by the sub-pixel P can be based on Figure 22 The driving waveform shown is used to drive in the first driving mode, and furthermore, it can be based on... Figure 23 The driving waveform shown is used to drive in the second driving mode.

[0153] like Figure 22 and Figure 23 As shown, the transmit control signal Em(n), the first scan signal Sc1(n), the second odd scan signal Sc2(n)_O, the second even scan signal Sc2(n)_E, the third scan signal Sc3(n) and the fourth scan signal Sc4(n) can be formed based on the gate high voltage Vgh and the gate low voltage Vgl, and can be changed based on the driving mode.

[0154] like Figures 21 to 23 As shown, based on a separate control scan signal Scv(n), the control transistor TR_VAR can be in an off (TR_VAR off) state during the period of the fourth scan signal Sc4(n) when a high gate voltage Vgh is applied. Furthermore, the control scan signal Scv(n) can be generated to block the coupling effect with the third scan signal Sc3(n) when a low gate voltage Vgl is applied. For example, the control scan signal Scv(n) can be generated to have a low gate voltage Vgl at a time equal to or similar to the time of the third scan signal Sc3(n).

[0155] exist Figure 22 An example is shown where a control scan signal Scv(n) is first generated with a gate high voltage Vgh, followed by a fourth scan signal Sc4(n) with a gate high voltage Vgh. The fourth scan signal Sc4(n) is then shifted to a gate low voltage Vgl, and subsequently, the control scan signal Scv(n) is also shifted to a gate low voltage Vgl. However, this disclosure is not limited to this. That is, the generation and termination times of the gate high voltage Vgh of the control scan signal Scv(n) can be synchronized with the generation and termination times of the gate high voltage Vgh of the fourth scan signal Sc4(n).

[0156] exist Figure 22 and Figure 23 The example shown illustrates that the generation and end times of the gate low voltage Vgl of the control scan signal Scv(n) are different from those of the gate low voltage Vgl of the third scan signal Sc3(n), but this disclosure is not limited thereto. That is, the generation and end times of the gate low voltage Vgl of the control scan signal Scv(n) can be synchronized with the generation and end times of the gate low voltage Vgl of the third scan signal Sc3(n).

[0157] In the foregoing, this disclosure provides a display device that can block the coupling effect between the initialization voltage applied through the anode electrode of a light-emitting device and the scanning signal applied by a neighboring light-emitting device, thereby preventing voltage ripple and enabling the stable application of the initialization voltage. Furthermore, this disclosure provides a display device that allows for the stable application of the initialization voltage and thus prevents the occurrence of horizontal moiré patterns (image quality defects with horizontal lines), thereby improving display quality.

[0158] The effects of this disclosure are not limited to the examples above, and various other effects may be included in this specification.

[0159] While this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A display device, comprising: A display panel, the display panel including sub-pixels; A scan driver configured to apply at least one scan signal to the display panel; A data driver configured to apply a data voltage to the display panel; An initialization voltage line is connected to the sub-pixel; as well as A control transistor configured to control whether an initialization voltage is applied through the initialization voltage line.

2. The display device according to claim 1, wherein, When the at least one scan signal is applied as a voltage to turn on the transistor, the control transistor is turned off to cut off the supply of the initialization voltage.

3. The display device according to claim 2, wherein, The at least one scan signal is applied to the display panel via at least one scan line, and the initialization voltage line includes an area configured to overlap with the at least one scan line.

4. The display device according to claim 1, wherein, The control transistor is located in the non-display area of ​​the display panel where no image is displayed.

5. The display device according to claim 3, wherein, The sub-pixel includes p-type transistors and n-type transistors. The at least one scan line includes a scan line A controlling the p-type transistor and a scan line B controlling the n-type transistor, and The control transistor is turned on or off based on the B-th scan signal applied through the B-th scan line.

6. The display device according to claim 1, wherein, The sub-pixel includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The at least one scan line includes a first scan line controlling the first transistor, a second scan line controlling the second transistor, a third scan line controlling the sixth and seventh transistors, and a fourth scan line controlling the fifth transistor. The control transistor is turned on or off based on a third scan signal applied through the third scan line.

7. The display device according to claim 6, wherein, The initialization voltage line includes a region that is configured to overlap with the fourth scan line.

8. The display device according to claim 7, wherein, When a fourth scan signal with a high gate voltage is applied through the fourth scan line, the control transistor is turned off to cut off the supply of the initialization voltage.

9. A driving method for a display device, the driving method comprising: The step of applying a scan signal by connecting at least one scan line to the display panel; The step of applying a data voltage via a data line connected to the display panel; as well as The initialization voltage is applied by connecting the initialization voltage line to the sub-pixel. The step of applying the initialization voltage includes: cutting off the supply of the initialization voltage when the scan signal is applied as a voltage for turning on the transistors included in the display panel.

10. The driving method according to claim 9, wherein, The initialization voltage line includes a region configured to overlap with the at least one scan line.

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