Control method of display panel, display panel

Abstract

This application discloses a control method for a display panel and a display panel itself. The control method includes: acquiring the modulation frequency, modulation depth, and panel refresh rate configured by a spread spectrum clock generator; determining the falling edge offset of the clock signal for the pixel driving circuit of each row based on the modulation frequency, modulation depth, and panel refresh rate; adjusting the rising edge timing of the data signal based on the falling edge offset and / or adjusting the voltage amplitude of the data signal based on the falling edge offset; and outputting the adjusted data signal to a source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal. By employing the above method, the occurrence of water ripples on the display panel during the spread spectrum process can be reduced.

Description

Technical Field

[0001] This application relates to the field of panel display technology, and in particular to control methods for display panels and display panels. Background Technology

[0002] Currently, to reduce electromagnetic interference (EMI) generated by high-order harmonics in digital and clock signals within and between electronic systems, spread-spectrum clock generators (SSCGs) are typically used to disperse the energy of the clock signal. However, spreading the clock signal also introduces problems. The larger the spread amplitude of the spread-spectrum clock, the better the EMI reduction effect. But frequency variations in the clock signal can cause jitter in the charging time of the display panel. This difference in charging time for each row of pixel driving circuits leads to variations in brightness, resulting in a wavy effect. Summary of the Invention

[0003] The control method and display panel provided in this application can reduce the occurrence of water ripple phenomenon on the display panel during the spread spectrum process.

[0004] In a first aspect, this application provides a control method for a display panel, the control method comprising: acquiring a modulation frequency and a panel refresh rate configured by a spread spectrum clock generator; determining a falling edge offset of the clock signal for the pixel driving circuit of each row according to the modulation frequency and the panel refresh rate; adjusting the rising edge timing of the data signal according to the falling edge offset and / or adjusting the voltage amplitude of the data signal according to the falling edge offset; and outputting the adjusted data signal to a source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal.

[0005] The step of determining the falling edge offset of the clock signal for each row of the pixel driving circuit based on the modulation frequency and the panel refresh rate includes: determining the start time of the clock signal for each row of the pixel driving circuit using the panel refresh rate and the total number of rows of the pixel driving circuit; and determining the falling edge offset of the clock signal for each row of the pixel driving circuit using the start time of each row and the modulation frequency.

[0006] The process of determining the start time of the clock signal for the pixel driving circuit of each row by using the panel refresh rate and the total number of rows of pixel driving circuits includes: determining the refresh time using the panel refresh rate; calculating a first ratio between the refresh time and the total number of rows of pixel driving circuits; and determining the start time of the clock signal for the pixel driving circuit of each row by using the order of each row and the first ratio.

[0007] The method of determining the falling edge offset of the clock signal of the pixel driving circuit for each row using the start time and modulation frequency of each row includes: calculating the total product of the start time, modulation frequency and 2π for each row; calculating the sine value of the total product; and determining the falling edge offset of the clock signal of the pixel driving circuit for each row based on the sine value, modulation frequency and clock path delay calibration coefficient.

[0008] The step of adjusting the rising edge timing of the data signal based on the falling edge offset includes: acquiring the rising edge timing of the data signal and the falling edge timing of the clock signal; determining the time difference between the rising edge timing of the data signal and the falling edge timing of the clock signal; and adjusting the rising edge timing of the data signal using the falling edge offset and the time difference.

[0009] The step of adjusting the voltage amplitude of the data signal based on the falling edge offset includes: obtaining the charging time corresponding to the pixel driving circuit and the default voltage amplitude of the data signal; determining the compensation coefficient using the falling edge offset and the charging time; and adjusting the default voltage amplitude using the compensation coefficient.

[0010] The compensation coefficient is determined using the falling edge offset and charging time, including: obtaining the Gamma curve fitting coefficient of the display panel; calculating the second ratio between the falling edge offset and the charging time; calculating the product of the Gamma curve fitting coefficient and the second ratio; and determining the compensation coefficient by adding 1 to the product.

[0011] The method further includes adjusting the voltage amplitude of the data signal according to the falling edge offset when the rising edge timing of the data signal is constrained based on the falling edge offset.

[0012] The adjustment of the rising edge timing of the data signal based on the falling edge offset and the adjustment of the voltage amplitude of the data signal based on the falling edge offset include: adjusting the rising edge timing of the data signal using a portion of the falling edge offset, and adjusting the voltage amplitude of the data signal using the remaining portion of the falling edge offset.

[0013] In a second aspect, this application provides a display panel, which includes a timing control circuit, a gate control circuit, a source control circuit, and a driving array composed of multiple pixel driving circuits; the timing control circuit is electrically connected to the gate control circuit and the source control circuit, respectively, and the gate control circuit and the source control circuit are electrically connected to the driving array, respectively; the timing control circuit is used to implement the method provided in the first aspect.

[0014] Thirdly, this application provides a computer-readable storage medium for storing a computer program, which, when executed by a processor, is used to implement the method provided in the first aspect.

[0015] The beneficial effects of this application are as follows: Unlike the prior art, the display panel control method and display panel provided in this application obtain the modulation frequency and panel refresh rate configured by the spread spectrum clock generator; determine the falling edge offset of the clock signal of the pixel driving circuit of each row according to the modulation frequency and panel refresh rate; adjust the rising edge timing of the data signal according to the falling edge offset to make the charging time of the inter-row pixel driving circuit uniform, and / or adjust the voltage amplitude of the data signal according to the falling edge offset to make the brightness of the inter-row pixel driving circuit uniform, and then output the adjusted data signal to the source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal, which can reduce the occurrence of water ripple phenomenon on the display panel during the spread spectrum process. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 These are schematic diagrams of the waveforms before and after signal modulation provided in this application; Figure 2 This is a schematic diagram of the waveform of the clock signal provided in this application before and after it is spread-spectrum processed by the spread-spectrum clock generator; Figure 3 This is a schematic diagram showing the charging time jitter after the clock signal is spread-spectrum processed by the spread-spectrum clock generator provided in this application; Figure 4 This is a schematic diagram illustrating the relationship between charging time and display panel brightness provided in this application; Figure 5 This is a schematic diagram of water ripples appearing on the display panel provided in this application; Figure 6 This is a flowchart illustrating an embodiment of the display panel control method provided in this application; Figure 7 yes Figure 6 A flowchart illustrating an embodiment of step 62; Figure 8 yes Figure 7 A flowchart of an embodiment of step 71; Figure 9 yes Figure 7 A flowchart illustrating an embodiment of step 72; Figure 10 This is a flowchart illustrating another embodiment of the control method for the display panel provided in this application; Figure 11This is a schematic diagram of the waveform after the rising edge timing of the adjusted data signal provided in this application; Figure 12 This is a flowchart illustrating another embodiment of the control method for the display panel provided in this application; Figure 13 yes Figure 12 A flowchart illustrating an embodiment of step 124; Figure 14 This is a schematic diagram of the waveform after adjusting the voltage amplitude of the data signal provided in this application; Figure 15 This is a flowchart illustrating another embodiment of the control method for the display panel provided in this application; Figure 16 This is a schematic diagram of the structure of an embodiment of the display panel provided in this application; Figure 17 This is a schematic diagram of an embodiment of the computer-readable storage medium provided in this application.

[0017] Annotation instructions: Display panel: 160; Timing control circuit: 161; Gate control circuit: 162; Source control circuit: 163; Drive array: 164; Computer readable storage medium: 170; Computer program: 171; Clock signals: CK1, CK2, CK3; Charging time: T1, T2, T3. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0019] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0020] Currently, to reduce electromagnetic interference (EMI) generated by high-order harmonics in digital and clock signals within and between electronic systems, spread-spectrum clock generators (SSCGs) are typically used to disperse the energy of the clock signal. However, spreading the clock signal also introduces problems. The larger the spread amplitude of the spread-spectrum clock, the better the EMI reduction effect. But frequency variations in the clock signal can cause jitter in the charging time of the display panel. This difference in charging time for each row of pixel driving circuits leads to variations in brightness, resulting in a wavy effect.

[0021] like Figure 1 As shown, to improve electromagnetic interference, the internal frequency modulation of the timing control circuit fluctuates within a certain range. For example... Figure 1 The left side shows a schematic diagram of the waveform before internal frequency modulation of the timing control circuit. For example... Figure 1 The diagram on the right shows the waveform after internal frequency modulation of the timing control circuit. That is, the waveform after modulation using a triangular wave.

[0022] The backlight driver of the display panel is related to the internal frequency of the display screen and the timing control circuit. When the internal frequency of the timing control circuit fluctuates regularly within a certain range, it causes charging time jitter. This results in different charging times for each row, leading to different brightness and thus producing a water ripple effect. Specifically, as shown below... Figure 2 , Figure 3 , Figure 4 and Figure 5 As shown. Figure 2 This demonstrates the changes in clock signals CK1, CK2, and CK3 after they have been spread-spectrum processed by the spread-spectrum clock generator. For example... Figure 2 As shown, before the spread spectrum processing, the charging time of clock signal CK1 is T1; after the spread spectrum processing, the charging time of clock signal CK1 is T2. Clock signals CK2 and CK3 will also change from charging time T1 to other charging times. This results in different charging times for each row, leading to different brightness and thus producing water ripples. Figure 2 In this context, SSCG represents a triangular wave signal. Figure 3 The diagram illustrates the jitter in charging time after the clock signal is spread-spectrum processed by the spread-spectrum clock generator. Figure 4 It demonstrates the relationship between charging time and display panel brightness. Figure 5 The illustration shows a water ripple pattern appearing on the display panel.

[0023] Based on this, the display panel control method and display panel provided in this application acquire the modulation frequency and panel refresh rate configured by the spread spectrum clock generator; determine the falling edge offset of the clock signal of the pixel driving circuit of each row according to the modulation frequency and panel refresh rate; adjust the rising edge timing of the data signal according to the falling edge offset to uniformize the charging time of the inter-row pixel driving circuit, and / or adjust the voltage amplitude of the data signal according to the falling edge offset to uniformize the brightness of the inter-row pixel driving circuit, and then output the adjusted data signal to the source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal, which can reduce the occurrence of water ripple phenomenon on the display panel during the spread spectrum process. See the technical solutions of any of the following embodiments for details.

[0024] See Figure 6 , Figure 6 This is a flowchart illustrating an embodiment of the control method for a display panel provided in this application. The display panel includes a gate control circuit, a source control circuit, and a driving array composed of multiple pixel driving circuits; the gate control circuit and the source control circuit are electrically connected to the driving array; the gate control circuit and the source control circuit are respectively used to receive a clock signal, and together charge the pixel driving circuit corresponding to each row according to the clock signal. The control method includes: Step 61: Obtain the modulation frequency and panel refresh rate configured for the spread spectrum clock generator.

[0025] A spread-spectrum clock generator (SSCG) is an electronic device that reduces electromagnetic interference (EMI) in digital chips through frequency modulation. Its core principle is to periodically jitter the clock signal, distributing energy across a specific frequency band to reduce spectral peaks. The modulation waveform typically uses a triangular wave or a Hershey-Kiss curve. This technology has three spread-spectrum types: down-spread, center-spread, and up-spread, with a spread rate range down to -2.5%, and modulation frequencies mostly in the 30kHz range. The device is usually implemented based on a phase-locked loop (PLL) architecture, using modulation of the charge pump current or voltage-controlled oscillator (VCO) to control the voltage and achieve frequency spread. Key parameters include spread amount, modulation frequency, and PLL bandwidth. Employing a fully differential charge pump structure and a passive low-pass filter can improve current mismatch issues.

[0026] In some embodiments, the modulation depth of the spread spectrum clock generator configuration can also be obtained. This modulation depth is a key parameter measuring the magnitude of clock frequency jitter, directly affecting electromagnetic interference (EMI) suppression and spectral distribution characteristics. Modulation depth is typically expressed as a percentage, representing the ratio of the maximum clock frequency offset to the original frequency. For example, a 100MHz clock spread down with a modulation depth of -1% will have an output frequency range of 99MHz to 100MHz.

[0027] In some embodiments, when the display panel has the spread spectrum function enabled, step 61 is performed.

[0028] Step 62: Determine the falling edge offset of the clock signal for the pixel driving circuit of each row based on the modulation frequency and panel refresh rate.

[0029] Since the modulation frequency of the spread spectrum clock generator and the panel refresh rate are determined, the falling edge offset of the clock signal for each row of pixel driving circuits can be calculated.

[0030] In some embodiments, see Figure 7 Step 62 can be the following process: Step 71: Using the panel refresh rate and the total number of rows of the pixel driving circuit, determine the start time of the clock signal for the pixel driving circuit of each row.

[0031] In some embodiments, see Figure 8 Step 71 can be the following process: Step 81: Determine the refresh time using the panel refresh rate.

[0032] In some embodiments, the reciprocal of the panel refresh rate is calculated, and the calculated reciprocal is used as the refresh time.

[0033] Step 82: Calculate the first ratio between the refresh time and the total number of rows of the pixel driving circuit.

[0034] In some embodiments, a first ratio is obtained by dividing the refresh time by the total number of rows of the pixel driving circuit.

[0035] Step 83: Using the order of each row and the first ratio, determine the start time of the clock signal for the pixel driving circuit of each row.

[0036] In some embodiments, the start time of the clock signal for the pixel driving circuit of each row can be obtained by multiplying the order of each row by a first ratio.

[0037] In some embodiments, steps 81 to 83 can be represented by the following formulas: ; . Indicates the first The start time of the clock signal for the pixel driving circuit of the row. Indicates the refresh time. Indicates the panel refresh rate. This indicates the total number of rows in the pixel driving circuit.

[0038] Step 72: Determine the falling edge offset of the clock signal for the pixel driving circuit of each row using the start time, modulation frequency, and modulation depth of each row.

[0039] In some embodiments, see Figure 9 Step 72 can be the following process: Step 91: Calculate the total product of the start time, modulation frequency, and 2π for each row.

[0040] Step 92: Calculate the sine of the total product.

[0041] Step 93: Determine the falling edge offset of the clock signal for each row of the pixel driving circuit based on the sine value, modulation frequency, and clock path delay calibration coefficient.

[0042] In some embodiments, the ratio between the modulation frequency and the clock signal frequency can be determined. This ratio is then multiplied by the modulation frequency and then by the clock path delay calibration factor to obtain the falling edge offset of the clock signal for each row of pixel driving circuits.

[0043] In some embodiments, steps 91 to 93 can be represented by the following formulas: .

[0044] in, This represents the falling edge offset of the clock signal for the pixel driving circuit in the i-th row. Indicates the modulation frequency. Indicates the frequency of the clock signal. This indicates the start time of the clock signal for the pixel driving circuit in each row i. This represents the clock path delay calibration factor.

[0045] Step 63: Adjust the rising edge timing of the data signal according to the falling edge offset and / or adjust the voltage amplitude of the data signal according to the falling edge offset.

[0046] In some embodiments, the rising edge timing of the data signal is adjusted according to a falling edge offset. For example, the rising edge timing of the data signal can be offset by a falling edge offset to keep the charging time of the pixel driving circuit in the corresponding row constant. Based on this, the charging time of the pixel driving circuit in adjacent rows will also be constant.

[0047] In some embodiments, the voltage amplitude of the data signal is adjusted based on the falling edge offset. The ripple effect occurs because after the clock signal is spread-spectrum processed, the clock signal for each row shifts, causing inconsistencies in the charging time of the pixel driving circuits in adjacent rows. This manifests as differences in brightness, thus producing the ripple effect. Therefore, adjusting the voltage amplitude of the data signal based on the falling edge offset compensates for the voltage amplitude of the data signal, thereby compensating for the brightness of the corresponding pixel driving circuits and making the brightness of the pixel driving circuits in adjacent rows more similar, thus reducing the ripple effect on the display panel.

[0048] In some embodiments, the rising edge timing of the data signal is adjusted according to the falling edge offset, and the voltage amplitude of the data signal is adjusted according to the falling edge offset.

[0049] For example, by adjusting both the rising edge timing and the voltage amplitude of the data signal according to the falling edge offset, the two methods can be combined to compensate for both charging time and brightness, thereby reducing the water ripple phenomenon on the display panel.

[0050] Step 64: Output the adjusted data signal to the source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal.

[0051] In this embodiment, the modulation frequency and panel refresh rate configured by the spread spectrum clock generator are obtained; the falling edge offset of the clock signal of the pixel driving circuit of each row is determined according to the modulation frequency and panel refresh rate; the rising edge timing of the data signal is adjusted according to the falling edge offset to make the charging time of the inter-row pixel driving circuit uniform, and / or the voltage amplitude of the data signal is adjusted according to the falling edge offset to make the brightness of the inter-row pixel driving circuit uniform, and then the adjusted data signal is output to the source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal, which can reduce the occurrence of water ripple phenomenon on the display panel during the spread spectrum process.

[0052] In some embodiments, the control method for the display panel provided in this application is performed in a frame-by-frame manner. For example, in the first frame, the rising edge timing of the data signal is calculated based on the falling edge offset and / or the voltage amplitude of the data signal is calculated based on the falling edge offset as described above. Then, in the second frame or several subsequent frames, the rising edge timing of the data signal is adjusted and / or the voltage amplitude of the data signal is adjusted. This can avoid the situation where the adjustment is not timely within a single frame, and can also reduce the amount of calculation, reduce the load on the controller, and reduce heat generation. A more specific implementation involves the following steps: In the first frame, the modulation frequency and panel refresh rate configured by the spread spectrum clock generator are first acquired. Then, the falling edge offset of the clock signal for each row's pixel driving circuit is determined based on the modulation frequency and the panel refresh rate. The timing controller calculates the rising edge timing of the data signal to be adjusted based on the falling edge offset, or the timing controller calculates the voltage amplitude of the data signal to be adjusted based on the falling edge offset, or the timing controller calculates both the rising edge timing and the voltage amplitude of the data signal to be adjusted based on the falling edge offset. In the second frame, the data signal calculated in the first frame (including the rising edge timing and / or voltage amplitude of the data signal) is output to the source control circuit. The source control circuit controls the pixel driving circuit of the corresponding row according to the aforementioned data signal. In high or ultra-high refresh rate scenarios, the time allotted for each row of pixels to be activated is very short (i.e., 1H; for example, for a 2250-row display panel, 1H at a 60Hz refresh rate is 7.4µs, while at a 144Hz refresh rate it's only 3.07µs). It's clear that the higher the refresh rate, the less time is allocated to each row of pixels. Therefore, there may not be enough time within a single frame. Frame-by-frame detection and processing prevents untimely adjustments within a single frame, avoiding data adjustment disorder. While this setting might slightly impact display quality, considering the continuity of the image, this setting and processing provides a better display effect than data adjustment disorder. Furthermore, at ultra-high refresh rates, the amount of data processing for the controller, processor, and the machine itself is enormous. Detection and calculation are performed continuously for each frame, further increasing the amount of data processing or calculation for the controller, processor, and the machine itself, and consequently increasing the heat generated by the controller, processor, and the machine itself. Therefore, by using frame-segmentation processing, some of the data processing or calculation can be reduced, thereby alleviating the data processing or load on the controller, processor, and the machine itself, and ensuring the stable operation of the display panel / machine while improving the display effect.

[0053] See Figure 10 , Figure 10This is a flowchart illustrating another embodiment of the control method for a display panel provided in this application. The display panel includes a gate control circuit, a source control circuit, and a driving array composed of multiple pixel driving circuits; the gate control circuit and the source control circuit are electrically connected to the driving array; the gate control circuit and the source control circuit are respectively used to receive a clock signal and, according to the clock signal, jointly charge the pixel driving circuit corresponding to each row. The control method includes: Step 101: Obtain the modulation frequency and panel refresh rate configured for the spread spectrum clock generator.

[0054] Step 102: Determine the falling edge offset of the clock signal for the pixel driving circuit of each row based on the modulation frequency and panel refresh rate.

[0055] In some embodiments, steps 101 to 102 can refer to the scheme of any embodiment of this application, and will not be described in detail here.

[0056] Step 103: Obtain the rising edge timing of the data signal and the falling edge timing of the clock signal.

[0057] In some embodiments, the rising edge of the data signal and the falling edge of the clock signal can be obtained.

[0058] It is understandable that the falling edge of the clock signal here refers to the falling edge of the clock signal after it has been spread spectrum processed.

[0059] In some embodiments, each row of pixel driving circuits corresponds to a clock signal after spread spectrum processing, so the falling edge timing of the clock signal and the rising edge timing of the corresponding data signal of each row can be obtained in the form of rows.

[0060] Step 104: Determine the time difference between the rising edge timing of the data signal and the falling edge timing of the clock signal.

[0061] In some embodiments, the time difference is obtained by subtracting the falling edge timing of the clock signal from the rising edge timing of the data signal. The duration corresponding to this time difference represents the charging time, that is, the charging time of the pixel driving circuit of each row before adjustment.

[0062] Step 105: Adjust the rising edge timing of the data signal using the falling edge offset and time difference.

[0063] After determining the time difference, the rising edge timing of the data signal can be adjusted by compensating for the time difference using the falling edge offset.

[0064] This process is equivalent to synchronously offsetting the rising edge timing of the data signal according to the falling edge offset of the clock signal, thereby offsetting the change in charging time caused by the falling edge offset of the clock signal.

[0065] In some embodiments, combined with Figure 11 Explanation: After determining the falling edge offset, the data signal is then synchronized ( Figure 11 The data in the middle is synchronized and offset to ensure the charging time ( Figure 11 Charge time is constant. Figure 11 The fluctuation in the charging time of the multi-row pixel driving circuit is reflected in the data signal timing, which is adjusted to keep the actual charging time constant. Figure 11 In this context, TP represents the control signal of the display screen, and CKV represents the field shift pulse signal, which is mainly used to control the clock signal in the vertical direction (V direction) of the screen.

[0066] Step 106: Output the adjusted data signal to the source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal.

[0067] In this embodiment, the modulation frequency and panel refresh rate configured by the spread spectrum clock generator are obtained; the falling edge offset of the clock signal of the pixel driving circuit of each row is determined according to the modulation frequency and panel refresh rate; the rising edge timing of the data signal is adjusted according to the falling edge offset to make the charging time of the inter-row pixel driving circuit uniform, and then the adjusted data signal is output to the source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal, which can reduce the occurrence of water ripple phenomenon on the display panel during the spread spectrum process.

[0068] See Figure 12 , Figure 12 This is a flowchart illustrating another embodiment of the control method for a display panel provided in this application. The display panel includes a gate control circuit, a source control circuit, and a driving array composed of multiple pixel driving circuits; the gate control circuit and the source control circuit are electrically connected to the driving array; the gate control circuit and the source control circuit are respectively used to receive a clock signal and, according to the clock signal, jointly charge the pixel driving circuit corresponding to each row. The control method includes: Step 121: Obtain the modulation frequency and panel refresh rate configured for the spread spectrum clock generator.

[0069] Step 122: Determine the falling edge offset of the clock signal for the pixel driving circuit of each row based on the modulation frequency and panel refresh rate.

[0070] In some embodiments, steps 121 to 122 can refer to the scheme of any embodiment of this application, and will not be described in detail here.

[0071] Step 123: Obtain the charging time and default voltage amplitude of the data signal corresponding to the pixel driving circuit.

[0072] The charging time refers to the default charging time when the clock signal is not spread spectrum processed, and this charging time is a fixed duration.

[0073] Step 124: Determine the compensation coefficient using the falling edge offset and charging time.

[0074] In some embodiments, see Figure 13 Step 124 can be the following process: Step 131: Obtain the Gamma curve fitting coefficients of the display panel.

[0075] In some embodiments, the Gamma curve fitting coefficient of the display panel typically refers to an exponential parameter describing the relationship between brightness and the input signal, with the core being the Gamma value (γ). The standard Gamma value is 2.2, which aligns with the non-linear perception of brightness by the human eye.

[0076] Step 132: Calculate the second ratio between the falling edge offset and the charging time.

[0077] In some embodiments, the charging duration refers to the default charging duration when the clock signal is not spread spectrum processed, and the charging duration is a fixed duration.

[0078] In some embodiments, the quotient obtained by dividing the falling edge offset by the charging duration can be used as a second ratio.

[0079] Step 133: Calculate the product of the Gamma curve fitting coefficient and the second ratio.

[0080] In some embodiments, the corresponding product can be obtained by multiplying the Gamma curve fitting coefficient by a second ratio.

[0081] Step 134: Determine the compensation coefficient by adding 1 to the product.

[0082] In some embodiments, 1 plus the sum of the products can be used as a compensation coefficient.

[0083] In some embodiments, the compensation coefficient can be calculated using the following formula: .

[0084] in, Indicates the compensation coefficient. Represents the fitting coefficients of the Gamma curve. This represents the falling edge offset of the pixel driving circuit in the i-th row. Indicates charging time.

[0085] Step 125: Adjust the default voltage amplitude using the compensation coefficient.

[0086] In some embodiments, the adjusted voltage amplitude of the data signal is obtained by multiplying the compensation coefficient by the default voltage amplitude of the data signal.

[0087] In some embodiments, the following formula can be used to calculate: .in, This represents the adjusted voltage amplitude of the data signal. This indicates the default voltage amplitude of the data signal. This represents the compensation coefficient.

[0088] In some embodiments, combined with Figure 14 Explanation: After determining the falling edge offset, the data signal is then synchronized ( Figure 14 The voltage amplitude of the Data in the image is adjusted to compensate for brightness differences. Figure 14 The fluctuation in the charging time of the multi-row pixel driving circuit is reflected in the data signal voltage amplitude adjustment to compensate for brightness differences. Figure 14 In this context, TP represents the control signal of the display screen, and CKV represents the field shift pulse signal, which is mainly used to control the clock signal in the vertical direction (V direction) of the screen.

[0089] Step 126: Output the adjusted data signal to the source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal.

[0090] In this embodiment, the modulation frequency and panel refresh rate configured by the spread spectrum clock generator are obtained; the falling edge offset of the clock signal of the pixel driving circuit of each row is determined according to the modulation frequency and panel refresh rate; the voltage amplitude of the data signal is adjusted according to the falling edge offset to make the brightness of the inter-row pixel driving circuit uniform, and then the adjusted data signal is output to the source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal, which can reduce the occurrence of water ripple phenomenon on the display panel during the spread spectrum process.

[0091] See Figure 15 , Figure 15 This is a flowchart illustrating another embodiment of the control method for a display panel provided in this application. The display panel includes a gate control circuit, a source control circuit, and a driving array composed of multiple pixel driving circuits; the gate control circuit and the source control circuit are electrically connected to the driving array; the gate control circuit and the source control circuit are respectively used to receive a clock signal and, according to the clock signal, jointly charge the pixel driving circuit corresponding to each row. The control method includes: Step 151: Obtain the modulation frequency and panel refresh rate configured for the spread spectrum clock generator.

[0092] Step 152: Determine the falling edge offset of the clock signal for the pixel driving circuit of each row based on the modulation frequency and panel refresh rate.

[0093] In some embodiments, steps 151 to 152 can refer to the scheme of any embodiment of this application, and will not be described in detail here.

[0094] Step 153: Adjust the rising edge timing of the data signal using a portion of the falling edge offset, and adjust the voltage amplitude of the data signal using the remaining portion of the falling edge offset.

[0095] In some embodiments, the timing control circuit can be used to determine the accuracy of the timing control circuit. When the accuracy of the timing control circuit is limited, that is, when the rising edge timing of the data signal is limited according to the falling edge offset, the voltage amplitude of the data signal is adjusted according to the falling edge offset, thereby making the brightness of the inter-row pixel driving circuit uniform.

[0096] In some embodiments, both the rising edge timing and the voltage amplitude of the data signal can be adjusted. For example, the falling edge offset can be divided according to the control precision of the timing control circuit. A portion of the falling edge offset is used to adjust the rising edge timing of the data signal, and the remaining portion is used to adjust the voltage amplitude of the data signal. Specific adjustment methods are described in any of the above embodiments. This approach allows for parallel processing of the two adjustment methods, improving processing efficiency and accelerating the formation of the data signal. The adjusted data signal is then output to the source control circuit, enabling the source control circuit to control the pixel driving circuit of the corresponding row according to the data signal. The entire process has less latency and can reduce the occurrence of water ripple effects on the display panel during spread spectrum processing.

[0097] In some embodiments, after calculating the falling edge offset of the current row, it is first determined whether the rising edge timing of the data signal can be adjusted entirely based on the falling edge offset. If so, the rising edge timing of the data signal is adjusted directly based on the falling edge offset. If not, the rising edge timing of the data signal is adjusted using a portion of the falling edge offset according to the maximum adjustment capability of the timing control circuit, and the voltage amplitude of the data signal is adjusted using the remaining portion of the falling edge offset, thus combining them into a new data signal.

[0098] In some embodiments, the weights of the rising edge timing of the adjusted data signal and the falling edge offset of the adjusted voltage amplitude can be pre-set. The falling edge offset is then divided according to these weights, and the rising edge timing and voltage amplitude of the data signal are adjusted according to their respective falling edge offsets, thus combining them into a new data signal. For example, the weight of the falling edge offset of the rising edge timing of the adjusted data signal is 'a', and the weight of the falling edge offset of the adjusted voltage amplitude is 'b'. Where a + b = 1, a > 0, and b > 0. For example, if the weight of the falling edge offset of the rising edge timing of the adjusted data signal is 0.5, then the weight of the falling edge offset of the adjusted voltage amplitude is also 0.5. Similarly, if the weight of the falling edge offset of the rising edge timing of the adjusted data signal is 0.2, then the weight of the falling edge offset of the adjusted voltage amplitude is 0.8. For example, if the weight of the falling edge offset of the rising edge timing of the data signal is 0.4, then the weight of the falling edge offset of the voltage amplitude of the data signal is 0.6.

[0099] In this embodiment, the data signal is adjusted from two angles (rising edge timing and voltage amplitude). On the one hand, the calculation process can be parallelized, improving the efficiency of data signal adjustment. On the other hand, it can avoid the failure of data signal adjustment from a single angle. For example, the failure of the calculation program corresponding to the rising edge timing adjustment will cause the data signal adjustment to fail. By adjusting from two angles, the probability of failure is reduced equally. Even if one fails, the other still has some adjustment, thereby effectively reducing the occurrence of water ripple phenomenon on the display panel during the spread spectrum process.

[0100] Step 154: Output the adjusted data signal to the source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal.

[0101] In this embodiment, the modulation frequency and panel refresh rate configured by the spread spectrum clock generator are obtained; the falling edge offset of the clock signal of the pixel driving circuit of each row is determined according to the modulation frequency and panel refresh rate; the rising edge timing of the data signal is adjusted using a portion of the falling edge offset, and the voltage amplitude of the data signal is adjusted using the remaining portion of the falling edge offset, and then the adjusted data signal is output to the source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal, which can reduce the occurrence of water ripple phenomenon on the display panel during the spread spectrum process.

[0102] In some embodiments, for a 60Hz refresh rate panel, the SSCG parameter... . Indicates the modulation depth.

[0103] Pre-read parameters, calculate . Indicates the modulation period.

[0104] Calculate the start time of the i-th row , .

[0105] calculate .

[0106] The adjustment plan is as follows: Option 1: Data rising edge compensation Output to compensate for the falling edge delay of CK (clock signal).

[0107] Option 2: Data output Equivalent compensation to make up for brightness differences.

[0108] Option 1 and Option 2 can be used in combination, which will not be elaborated here.

[0109] See Figure 16 , Figure 16 This is a schematic diagram of a display panel embodiment provided in this application. The display panel 160 includes a timing control circuit 161, a gate control circuit 162, a source control circuit 163, and a driving array 164 composed of multiple pixel driving circuits. The timing control circuit 161 is electrically connected to the gate control circuit 162 and the source control circuit 163, respectively. The gate control circuit 162 and the source control circuit 163 are electrically connected to the driving array 164, respectively. The timing control circuit 161 is used to implement the following method: Obtain the modulation frequency and panel refresh rate configured by the spread spectrum clock generator; determine the falling edge offset of the clock signal for each row's pixel driving circuit based on the modulation frequency and panel refresh rate; adjust the rising edge timing of the data signal and / or adjust the voltage amplitude of the data signal based on the falling edge offset; output the adjusted data signal to the source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal.

[0110] In some embodiments, the timing control circuit 161 is further configured to implement the following method: using the panel refresh rate and the total number of rows of the pixel driving circuit, determine the start time of the clock signal of the pixel driving circuit of each row; using the start time of each row and the modulation frequency, determine the falling edge offset of the clock signal of the pixel driving circuit of each row.

[0111] In some embodiments, the timing control circuit 161 is further configured to implement the following method: determining the refresh time using the panel refresh rate; calculating a first ratio between the refresh time and the total number of rows of the pixel driving circuit; and determining the start time of the clock signal of the pixel driving circuit for each row using the order of each row and the first ratio.

[0112] In some embodiments, the timing control circuit 161 is further configured to implement the following method: calculate the total product of the start time of each row, the modulation frequency, and 2π; calculate the sine value of the total product; and determine the falling edge offset of the clock signal of the pixel driving circuit for each row based on the sine value, the modulation frequency, and the clock path delay calibration coefficient.

[0113] In some embodiments, the timing control circuit 161 is further configured to implement the following method: acquiring the rising edge timing of the data signal and the falling edge timing of the clock signal; determining the time difference between the rising edge timing of the data signal and the falling edge timing of the clock signal; and adjusting the rising edge timing of the data signal using the falling edge offset and the time difference.

[0114] In some embodiments, the timing control circuit 161 is further configured to implement the following method: obtaining the charging duration and default voltage amplitude of the data signal corresponding to the pixel driving circuit; determining the compensation coefficient using the falling edge offset and the charging duration; and adjusting the default voltage amplitude using the compensation coefficient.

[0115] In some embodiments, the timing control circuit 161 is further configured to implement the following methods: obtaining the Gamma curve fitting coefficient of the display panel; calculating a second ratio between the falling edge offset and the charging duration; calculating the product of the Gamma curve fitting coefficient and the second ratio; and determining the compensation coefficient by adding 1 to the product.

[0116] In some embodiments, the timing control circuit 161 is further configured to implement the following method: when the rising edge timing of the data signal is constrained according to the falling edge offset, the voltage amplitude of the data signal is adjusted according to the falling edge offset.

[0117] In some embodiments, the timing control circuit 161 is further configured to implement the following methods: adjusting the rising edge timing of the data signal using a portion of the falling edge offset, and adjusting the voltage amplitude of the data signal using the remaining portion of the falling edge offset.

[0118] In some embodiments, the timing control circuit 161 is also used to implement the technical solutions of any embodiment of this application.

[0119] See Figure 17 , Figure 17This is a schematic diagram of an embodiment of the computer-readable storage medium provided in this application. The computer-readable storage medium 170 is used to store a computer program 171, which, when executed by a processor, implements the following methods: Obtain the modulation frequency, modulation depth, and panel refresh rate configured in the spread spectrum clock generator; determine the falling edge offset of the clock signal for each row's pixel driving circuit based on the modulation frequency, modulation depth, and panel refresh rate; adjust the rising edge timing of the data signal based on the falling edge offset and / or adjust the voltage amplitude of the data signal based on the falling edge offset; output the adjusted data signal to the source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal.

[0120] In some embodiments, when the computer program 171 is executed by the processor, it is further configured to implement the following method: determining the start time of the clock signal of the pixel driving circuit for each row using the panel refresh rate and the total number of rows of the pixel driving circuit; and determining the falling edge offset of the clock signal of the pixel driving circuit for each row using the start time of each row, the modulation frequency, and the modulation depth.

[0121] In some embodiments, when executed by a processor, the computer program 171 is further configured to implement the following method: determining a refresh time using the panel refresh rate; calculating a first ratio between the refresh time and the total number of rows of the pixel driving circuit; and determining the start time of the clock signal of the pixel driving circuit for each row using the order of each row and the first ratio.

[0122] In some embodiments, when executed by a processor, computer program 171 is further configured to implement the following methods: calculating the total product of the start time of each row, the modulation frequency, and 2π; calculating the sine value of the total product; and determining the falling edge offset of the clock signal of the pixel driving circuit for each row based on the sine value, the modulation frequency, and the clock path delay calibration coefficient.

[0123] In some embodiments, when the computer program 171 is executed by the processor, it is further configured to implement the following methods: acquiring the rising edge timing of the data signal and the falling edge timing of the clock signal; determining the time difference between the rising edge timing of the data signal and the falling edge timing of the clock signal; and adjusting the rising edge timing of the data signal using the falling edge offset and the time difference.

[0124] In some embodiments, when the computer program 171 is executed by the processor, it is further configured to implement the following methods: obtain the charging duration and default voltage amplitude of the data signal corresponding to the pixel driving circuit; determine the compensation coefficient using the falling edge offset and the charging duration; and adjust the default voltage amplitude using the compensation coefficient.

[0125] In some embodiments, when executed by a processor, computer program 171 is further configured to implement the following methods: obtaining the Gamma curve fitting coefficient of the display panel; calculating a second ratio between the falling edge offset and the charging duration; calculating the product of the Gamma curve fitting coefficient and the second ratio; and determining a compensation coefficient by adding 1 to the product.

[0126] In some embodiments, when executed by a processor, the computer program 171 is further configured to implement the method of adjusting the voltage amplitude of a data signal according to a falling edge offset when the rising edge timing of the data signal is constrained according to the falling edge offset.

[0127] In some embodiments, when executed by a processor, the computer program 171 is further configured to implement the following methods: adjusting the rising edge timing of a data signal using a portion of the falling edge offset, and adjusting the voltage amplitude of the data signal using the remaining portion of the falling edge offset.

[0128] In some embodiments, when executed by a processor, computer program 171 is also used to implement the methods of any of the above embodiments.

[0129] In summary, the display panel control method and display panel provided in this application acquire the modulation frequency and panel refresh rate configured by the spread spectrum clock generator; determine the falling edge offset of the clock signal of the pixel driving circuit of each row according to the modulation frequency and panel refresh rate; adjust the rising edge timing of the data signal according to the falling edge offset to uniformize the charging time of the inter-row pixel driving circuit, and / or adjust the voltage amplitude of the data signal according to the falling edge offset to uniformize the brightness of the inter-row pixel driving circuit, and then output the adjusted data signal to the source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal, which can reduce the occurrence of water ripple phenomenon on the display panel during the spread spectrum process.

[0130] In some embodiments, after adopting the technical solution of this application, the visibility of the water ripple on the display panel is reduced by 90%, and the SSCG modulation depth can be maintained at ±1.5% or more, with EMI peak attenuation ≥9dB.

[0131] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0132] If the integrated units in the other embodiments described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processing circuit component (processor) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0133] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for controlling a display panel, characterized in that, The control method includes: Obtain the modulation frequency and panel refresh rate configured for the spread spectrum clock generator; The falling edge offset of the clock signal for the pixel driving circuit of each row is determined based on the modulation frequency and the panel refresh rate. Adjust the rising edge timing of the data signal according to the falling edge offset and / or adjust the voltage amplitude of the data signal according to the falling edge offset; The adjusted data signal is output to the source control circuit so that the source control circuit controls the pixel driving circuit of the corresponding row according to the data signal.

2. The control method according to claim 1, characterized in that, The step of determining the falling edge offset of the clock signal for the pixel driving circuit of each row based on the modulation frequency and the panel refresh rate includes: Using the panel refresh rate and the total number of rows of the pixel driving circuit, the start time of the clock signal for the pixel driving circuit of each row is determined; The falling edge offset of the clock signal of the pixel driving circuit for each row is determined using the start time and the modulation frequency of each row.

3. The control method according to claim 2, characterized in that, The step of determining the start time of the clock signal for each row of the pixel driving circuit using the panel refresh rate and the total number of rows of the pixel driving circuit includes: The refresh rate of the panel is used to determine the refresh time; Calculate a first ratio between the refresh time and the total number of rows of the pixel driving circuit; Using the order of each row and the first ratio, the start time of the clock signal of the pixel driving circuit for each row is determined.

4. The control method according to claim 2 or 3, characterized in that, The step of determining the falling edge offset of the clock signal of the pixel driving circuit for each row using the start time and modulation frequency of each row includes: Calculate the total product of the start time, the modulation frequency, and 2π for each row; Calculate the sine of the total product; The falling edge offset of the clock signal for the pixel driving circuit of each row is determined based on the sine value, the modulation frequency, and the clock path delay calibration coefficient.

5. The control method according to claim 1, characterized in that, The step of adjusting the rising edge timing of the data signal according to the falling edge offset includes: Obtain the rising edge timing of the data signal and the falling edge timing of the clock signal; Determine the time difference between the rising edge timing of the data signal and the falling edge timing of the clock signal; The rising edge timing of the data signal is adjusted using the falling edge offset and the time difference.

6. The control method according to claim 1, characterized in that, The step of adjusting the voltage amplitude of the data signal according to the falling edge offset includes: Obtain the charging duration corresponding to the pixel driving circuit and the default voltage amplitude of the data signal; The compensation coefficient is determined using the falling edge offset and the charging duration. The default voltage amplitude is adjusted using the compensation coefficient.

7. The control method according to claim 6, characterized in that, The determination of the compensation coefficient using the falling edge offset and the charging duration includes: Obtain the Gamma curve fitting coefficients of the display panel; Calculate a second ratio between the falling edge offset and the charging duration; Calculate the product of the Gamma curve fitting coefficient and the second ratio; The compensation coefficient is determined by adding 1 to the product.

8. The control method according to claim 1, characterized in that, The method further includes: When the rising edge timing of the data signal is constrained according to the falling edge offset, the voltage amplitude of the data signal is adjusted according to the falling edge offset.

9. The control method according to claim 1 or 8, characterized in that, The step of adjusting the rising edge timing of the data signal according to the falling edge offset and adjusting the voltage amplitude of the data signal according to the falling edge offset includes: The rising edge timing of the data signal is adjusted using a portion of the falling edge offset, and the voltage amplitude of the data signal is adjusted using the remaining portion of the falling edge offset.

10. A display panel, characterized in that, The display panel includes a timing control circuit, a gate control circuit, a source control circuit, and a driving array composed of multiple pixel driving circuits; The timing control circuit is electrically connected to the gate control circuit and the source control circuit, respectively, and the gate control circuit and the source control circuit are electrically connected to the driving array, respectively. The timing control circuit is used to implement the method as described in any one of claims 1-9.

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