Pixel circuit of light emitting element

Abstract

A pixel driving circuit (300, 400, 500, 600, 700, 900, 1100, 1300, 1500, 1700, 1900, 2100) includes a first transistor (506, 606, 706), a second transistor (508, 608, 708), and a first capacitor (C1). The first transistor (506, 606, 706) is configured to receive a data signal (VDATA) and drive light-emitting elements (302, 402, 502, 602, 702) according to the data signal (VDATA). The first transistor (506, 606, 706) includes a first gate terminal, a first source terminal, and a first drain terminal. The second transistor (508, 608, 708) includes a second gate terminal receiving a first bias signal from a first bias source (V3), a second source terminal coupled to a first transistor (506, 606, 706), and a second drain terminal coupled to a light-emitting element (302, 402, 502, 602, 702). A first capacitor (C1) is disposed between the first gate terminal and the second gate terminal. The first transistor (506, 606, 706) and the second transistor (508, 608, 708) are transistors of different types.

Description

This invention is a divisional application of the invention patent application number 202380012680.6 filed with the China National Intellectual Property Administration on November 4, 2023, entitled "Pixel Circuit of Light Emitting Element". Background Technology

[0001] This disclosure generally relates to display technologies, and more specifically to pixel circuits.

[0002] Some display devices may require the use of tandem or triple OLEDs with high cross-voltage drive. In typical complementary metal-oxide-semiconductor (CMOS) transistor processes, transistors driving OLEDs using threshold voltage (Vth) compensation architectures can have a withstand voltage of 6 to 8 volts. When these transistors are used in pixel driving circuitry to drive tandem or triple OLEDs, the gate-drain voltage (VGD) or body-drain voltage (VBD) may exceed the device's withstand voltage.

[0003] Therefore, display devices may have hot carrier injection (HCI) effects or current leakage, leading to some defects or irregularities. Summary of the Invention

[0004] In one aspect, a pixel driving circuit is disclosed. The pixel driving circuit includes a first transistor, a second transistor, and a first capacitor. The first transistor is configured to receive a data signal and drive a light-emitting element based on the data signal. The first transistor includes a first gate terminal, a first source terminal, and a first drain terminal. The second transistor includes a second gate terminal receiving a first bias signal from a first bias source, a second source terminal coupled to the first transistor, and a second drain terminal coupled to the light-emitting element. The first capacitor is disposed between the first gate terminal and the second bias source. The first transistor and the second transistor are transistors of different types.

[0005] In some embodiments, the pixel driving circuit further includes a driving sub-circuit and a data writing sub-circuit. The driving sub-circuit is coupled to a first gate terminal and a first source terminal to selectively provide a second bias signal to a first transistor via a third bias source. The data writing sub-circuit is coupled to the driving sub-circuit to selectively provide a data signal to the first transistor.

[0006] In some implementations, the pixel driving circuit further includes a second capacitor disposed between the driving sub-circuit and the data writing sub-circuit.

[0007] In some implementations, the scan cycle of each display frame includes a reset cycle and a light emission cycle, during which the driving sub-circuit provides a second bias signal to the first transistor to drive the light-emitting element.

[0008] In some implementations, the reset period includes an initialization period, a compensation period, and a data writing period, and the driving sub-circuit provides a first initialization bias signal to the first capacitor during the initialization period.

[0009] In some implementations, the data writing subcircuit provides a second initialization bias signal to the second capacitor during the initialization and compensation periods.

[0010] In some implementations, the data writing sub-circuit provides a data signal to the first transistor during the data writing cycle.

[0011] In some embodiments, the driving sub-circuit includes a first switching element disposed between a first source terminal and a first terminal of a second capacitor; a second switching element disposed between a first terminal of the second capacitor and a third bias source; and a third switching element disposed between a first terminal of the second capacitor and a first gate terminal.

[0012] In some embodiments, the driving sub-circuit includes a fourth switching element disposed between a third bias source and a first terminal of a second capacitor; and a fifth switching element disposed between a first terminal and a first gate terminal of the second capacitor.

[0013] In some embodiments, the drive sub-circuit includes a sixth switching element disposed between the first source terminal and the third bias source; a seventh switching element disposed between the first source terminal and the first terminal of the second capacitor; and an eighth switching element disposed between the first terminal of the second capacitor and the first initialization bias source.

[0014] In some embodiments, the driving sub-circuit includes a ninth switching element disposed between the first source terminal and the third bias source; a tenth switching element disposed between the first source terminal and the first terminal of the second capacitor; and an eleventh switching element disposed between the first terminal and the first gate terminal of the second capacitor.

[0015] In some implementations, the data writing sub-circuit includes a twelfth switching element disposed between the second terminal of the second capacitor and the data signal source; and a thirteenth switching element disposed between the second terminal of the second capacitor and the second initialization bias source.

[0016] In some implementations, the data writing subcircuit includes a fourteenth switching element disposed between the second terminal of the second capacitor and the data signal source.

[0017] In some implementations, the data writing sub-circuit and the second capacitor are shared by multiple drive sub-circuits.

[0018] In some embodiments, the first bias source and the second bias source are provided by different voltage sources. In some embodiments, the first bias source and the second bias source are provided by the same voltage source.

[0019] In another aspect, a light-emitting device is disclosed. The light-emitting device includes a light-emitting element and a driving circuit for driving the light-emitting element. The driving circuit includes a first type of transistor that receives a data signal and includes a first gate terminal, a first source terminal, and a first drain terminal. A second type of transistor includes a second gate terminal that receives a first bias signal from a first bias source, a second source terminal coupled to the first drain terminal, and a second drain terminal coupled to the light-emitting element. A first capacitor is disposed between the first gate terminal and a second bias source; a driving sub-circuit is coupled to the first gate terminal and the first source terminal to provide a data signal and a second bias signal provided by a third bias source. A data writing sub-circuit is coupled to the driving sub-circuit to provide a data signal to the driving sub-circuit; a second capacitor is disposed between the driving sub-circuit and the data writing sub-circuit.

[0020] In some implementations, the first type of transistor is a p-type transistor, and the second type of transistor is an n-type transistor.

[0021] In some embodiments, the driving sub-circuit includes a first switching element disposed between a first source terminal and a first terminal of a second capacitor; a second switching element disposed between a first terminal of the second capacitor and a third bias source; and a third switching element disposed between a first terminal of the second capacitor and a first gate terminal.

[0022] In some embodiments, the driving sub-circuit includes a fourth switching element disposed between a third bias source and a first terminal of a second capacitor; and a fifth switching element disposed between a first terminal and a first gate terminal of the second capacitor.

[0023] In some embodiments, the drive sub-circuit includes a sixth switching element disposed between the first source terminal and the third bias source; a seventh switching element disposed between the first source terminal and the first terminal of the second capacitor; and an eighth switching element disposed between the first terminal of the second capacitor and the first initialization bias source.

[0024] In some embodiments, the driving sub-circuit includes a ninth switching element disposed between the first source terminal and the third bias source; a tenth switching element disposed between the first source terminal and the first terminal of the second capacitor; and an eleventh switching element disposed between the first terminal and the first gate terminal of the second capacitor.

[0025] In some implementations, the data writing sub-circuit includes a twelfth switching element disposed between the second terminal of the second capacitor and the data signal source; and a thirteenth switching element disposed between the second terminal of the second capacitor and the second initialization bias source.

[0026] In some implementations, the data writing subcircuit includes a fourteenth switching element disposed between the second terminal of the second capacitor and the data signal source.

[0027] In some implementations, the drive circuit also includes a reset signal coupled to the second drain terminal.

[0028] In some embodiments, the first bias source and the second bias source are provided by different voltage sources. In some embodiments, the first bias source and the second bias source are provided by the same voltage source.

[0029] In another aspect, a method for driving a light-emitting element via a pixel circuit is disclosed. The pixel circuit includes a first transistor, a second transistor disposed between the first transistor and the light-emitting element, a first capacitor disposed between a first gate terminal of the first transistor and a second gate terminal of the second transistor, and a second capacitor disposed between the first transistor and a data signal source. During an initialization period, a first terminal of the first capacitor is initialized to a first initialization bias voltage, and a first terminal of the second capacitor is initialized to a second initialization bias voltage. During a compensation period, the first terminal of the first capacitor is compensated to a compensation bias voltage. During a data writing period, a data signal is provided to the first terminal of the second capacitor. During an emission period, the light-emitting element is driven to emit light according to the data signal.

[0030] In some implementations, the pixel circuit also includes a reset bias source coupled to the second transistor and the light-emitting element. During initialization, compensation, and data writing, the reset bias source provides a reset bias to the pixel circuit.

[0031] In some implementations, the sum of the initialization period, compensation period, data writing period, and transmission period is the frame period.

[0032] In some implementations, a first initial bias voltage is provided to a first terminal of a first capacitor; a first bias voltage is also provided to a second terminal of the first capacitor. A second initial bias voltage is provided to a first terminal of a second capacitor. The first terminal of the first capacitor is coupled to the second terminal of the second capacitor.

[0033] In some implementations, a first initial bias voltage at a first terminal of a first capacitor is discharged to a reset bias voltage via a first transistor and a second transistor.

[0034] In some implementations, the voltage difference between the first and second terminals of the first capacitor is at least the sum of the first threshold voltage of the first transistor and the second threshold voltage of the second transistor.

[0035] In some implementations, the compensation bias is at least the sum of the first threshold voltage of the first transistor and the second threshold voltage of the second transistor. Attached Figure Description

[0036] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the disclosure presented and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use the disclosure. Figure 1 An apparatus including display and control logic is shown according to some aspects of this disclosure. Figure 2 Some aspects of this disclosure are shown. Figure 1 The block diagram of the display shown. Figure 3 A circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of this disclosure is shown. Figure 4 A circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of this disclosure is shown. Figure 5 A circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of this disclosure is shown. Figure 6A and 6B A circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of this disclosure is shown. Figure 7 A circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of this disclosure is shown. Figure 8 Illustrations of some aspects according to this disclosure are shown. Figure 7 The timing diagram of the operation of the pixel driving circuit. Figure 9 A circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of this disclosure is shown. Figure 10 Illustrations of some aspects according to this disclosure are shown. Figure 9 The timing diagram shows the operation of the pixel driving circuit. Figure 11 A circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of this disclosure is shown. Figure 12 Illustrations of some aspects according to this disclosure are shown. Figure 11 The timing diagram of the operation of the pixel driving circuit. Figure 13 A circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of this disclosure is shown. Figure 14 Illustrations of some aspects according to this disclosure are shown. Figure 13 The timing diagram of the operation of the pixel driving circuit. Figure 15 A circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of this disclosure is shown. Figure 16 Illustrations of some aspects according to this disclosure are shown. Figure 15 The timing diagram of the operation of the pixel driving circuit. Figure 17 A circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of this disclosure is shown. Figure 18 Illustrations of some aspects according to this disclosure are shown. Figure 17 The timing diagram of the operation of the pixel driving circuit. Figure 19 A circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of this disclosure is shown. Figure 20 Illustrations of some aspects according to this disclosure are shown. Figure 19 The timing diagram of the operation of the pixel driving circuit. Figure 21 A circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of this disclosure is shown. Figure 22 Illustrations of some aspects according to this disclosure are shown. Figure 21 The timing diagram of the operation of the pixel driving circuit. Figure 23 The application of a pixel driving circuit 700 according to some aspects of this disclosure is shown. Figure 24 The application of a pixel driving circuit 900 according to some aspects of this disclosure is shown. Figure 25 The application of a pixel driving circuit 1100 according to some aspects of this disclosure is shown. Figure 26 The application of a pixel driving circuit 1300 according to some aspects of this disclosure is shown. Figure 27 The application of a pixel driving circuit 1300 according to some aspects of this disclosure is shown. Figure 28 The application of a pixel driving circuit 1100 according to some aspects of this disclosure is shown. Figure 29A flowchart of a method for driving a light-emitting element via a pixel circuit is shown, according to some aspects of this disclosure. This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0037] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. It is conceivable that other configurations and arrangements may be used without departing from the spirit and scope of this disclosure. Furthermore, this disclosure is expected to be applicable to a variety of other applications.

[0038] It should be noted that the expressions "one embodiment," "this embodiment," "example embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment does not necessarily include specific features, structures, or characteristics. Furthermore, these phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, it is contemplated that such feature, structure, or characteristic may also be used in conjunction with other embodiments, whether or not explicitly described.

[0039] Generally, terms can be understood, at least in part, based on their use in context. For example, the term "one or more," as used herein, can be used, at least in part, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination or multiple features, structures, or characteristics. Similarly, terms such as "a," "an," or "the" can be understood to express either a singular or a plural usage, at least in part, based on context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, again, at least in part, based on context.

[0040] As will be detailed below, among other novel features, the pixel circuits disclosed herein for light-emitting elements such as organic light-emitting elements (OLEDs) and micro-LEDs can improve a variety of display specifications. It should be understood that the light-emitting elements described herein are for illustrative purposes only, and other types of light-emitting elements may also be applied.

[0041] Figure 1A device 100, comprising a display 102 and control logic 104, is illustrated according to some aspects of this disclosure. Device 100 can be any suitable device, such as a VR, AR, or MR device (e.g., VR headsets, etc.), a handheld device (e.g., a dumbphone or smartphone, tablet, etc.), a wearable device (e.g., glasses, watches, etc.), a car console, a game console, a television, a laptop computer, a desktop computer, a netbook computer, a media center, a set-top box, a Global Positioning System (GPS), an electronic billboard, an electronic signage, a printer, or any other suitable device. In some implementations, display 102 is operatively coupled to control logic 104 and is part of device 100, such as, but not limited to, an HMD, a handheld device screen, a computer monitor, a television screen, a dashboard, an electronic billboard, or an electronic signage. Display 102 can be an OLED display, a microLED display, a liquid crystal display (LCD), an electronic ink display, an electroluminescent display (ELD), a billboard display with LEDs or incandescent lamps, or any other suitable type of display.

[0042] Control logic 104, which may be any suitable hardware, software, firmware, or a combination thereof, is configured to receive display data 106 (e.g., pixel data) and generate control signals 108 for driving subpixels on display 102. Control signals 108 are used to control the writing of display data 106 to subpixels and to direct the operation of display 102. For example, a subpixel rendering (SPR) algorithm for various subpixel arrangements may be part of or implemented by control logic 104. Control logic 104 may be implemented as a separate integrated circuit (IC) chip, such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Device 100 may also include any other suitable components, such as, but not limited to, tracking device 110 (e.g., an inertial sensor, camera, eye tracker, GPS receiver, or any other suitable device for tracking eye movements, facial expressions, head movements, body movements, and gestures), input device 112 (e.g., a mouse, keyboard, remote control, handwriting device, microphone, scanner, etc.), and a speaker (not shown).

[0043] In some implementations, device 100 may be a handheld or VR / AR / MR device, such as a smartphone, tablet, or VR headset. Device 100 may also include processor 114 and memory 116. Processor 114 may be, for example, a graphics processor (e.g., a graphics processing unit (GPU)), an application processor (AP), a general-purpose processor (e.g., an APU, an accelerated processing unit; a general-purpose processor on a GPGPU GPU), or any other suitable processor. Memory 116 may be, for example, a discrete frame buffer or unified memory. Processor 114 is configured to generate display data 106 in a display frame and may temporarily store the display data 106 in memory 116 before sending it to control logic 104. Processor 114 may also generate other data, such as, but not limited to, control instructions 118 or test signals, and provide them directly or via memory 116 to control logic 104. Control logic 104 then receives display data 106 from memory 116 or directly from processor 114.

[0044] Figure 2 Some aspects of this disclosure are shown. Figure 1 The diagram shown is a block diagram of a display 102 including driving circuitry. In some embodiments, display 102 may include a display panel having an active region 200 comprising a plurality of subpixels. The display panel may also include on-panel driving circuitry, such as gate driving circuitry 202 and source driving circuitry 204. It should be understood that in some embodiments, gate driving circuitry 202 and source driving circuitry 204 may not be on-panel driving circuitry, i.e., not part of the display panel, but operatively coupled to the display panel.

[0045] Each subpixel can be any unit constituting a pixel, i.e., a subdivision of a pixel. For example, a subpixel can be an individually addressable monochrome display element. In some embodiments where the display 102 is a light-emitting element display (e.g., an OLED display or a microLED display), each subpixel may include a light-emitting element (e.g., an OLED or microLED display) and pixel circuitry for driving the light-emitting element. Multiple subpixels (and their light-emitting elements) can be arranged in an array with multiple rows and columns according to any suitable subpixel arrangement. Each light-emitting element can emit light of a predetermined brightness and color, such as, but not limited to, red, green, blue, yellow, cyan, magenta, or white. Each pixel circuitry includes a thin-film transistor (TFT) and a capacitor, and is configured to drive the corresponding subpixel by controlling the light emitted from the corresponding light-emitting element according to a control signal 108 from control logic 104. The pixel circuitry can be a 2T1C configuration (i.e., including a switching transistor, a driving transistor, and a storage capacitor), or can include compensation circuitry with more transistors and / or capacitors to achieve brightness uniformity, such as in a 7T1C, 5T1C, 5T2C, or 6T1C configuration.

[0046] In some implementations, the gate drive circuit 202 is operatively coupled to the active region 200 via multiple gate lines G1-Gm (aka scan lines) and configured to scan multiple sub-pixels. For example, the gate drive circuit 202 applies multiple scan signals generated based on control signals 108 from control logic 104 to the multiple gate lines G1-Gm to scan multiple sub-pixels in a gate scan sequence. During scanning, a scan signal is applied to the gate of the switching transistor of each pixel circuit to turn on the switching transistor, so that the source drive circuit 204 can write the data signal of the corresponding sub-pixel. It should be understood that, although Figure 2 The diagram shows a gate drive circuit 202, but in some embodiments, multiple gate drive circuits can work together to scan sub-pixels.

[0047] In some implementations, the source drive circuit 204 is operatively coupled to the active region 200 via multiple source lines S1-Sn (data lines) and configured to write display data 106 in a frame to the multiple source lines S1-Sn (data lines) of a sub-pixel. For example, the source drive circuit 204 can simultaneously apply multiple data signals to the multiple source lines S1-Sn of a sub-pixel. That is, the source drive circuit 204 may include one or more shift registers, a digital-to-analog converter (DAC), a multiplexer (MUX), and arithmetic circuitry for controlling the timing of applying voltages to the sources of the switching transistors of each pixel circuit (i.e., during the scan period of each frame) and the magnitude of the voltages applied according to the grayscale of the display data 106. It should be understood that, although Figure 2The diagram shows a source drive circuit 204, but in some implementations, multiple source drive circuits can work together to apply data signals to the source lines of sub-pixels.

[0048] Additionally, the light-emitting driving circuit 206 can be included on the display panel. The light-emitting driving circuit 206 can be operatively coupled to the active region 200 and configured to cause each sub-pixel to emit light for a specific time period in each frame by applying multiple light-emitting signals to multiple emission lines E1-Ek. It should be understood that, although... Figure 2 The diagram shows a light-emitting driving circuit 206, but in some embodiments, multiple light-emitting driving circuits can be combined with each other.

[0049] Figure 3 A circuit diagram of a pixel driving circuit 300 for a light-emitting element 302 according to some aspects of this disclosure is shown. The light-emitting element 302 can be an OLED or a micro-OLED driven by the pixel driving circuit 300. The pixel driving circuit 300 includes a p-type driving transistor 304 and a capacitor 306 (e.g., a storage capacitor). In some embodiments, the pixel driving circuit 300 may also include a switch (e.g., a switching transistor or a discharge control switch) or other elements. Figure 3 As shown, the maximum value of the gate-to-drain voltage (VGD) of the p-type driving transistor 304 can be (VDD - VSS), that is, the maximum value of the body-to-drain voltage (VBD) of the p-type driving transistor 304. The type of driving transistor 304 can be (VDD - VSS - VOLED_Min), and the minimum voltage at the anode of the light-emitting element 302 can be (VSS + VOLED_Min). In some embodiments, the gate-to-drain voltage (VGD) or the body-to-drain voltage (VBD) of the p-type driving transistor 304 can exceed the withstand voltage of the p-type driving transistor 304.

[0050] Figure 4 A circuit diagram of another pixel driving circuit 400 for a light-emitting element 402 according to some aspects of this disclosure is shown. The light-emitting element 402 may be an OLED or a micro-OLED driven by the pixel driving circuit 400. The pixel driving circuit 400 includes an n-type driving transistor 404 and a capacitor 406 (e.g., a storage capacitor). In some embodiments, the pixel driving circuit 400 may also include a switch (e.g., a switching transistor or a discharge control switch) or other elements. Figure 4As shown, the maximum value of the drain-to-gate voltage (VDG) of the n-type driving transistor 404 can be (VDD - VSS), the maximum value of the drain-to-body voltage (VDB) of the n-type driving transistor 404 can be (VDD - VSS), and the minimum voltage at the anode of the light-emitting element 402 can be (VSS + VOLED_Min). In some embodiments, the drain-to-gate voltage (VDG) or the drain-to-body voltage (VDB) of the n-type driving transistor 404 can exceed the withstand voltage of the n-type driving transistor 404.

[0051] Figure 5 A circuit diagram of a pixel driving circuit 500 for a light-emitting element 502, according to some aspects of this disclosure, is shown. For example... Figure 5 As shown, n-type transistor 506 is connected to p-type transistor 508 to drive light-emitting element 502. In some embodiments, n-type transistor 506 and p-type transistor 508 are collectively referred to as pixel core 504. Capacitor 510 (C1) is coupled between the gate of n-type transistor 506 and the gate of p-type transistor 508, and provides bias V3 to the gate of p-type transistor 508. In some embodiments, bias V4 may also be provided to the body of n-type transistor 506, and bias V5 may be further provided to the body of p-type transistor 508. Figure 5 As shown, the maximum value of the drain-to-gate voltage (VDG) of the n-type transistor 506 can be (VDD-V3), which is less than (Vdd-VSS). The maximum value of the drain-to-body voltage (VDB) of the n-type transistor 506 can be (VDD-V4), which is less than (VDD-VSS). Additionally, as... Figure 5 As shown, the maximum value of the gate-drain voltage (VGD) of the p-type transistor 508 can be (V3 - VSS - VOLED_Min), which is less than (VDD - VSS). The maximum value of the body-drain voltage (VBD) of the p-type transistor 508 can be (V5 - VSS - VOLED_Min), which is less than (VDD - VSS - VOLED_Min). The minimum voltage at the anode of the light-emitting element 502 can be (VSS + VOLED_Min). With this circuit structure, when a high level (VDD - VSS) is used to drive the light-emitting element 502, the drain-to-gate voltage (VDG) of the n-type transistor 506, the gate-to-drain voltage (VGD) of the p-type transistor 508, the drain-to-body voltage (VDB) of the n-type transistor 506, or the body-drain voltage (VBD) of the p-type transistor 508 will operate within a safe bias range.

[0052] Figure 6A A circuit diagram of a pixel driving circuit 600 for a light-emitting element 602, according to some aspects of this disclosure, is shown. For example... Figure 6AAs shown, the pixel driving circuit 600 includes a first transistor 606, a second transistor 608, and a first capacitor 610. In some embodiments, the first transistor 606 and the second transistor 608 are transistors of different types. In some embodiments, the first transistor 606 is an n-type transistor, and the second transistor 608 is a p-type transistor. In some embodiments, the first transistor 606 and the second transistor 608 are collectively referred to as the pixel core 604. The first transistor 606 is configured to receive a data signal VDATA and drive the light-emitting element 602 based on the data signal. The first transistor 606 includes a first gate terminal, a first source terminal, and a first drain terminal. The second transistor 608 includes a second gate terminal that receives a bias signal from a bias source V3, a second source terminal coupled to the source terminal of the first transistor 606, and a second drain terminal coupled to the light-emitting element 602. The first capacitor 610 (C1) is disposed between the first gate terminal of the first transistor 606 and the second gate terminal of the second transistor 608.

[0053] like Figure 6A As shown, the pixel driving circuit 600 further includes a driving sub-circuit 620 and a data writing sub-circuit 630. The driving sub-circuit 620 is coupled to the first gate terminal and the first drain terminal of the first transistor 606 to selectively provide a bias signal to the first transistor 606, the second transistor 608, and the light-emitting element 602 via a bias source VDD. The data writing sub-circuit 630 is coupled to the driving sub-circuit 620 to selectively provide a data signal to the first transistor 606 and the second transistor 608. A second capacitor 612 (C2) is disposed between the driving sub-circuit 620 and the data writing sub-circuit 630.

[0054] It should be understood that, depending on the different operating cycles, the driving sub-circuit 620 can be an initialization / compensation / driving sub-circuit. For example, in some embodiments, during the initialization period P1, the driving sub-circuit 620 functions as an initialization circuit. As another example, in some embodiments, during the compensation period P2, the driving sub-circuit 620 functions as a compensation circuit. As yet another example, during the light emission period P4, the driving sub-circuit 620 functions as a light emission driving circuit. The detailed operation of the initialization period P1, the compensation period P2, and the light emission period P4 will be discussed below.

[0055] In some embodiments, when the display panel is driven by a driving circuit, the source driving circuit can provide display data, such as a data signal VDATA, which is transmitted to multiple sub-pixels, such as the light-emitting element 602, through multiple source lines within a frame. In some embodiments, the switching operation of the data signal VDATA can be controlled by providing switching signals S2-1, S2-2… to the data writing sub-circuit 630. Additionally, the driving sub-circuit 620 can be operatively coupled to the light-emitting element 602 through the pixel core 604, and by providing switching signals EM, S1-1, S1-2… to the driving sub-circuit 620, each sub-pixel (light-emitting element 602) emits light for a certain period of time in each frame. In some embodiments, multiple driving sub-circuits 620 can work collaboratively with each other.

[0056] In some embodiments, the scan cycle of each display frame may include a reset cycle and a light emission cycle, during which the driving sub-circuit 620 provides a bias signal VDD to the pixel core 604 to drive the light-emitting element 602. In some embodiments, the reset period may include an initialization period, a compensation period, and a data writing period.

[0057] Figure 6B Another circuit diagram of a pixel driving circuit 600 for a light-emitting element 602 according to some aspects of this disclosure is shown. Figure 6B The circuit diagram in the middle is similar to Figure 6A The circuit diagram is shown, but the gate terminals of the first capacitor 610 and the second transistor 608 are not coupled to the same voltage source. Figure 6B As shown, the gate of the second transistor is connected to bias source V3a, and one end of the first capacitor 610 is connected to bias source V3b. In some embodiments, bias sources V3a and V3b may have different voltage levels. In some embodiments, bias sources V3a and V3b may have the same voltage level.

[0058] Figure 7 A circuit diagram of a pixel driving circuit 700 for a light-emitting element 702 according to some aspects of this disclosure is shown. Figure 8 Some aspects of this disclosure are shown. Figure 7 The timing diagram shows the operation of the pixel driving circuit 700. To better describe the invention, [the following is a description of the process]. Figure 7 The pixel driving circuit 700 and Figure 8 Timing in Figure 1 Let's start a discussion.

[0059] like Figure 7As shown, the pixel driving circuit 700 may include a first transistor 706, a second transistor 708, a first capacitor 710, and a second capacitor 712. In some embodiments, the first transistor 706 and the second transistor 708 are transistors of different types. In some embodiments, the first transistor 706 is an n-type transistor and the second transistor 708 is a p-type transistor. In some embodiments, the first transistor 706 and the second transistor 708 are collectively referred to as the pixel core 704. The first transistor 706 includes a first gate terminal, a first source terminal, and a first drain terminal. The second transistor 708 includes a second gate terminal receiving a bias signal from a bias source V3, a second source terminal coupled to the source terminal of the first transistor 706, and a second drain terminal coupled to the light-emitting element 702. The first capacitor 710 (C1) is disposed between the first gate terminal of the first transistor 706 and the second gate terminal of the second transistor 708.

[0060] Additionally, switching element S1 is disposed between the first drain terminal of the first transistor 706 and the first terminal of the second capacitor 712 (C2). Switching element S2 is disposed between the first terminal of the second capacitor 712 and the bias source VDD / V2. Switching element S3 is disposed between the first terminal of the second capacitor 712 and the first gate terminal of the first transistor 706. In some embodiments, the drive sub-circuit 620 in FIG6 collectively includes Figure 7 The switching elements S1, S2, and S3 are described. In some embodiments, switching elements S1, S2, and S3 can be implemented using switching transistors or other suitable components.

[0061] like Figure 7 As shown, switching element S12 is disposed between the second terminal of the second capacitor 712 and the data signal source providing the data signal VDATA, and switching element S13 is disposed between the second terminal of the second capacitor 712 and the bias source V1. In some embodiments, the data writing sub-circuit 630 in FIG. 6 may collectively include switching element S12 and switching element S13. In some embodiments, switching element S12 and switching element S13 can be implemented by using a switching transistor or other suitable components.

[0062] like Figure 8As shown, during the initialization period P1, the reset signal RS can connect the reset bias voltage VR to the anode of the light-emitting element 702 to start the reset period. Control signal S1-1 can turn on switching element S2 to connect the first terminal of the second capacitor 712 and the gate terminal of the first transistor 706. Control signal EM can turn on switching element S2 to connect the bias source G and the first terminal of the second capacitor 712. Control signal S2-1 can turn on switching element S13 to connect the bias source V1 and the second terminal of the second capacitor 712. In some embodiments, the bias source G can provide the bias voltage V2 and the light-emitting voltage VDD together at different times. In some embodiments, during the initialization period P1, the first terminal of the first capacitor 710 is initialized to the first initialization bias voltage V2, and the first terminal of the second capacitor 712 is initialized to the second initialization bias voltage V1.

[0063] In some embodiments, during the initialization period P1, the gate terminal of the first transistor 706 may have an initial voltage. In some embodiments, the initial voltage is a first initialization bias V2. In other words, (VG_N1 = V2 = initial voltage). In some embodiments, during the initialization period P1, the voltage across the first capacitor 710 may be (V2 - V3). In other words, (VCAP_C1 = V2 - V3). In some embodiments, when the gate terminals of the first capacitor 610 and the second transistor 608 are not coupled to the same voltage source, such as... Figure 6B As shown, the voltage across the first capacitor 710 can be (V2-V3b). In other words, (VCAP_C1=V2-V3b).

[0064] During the compensation period P2, control signal EM can turn off switching element S2, and control signals S1-2 can turn on switching element S1. In some embodiments, during the compensation period P2, the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some embodiments, the drain terminal of the first transistor 706 is used to compensate for the initialization bias V2 at the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712.

[0065] In some embodiments, during the compensation period P2, the voltage level at the gate terminal of the first transistor 706 can be equal to the sum of the threshold voltage of the first transistor 706, the threshold voltage of the second transistor 708, and voltage V3. In other words, (VG_N1 = VTH_N1 + VTH_P1 + V3). In some embodiments, when the gate terminals of the first capacitor 610 and the second transistor 608 are not coupled to the same voltage source, such as... Figure 6BAs shown, (VG_N1 = VTH_N1 + VTH_P1 + V3a). In some embodiments, during the compensation period P2, the voltage difference between the two ends of the first capacitor 710 can be the sum of the threshold voltage of the first transistor 706 and the threshold voltage of the second transistor 708. In other words, (VCAP_C1 = VTH_N1 + VTH_P1). In some embodiments, when the gate terminals of the first capacitor 610 and the second transistor 608 are not coupled to the same voltage source, such as... Figure 6B As shown, the voltage difference between the two ends of the first capacitor 710 is (VCAP_C1=VTH_N1+VTH_P1+(V3a-V3b)).

[0066] During the data writing period P3, control signal S1-2 can turn off switching element S1, control signal S2-1 can turn off switching element S13, and control signal S2-2 can turn on switching element S12. In some embodiments, during the data writing period P3, data signal VDATA is provided to the second terminal of the second capacitor 712.

[0067] In some implementations, during write cycle P3, the voltage difference across the first capacitor 710 can be the threshold voltage of the first transistor 706, the threshold voltage of the second transistor 708, and the voltage division at the second terminal of the second capacitor 712 divided by the sum of the voltages across the first capacitor 710 and the second capacitor 712. In other words, the voltage difference across the first capacitor 710 is (VCAP_C1=VTH_N1+VTH_P1+ΔV_2). nd end_C2*C2 / (C1+C2)). In some embodiments, when the gate terminals of the first capacitor 610 and the second transistor 608 are not coupled to the same voltage source, such as Figure 6B As shown, the voltage difference across the first capacitor 710 is (VCAP_C1=VTH_N1+VTH_P1+(V3a-V3b)+ΔV_2) nd end_C2*C2 / (C1+C2)).

[0068] During the light-emitting period P4, the reset signal RS can disconnect the reset bias voltage VR from the anode of the light-emitting element 702 to begin the light-emitting cycle. The control signal EM can turn on the switching element S2 again to provide the emission voltage VDD, the control signal S1-1 can turn off the switching element S2, and the control signal S2-2 can turn off the switching element S12. In some embodiments, during the light-emitting period P4, the emission voltage VDD can drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0069] In some embodiments, during the light-emitting period P4, the light-emitting element 702 emits a current I. EMIt is (1 / 2*μn*Cox*W_N1 / L_N1*(VGS_N1-VTH_N1)) 2 ) or (1 / 2*μp*Cox*W_P1 / L_P1*(VSG_P1-VTH_P1) 2 Here, W / L is the aspect ratio of the first transistor 606 or the second transistor 608, μ is the channel carrier mobility, and Cox is the capacitance of the channel insulating layer of the first transistor 606 or the second transistor 608. In some embodiments, the gate-source voltage (VGS) of the first transistor 606 is VGS_N1 = [α*ΔV_2] nd end_C2*C2 / (C1+C2)]+VTH_N1. The gate-source voltage (VGS) of the second transistor 608 is VGS_P1=[β*ΔV_2] nd end_C2*C2 / (C1+C2)]+VTH_P1, where α+β=1.

[0070] Using this circuit structure, when a high level (VDD-VSS) is used to drive the light-emitting element 702, the drain-to-gate voltage (VDG) of the first transistor 706, the gate-to-drain voltage (VGD) of the second transistor 708, the drain-to-body voltage (VDB) of the first transistor 708, and the body-drain voltage (VBD) of the second transistor 708 will operate within a safe bias range.

[0071] Figure 9 A circuit diagram of another pixel driving circuit 900 for a light-emitting element 702 is shown, according to some aspects of this disclosure. Figure 10 Illustrations of some aspects according to this disclosure are shown. Figure 9 The timing diagram shows the operation of the pixel driving circuit 900. To better describe the invention, [the following is a description of the process]. Figure 9 The pixel driving circuit 900 and Figure 10 Timing in Figure 1 Let's start a discussion.

[0072] like Figure 9 As shown, the driving sub-circuit 620 in Figure 6 collectively includes Figure 9 The switching elements S1, S2, and S3 in the middle are... Figure 7 The circuit structure is similar to that in Figure 6. The data writing sub-circuit 630 in Figure 6 may include... Figure 9 The switching element S14 is located between the second terminal of the second capacitor 712 and the bias source D. In some embodiments, the bias source D can provide the bias voltage V1 and the data signal VDATA at different times.

[0073] like Figure 10As shown, during the initialization period P1, the reset signal RS can connect the reset bias voltage VR to the anode of the light-emitting element 702 to start the reset period. Control signal S1-1 can turn on switching element S2 to connect the first terminal of the second capacitor 712 and the gate terminal of the first transistor 706. Control signal EM can turn on switching element S2 to connect the bias source G and the first terminal of the second capacitor 712. Control signal S2-1 can turn on switching element S14 to connect the bias source V1 and the second terminal of the second capacitor 712. In some embodiments, the bias source G can provide the bias voltage V2 and the light-emitting voltage VDD together at different times. In some embodiments, during the initialization period P1, the first terminal of the first capacitor 710 is initialized to the first initialization bias voltage V2, and the first terminal of the second capacitor 712 is initialized to the second initialization bias voltage V1.

[0074] During the compensation period P2, control signal EM can turn off switching element S2, and control signals S1-2 can turn on switching element S1. In some embodiments, during the compensation period P2, the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some embodiments, the drain terminal of the first transistor 706 is used to compensate for the initialization bias V2 at the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712.

[0075] During the data writing period P3, control signal S1-2 can turn off switching element S1. Control signal S2-1 can keep switching element S14 on and can change the bias source D to provide the data signal VDATA instead of the bias voltage V1.

[0076] During the light-emitting period P4, the reset signal RS can disconnect the reset bias voltage VR from the anode of the light-emitting element 702 to start the light-emitting period. The control signal EM can turn on the switching element S2 again to provide the emission voltage VDD. The control signal S1-1 can turn off the switching element S2, and the control signal S2-1 can turn off the switching element S14. In some embodiments, during the light-emitting period P4, the emission voltage VDD can drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0077] Using this circuit structure, when a high level (VDD-VSS) is used to drive the light-emitting element 702, the drain-to-gate voltage (VDG) of the first transistor 706, the gate-to-drain voltage (VGD) of the second transistor 708, the drain-to-body voltage (VDB) of the first transistor 708, and the body-drain voltage (VBD) of the second transistor 708 will operate within a safe bias range.

[0078] Figure 11 A circuit diagram of another pixel driving circuit 1100 for a light-emitting element 702 is shown, according to some aspects of this disclosure. Figure 12 Illustrations of some aspects according to this disclosure are shown. Figure 11 A timing diagram of the operation of the pixel driving circuit 1100 is shown. To better describe the invention, [the following is a more detailed description]. Figure 11 The pixel driving circuit 1100 and Figure 12 Timing in Figure 1 Let's start a discussion.

[0079] like Figure 11 As shown, switching element S4 is disposed between the bias source G and the first terminal of the second capacitor 712, and switching element S5 is disposed between the first terminal of the second capacitor 712 and the gate of the first transistor 706. In some embodiments, the driving sub-circuit 620 in FIG6 collectively includes Figure 1 The switching elements S4 and S5 are shown in the figure. In some embodiments, the switching elements S4 and S5 can be implemented by using switching transistors or other suitable components.

[0080] like Figure 11 As shown, switching element S12 is disposed between the second terminal of the second capacitor 712 and the data signal source providing the data signal VDATA, and switching element S13 is disposed between the second terminal of the second capacitor 712 and the bias source V1. In some embodiments, the data writing sub-circuit 630 in FIG. 6 may collectively include switching element S12 and switching element S13. In some embodiments, switching element S12 and switching element S13 can be implemented using switching transistors or other suitable components. In some embodiments, Figure 11 The structure and operation of switching elements S12 and S13 can be similar to Figure 7 The switching elements S12 and S13 are in the middle.

[0081] like Figure 12 As shown, during the initialization period P1, the reset signal RS can connect the reset bias voltage VR to the anode of the light-emitting element 702 to start the reset period. The control signal S1-1 can turn on the switching element S5 to connect the first terminal of the second capacitor 712 and the gate terminal of the first transistor 706. The control signal EM can turn on the switching element S4 to connect the bias source G and the first terminal of the second capacitor 712. In some embodiments, the bias source G can provide the bias voltage V2 and the light-emitting voltage VDD together at different times. In some embodiments, during the initialization period P1, the first terminal of the first capacitor 710 is initialized to the first initialization bias voltage V2, and the second terminal of the second capacitor 712 is initialized to the second initialization bias voltage V1.

[0082] During the compensation period P2, the control signal EM can turn off the switching element S4. In some embodiments, during the compensation period P2, the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some embodiments, the drain terminal of the first transistor 706 is used to compensate for the initialization bias V2 at the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712.

[0083] During the data writing period P3, control signal S2-1 can turn off switching element S13, and control signal S2-2 can turn on switching element S12. In some embodiments, during the data writing period P3, data signal VDATA is provided to the second terminal of the second capacitor 712.

[0084] During the light-emitting period P4, the reset signal RS can disconnect the reset bias voltage VR from the anode of the light-emitting element 702 to start the light-emitting period. The control signal EM can turn on the switching element S4 again to provide the emission voltage VDD. The control signal S1-1 can turn off the switching element S5, and the control signal S2-2 can turn off the switching element S12. In some embodiments, during the light-emitting period P4, the emission voltage VDD can drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0085] Using this circuit structure, when a high level (VDD-VSS) is used to drive the light-emitting element 702, the drain-to-gate voltage (VDG) of the first transistor 706, the gate-to-drain voltage (VGD) of the second transistor 708, the drain-to-body voltage (VDB) of the first transistor 708, and the body-drain voltage (VBD) of the second transistor 708 will operate within a safe bias range.

[0086] Figure 13 A circuit diagram of another pixel driving circuit 1300 for a light-emitting element 702 is shown, according to some aspects of this disclosure. Figure 14 Illustrations of some aspects according to this disclosure are shown. Figure 13 A timing diagram of the operation of the pixel driving circuit 1300 is shown. To better describe the invention, [the following is a more detailed description]. Figure 13 The pixel driving circuit 1300 and Figure 14 Timing in Figure 1 Let's start a discussion.

[0087] like Figure 13 As shown, the driving sub-circuit 620 in Figure 6 collectively includes Figure 13 Switching elements S4 and S5 in the middle, with Figure 11The circuit structure is similar to that in Figure 6. The data writing sub-circuit 630 in Figure 6 may include... Figure 13 The switching element S14 in, and with Figure 9 The switching element S14 is similar.

[0088] like Figure 14 As shown, during the initialization period P1, the reset signal RS can connect the reset bias voltage VR to the anode of the light-emitting element 702 to start the reset period. The control signal S1-1 can turn on the switching element S5 to connect the first terminal of the second capacitor 712 and the gate terminal of the first transistor 706. The control signal EM can turn on the switching element S4 to connect the bias source G and the first terminal of the second capacitor 712. In some embodiments, the bias source G can provide the bias voltage V2 and the light-emitting voltage VDD together at different times. In some embodiments, during the initialization period P1, the first terminal of the first capacitor 710 is initialized to the first initialization bias voltage V2, and the second terminal of the second capacitor 712 is initialized to the second initialization bias voltage V1.

[0089] During the compensation period P2, the control signal EM can turn off the switching element S4. In some embodiments, during the compensation period P2, the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some embodiments, the drain terminal of the first transistor 706 is used to compensate for the initialization bias V2 at the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712.

[0090] During the data writing period P3, the control signal S2-1 can keep the switching element S14 on and can change the bias source D to provide the data signal VDATA instead of the bias voltage V1.

[0091] During the light-emitting period P4, the reset signal RS can disconnect the reset bias voltage VR from the anode of the light-emitting element 702 to start the light-emitting period. The control signal EM can turn on the switching element S4 again to provide the emission voltage VDD. The control signal S1-1 can turn off the switching element S5, and the control signal S2-1 can turn off the switching element S14. In some embodiments, during the light-emitting period P4, the emission voltage VDD can drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0092] Using this circuit structure, when a high level (VDD-VSS) is used to drive the light-emitting element 702, the drain-to-gate voltage (VDG) of the first transistor 706, the gate-to-drain voltage (VGD) of the second transistor 708, the drain-to-body voltage (VDB) of the first transistor 708, and the body-drain voltage (VBD) of the second transistor 708 will operate within a safe bias range.

[0093] Figure 15 A circuit diagram of another pixel driving circuit 1500 for a light-emitting element 702 is shown, according to some aspects of this disclosure. Figure 16 Illustrations of some aspects according to this disclosure are shown. Figure 15 The timing diagram shows the operation of the pixel driving circuit 1500. To better describe the invention, [the following is a description of the process]. Figure 15 The pixel driving circuit 1500 and Figure 16 Timing in Figure 1 Let's start a discussion.

[0094] like Figure 15 As shown, switching element S6 is disposed between the bias source VDD and the first drain terminal of the first transistor 706, switching element S7 is disposed between the first drain terminal of the first transistor 706 and the first terminal of the second capacitor 712, and switching element S8 is disposed between the first terminal of the second capacitor 712 and the bias source V2. In some embodiments, the drive sub-circuit 620 in FIG6 collectively includes Figure 15 The switching elements S6, S7, and S8 are described. In some embodiments, switching elements S6, S7, and S8 can be implemented using switching transistors or other suitable components.

[0095] like Figure 15 As shown, switching element S12 is disposed between the second terminal of the second capacitor 712 and the data signal source providing the data signal VDATA, and switching element S13 is disposed between the second terminal of the second capacitor 712 and the bias source V1. In some embodiments, the data writing sub-circuit 630 in FIG. 6 may collectively include switching element S12 and switching element S13. In some embodiments, switching element S12 and switching element S13 can be implemented by using a switching transistor or other suitable components.

[0096] like Figure 16As shown, during the initialization period P1, the reset signal RS can connect the reset bias voltage VR to the anode of the light-emitting element 702 to start the reset period. The control signal S1-1 can turn on the switching element S8 to connect the bias source V2 to the first terminal of the second capacitor 712 and the gate terminal of the first transistor 706. The control signal S2-1 can turn on the switching element S13 to connect the bias source V1 and the second terminal of the second capacitor 712. In some embodiments, during the initialization period P1, the first terminal of the first capacitor 710 is initialized to the first initialization bias voltage V2, and the first terminal of the second capacitor 712 is initialized to the second initialization bias voltage V1.

[0097] During the compensation period P2, control signal S1-1 can turn off switching element S8, and control signal S1-2 can turn on switching element S7. In some embodiments, during the compensation period P2, the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some embodiments, the drain terminal of the first transistor 706 is used to compensate for the initialization bias V2 at the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712.

[0098] During the data writing period P3, control signal S1-2 can turn off switching element S7, control signal S2-1 can turn off switching element S13 to disconnect bias source V1 and the second terminal of second capacitor 712, and control signal S2-2 can turn on switching element S12. In some embodiments, during the data writing period P3, data signal VDATA is provided to the second terminal of second capacitor 712.

[0099] During the light-emitting period P4, the reset signal RS can disconnect the reset bias voltage VR from the anode of the light-emitting element 702 to start the light-emitting period, the control signal EM can turn on the switching element S6 to provide the emission voltage VDD, and the control signal S2-2 can turn off the switching element S12. In some embodiments, during the light-emitting period P4, the emission voltage VDD can drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0100] With this circuit structure, when a high level (VDD-VSS) is used to drive the light-emitting element 702, the drain-to-gate voltage (VDG) of the first transistor 706, the gate-to-drain voltage (VGD) of the second transistor 708, the drain-to-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 will operate within a safe bias range.

[0101] Figure 17A circuit diagram of another pixel driving circuit 1700 for a light-emitting element 702 is shown, according to some aspects of this disclosure. Figure 18 Illustrations of some aspects according to this disclosure are shown. Figure 17 The timing diagram shows the operation of the pixel driving circuit 1700. To better describe the invention, [the following is a description of the process]. Figure 17 The pixel driving circuit 1700 and Figure 18 Timing in Figure 1 Let's start a discussion.

[0102] like Figure 17 As shown, the driving sub-circuit 620 in Figure 6 collectively includes Figure 17 Switching elements S6, S7, and S8 in the middle, and Figure 15 The circuit structure is similar to that in Figure 6. The data writing sub-circuit 630 in Figure 6 may include... Figure 17 The switching element S14 in, and with Figure 9 The switching element S14 is similar.

[0103] like Figure 18 As shown, during the initialization period P1, the reset signal RS can connect the reset bias voltage VR to the anode of the light-emitting element 702 to start the reset period. The control signal S1-1 can turn on the switching element S8 to connect the bias source V2 to the first terminal of the second capacitor 712 and the gate terminal of the first transistor 706. The control signal S2-1 can turn on the switching element S14 to connect the bias source D and the second terminal of the second capacitor 712. In some embodiments, during the initialization period P1, the first terminal of the first capacitor 710 is initialized to the first initialization bias voltage V2, and the first terminal of the second capacitor 712 is initialized to the second initialization bias voltage V1.

[0104] During the compensation period P2, control signal S1-1 can turn off switching element S8, and control signal S1-2 can turn on switching element S7. In some embodiments, during the compensation period P2, the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some embodiments, the drain terminal of the first transistor 706 is used to compensate for the initialization bias V2 at the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712.

[0105] During the data writing period P3, control signal S1-2 can turn off switching element S7, and control signal S2-1 can keep switching element S14 on. The bias source D changes from providing bias voltage V1 to providing data signal VDATA.

[0106] During the light-emitting period P4, the reset signal RS can disconnect the reset bias voltage VR from the anode of the light-emitting element 702 to start the light-emitting period, the control signal EM can turn on the switching element S6 to provide the emission voltage VDD, and the control signal S2-1 can turn off the switching element S14. In some embodiments, during the light-emitting period P4, the emission voltage VDD can drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0107] With this circuit structure, when a high level (VDD-VSS) is used to drive the light-emitting element 702, the drain-to-gate voltage (VDG) of the first transistor 706, the gate-to-drain voltage (VGD) of the second transistor 708, the drain-to-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 will operate within a safe bias range.

[0108] Figure 19 A circuit diagram of another pixel driving circuit 1900 for a light-emitting element 702 is shown, according to some aspects of this disclosure. Figure 20 Illustrations of some aspects according to this disclosure are shown. Figure 19 A timing diagram of the operation of the pixel driving circuit 1900 is shown. To better describe the invention, [the following is a more detailed description]. Figure 19 The pixel driving circuit 1900 and Figure 20 Timing in Figure 1 Let's start a discussion.

[0109] like Figure 19 As shown, switching element S9 is disposed between the bias source G and the first drain terminal of the first transistor 706. Switching element S10 is disposed between the first drain terminal of the first transistor 706 and the first terminal of the second capacitor 712, and switching element S11 is disposed between the first terminal of the second capacitor 712 and the gate terminal of the first transistor 706. In some embodiments, the drive sub-circuit 620 in FIG. 6 collectively includes Figure 19 The switching elements S9, S10, and S11 are described in the text. In some embodiments, the switching elements S9, S10, and S11 can be implemented using switching transistors or other suitable components.

[0110] like Figure 19 As shown, switching element S12 is disposed between the second terminal of the second capacitor 712 and the data signal source providing the data signal VDATA, and switching element S13 is disposed between the second terminal of the second capacitor 712 and the bias source V1. In some embodiments, the data writing sub-circuit 630 in FIG. 6 may collectively include switching element S12 and switching element S13. In some embodiments, switching element S12 and switching element S13 can be implemented by using a switching transistor or other suitable components.

[0111] like Figure 20 As shown, during the initialization period P1, the reset signal RS can connect the reset bias voltage VR to the anode of the light-emitting element 702 to start the reset period. The control signal S1-1 can turn on the switching element S11 to connect the gate terminal of the first transistor 706 and the first terminal of the second capacitor 712. The control signal EM can turn on the switching element S9 to provide a bias signal V2 to the drain terminal of the first transistor 706. The control signal S1-2 can turn on the switching element S10 to connect the first terminal of the second capacitor 712 and the drain terminal of the first transistor 706. The control signal S2-1 can turn on the switching element S13 to connect the bias source V1 and the second terminal of the second capacitor 712. In some embodiments, during the initialization period P1, the first terminal of the first capacitor 710 is initialized to a first initialization bias voltage V2, and the first terminal of the second capacitor 712 is initialized to a second initialization bias voltage V1.

[0112] During the compensation period P2, the control signal EM can turn off the switching element S9. In some embodiments, during the compensation period P2, the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some embodiments, the drain terminal of the first transistor 706 is used to compensate for the initialization bias V2 at the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712.

[0113] During the data writing period P3, control signal S1-2 can turn off switching element S10, and control signal S2-1 can turn off switching element S13 to disconnect the bias source V1 from the second terminal of the second capacitor 712. Control signal S2-2 can turn on switching element S12. In some embodiments, during the data writing period P3, data signal VDATA is provided to the second terminal of the second capacitor 712.

[0114] During the light-emitting period P4, the reset signal RS can disconnect the reset bias voltage VR from the anode of the light-emitting element 702 to start the light-emitting period, the control signal EM can turn on the switching element S9 again to provide the emission voltage VDD, and the control signal S2-2 can turn off the switching element S12. In some embodiments, during the light-emitting period P4, the emission voltage VDD can drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0115] Using this circuit structure, when a high level (VDD-VSS) is used to drive the light-emitting element 702, the drain-to-gate voltage (VDG) of the first transistor 706, the gate-to-drain voltage (VGD) of the second transistor 708, the drain-to-body voltage (VDB) of the first transistor 708, and the body-drain voltage (VBD) of the second transistor 708 will operate within a safe bias range.

[0116] Figure 21 A circuit diagram of another pixel driving circuit 2100 for a light-emitting element 702 is shown, according to some aspects of this disclosure. Figure 22 Illustrations of some aspects according to this disclosure are shown. Figure 21 The timing diagram shows the operation of the pixel driving circuit 2100. To better describe the invention, [the following is a description of the process]. Figure 21 The pixel driving circuit 2100 and Figure 22 Timing in Figure 1 Let's start a discussion.

[0117] like Figure 21 As shown, the driving sub-circuit 620 in Figure 6 collectively includes Figure 21 Switching elements S9, S10, and S11 in the middle, and Figure 19 The circuit structure is similar to that in Figure 6. The data writing sub-circuit 630 in Figure 6 may include... Figure 21 The switching element S14 in, and with Figure 9 The switching element S14 is similar.

[0118] like Figure 22 As shown, during the initialization period P1, the reset signal RS can connect the reset bias voltage VR to the anode of the light-emitting element 702 to start the reset period. The control signal S1-1 can turn on the switching element S11 to connect the gate terminal of the first transistor 706 and the first terminal of the second capacitor 712. The control signal EM can turn on the switching element S9 to provide a bias signal V2 to the drain terminal of the first transistor 706. The control signal S1-2 can turn on the switching element S10 to connect the first terminal of the second capacitor 712 and the drain terminal of the first transistor 706. The control signal S2-1 can turn on the switching element S14 to connect the bias source D and the second terminal of the second capacitor 712. In some embodiments, during the initialization period P1, the first terminal of the first capacitor 710 is initialized to a first initialization bias voltage V2, and the first terminal of the second capacitor 712 is initialized to a second initialization bias voltage V1.

[0119] During the compensation period P2, the control signal EM can turn off the switching element S9. In some embodiments, during the compensation period P2, the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some embodiments, the drain terminal of the first transistor 706 is used to compensate for the initialization bias V2 at the gate terminal of the first transistor 706, the first terminal of the first capacitor 710, and the first terminal of the second capacitor 712.

[0120] During the data writing period P3, control signal S1-2 can turn off switching element S10. Control signal S2-1 can keep switching element S14 on. The bias source D changes from providing bias voltage V1 to providing data signal VDATA.

[0121] During the light-emitting period P4, the reset signal RS can disconnect the reset bias voltage VR from the anode of the light-emitting element 702 to start the light-emitting period, the control signal EM can turn on the switching element S9 again to provide the emission voltage VDD, and the control signal S2-1 can turn off the switching element S14. In some embodiments, during the light-emitting period P4, the emission voltage VDD can drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0122] Using this circuit structure, when a high level (VDD-VSS) is used to drive the light-emitting element 702, the drain-to-gate voltage (VDG) of the first transistor 706, the gate-to-drain voltage (VGD) of the second transistor 708, the drain-to-body voltage (VDB) of the first transistor 708, and the body-drain voltage (VBD) of the second transistor 708 will operate within a safe bias range.

[0123] Figure 23-26 Applications of pixel driving circuits 700, 900, 1100, and 1300 according to some aspects of this disclosure are shown. For example... Figure 23-26 As shown, a data writing sub-circuit 630 can be coupled to multiple driving sub-circuits 620. In some embodiments, such as Figure 23 and Figure 25 As shown, a set of second capacitors 712, switching elements S12 and S13 can be shared by multiple driving sub-circuits 620 to drive multiple light-emitting elements 702.

[0124] Similarly, as Figure 24 and Figure 26 As shown, multiple driving sub-circuits 620 can share a set of second capacitors 712 and switching elements S14 to drive multiple light-emitting elements 702. Additionally, as... Figure 23-26As shown, the switching element S2 or the switching element S4 coupled to the bias source G can also be shared by multiple drive sub-circuits 620.

[0125] Figure 27 and Figure 28 Another application of the pixel driving circuitry 1100 or 1300 according to some aspects of this disclosure is shown. For example... Figure 27 and Figure 28 As shown, a second capacitor 712 can be shared by multiple drive sub-circuits 620 and / or multiple data write sub-circuits 630.

[0126] Figure 29 A flowchart of a method 2900 for driving a light-emitting element via a pixel circuit is shown, according to some aspects of this disclosure. The pixel circuit may include a first transistor 706 and a second transistor 708 disposed between the first transistor 706 and the light-emitting element 702. A first capacitor 710 is disposed between a first gate terminal of the first transistor 706 and a second gate terminal of the second transistor 706, and a second capacitor 712 is disposed between the first transistor 706 and a data signal source VDATA.

[0127] like Figure 29 As shown in operation 2902, during initialization, the first terminal of the first capacitor 710 is initialized to a first initialization bias V2, and the first terminal of the second capacitor 712 is initialized to a second initialization bias V1. Then, as... Figure 29 As shown in operation 2904, during the compensation period, the first terminal of the first capacitor 710 is compensated to the compensation bias. Figure 29 As shown in operation 2906, during the data write cycle, a data signal is provided to the first terminal of the second capacitor 712. Figure 29 As shown in operation 2908, during the light emission period, the pixel driving circuit drives the light-emitting element 702 to emit light based on the data signal.

[0128] In some implementations, the pixel circuit may further include a reset bias source VR coupled to the second transistor 708 and the light-emitting element 702. During initialization, compensation, and data writing, the reset bias source provides a reset bias VR to the pixel circuit.

[0129] In some implementations, the sum of the initialization period, compensation period, data writing period, and transmission period is the frame period. In some embodiments, a first initialization bias V2 is provided to a first terminal of a first capacitor 710, and a first bias V3 is provided to a second terminal of the first capacitor 710. A second initialization bias V1 is provided to a first terminal of a second capacitor 712. The first terminal of the first capacitor 710 and the second terminal of the second capacitor 710 are coupled together.

[0130] In some embodiments, a first initial bias voltage V2 at a first terminal of the first capacitor 710 discharges to a reset bias voltage through a first transistor 706 and a second transistor 708. The compensation bias is at least the sum of a first threshold voltage of the first transistor and a second threshold voltage of the second transistor.

[0131] The foregoing description of the specific implementation can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0132] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A light-emitting device, comprising: Light-emitting elements; and A driving circuit for driving the light-emitting element, the driving circuit comprising: A first type of transistor receives a data signal and includes a first gate terminal, a first source terminal, and a first drain terminal; The second type of transistor includes a second gate terminal that receives a first bias signal from a first bias source, a second source terminal coupled to a first drain terminal, and a second drain terminal coupled to a light-emitting element; A first capacitor is disposed between a first gate terminal and a second bias source; The driving sub-circuit is coupled to the first gate terminal and the first source terminal to provide a data signal and a third bias signal provided by the third bias source; The data writing sub-circuit is coupled to the driving sub-circuit to provide data signals to the driving sub-circuit; and The second capacitor is positioned between the driver sub-circuit and the data writing sub-circuit.

2. The light-emitting device according to claim 1, wherein the first type of transistor is a p-type transistor and the second type of transistor is an n-type transistor.

3. The light-emitting device according to claim 1, wherein the driving sub-circuit comprises: A first switching element is disposed between a first source terminal and a first terminal of a second capacitor; The second switching element is disposed between the first terminal of the second capacitor and the third bias source; and The third switching element is disposed between the first terminal and the first gate terminal of the second capacitor.

4. The light-emitting device according to claim 1, wherein the driving sub-circuit comprises: The fourth switching element is disposed between the third bias source and the first terminal of the second capacitor; and The fifth switching element is disposed between the first terminal and the first gate terminal of the second capacitor.

5. The light-emitting device according to claim 1, wherein the driving sub-circuit comprises: The sixth switching element is located between the first source terminal and the third bias source; The seventh switching element is disposed between the first source terminal and the first terminal of the second capacitor; and The eighth switching element is disposed between the first terminal of the second capacitor and the first initialization bias source.

6. The light-emitting device according to claim 1, wherein the driving sub-circuit comprises: The ninth switching element is located between the first source terminal and the third bias source; The tenth switching element is disposed between the first source terminal and the first terminal of the second capacitor; and The eleventh switching element is disposed between the first terminal and the first gate terminal of the second capacitor.

7. The light-emitting device according to claim 1, wherein the data writing sub-circuit comprises: The twelfth switching element is disposed between the second terminal of the second capacitor and the data signal source; and The thirteenth switching element is located between the second terminal of the second capacitor and the second initialization bias source.

8. A method for driving a light-emitting element through a pixel circuit, wherein the pixel circuit includes a first transistor, a second transistor disposed between the first transistor and the light-emitting element, a first capacitor disposed between a first gate terminal of the first transistor and a second gate terminal of the second transistor, and a second capacitor disposed between the first transistor and a data signal source based on a data signal, the method comprising: During initialization, the first terminal of the first capacitor is initialized to the first initial bias voltage, and the first terminal of the second capacitor is initialized to the second initial bias voltage. During the compensation period, the first terminal of the first capacitor is compensated to the compensation bias voltage; During data writing, a data signal is provided to the first terminal of the second capacitor; and During the emission period, the light-emitting element is driven to emit light according to the data signal.

9. The method of claim 8, wherein the pixel circuit further comprises a reset bias source coupled to the second transistor and the light-emitting element, and the method further comprises: During initialization, compensation, and data writing, a reset bias is provided to the pixel circuit via a reset bias source.

10. The method of claim 9, wherein initializing the first terminal of the first capacitor to the first initial bias voltage and initializing the first terminal of the second capacitor to the second initial bias voltage comprises: Provide a first initial bias voltage to the first terminal of the first capacitor; A first bias voltage is provided to the second terminal of the first capacitor; Provide a second initial bias voltage to the first terminal of the second capacitor; and The first terminal of the first capacitor is coupled to the second terminal of the second capacitor.

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