Pixel circuit, display device, and electronic device

Abstract

A pixel circuit, a display device, and an electronic device are provided. The pixel circuit includes: a first circuit section that performs PWM operation based on PWM data voltage; a second circuit section that generates a drive current based on a constant current voltage; and a light-emitting element that emits light based on the PWM data voltage and the constant current voltage. The first circuit section may include: a first transistor, including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor that transmits the PWM data voltage to the second node; and a third transistor connected to the first node and the third node. The second circuit section includes: a seventh transistor, including a control electrode connected to a fourth node, a first electrode connected to a fifth node, and a second electrode connected to the anode electrode of the light-emitting element; an eighth transistor that transmits the constant current voltage to the fourth node; and a third capacitor, including a first electrode connected to the fourth node and a second electrode to which a stabilizing voltage is applied.

Description

Technical Field

[0001] The present invention relates to a pixel circuit, a display device including the pixel circuit, and an electronic device including the display device. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driving unit. The display panel may include multiple gate lines, multiple data lines, and multiple pixels. The display panel driving unit may include a gate driving unit that provides gate signals to the gate lines, a data driving unit that provides data voltages to the data lines, and a drive control unit that controls the gate driving unit and the data driving unit.

[0003] Existing pixel circuits that drive and perform internal compensation of threshold voltage using pulse width modulation can include more than 19 transistors and more than 3 capacitors. In this case, due to the limitation of integration, it is difficult to apply them to ultra-high resolution display devices. Summary of the Invention

[0004] One object of the present invention is to provide a pixel circuit that drives and performs internal compensation of threshold voltage in a pulse width modulation manner, and includes a small number of transistors, thereby enabling its application in ultra-high resolution display devices.

[0005] Another object of the present invention is to provide a display device including the pixel circuit.

[0006] Another object of the present invention is to provide an electronic device including the aforementioned display device.

[0007] However, the purpose of this invention is not limited to the above-described purpose, and can be extended in various ways without departing from the concept and scope of this invention.

[0008] To achieve an objective of the present invention, a pixel circuit according to an embodiment of the present invention may include: a first circuit section for performing pulse width modulation (PWM) operation based on a pulse width modulation data voltage; a second circuit section for generating a drive current based on a constant current voltage; and a light-emitting element for emitting light based on the PWM data voltage and the constant current voltage. The first circuit section may include: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor for transmitting the PWM data voltage to the second node; and a third transistor connected to the first node and the third node. The second circuit section may include: a seventh transistor including a control electrode connected to a fourth node, a first electrode connected to a fifth node, and a second electrode connected to the anode electrode of the light-emitting element; an eighth transistor for transmitting the constant current voltage to the fourth node; and a third capacitor including a first electrode connected to the fourth node and a second electrode to which a stabilizing voltage is applied.

[0009] In one embodiment, the second transistor may include a control electrode to which a first write gate signal is applied, a first electrode connected to a data voltage terminal, and a second electrode connected to the second node, and the eighth transistor may include a control electrode to which a second write gate signal is applied, a first electrode connected to the data voltage terminal, and a second electrode connected to the fourth node.

[0010] In one embodiment, the second circuit section may further include a second capacitor, comprising a first electrode connected to the fifth node and a second electrode connected to the fourth node.

[0011] In one embodiment, the second circuit section may further include: a tenth transistor, including a control electrode to which a third initialization gate signal is applied, a first electrode connected to the anode electrode of the light-emitting element, and a second electrode to which a second initialization voltage is applied.

[0012] In one embodiment, the second electrode of the third capacitor may be connected to the control electrode of the tenth transistor, and the stabilization voltage may be the third initialization gate signal.

[0013] In one embodiment, the first circuit section may further include: a fourth transistor, including a control electrode to which a first initialization gate signal is applied, a first electrode connected to the first node, and a second electrode to which a first initialization voltage is applied.

[0014] In one embodiment, the first circuit section may further include: a first capacitor, including a first electrode to which a scan signal is applied and a second electrode connected to the first node.

[0015] In one embodiment, the second circuit section may further include an eleventh transistor, comprising a control electrode to which a second initialization gate signal is applied, a first electrode connected to the fourth node, and a second electrode to which a first initialization voltage is applied.

[0016] In one embodiment, the first circuit section may further include: a fifth transistor, including a control electrode to which a transmission signal is applied, a first electrode to which a first power supply voltage is applied, and a second electrode connected to the second node; and a sixth transistor, including a control electrode to which the transmission signal is applied, a first electrode connected to the third node, and a second electrode connected to the fourth node. The second circuit section may further include: a ninth transistor, including a control electrode, a first electrode to which a second power supply voltage is applied, and a second electrode connected to the fifth node.

[0017] In one embodiment, the transmit signal may be applied to the control electrode of the ninth transistor.

[0018] In one embodiment, the eighth transistor may include a control electrode to which a second write gate signal is applied, a first electrode connected to a data voltage terminal, and a second electrode connected to the fourth node, and may apply the second write gate signal to the control electrode of the ninth transistor.

[0019] In one embodiment, the second transistor may include a control electrode to which a first write gate signal is applied, a first electrode connected to a data voltage terminal, and a second electrode connected to the second node; the third transistor may include a control electrode to which a compensation gate signal is applied, a first electrode connected to the first node, and a second electrode connected to the third node; the eighth transistor may include a control electrode to which a second write gate signal is applied, a first electrode connected to the data voltage terminal, and a second electrode connected to the fourth node; the light-emitting element may include the anode electrode and a cathode electrode to which a third power supply voltage is applied; and the first circuit section may further include: a fourth transistor, including a control electrode to which a first initialization gate signal is applied, a first electrode connected to the first node, and a second electrode to which a first initialization voltage is applied; and a fifth transistor, including a control electrode to which an emission signal is applied, a first electrode to which a first power supply voltage is applied, and a second electrode connected to the second node. The second circuit section may further include: a second electrode connected to the first node; a sixth transistor, including a control electrode to which the emission signal is applied, a first electrode connected to the third node, and a second electrode connected to the fourth node; and a first capacitor, including a first electrode to which a scan signal is applied and a second electrode connected to the first node. The second circuit section may also include: a ninth transistor, including a control electrode to which the emission signal is applied, a first electrode to which a second power supply voltage is applied, and a second electrode connected to the fifth node; a tenth transistor, including a control electrode to which a third initialization gate signal is applied, a first electrode connected to the anode electrode of the light-emitting element, and a second electrode to which a second initialization voltage is applied; an eleventh transistor, including a control electrode to which a second initialization gate signal is applied, a first electrode connected to the fourth node, and a second electrode to which the first initialization voltage is applied; and a second capacitor, including a first electrode connected to the fifth node and a second electrode connected to the fourth node.

[0020] In one embodiment, in the first interval, the first initialization gate signal may have an active level, the second initialization gate signal may have an inactive level, the third initialization gate signal may have an active level, the first write gate signal may have an inactive level, the second write gate signal may have an inactive level, the compensation gate signal may have an inactive level, the transmit signal may have an inactive level, and the scan signal may have a high level.

[0021] In one embodiment, in the second interval, the first initialization gate signal may have an inactive level, the second initialization gate signal may have an inactive level, the third initialization gate signal may have an active level, the first write gate signal may have an active pulse, the second write gate signal may have an inactive level, the compensation gate signal may have an active pulse, the transmit signal may have an inactive level, the scan signal may have a high level, and the data voltage applied to the data voltage terminal may have a first level, wherein the data voltage having the first level may be the pulse width modulation data voltage.

[0022] In one embodiment, in the third interval, the first initialization gate signal may have an inactive level, the second initialization gate signal may have an active level, the third initialization gate signal may have an active level, the first write gate signal may have an inactive level, the second write gate signal may have an inactive level, the compensation gate signal may have an inactive level, the transmit signal may have an active level, the scan signal may have a high level, and the data voltage applied to the data voltage terminal may have a second level, wherein the data voltage having the second level may be the constant current voltage.

[0023] In one embodiment, in the fourth interval, the first initialization gate signal may have an inactive level, the second initialization gate signal may have an inactive level, the third initialization gate signal may have an active level, the first write gate signal may have an inactive level, the second write gate signal may have an active level, the compensation gate signal may have an inactive level, the transmit signal may have an inactive level, the scan signal may have a high level, and the data voltage applied to the data voltage terminal may have a second level, wherein the data voltage having the second level may be the constant current voltage.

[0024] In one embodiment, in the fifth and sixth intervals, the first initialization gate signal may have an inactive level, the second initialization gate signal may have an inactive level, the third initialization gate signal may have an inactive level, the first write gate signal may have an inactive level, the second write gate signal may have an inactive level, the compensation gate signal may have an inactive level, the transmit signal may have an active level, and the scan signal may gradually decrease from a high level.

[0025] To achieve another objective of the present invention, the display device may include: a display panel including pixel circuitry; a gate driving unit providing a gate signal to the pixel circuitry; an emission driving unit providing an emission signal to the pixel circuitry; and a data driving unit providing a data voltage to the pixel circuitry, wherein the pixel circuitry may include: a first circuit unit performing pulse width modulation (PWM) based on the PWM data voltage. The first circuit section includes: a first transistor, comprising a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor, transmitting the pulse width modulation data voltage to the second node; and a third transistor, connected to the first node and the third node. The second circuit section includes: a seventh transistor, comprising a control electrode connected to a fourth node, a first electrode connected to a fifth node, and a second electrode connected to the anode electrode of the light-emitting element; an eighth transistor, transmitting the constant current voltage to the fourth node; and a third capacitor, comprising a first electrode connected to the fourth node and a second electrode to which a stabilizing voltage is applied.

[0026] In one embodiment, the second transistor may include a control electrode to which a first write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the second node; the third transistor may include a control electrode to which a compensation gate signal is applied, a first electrode connected to the first node, and a second electrode connected to the third node; the eighth transistor may include a control electrode to which a second write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the fourth node; the light-emitting element may include the anode electrode and a cathode electrode to which a third power supply voltage is applied; and the first circuit section may further include: a fourth transistor, including a control electrode to which a first initialization gate signal is applied, a first electrode connected to the first node, and a second electrode to which a first initialization voltage is applied; and a fifth transistor, including a control electrode to which the emission signal is applied, a first electrode to which a first power supply voltage is applied, and a second electrode connected to the second node. The second circuit section may further include: a second electrode connected to the first node; a sixth transistor, including a control electrode to which the emission signal is applied, a first electrode connected to the third node, and a second electrode connected to the fourth node; and a first capacitor, including a first electrode to which a scan signal is applied and a second electrode connected to the first node. The second circuit section may also include: a ninth transistor, including a control electrode to which the emission signal is applied, a first electrode to which a second power supply voltage is applied, and a second electrode connected to the fifth node; a tenth transistor, including a control electrode to which a third initialization gate signal is applied, a first electrode connected to the anode electrode of the light-emitting element, and a second electrode to which a second initialization voltage is applied; an eleventh transistor, including a control electrode to which a second initialization gate signal is applied, a first electrode connected to the fourth node, and a second electrode to which the first initialization voltage is applied; and a second capacitor, including a first electrode connected to the fifth node and a second electrode connected to the fourth node.

[0027] To achieve another objective of the present invention, an electronic device according to an embodiment of the present invention may include: a processor for generating input control signals and input image data; a display panel including pixel circuitry; and a display panel driving unit for driving the display panel based on the input control signals and the input image data, wherein the pixel circuitry may include: a first circuit unit for performing pulse width modulation (PWM) based on pulse width modulation data voltage. The first circuit section includes: a first transistor, comprising a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor, transmitting the pulse width modulation data voltage to the second node; and a third transistor, connected to the first node and the third node. The second circuit section includes: a seventh transistor, comprising a control electrode connected to a fourth node, a first electrode connected to a fifth node, and a second electrode connected to the anode electrode of the light-emitting element; an eighth transistor, transmitting the constant current voltage to the fourth node; and a third capacitor, comprising a first electrode connected to the fourth node and a second electrode to which a stabilizing voltage is applied.

[0028] According to an embodiment of the present invention, the pixel circuit may include 11 transistors and 3 capacitors. The pixel circuit can be driven using pulse width modulation (PWM) and performs internal compensation for the threshold voltage. Compared to existing pixel circuits, the pixel circuit has a relatively small number of transistors, thus increasing the integration density of pixels included in the display panel. Increased pixel integration allows for increased resolution of the display device. Therefore, the pixel circuit can be applied to ultra-high resolution display devices.

[0029] The pixel circuit may include a first circuit section and a second circuit section. In this case, by configuring at least one transistor in the first circuit section and at least one transistor in the second circuit section as an N-channel metal-oxide-semiconductor (NMOS) transistor, power consumption can be reduced.

[0030] Furthermore, a second capacitor is included to compensate for the threshold voltage of the seventh transistor included in the second circuit section, thereby reducing the number of transistors.

[0031] Furthermore, when the second electrode of the third capacitor included in the second circuit section is connected to the stabilization voltage terminal, a stabilization voltage, which is a constant voltage, can be applied to the second electrode of the third capacitor. Therefore, coupling operations caused by the third capacitor can be prevented. Thus, the voltage of the fourth node can be stabilized. Therefore, the stability of the pixel circuit can be improved.

[0032] Furthermore, the first transistor included in the first circuit section and the seventh transistor included in the second circuit section can be P-channel metal-oxide-semiconductor (PMOS) transistors, in which case the mobility of the first transistor and the seventh transistor can be improved.

[0033] Furthermore, since the voltage level of the second initialization voltage used to initialize the anode electrode of the light-emitting element is lower than the voltage level of the third power supply voltage applied to the cathode electrode of the light-emitting element, leakage current can be prevented from flowing to the light-emitting element. Therefore, the black characteristics of the pixel circuit can be improved.

[0034] Furthermore, the pulse width modulation data voltage (VPWM) applied to the first electrode of the first transistor and the constant current voltage applied to the control electrode of the seventh transistor are both applied to the first circuit section or the second circuit section through the data voltage terminal, thus reducing the number of transistors and signal wiring. Therefore, the dead space of the display device can be reduced.

[0035] However, the effects of the present invention are not limited to those described above, and can be extended in various ways without departing from the concept and scope of the present invention. Attached Figure Description

[0036] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0037] Figure 2 It is shown that it includes Figure 1 A circuit diagram of an example of a pixel circuit in the display panel of a display device.

[0038] Figure 3 yes Figure 2 Timing diagram of pixel circuit operation.

[0039] Figure 4 It is shown Figure 2 The pixel circuit in Figure 3 The circuit diagram for the operation in the first interval of the timing diagram.

[0040] Figure 5 It is shown Figure 2 The pixel circuit in Figure 3 The circuit diagram for the operation in the second interval of the timing diagram.

[0041] Figure 6 It is shown Figure 2 The pixel circuit in Figure 3 The circuit diagram for the operation in the third interval of the timing diagram.

[0042] Figure 7 It is shown Figure 2 The pixel circuit in Figure 3 The circuit diagram for the operation in the fourth interval of the timing diagram.

[0043] Figure 8 It is shown Figure 2 The pixel circuit in Figure 3 The circuit diagram for the operation in the fifth interval of the timing diagram.

[0044] Figure 9 It is shown Figure 2 The pixel circuit in Figure 3 The circuit diagram for the operation in the sixth interval of the timing diagram.

[0045] Figure 10 It is shown that it includes Figure 1 A conceptual diagram of the driving frequency of the display panel in a display device.

[0046] Figure 11 yes Figure 2 The timing diagram of the pixel circuitry operating in the write frame.

[0047] Figure 12 yes Figure 2 The timing diagram of the pixel circuitry operating in the holding frame.

[0048] Figure 13 It is shown that it includes Figure 1 A circuit diagram of another example of pixel circuitry in the display panel of a display device.

[0049] Figure 14 yes Figure 13 Timing diagram of pixel circuit operation.

[0050] Figure 15 It is shown that it includes Figure 1 A circuit diagram of yet another example of pixel circuitry in the display panel of a display device.

[0051] Figure 16 yes Figure 15 Timing diagram of pixel circuit operation.

[0052] Figure 17 It is shown that it includes Figure 1A circuit diagram of yet another example of pixel circuitry in the display panel of a display device.

[0053] Figure 18 yes Figure 17 Timing diagram of pixel circuit operation.

[0054] Figure 19 It is shown that it includes Figure 1 A circuit diagram of yet another example of pixel circuitry in the display panel of a display device.

[0055] Figure 20 yes Figure 19 Timing diagram of pixel circuit operation.

[0056] Figure 21 This is a block diagram illustrating an electronic device according to an embodiment of the present invention.

[0057] Figure 22 It is shown Figure 21 The diagram shows an example of an electronic device implemented as a smartphone.

[0058] Explanation of reference numerals in the attached figures 100: Display panel; 200: Drive control unit 300: Gate driving section; 400: Gamma reference voltage generation section 500: Data drive unit; 600: Transmission drive unit 1000: Electronic devices Detailed Implementation

[0059] The present invention will now be described in more detail with reference to the accompanying drawings.

[0060] Figure 1 This is a block diagram illustrating a display device 1 according to an embodiment of the present invention.

[0061] Reference Figure 1 The display device 1 may include a display panel 100 and a display panel driving unit 700. The display panel driving unit 700 may include a driving control unit 200, a gate driving unit 300, a gamma reference voltage generating unit 400, and a data driving unit 500. The display panel driving unit 700 may include a transmission driving unit 600.

[0062] The display panel 100 may include a display section for displaying images and a peripheral section arranged adjacent to the display section.

[0063] The display panel 100 may include circuitry for gate lines GL, emitter lines EL, data lines DL, and pixels PX. Gate lines GL may extend along a first direction D1, emitter lines EL may extend along the first direction D1, and data lines DL may extend along a second direction D2 that intersects the first direction D1.

[0064] The drive control unit 200 can receive input image data IMG and input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. According to an embodiment, the input image data IMG may also include white image data. As another example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0065] The drive control unit 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0066] The drive control unit 200 can generate a first control signal CONT1 for controlling the operation of the gate drive unit 300 based on the input control signal CONT and output it to the gate drive unit 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0067] The drive control unit 200 can generate a second control signal CONT2 for controlling the operation of the data drive unit 500 based on the input control signal CONT and output it to the data drive unit 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0068] The drive control unit 200 can generate a data signal DATA based on the input image data IMG. The drive control unit 200 can output the data signal DATA to the data drive unit 500.

[0069] The drive control unit 200 can generate a third control signal CONT3 for controlling the operation of the gamma reference voltage generation unit 400 based on the input control signal CONT, and output it to the gamma reference voltage generation unit 400.

[0070] The drive control unit 200 can generate a fourth control signal CONT4 for controlling the operation of the transmitter drive unit 600 based on the input control signal CONT and output it to the transmitter drive unit 600.

[0071] The gate driving unit 300 can generate a gate signal transmitted to the gate line GL via the circuit of the pixel PX in response to the first control signal CONT1 received from the driving control unit 200. The gate driving unit 300 can output the gate signal to the gate line GL.

[0072] In one embodiment, the gate driving portion 300 may be integrated into the periphery of the display panel 100.

[0073] The gamma reference voltage generation unit 400 can generate a gamma reference voltage VGREF based on the third control signal CONT3 received from the drive control unit 200. The gamma reference voltage generation unit 400 can provide the gamma reference voltage VGREF to the data drive unit 500. The gamma reference voltage VGREF can have a value corresponding to each data signal DATA.

[0074] For example, the gamma reference voltage generation unit 400 can be arranged in the drive control unit 200, or it can be arranged in the data drive unit 500.

[0075] The data drive unit 500 can receive a second control signal CONT2 and a data signal DATA from the drive control unit 200, and a gamma reference voltage VGREF from the gamma reference voltage generation unit 400. The data drive unit 500 can use the gamma reference voltage VGREF to convert the digital data signal DATA into an analog data voltage. The data drive unit 500 can output the data voltage to the data line DL.

[0076] In one embodiment, the data driver unit 500 may be integrated into the periphery of the display panel 100.

[0077] The transmit drive unit 600 can generate a transmit signal in response to the fourth control signal CONT4 received from the drive control unit 200. The transmit drive unit 600 can output the transmit signal to the transmit line EL.

[0078] In one embodiment, the transmission driver 600 may be integrated into the periphery of the display panel 100.

[0079] Figure 2 It is shown that it includes Figure 1 A circuit diagram of an example of the circuitry for the pixel PX in the display panel 100 of the display device 1.

[0080] Reference Figure 2 The circuitry of a pixel PX may include a first circuit section PC and a second circuit section CC.

[0081] The first circuit section PC can be a pulse width modulation circuit section for performing pulse width modulation (PWM) operation. The second circuit section CC can be a constant current generation circuit section for performing constant current generation (CCG) operation.

[0082] The first circuit section PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, as well as a first capacitor C1. The second circuit section CC may include a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a second capacitor C2, a third capacitor C3, and a light-emitting element EE.

[0083] The first transistor T1 may include a control electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first transistor T1 may be designated as the driving transistor of the first circuit section PC.

[0084] In one embodiment, the first transistor T1 may further include a second control electrode to which a first power supply voltage VDD1 is applied. If the charge of the first transistor T1 concentrates in one direction, resulting in a charge imbalance, spots may appear on the display panel 100 due to this charge imbalance. By including a second control electrode to which the first power supply voltage VDD1 is applied in the first transistor T1, the charge imbalance can be resolved, thereby preventing spots from appearing on the display panel 100.

[0085] The second transistor T2 may include a control electrode to which a first write gate signal GW1[n] is applied, a first electrode connected to the data voltage VDATA terminal, and a second electrode connected to the second node N2.

[0086] The third transistor T3 may include a control electrode to which a compensation gate signal GC[n] is applied, a first electrode connected to the first node N1, and a second electrode connected to the third node N3.

[0087] In one embodiment, the third transistor T3 may further include a second control electrode connected to the control electrode of the third transistor T3. This can improve the mobility of the third transistor T3.

[0088] The fourth transistor T4 may include a control electrode to which a first initialization gate signal GI1 is applied, a first electrode connected to the first node N1, and a second electrode to which a first initialization voltage VINT is applied.

[0089] In one embodiment, the fourth transistor T4 may further include a second control electrode connected to the control electrode of the fourth transistor T4. Accordingly, the mobility of the fourth transistor T4 can be improved.

[0090] The fifth transistor T5 may include a control electrode to which a transmission signal EM is applied, a first electrode to which a first power supply voltage VDD1 is applied, and a second electrode connected to the second node N2.

[0091] The sixth transistor T6 may include a control electrode to which an emission signal EM is applied, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4.

[0092] The seventh transistor T7 may include a control electrode connected to the fourth node N4, a first electrode connected to the fifth node N5, and a second electrode connected to the anode ANODE of the light-emitting element EE. The seventh transistor T7 may be designated as the driving transistor of the second circuit section CC.

[0093] In one embodiment, the seventh transistor T7 may further include a second control electrode to which a second power supply voltage VDD2 is applied. If the charge of the seventh transistor T7 concentrates in one direction, resulting in a charge imbalance, spots may be generated on the display panel 100 due to the charge imbalance of the seventh transistor T7. When the seventh transistor T7 also includes a second control electrode to which the second power supply voltage VDD2 is applied, the charge imbalance can be resolved, thereby preventing spots from forming on the display panel 100.

[0094] The eighth transistor T8 may include a control electrode to which a second write gate signal GW2 is applied, a first electrode connected to the data voltage VDATA terminal, and a second electrode connected to the fourth node N4.

[0095] The ninth transistor T9 may include a control electrode to which a transmit signal EM is applied, a first electrode to which a second power supply voltage VDD2 is applied, and a second electrode connected to the fifth node N5.

[0096] The tenth transistor T10 may include a control electrode to which a third initialization gate signal BCB is applied, a first electrode connected to the anode electrode ANODE, and a second electrode to which a second initialization voltage VAINT is applied.

[0097] The eleventh transistor T11 may include a control electrode to which a second initialization gate signal GI2 is applied, a first electrode connected to the fourth node N4, and a second electrode to which a first initialization voltage VINT is applied.

[0098] The first capacitor C1 may include a first electrode to which the scan signal SWEEP is applied and a second electrode connected to the first node N1.

[0099] The second capacitor C2 may include a first electrode connected to the fifth node N5 and a second electrode connected to the fourth node N4.

[0100] The third capacitor C3 may include a first electrode connected to the fourth node N4 and a second electrode connected to the stabilization voltage DC terminal. A stabilization voltage DC can be applied to the stabilization voltage DC terminal. In this case, the stabilization voltage DC can be a constant voltage. For example, the stabilization voltage DC can be a first power supply voltage VDD1. For example, the stabilization voltage DC can be a second power supply voltage VDD2. For example, the stabilization voltage DC can be a third power supply voltage VSS. For example, the stabilization voltage DC can be a first initialization voltage VINT. For example, the stabilization voltage DC can be a second initialization voltage VAINT.

[0101] When the second electrode of the third capacitor C3 is connected to the anode electrode ANODE of the light-emitting element EE, the voltage of the fourth node N4 can change due to the coupling operation of the third capacitor C3 when the voltage of the anode electrode ANODE of the light-emitting element EE changes. In this case, the stability of the pixel PX circuit may decrease. Conversely, when the second electrode of the third capacitor C3 is connected to the stabilization voltage DC terminal, the stabilization voltage DC, which is a constant voltage, can be applied to the second electrode of the third capacitor C3. Therefore, the coupling operation caused by the third capacitor C3 can be prevented. Therefore, the voltage of the fourth node N4 can be stabilized. Therefore, the stability of the pixel PX circuit can be improved.

[0102] The light-emitting element EE may include an anode electrode ANODE connected to the second electrode of the seventh transistor T7 and a cathode electrode to which a third power supply voltage VSS is applied. For example, the light-emitting element EE may be a light-emitting diode. For example, the light-emitting element EE may be a micro light-emitting diode.

[0103] One portion of the transistors in the pixel PX's circuitry can be P-channel metal-oxide-semiconductor (PMOS) transistors, while another portion can be N-channel metal-oxide-semiconductor (NMOS) transistors. For example, a PMOS transistor can be a low-temperature polysilicon (LTPS) transistor. Similarly, an NMOS transistor can be an oxide transistor.

[0104] The third transistor T3, the fourth transistor T4, and the eleventh transistor T11 can be NMOS transistors, thereby reducing their leakage current. Therefore, even with relatively low power supply voltages applied to the third transistor T3, the fourth transistor T4, and the eleventh transistor T11, the pixel PX circuit can operate stably. As a result, the power consumption of the display device 1 can be reduced.

[0105] The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can be PMOS transistors.

[0106] The data voltage VDATA output from the data voltage VDATA terminal can be an AC voltage. The data voltage VDATA output from the data voltage VDATA terminal can have one of a first level, a second level, and a third level. For example, the data voltage VDATA with the first level can be a pulse-width modulated data voltage applied to the first electrode of the second transistor T2. Figure 3 The VPWM (Voltage Width Modulation) of the second level data voltage VDATA can be a constant current voltage applied to the first electrode of the eighth transistor T8. Figure 3 (VCCG). The data voltage VDATA with a third level can be a low voltage.

[0107] When the second transistor T2 is turned on, the data voltage VDATA can be transmitted to the second node N2. At this time, the data voltage VDATA can be a pulse-width modulated data voltage (PWM). Figure 3 (VPWM). When the eighth transistor T8 is turned on, the data voltage VDATA can be transmitted to the fourth node N4. At this time, the data voltage VDATA can be a constant current voltage (VPWM). Figure 3 (VCCG).

[0108] At this time, the pulse width modulation data voltage ( Figure 3 VPWM) and constant current voltage ( Figure 3 Both VCCG are applied through the data voltage VDATA terminal, therefore it is not necessary to use a constant current voltage (VCCG) to apply the constant current voltage (VCCG). Figure 3 The additional voltage wiring (VCCG) is transmitted to the fourth node N4. Therefore, the dead space of the display device 1 can be reduced.

[0109] In one embodiment, pulse width modulated data voltage ( Figure 3 The VPWM (Voltage Width Modulation) can vary depending on the luminous intensity of the pixel PX's circuitry. In one embodiment, the constant current voltage (VPWM) Figure 3The VCCG circuitry can be identical for all pixel PXs. In one embodiment, the constant current voltage (VCCG) Figure 3 The VCCG (Color, Color, and Variable Voltage) can vary depending on the color of the circuitry of a pixel PX. For example, the constant current voltage applied to the circuitry of a pixel PX that emits red light (VCCG) can vary. Figure 3 The VCCG can have a first voltage level, a constant current voltage applied to the circuitry of the green-emitting pixel PX. Figure 3 The VCCG can have a second voltage level different from the first voltage level, and a constant current voltage is applied to the circuitry of the blue-emitting pixel PX. Figure 3 The VCCG can have a third voltage level that is different from the first voltage level and the second voltage level.

[0110] For example, the first power supply voltage VDD1 and the second power supply voltage VDD2 can be high power supply voltages used to determine the luminous intensity of the light-emitting element EE, and the third power supply voltage VSS can be a low power supply voltage used to determine the luminous intensity of the light-emitting element EE. The voltage level of the first power supply voltage VDD1 and the voltage level of the second power supply voltage VDD2 can be higher than the voltage level of the third power supply voltage VSS. Furthermore, the voltage level of the first power supply voltage VDD1 can be higher than the voltage level of the second power supply voltage VDD2.

[0111] During the light-emitting interval, the light-emitting element EE can emit light while the first transistor T1 is turned off and the seventh transistor T7 is turned on. During the light-emitting off interval, if the first transistor T1 is turned on and the first power supply voltage VDD1 is applied to the control electrode of the seventh transistor T7, the seventh transistor T7 can be turned off, and the light-emitting element EE can stop emitting light.

[0112] At this time, if the voltage level of the first power supply voltage VDD1 is higher than the voltage level of the second power supply voltage VDD2, then when the first power supply voltage VDD1 is applied to the control electrode of the seventh transistor T7, the seventh transistor T7 can more reliably remain in the off state.

[0113] For example, the voltage level of the second initialization voltage VAINT can be lower than the voltage level of the third power supply voltage VSS. If the voltage level of the second initialization voltage VAINT is lower than the voltage level of the third power supply voltage VSS, leakage current will not flow to the light-emitting element EE. Therefore, the black characteristics of the pixel PX circuit can be improved.

[0114] In the first circuit section PC, the threshold voltage of the first transistor T1 can be internally compensated by utilizing the diode connection structure of the third transistor T3.

[0115] On the other hand, in the second circuit section CC, a source follower structure including the second capacitor C2 can be used to internally compensate the threshold voltage of the seventh transistor T7.

[0116] In the case of the first circuit section PC, since pulse width modulation operation is performed, a relatively low current may flow through it. If the first circuit section PC uses a source follower structure, spotting may occur because the threshold voltage of the first transistor T1 is not adequately compensated. Therefore, the first circuit section PC can employ a diode connection structure using the third transistor T3 to achieve internal compensation of the threshold voltage of the first transistor T1.

[0117] Conversely, in the case of the second circuit section CC, since a constant current application operation is performed, a relatively high current may be applied. Because the second circuit section CC employs a source follower structure, a high current can be applied to the second circuit section CC even if the threshold voltage of the seventh transistor T7 is not adequately compensated, thus reducing the likelihood of image quality issues. Therefore, the second circuit section CC can employ a source follower structure utilizing the second capacitor C2 to achieve internal compensation of the threshold voltage of the seventh transistor T7, thereby reducing the number of transistors in the pixel PX circuit.

[0118] Furthermore, as the capacitance of the second capacitor C2 increases and the capacitance of the third capacitor C3 decreases, the compensation capability for the threshold voltage of the seventh transistor T7 can be improved.

[0119] The first write gate signal GW1[n] can be a progressive scan signal with different timing for each pixel row. Here, n is an integer greater than or equal to 1. The first write gate signal GW1[n] is applied to... Figure 2 The circuit for pixel PX can be the circuit for pixel PX included in the nth pixel row.

[0120] The first initialization gate signal GI1, the second initialization gate signal GI2, the third initialization gate signal BCB, and the second write gate signal GW2 can be global signals with the same timing independent of pixel rows. The transmit signal EM can also be a global signal with the same timing independent of pixel rows. That is, the first initialization gate signal GI1, the second initialization gate signal GI2, the third initialization gate signal BCB, the second write gate signal GW2, and the transmit signal EM can be simultaneously applied to the circuitry of the pixel PX included in the display panel 100.

[0121] Furthermore, the first power supply voltage VDD1, the second power supply voltage VDD2, the third power supply voltage VSS, the first initialization voltage VINT, and the second initialization voltage VAINT can be constant voltages. Additionally, the stabilization voltage DC can also be a constant voltage.

[0122] Figure 3 yes Figure 2 Timing diagram of the circuit operation of pixel PX. Figure 4 It is shown Figure 2 The circuitry of the pixel PX in Figure 3 The circuit diagram for the operation in the first interval DR1 of the timing diagram. Figure 5 It is shown Figure 2 The circuitry of the pixel PX in Figure 3 The circuit diagram for the operation in the second interval DR2 of the timing diagram. Figure 6 It is shown Figure 2 The circuitry of the pixel PX in Figure 3 The circuit diagram for the operation in the third interval DR3 of the timing diagram. Figure 7 It is shown Figure 2 The circuitry of the pixel PX in Figure 3 The circuit diagram for the operation in the fourth interval DR4 of the timing diagram. Figure 8 It is shown Figure 2 The circuitry of the pixel PX in Figure 3 The circuit diagram for the operation in the fifth interval DR5 of the timing diagram. Figure 9 It is shown Figure 2 The circuitry of the pixel PX in Figure 3 The circuit diagram for the operation in the sixth interval DR6 of the timing diagram.

[0123] Reference Figure 3 The range of signals applied to the circuit that applies signals to the pixel PX may include the first range DR1, the second range DR2, the third range DR3, the fourth range DR4, the fifth range DR5, and the sixth range DR6.

[0124] The first interval DR1 can be the first initialization interval, the second interval DR2 can be the pulse width modulation data voltage VPWM writing and first compensation interval, the third interval DR3 can be the second initialization interval, the fourth interval DR4 can be the constant current voltage VCCG writing and second compensation interval, the fifth interval DR5 can be the light emission interval, and the sixth interval DR6 can be the light emission off interval.

[0125] The width of the fifth interval DR5 can be determined by the level of the pulse width modulation data voltage VPWM of the second interval DR2.

[0126] The scanning signal SWEEP can have a constant high level in the first interval DR1 to the fourth interval DR4, and can gradually decrease in the fifth interval DR5 and the sixth interval DR6.

[0127] For ease of explanation, Figure 3 , Figure 11 , Figure 14 , Figure 16 , Figure 18 as well as Figure 20 In the second interval DR2, the waveforms of the first write gate signal GW1[n] and the pulse width modulation data voltage VPWM are shown as multiple times. However, this does not mean that the first write gate signal GW1[n] and the pulse width modulation data voltage VPWM are applied multiple times. Rather, it means that while the first write gate signal GW1[n] is applied to each pixel row in sequence, the pulse width modulation data voltage VPWM is written on a pixel row basis.

[0128] Reference Figure 3 In the first interval DR1, the first initialization gate signal GI1 and the third initialization gate signal BCB can have an active level. For example, the first initialization gate signal GI1 can have a high level, and the third initialization gate signal BCB can have a low level. Furthermore, the second initialization gate signal GI2, the first write gate signal GW1[n], the second write gate signal GW2, the compensation gate signal GC[n], and the transmit signal EM can have an inactive level. For example, the second initialization gate signal GI2 can have a low level, the first write gate signal GW1[n], the second write gate signal GW2, and the transmit signal EM can have a high level, and the compensation gate signal GC[n] can have a low level. Additionally, the scan signal SWEEP can have a high level. Furthermore, the data voltage VDATA applied to the data voltage VDATA terminal can have a third level. That is, the data voltage VDATA is a low voltage, and a low voltage can be applied to the data voltage VDATA terminal.

[0129] The fourth transistor T4 and the tenth transistor T10 can be turned on. Therefore, the fourth transistor T4 can transmit the first initialization voltage VINT to the first node N1, and the tenth transistor T10 can transmit the second initialization voltage VAINT to the anode ANODE of the light-emitting element EE.

[0130] The voltage at the first node N1 can be initialized to a first initialization voltage VINT. The first initialization voltage VINT can have a level used to turn on the first transistor T1. In the first interval DR1, the anode electrode ANODE of the light-emitting element EE can be initialized to a second initialization voltage VAINT.

[0131] Reference Figure 5 In the second interval DR2, the first write gate signal GW1[n] and the compensation gate signal GC[n] can have activation pulses. Furthermore, the third initialization gate signal BCB can have an activation level. For example, the third initialization gate signal BCB can have a low level. Additionally, the first initialization gate signal GI1, the second initialization gate signal GI2, the second write gate signal GW2, and the transmit signal EM can have inactive levels. For example, the first initialization gate signal GI1 and the second initialization gate signal GI2 can have low levels, while the second write gate signal GW2 and the transmit signal EM can have high levels. Furthermore, the scan signal SWEEP can remain high. Furthermore, the data voltage VDATA applied to the data voltage VDATA terminal can have a first level. That is, the data voltage VDATA can be a pulse width modulated data voltage VPWM, and the pulse width modulated data voltage VPWM can be applied to the data voltage VDATA terminal.

[0132] The tenth transistor T10 can be turned on. Furthermore, the second transistor T2 can be turned on by the first write gate signal GW1[n]. The first transistor T1 can be turned on by the voltage of the first node N1. Furthermore, the third transistor T3 can be turned on by the compensation gate signal GC[n]. Therefore, the pulse width modulation data voltage VPWM can be transmitted to the first node N1 through the first transistor T1 to the third transistor T3. At this time, the threshold voltage of the first transistor T1 can be compensated by the third transistor T3, which connects its diode.

[0133] The voltage of the control electrode of the first transistor T1 can be "VPWM-Vth1" (VPWM refers to the pulse width modulation data voltage, and Vth1 refers to the threshold voltage of the first transistor T1). In the second interval DR2, if the first node N1 completes the storage of a voltage of "VPWM-Vth1", then the first transistor T1 can be turned off.

[0134] Reference Figure 6In the third interval DR3, the second initialization gate signal GI2, the transmit signal EM, and the third initialization gate signal BCB can have an active level. For example, the second initialization gate signal GI2 can have a high level, and the transmit signal EM and the third initialization gate signal BCB can have a low level. Furthermore, the first initialization gate signal GI1, the first write gate signal GW1[n], the second write gate signal GW2, and the compensation gate signal GC[n] can have an inactive level. For example, the first initialization gate signal GI1 and the compensation gate signal GC[n] can have a low level, and the first write gate signal GW1[n] and the second write gate signal GW2 can have a high level. Additionally, the scan signal SWEEP can remain at a high level. Furthermore, the data voltage VDATA applied to the data voltage VDATA terminal can have a second level. That is, the data voltage VDATA can be a constant current voltage VCCG, and the constant current voltage VCCG can be applied to the data voltage VDATA terminal.

[0135] The tenth transistor T10 can be turned on. Furthermore, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, and the eleventh transistor T11 can be turned on. Therefore, the fifth transistor T5 can transmit the first power supply voltage VDD1 to the second node N2. The first initialization voltage VINT can be transmitted to the third node N3 through the sixth transistor T6 and the eleventh transistor T11. The first initialization voltage VINT can be transmitted to the fourth node N4 through the eleventh transistor T11. The second power supply voltage VDD2 can be transmitted to the fifth node N5 through the ninth transistor T9.

[0136] At this point, the voltage of the fifth node N5 can be initialized to the first initialization voltage VINT.

[0137] Reference Figure 7In the fourth interval DR4, the second write gate signal GW2 and the third initialization gate signal BCB can have an active level. For example, the second write gate signal GW2 and the third initialization gate signal BCB can have a low level. Furthermore, the first initialization gate signal GI1, the second initialization gate signal GI2, the first write gate signal GW1[n], the compensation gate signal GC[n], and the transmit signal EM can have an inactive level. For example, the first initialization gate signal GI1, the second initialization gate signal GI2, and the compensation gate signal GC[n] can have a low level, while the first write gate signal GW1[n] and the transmit signal EM can have a high level. Furthermore, the scan signal SWEEP can remain at a high level. Additionally, the data voltage VDATA applied to the data voltage VDATA terminal can have a second level. That is, the data voltage VDATA can be a constant current voltage VCCG, and the constant current voltage VCCG can be applied to the data voltage VDATA terminal.

[0138] The tenth transistor T10 can be turned on. Furthermore, the eighth transistor T8 can be turned on. Therefore, the eighth transistor T8 can transfer the constant current voltage VCCG to the fourth node N4. Thus, the constant current voltage VCCG can be applied to the fourth node N4.

[0139] At this point, the constant current voltage VCCG can be stored in the third capacitor C3.

[0140] In the fourth interval DR4, the voltage of the fourth node N4 can be "VCCG", and the voltage of the fifth node N5 can be "VCCG+Vth7" (VCCG refers to the constant current voltage VCCG, and Vth7 represents the threshold voltage of the seventh transistor T7).

[0141] Reference Figure 8 In the fifth interval DR5, the transmit signal EM can have an active level. For example, the transmit signal EM can have a low level. Furthermore, the first initialization gate signal GI1, the second initialization gate signal GI2, the third initialization gate signal BCB, the first write gate signal GW1[n], the second write gate signal GW2, and the compensation gate signal GC[n] can have inactive levels. For example, the first initialization gate signal GI1, the second initialization gate signal GI2, and the compensation gate signal GC[n] can have low levels, while the first write gate signal GW1[n], the second write gate signal GW2, and the third initialization gate signal BCB can have high levels. Furthermore, the scan signal SWEEP can gradually decrease from a high level to a low level. Additionally, the data voltage VDATA applied to the data voltage VDATA terminal can have a third level. That is, the data voltage VDATA can be a low voltage, and a low voltage can be applied to the data voltage VDATA terminal.

[0142] The fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 can be turned on. In addition, the seventh transistor T7 can be turned on by the constant current voltage VCCG of the fourth node N4.

[0143] As current flows along the path of the ninth transistor T9, the seventh transistor T7, and the light-emitting element EE, the light-emitting element EE can emit light.

[0144] At this point, the voltage at the fourth node N4 can be the same as in the following mathematical formula 1.

[0145] [Mathematical Expression 1]

[0146] Wherein, VCCG refers to the constant current voltage VCCG, Vth7 refers to the threshold voltage of the seventh transistor T7, C2 refers to the capacitance of the second capacitor C2, and C3 refers to the capacitance of the third capacitor C3.

[0147] Reference Figure 9 In the sixth interval DR6, the transmit signal EM can remain at the active level. For example, the transmit signal EM can remain at a low level. Furthermore, the first initialization gate signal GI1, the second initialization gate signal GI2, the third initialization gate signal BCB, the first write gate signal GW1[n], the second write gate signal GW2, and the compensation gate signal GC[n] can remain at the inactive level. For example, the first initialization gate signal GI1, the second initialization gate signal GI2, and the compensation gate signal GC[n] can remain at a low level, while the first write gate signal GW1[n], the second write gate signal GW2, and the third initialization gate signal BCB can remain at a high level. Furthermore, the scan signal SWEEP can continue to gradually decrease after the fifth interval DR5. Additionally, the data voltage VDATA applied to the data voltage VDATA terminal can have a third level. That is, the data voltage VDATA can be a low voltage, and a low voltage can be applied to the data voltage VDATA terminal.

[0148] As the scan signal SWEEP gradually decreases, the voltage of the first node N1 can also gradually decrease through the coupling operation of the first capacitor C1. The voltage of the first node N1 can decrease from "VPWM-Vth1" due to the gradually decreasing scan signal SWEEP. Here, VPWM is the pulse width modulation data voltage, and Vth1 refers to the threshold voltage of the first transistor T1. When the voltage of the first node N1 has a specific level, the first transistor T1 can be turned on.

[0149] If the first transistor T1 is turned on, the first power supply voltage VDD1 can be applied to the control electrode of the seventh transistor T7 along the path of the fifth transistor T5, the first transistor T1, and the sixth transistor T6.

[0150] If the first power supply voltage VDD1 is applied to the control electrode of the seventh transistor T7, the seventh transistor T7 can be turned off, and the light-emitting element EE can stop emitting light.

[0151] The timing at which the first transistor T1 is turned on can be determined by the level of the pulse width modulation data voltage VPWM applied to the control electrode of the first transistor T1. That is, the length of the light-emitting region of the light-emitting element EE can be determined by the pulse width modulation data voltage VPWM.

[0152] The circuitry for a pixel (PX) can include 11 transistors and 3 capacitors. The PX circuitry can be driven using pulse-width modulation (PWM) and perform internal compensation for the threshold voltage. Compared to existing pixel circuits, the PX circuitry has a relatively small number of transistors, thus increasing the integration density of the PX circuitry included in the display panel 100. Increased integration density of the PX circuitry allows for an increase in the resolution of the display device 1. Therefore, the PX circuitry can be applied to ultra-high resolution display devices.

[0153] Furthermore, at least one transistor in the first circuit section PC and at least one transistor in the second circuit section CC can be configured as an NMOS transistor, thereby reducing power consumption.

[0154] In addition, the second circuit section CC may include a second capacitor C2 that performs internal compensation on the threshold voltage of the seventh transistor T7, thereby reducing the number of transistors.

[0155] Furthermore, the first transistor T1 of the first circuit section PC and the seventh transistor T7 of the second circuit section CC can be PMOS transistors. In this case, the mobility of the first transistor T1 and the seventh transistor T7 can be improved.

[0156] Furthermore, since the voltage level of the second initialization voltage VAINT used to initialize the anode electrode ANODE of the light-emitting element EE is lower than the voltage level of the third power supply voltage VSS applied to the cathode electrode of the light-emitting element EE, leakage current flowing to the light-emitting element EE can be prevented. Therefore, the black characteristics of the pixel PX circuitry can be improved.

[0157] Furthermore, since the pulse width modulation data voltage VPWM applied to the first electrode of the first transistor T1 and the constant current voltage VCCG applied to the control electrode of the seventh transistor T7 are both applied to the first circuit section PC or the second circuit section CC through the data voltage VDATA terminal, the number of transistors and the number of signal wirings can be reduced. Therefore, the dead zone of the display device 1 can be reduced.

[0158] Figure 10 It is shown that it includes Figure 1 A conceptual diagram of the driving frequency of the display panel 100 in the display device 1. Figure 11 yes Figure 2 Timing diagram of the circuitry of the pixel PX operating in the writing frame FRAME. Figure 12 yes Figure 2 The timing diagram of the circuitry for pixel PX operating in the holding frame.

[0159] Reference Figures 10 to 12 The display panel 100 can be driven at a variable frequency.

[0160] A first frame FR1 having a first frequency may include a first active interval AC1 and a first blank interval BL1. A second frame FR2 having a second frequency different from the first frequency may include a second active interval AC2 and a second blank interval BL2. A third frame FR3 having a third frequency different from the first frequency and the second frequency may include a third active interval AC3 and a third blank interval BL3.

[0161] The first valid interval AC1 can have the same length as the second valid interval AC2, and the first blank interval BL1 can have a different length than the second blank interval BL2.

[0162] The second valid interval AC2 can have the same length as the third valid interval AC3, and the second blank interval BL2 can have a different length than the third blank interval BL3.

[0163] The variable frequency display device 1 may include: a writing frame (WRITING FRAME) that writes a pulse width modulation data voltage (VPWM) to the circuitry of pixel PX; and a holding frame (HOLDING FRAME) that does not write the VPWM to the circuitry of pixel PX and only performs light emission. The writing frame (WRITING FRAME) may be arranged within the active range AC. The holding frame (HOLDING FRAME) may be arranged within the blank range BL.

[0164] For example, in a writing frame, the pulse width modulation data voltage VPWM can be applied to the first transistor T1, and the light-emitting element EE can emit light. Conversely, in a holding frame, the pulse width modulation data voltage VPWM may not be applied to the first transistor T1, and the light-emitting element EE can still emit light.

[0165] exist Figure 11 In the writing frame, the first interval DR1 can be the first initialization interval, the second interval DR2 can be the pulse width modulation data voltage VPWM writing and first compensation interval, the third interval DR3 can be the second initialization interval, the fourth interval DR4 can be the constant current voltage VCCG writing and second compensation interval, the fifth interval DR5 can be the light emission interval, and the sixth interval DR6 can be the light emission off interval. Figure 11 The timing diagram can be combined with Figure 3 The timing diagrams are the same. Therefore, the sequence will be omitted. Figure 11 Explanation of the timing diagram.

[0166] exist Figure 12 In the holding frame, the first interval DR1 can be the first initialization interval, the second interval DR2 can be the pulse width modulation data voltage VPWM writing and the first compensation interval, the third interval DR3 can be the second initialization interval, the fourth interval DR4 can be the constant current voltage VCCG writing and the second compensation interval, the fifth interval DR5 can be the light emission interval, and the sixth interval DR6 can be the light emission off interval.

[0167] In addition to the data voltage VDATA, the first write gate signal GW1[n], the first initialization gate signal GI1, and the compensation gate signal GC[n], Figure 12 The timing diagram and Figure 3 The timing diagrams are essentially the same; therefore, the same reference numerals are used for the same or similar components, and repeated descriptions are omitted.

[0168] In the holding frame, the data voltage VDATA can have a third level in the first interval DR1, the second interval DR2, the fifth interval DR5, and the sixth interval DR6. That is, in the holding frame, the data voltage VDATA can be a low voltage.

[0169] In the third interval DR3 and the fourth interval DR4 of the holding frame, the data voltage VDATA can have a second level. That is, in the third interval DR3 and the fourth interval DR4 of the holding frame, the data voltage VDATA can be a constant current voltage VCCG.

[0170] In the first interval DR1 to the sixth interval DR6 of the holding frame, the first write gate signal GW1[n], the first initialization gate signal GI1, and the compensation gate signal GC[n] can be kept at an inactive level. For example, in the first interval DR1 to the sixth interval DR6, the first initialization gate signal GI1 and the compensation gate signal GC[n] can be kept at a low level, and the first write gate signal GW1[n] can be kept at a high level.

[0171] Therefore, in a holding frame, the pulse width modulation data voltage VPWM does not need to be written into the circuitry of the pixel PX, and the light-emitting element EE can emit light based on the constant current voltage VCCG.

[0172] Figure 13 It is shown that it includes Figure 1 A circuit diagram of another example of the circuitry for pixel PXa in the display panel 100 of the display device 1. Figure 14 yes Figure 13 Timing diagram of the circuit operation of pixel PXa.

[0173] Reference Figure 13 and Figure 14 The circuitry of pixel PXa may include a first circuit section PC and a second circuit section CCa.

[0174] The first circuit section PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, as well as a first capacitor C1. The second circuit section CCa may include a seventh transistor T7, an eighth transistor T8a, a ninth transistor T9a, a tenth transistor T10, and an eleventh transistor T11, a second capacitor C2, and a third capacitor C3. The second circuit section CCa may include a light-emitting element EE.

[0175] At this point, apart from the configuration of the second write gate signal GW2a, the transmit signal EMa, the eighth transistor T8a, and the ninth transistor T9a, the circuit and timing diagram of pixel PXa are the same as those of the other transistors. Figure 2 The circuitry of the pixel PX and Figure 3 The timing diagrams are essentially the same; therefore, the same reference numerals are used for the same or similar components, and repeated descriptions are omitted.

[0176] The eighth transistor T8a may include a control electrode to which a second write gate signal GW2a is applied, a first electrode connected to the data voltage VDATA terminal, and a second electrode connected to the fourth node N4.

[0177] The ninth transistor T9a may include a control electrode to which a second write gate signal GW2a is applied, a first electrode to which a second power supply voltage VDD2 is applied, and a second electrode connected to the fifth node N5.

[0178] At this point, the types of the eighth transistor T8a and the ninth transistor T9a can be different from each other.

[0179] In one embodiment, the eighth transistor T8a can be an NMOS transistor, and the ninth transistor T9a can be a PMOS transistor.

[0180] At this time, in the first interval DR1 to the third interval DR3, the fifth interval DR5, and the sixth interval DR6, the second write gate signal GW2a can have an inactive level relative to the eighth transistor T8a, and can have an active level relative to the ninth transistor T9a. For example, in the first interval DR1 to the third interval DR3, the fifth interval DR5, and the sixth interval DR6, the second write gate signal GW2a can have a low level.

[0181] In the first interval DR1 to the third interval DR3, the fifth interval DR5 and the sixth interval DR6, the eighth transistor T8a can be turned off and the ninth transistor T9a can be turned on by the second write gate signal GW2a.

[0182] In the fourth interval DR4, the second write gate signal GW2a can have an active level relative to the eighth transistor T8a and an inactive level relative to the ninth transistor T9a. For example, in the fourth interval DR4, the second write gate signal GW2a can have a high level.

[0183] In the fourth interval DR4, the eighth transistor T8a can be turned on and the ninth transistor T9a can be turned off by the second write gate signal GW2a. The eighth transistor T8a can transmit the constant current voltage VCCG to the fourth node N4.

[0184] Furthermore, in the first interval DR1 to the fourth interval DR4, the transmitted signal EMA can have an inactive level. For example, the transmitted signal EMA can have a high level. In the fifth interval DR5 and the sixth interval DR6, the transmitted signal EMA can have an active level. For example, the transmitted signal EMA can have a low level.

[0185] By applying the second write gate signal GW2a to the control electrode of the ninth transistor T9, the time required for internal compensation of the threshold voltage of the seventh transistor T7 can be reduced. Furthermore, the transmit signal EMA remains at an inactive level in the third interval DR3, thus the level of the transmit signal EMA does not change. Therefore, the power consumption consumed by changing the level of the transmit signal EMA can be reduced.

[0186] Figure 15 It is shown that it includes Figure 1 A circuit diagram of another example of the circuitry for the pixel PXb in the display panel 100 of the display device 1. Figure 16 yes Figure 15 Timing diagram of the circuit operation of pixel PXb.

[0187] Reference Figure 15 and Figure 16 The circuitry of pixel PXb may include a first circuit section PC and a second circuit section CCb.

[0188] The first circuit section PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, as well as a first capacitor C1. The second circuit section CCb may include a seventh transistor T7, an eighth transistor T8b, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11, a second capacitor C2, and a third capacitor C3. The second circuit section CCb may include a light-emitting element EE.

[0189] At this point, apart from the configuration of the eighth transistor T8b and the data voltage VDATA, the circuitry and timing diagram of pixel PXb are the same as those of the other transistors. Figure 2 The circuitry of the pixel PX and Figure 3 The timing diagrams are essentially the same, therefore the same reference numerals are used for the same or similar components, and repeated descriptions are omitted.

[0190] The eighth transistor T8b may include a control electrode to which a second write gate signal GW2 is applied, a first electrode connected to a constant current voltage VCCG terminal, and a second electrode connected to a fourth node N4.

[0191] A constant current voltage VCCG can be applied to the constant current voltage VCCG terminal. In this case, the constant current voltage VCCG terminal can be distinguished from the data voltage VDATA terminal.

[0192] The data voltage VDATA applied to the data voltage VDATA terminal can have a first data voltage level and a second data voltage level. For example, the data voltage VDATA with the first data voltage level can be a pulse width modulation data voltage VPWM, and the data voltage VDATA with the second data voltage level can be a low voltage.

[0193] The data voltage VDATA applied to the data voltage VDATA terminal can have a second data voltage level in the first interval DR1 and the third intervals DR3 to DR6. That is, the data voltage VDATA can be a low voltage in the first interval DR1 and the third intervals DR3 to DR6. Furthermore, the data voltage VDATA applied to the data voltage VDATA terminal can have a first data voltage level in the second interval DR2. In the second interval DR2, the data voltage VDATA can be a pulse width modulation (VPWM) data voltage.

[0194] The constant current voltage VCCG applied to the constant current voltage VCCG terminal can have a first constant current voltage level and a second constant current voltage level.

[0195] The constant current voltage VCCG applied to the VCCG terminal can have a second constant current voltage level in the first interval DR1, the second interval DR2, the fifth interval DR5, and the sixth interval DR6. Furthermore, the constant current voltage VCCG applied to the VCCG terminal can have a first constant current voltage level in the third interval DR3 and the fourth interval DR4.

[0196] In the fourth interval DR4, the eighth transistor T8b can be turned on in response to the second write gate signal GW2. The eighth transistor T8b can transmit a constant current voltage VCCG with a first constant current voltage level to the fourth node N4.

[0197] By distinguishing between the constant current voltage VCCG terminal and the data voltage VDATA terminal, a constant current voltage VCCG with a first constant current voltage level can be applied to each pixel row at different times. Therefore, the timing of pixel PXb emission in each pixel row can be different. For example, pixels PXb can emit light sequentially.

[0198] Figure 17 It is shown that it includes Figure 1 A circuit diagram of another example of the circuitry for the pixel PXc in the display panel 100 of the display device 1. Figure 18 yes Figure 17 Timing diagram of the circuit operation of pixel PXc.

[0199] Reference Figure 17 and Figure 18 The circuitry of pixel PXc may include a first circuit section PC and a second circuit section CCc.

[0200] The first circuit section PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, as well as a first capacitor C1. The second circuit section CCc may include a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10c, and an eleventh transistor T11, a second capacitor C2, and a third capacitor C3c. The second circuit section CCc may include a light-emitting element EE.

[0201] At this point, apart from the configuration of the third capacitor C3c, the configuration of the tenth transistor T10c, and the third initialization gate signal BCBc, the circuit and timing diagram of pixel PXc are the same as those of the other transistors. Figure 2 The circuitry of the pixel PX and Figure 3 The timing diagrams are essentially the same. The same reference numerals are used for identical or similar components, and repeated descriptions are omitted.

[0202] The tenth transistor T10c may include a control electrode to which a third initialization gate signal BCBc is applied, a first electrode connected to the anode electrode ANODE of the light-emitting element EE, and a second electrode to which a second initialization voltage VAINT is applied. The tenth transistor T10c may be an NMOS transistor.

[0203] The third capacitor C3c may include a first electrode connected to the fourth node N4 and a second electrode connected to the control electrode of the tenth transistor T10c. Furthermore, a third initialization gate signal BCBc may be applied to the second electrode of the third capacitor C3c.

[0204] Within the first interval DR1 to the fourth interval DR4, the third initialization gate signal BCBc can have an active level. For example, within the first interval DR1 to the fourth interval DR4, the third initialization gate signal BCBc can have a high level. Furthermore, within the fifth interval DR5 and the sixth interval DR6, the third initialization gate signal BCBc can have a deactivated level. For example, within the fifth interval DR5 and the sixth interval DR6, the third initialization gate signal BCBc can have a low level.

[0205] Therefore, the tenth transistor T10c can be turned on in the first interval DR1 to the fourth interval DR4. In the fifth interval DR5 and the sixth interval DR6, the tenth transistor T10c can be turned off.

[0206] At this point, the voltage at the fourth node N4 can be the same as in the following mathematical formula 2.

[0207] [Mathematical Expression 2]

[0208] Wherein, VCCG refers to the constant current voltage VCCG, Vth7 refers to the threshold voltage of the seventh transistor T7, C2 refers to the capacitance of the second capacitor C2, C3 refers to the capacitance of the third capacitor C3c, VDD2 refers to the second power supply voltage VDD2, VGL refers to the first gate power supply voltage applied to the gate driving section 300, and VGH refers to the second gate power supply voltage applied to the gate driving section 300.

[0209] As the capacitance of the second capacitor C2 increases and the capacitance of the third capacitor C3c decreases, the internal compensation capability for the threshold voltage of the seventh transistor T7 can be improved. Furthermore, in the fifth interval DR5, the level of the third initialization gate signal BCBc can decrease from a high level to a low level. At this time, the voltage level of the fourth node N4 can be reduced by the coupling operation of the third capacitor C3c. Specifically, when the capacitance of the second capacitor C2 increases and the capacitance of the third capacitor C3c decreases, a lower constant current voltage VCCG needs to be applied to the fourth node N4 to reliably turn on the seventh transistor T7. At this time, the constant current voltage VCCG applied to the fourth node N4 can be further reduced by the coupling operation of the third capacitor C3c, and the seventh transistor T7 can be reliably turned on. That is, the voltage of the fourth node N4 can be further reduced without needing to generate a lower constant current voltage VCCG separately, thus reducing or minimizing the power consumption of the display device 1.

[0210] Figure 19 It is shown that it includes Figure 1 A circuit diagram of yet another example of the circuitry for the pixel PXd in the display panel 100 of the display device 1. Figure 20 yes Figure 19 Timing diagram of the circuit operation of pixel PXd.

[0211] Reference Figure 19 and Figure 20 The circuitry of pixel PXd may include a first circuit section PCd and a second circuit section CCd.

[0212] The first circuit section PCd may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, as well as a first capacitor C1. The second circuit section CCd may include a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a second capacitor C2, and a third capacitor C3. The second circuit section CCd may include a light-emitting element EE.

[0213] At this point, except that the circuit of pixel PXd does not include the eleventh transistor T11 and the level of the second write gate signal GW2 is different in the third interval DR3, the circuit and timing diagram of pixel PXd are the same as those of pixel PXd. Figure 2The circuitry of the pixel PX and Figure 3 The timing diagrams are essentially the same. The same reference numerals are used for identical or similar components, and repeated descriptions are omitted.

[0214] The circuitry for pixel PXd may not include the eleventh transistor T11. Furthermore, the second write gate signal GW2 may have an inactive level in the first interval DR1, the second interval DR2, the fourth interval DR4, and the fifth interval DR5. For example, the second write gate signal GW2 may have a high level in the first interval DR1, the second interval DR2, the fifth interval DR5, and the sixth interval DR6. Additionally, the second write gate signal GW2 may have an active level in the third interval DR3. For example, the second write gate signal GW2 may have a low level in the third interval DR3.

[0215] Therefore, the circuitry for a pixel PXd can include 10 transistors and 3 capacitors. (Compared to...) Figure 2 Compared to the circuitry of the pixel PX, Figure 19 The number of transistors included in the circuitry of a pixel PXd can be reduced. Because the number of transistors is reduced, the integration density of the pixel PXd included in the display panel 100 can be increased.

[0216] Figure 21 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the present invention. Figure 22 It is shown Figure 21 The diagram shows an example of an electronic device 1000 implemented as a smartphone.

[0217] Reference Figure 21 and Figure 22 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and a display device 1060. Furthermore, the electronic device 1000 may also include multiple ports capable of communicating with video cards, sound cards, memory cards, Universal Serial Bus (USB) devices, or other systems.

[0218] In one embodiment, such as Figure 22 As shown, electronic device 1000 can be implemented by a smartphone. However, this is merely an example, and electronic device 1000 is not limited thereto. For example, electronic device 1000 can be implemented by a portable phone, video phone, smart tablet, smartwatch, tablet PC, vehicle navigation system, computer monitor, laptop computer, head-mounted display device, etc.

[0219] Processor 1010 can perform specific calculations or tasks. According to embodiments, processor 1010 can be a microprocessor, a central processing unit, an application processor, etc. Processor 1010 can be connected to other components via address bus, control bus, and data bus. According to embodiments, processor 1010 can also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0220] Processor 1010 can generate input image data IMG and input control signal CONT, and can send... Figure 1 The drive control unit 200 of the display device 1 outputs and inputs image data IMG and inputs control signal CONT.

[0221] The memory device 1020 can store data required for the operation of the electronic device 1000. For example, memory device 1020 may include non-volatile memory devices such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory device, phase change random access memory (PRAM), resistive random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), and / or non-volatile memory devices such as dynamic random access memory (DRAM) and static random access memory (SRAM). Volatile memory devices such as memory devices and mobile DRAM devices.

[0222] Storage device 1030 may include solid state drive (SSD), hard disk drive (HDD), read-only optical disc storage (CD-ROM), etc.

[0223] Input / output device 1040 may include input devices such as a keyboard, keypad, touchpad, touch screen, and mouse, and output devices such as a speaker and printer. According to an embodiment, display device 1060 may also be included in input / output device 1040.

[0224] The power supply 1050 can supply the power required for the operation of the electronic device 1000.

[0225] The display device 1060 can be connected to other components via the bus or other communication links.

[0226] In one embodiment, the display device 1060 may be Figure 1 The display device 1 includes a display panel 100 that may include circuitry for pixels PX. The circuitry for pixels PX may include a first circuit section PC and a second circuit section CC. In this case, the first circuit section PC may be a pulse width modulation (PWM) circuit section. The second circuit section CC may be a constant current generation (CCG) circuit section.

[0227] The circuitry for a pixel PX may include 11 transistors and 3 capacitors. Compared to existing pixel circuits, the pixel PX circuitry has a relatively small number of transistors, thus increasing the integration density of the pixel PX circuitry included in the display panel 100. Increased integration density of the pixel PX circuitry allows for an increase in the resolution of the display device 1060.

[0228] Furthermore, the pulse width modulation data voltage VPWM applied to the first electrode of the first transistor T1 included in the first circuit section PC and the constant current voltage VCCG applied to the control electrode of the seventh transistor T7 included in the second circuit section CC are both applied to the first circuit section PC or the second circuit section CC through the data voltage VDATA terminal, thus reducing the number of transistors and signal wiring. Therefore, the dead zone of the display device 1 can be reduced.

[0229] Furthermore, when the second electrode of the third capacitor C3, included in the second circuit section CC, is connected to the stabilization voltage DC terminal, the stabilization voltage DC, which is a constant voltage, can be applied to the second electrode of the third capacitor C3. Therefore, coupling operations caused by the third capacitor C3 can be prevented. Therefore, the voltage of the fourth node N4 can be stabilized. Therefore, the stability of the pixel PX circuit can be improved.

[0230] Industrial availability This invention can be applied to display devices and electronic devices including them. For example, it can be applied to high-resolution smartphones, mobile phones, smart tablets, smartwatches, tablet PCs, vehicle navigation systems, televisions, computer monitors, laptops, etc.

[0231] The invention has been described above with reference to embodiments; however, those skilled in the art will understand that various modifications and variations can be made to the invention without departing from the concept and scope of the invention as set forth in the appended claims.

Claims

1. A pixel circuit, characterized in that, include: The first circuit section performs pulse width modulation operation based on the pulse width modulation data voltage; The second circuit section generates drive current based on constant current voltage; as well as The light-emitting element emits light based on the pulse width modulation data voltage and the constant current voltage. The first circuit section includes: The first transistor includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; The second transistor transmits the pulse width modulated data voltage to the second node; and The third transistor is connected to both the first node and the third node. The second circuit section includes: The seventh transistor includes a control electrode connected to the fourth node, a first electrode connected to the fifth node, and a second electrode connected to the anode electrode of the light-emitting element. The eighth transistor transmits the constant current voltage to the fourth node; and The third capacitor includes a first electrode connected to the fourth node and a second electrode to which a stabilizing voltage is applied.

2. The pixel circuit according to claim 1, characterized in that, The second transistor includes a control electrode to which a first write gate signal is applied, a first electrode connected to a data voltage terminal, and a second electrode connected to the second node. The eighth transistor includes a control electrode to which a second write gate signal is applied, a first electrode connected to the data voltage terminal, and a second electrode connected to the fourth node.

3. The pixel circuit according to claim 1, characterized in that, The second circuit section also includes: The second capacitor includes a first electrode connected to the fifth node and a second electrode connected to the fourth node.

4. The pixel circuit according to claim 1, characterized in that, The second circuit section also includes: The tenth transistor includes a control electrode to which a third initialization gate signal is applied, a first electrode connected to the anode electrode of the light-emitting element, and a second electrode to which a second initialization voltage is applied.

5. The pixel circuit according to claim 4, characterized in that, The second electrode of the third capacitor is connected to the control electrode of the tenth transistor. The stabilization voltage is the third initialization gate signal.

6. The pixel circuit according to claim 1, characterized in that, The first circuit section further includes: The fourth transistor includes a control electrode to which a first initialization gate signal is applied, a first electrode connected to the first node, and a second electrode to which a first initialization voltage is applied.

7. The pixel circuit according to claim 1, characterized in that, The first circuit section further includes: The first capacitor includes a first electrode to which a scan signal is applied and a second electrode connected to the first node.

8. The pixel circuit according to claim 1, characterized in that, The second circuit section also includes: The eleventh transistor includes a control electrode to which a second initialization gate signal is applied, a first electrode connected to the fourth node, and a second electrode to which a first initialization voltage is applied.

9. The pixel circuit according to claim 1, characterized in that, The first circuit section further includes: The fifth transistor includes a control electrode to which a transmission signal is applied, a first electrode to which a first power supply voltage is applied, and a second electrode connected to the second node; and The sixth transistor includes a control electrode to which the transmission signal is applied, a first electrode connected to the third node, and a second electrode connected to the fourth node. The second circuit section also includes: The ninth transistor includes a control electrode, a first electrode to which a second power supply voltage is applied, and a second electrode connected to the fifth node.

10. The pixel circuit according to claim 9, characterized in that, The transmit signal is applied to the control electrode of the ninth transistor.

11. The pixel circuit according to claim 9, characterized in that, The eighth transistor includes a control electrode to which a second write gate signal is applied, a first electrode connected to a data voltage terminal, and a second electrode connected to the fourth node. The second write gate signal is applied to the control electrode of the ninth transistor.

12. The pixel circuit according to claim 1, characterized in that, The second transistor includes a control electrode to which a first write gate signal is applied, a first electrode connected to a data voltage terminal, and a second electrode connected to the second node. The third transistor includes a control electrode to which a compensation gate signal is applied, a first electrode connected to the first node, and a second electrode connected to the third node. The eighth transistor includes a control electrode to which a second write gate signal is applied, a first electrode connected to the data voltage terminal, and a second electrode connected to the fourth node. The light-emitting element includes the anode electrode and the cathode electrode to which a third power supply voltage is applied. The first circuit section further includes: The fourth transistor includes a control electrode to which a first initialization gate signal is applied, a first electrode connected to the first node, and a second electrode to which a first initialization voltage is applied; The fifth transistor includes a control electrode to which a transmission signal is applied, a first electrode to which a first power supply voltage is applied, and a second electrode connected to the second node; The sixth transistor includes a control electrode to which the transmission signal is applied, a first electrode connected to the third node, and a second electrode connected to the fourth node; and The first capacitor includes a first electrode to which a scan signal is applied and a second electrode connected to the first node. The second circuit section also includes: The ninth transistor includes a control electrode to which the transmission signal is applied, a first electrode to which a second power supply voltage is applied, and a second electrode connected to the fifth node; The tenth transistor includes a control electrode to which a third initialization gate signal is applied, a first electrode connected to the anode electrode of the light-emitting element, and a second electrode to which a second initialization voltage is applied; The eleventh transistor includes a control electrode to which a second initialization gate signal is applied, a first electrode connected to the fourth node, and a second electrode to which the first initialization voltage is applied; and The second capacitor includes a first electrode connected to the fifth node and a second electrode connected to the fourth node.

13. The pixel circuit according to claim 12, characterized in that, In the first interval, The first initialization gate signal has an activation level. The second initialization gate signal has an inactive level. The third initialization gate signal has an activation level. The first write gate signal has an inactive level. The second write gate signal has an inactive level. The compensation gate signal has an inactive level. The transmitted signal has an inactive level. The scanning signal has a high level.

14. The pixel circuit according to claim 12, characterized in that, In the second interval, The first initialization gate signal has an inactive level. The second initialization gate signal has an inactive level. The third initialization gate signal has an activation level. The first write gate signal has an activation pulse. The second write gate signal has an inactive level. The compensation gate signal has an activation pulse. The transmitted signal has an inactive level. The scanning signal has a high level. The data voltage applied to the data voltage terminal has a first level. The data voltage having the first level can be the pulse width modulation data voltage.

15. The pixel circuit according to claim 12, characterized in that, In the third interval, The first initialization gate signal has an inactive level. The second initialization gate signal has an activation level. The third initialization gate signal has an activation level. The first write gate signal has an inactive level. The second write gate signal has an inactive level. The compensation gate signal has an inactive level. The transmitted signal has an activation level. The scanning signal has a high level. The data voltage applied to the data voltage terminal has a second level. The data voltage having the second level is the constant current voltage.

16. The pixel circuit according to claim 12, characterized in that, In the fourth interval, The first initialization gate signal has an inactive level. The second initialization gate signal has an inactive level. The third initialization gate signal has an activation level. The first write gate signal has an inactive level. The second write gate signal has an activation level. The compensation gate signal has an inactive level. The transmitted signal has an inactive level. The scanning signal has a high level. The data voltage applied to the data voltage terminal has a second level. The data voltage having the second level is the constant current voltage.

17. The pixel circuit according to claim 12, characterized in that, In the fifth and sixth intervals The first initialization gate signal has an inactive level. The second initialization gate signal has an inactive level. The third initialization gate signal has an inactive level. The first write gate signal has an inactive level. The second write gate signal has an inactive level. The compensation gate signal has an inactive level. The transmitted signal has an activation level. The scanning signal gradually decreases from a high level.

18. A display device, characterized in that, include: Display panel, including pixel circuitry; The gate driving section applies a gate signal to the pixel circuit; The emission driving unit applies an emission signal to the pixel circuit; as well as The data driving unit applies a data voltage to the pixel circuit. The pixel circuit is the pixel circuit according to any one of claims 1 to 17.

19. An electronic device, characterized in that, include: The processor generates input control signals and input image data; Display panel, including pixel circuitry; as well as The display panel driver unit drives the display panel based on the input control signal and the input image data. The pixel circuit is the pixel circuit according to any one of claims 1 to 17.

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