Display device and driving method thereof

Abstract

This application discloses a display device and its driving method. The display device determines the output order of image data to prioritize low grayscale image data and accordingly sets the switching order of the demultiplexer, thereby preventing or suppressing brightness drop caused by insufficient charging time and enabling sub-pixels to be charged to the desired grayscale, thus improving the image quality of the display device employing demultiplexer technology.

Description

Technical Field

[0001] This application relates to a display device, and more particularly to a display device and its driving method for improving data charging characteristics related to time-division driving. Background Technology

[0002] Organic light-emitting displays (OLEDs) are self-emissive display devices that, unlike liquid crystal displays (LCDs), do not require a separate light source, thus enabling thinner and lighter manufacturing. Furthermore, OLEDs offer advantages in power consumption due to their low-voltage operation, and also excel in color reproduction, response speed, viewing angle, and contrast ratio (CR), positioning them as the next generation of displays currently under research.

[0003] Display devices are constantly being improved to enhance screen resolution and brightness, thereby providing users with clearer images. Summary of the Invention

[0004] Display devices employ demultiplexer technology to reduce the number of data pins on the data lines supplied from the data driver to the display panel. In demultiplexer technology, the demultiplexer switches are driven in a time-division manner, causing the data voltage of a single data pin to be sequentially delivered to multiple sub-pixels.

[0005] However, in conventional technologies, when a high grayscale voltage is applied to the first switch that is turned on during the time-division driving of the demultiplexer, the charging time is insufficient, resulting in the inability to represent the desired grayscale. To address this issue, the inventors of this application have designed a display device capable of preventing or suppressing image quality degradation caused by insufficient charging time during the time-division driving of the demultiplexer.

[0006] The purpose of this application is to provide a display device and its driving method that can solve the problem of reduced brightness caused by insufficient charging time depending on the load of the display panel during demultiplexer driving.

[0007] Another objective of this application is to provide a display device and its driving method that can reduce color shift and line mura caused by differences in the charging rates of individual sub-pixels during demultiplexer driving.

[0008] The purposes of the embodiments described in this application are not limited to those described above, and other purposes not mentioned will be clearly understood by those skilled in the art based on the detailed description.

[0009] A display apparatus according to an exemplary embodiment of this application is provided. The display apparatus determines the output order of image data to prioritize low grayscale image data, and determines the switching order of the demultiplexer based on the output order.

[0010] According to an exemplary embodiment, the display device compares the magnitude of image data within a horizontal time period and determines the output order of the image data in ascending order, starting from the lowest grayscale data among the image data within the horizontal time period.

[0011] A display device according to an exemplary embodiment of this application is provided. The display device includes: a demultiplexer that selectively transmits data voltages from a single data pin to a first sub-pixel to a fifth sub-pixel via a first switch to a fifth switch, respectively; and a controller that compares the magnitudes of first image data to fifth image data in a first horizontal time period, determines the output order of the first image data to fifth image data to be output in ascending order starting from the lowest grayscale data among the first image data to fifth image data, and controls the first switch to the fifth switch based on the output order of the first image data to fifth image data.

[0012] A method for driving a display device according to an exemplary embodiment of this application is provided. The method for driving a display device includes: comparing the sizes of first image data to fifth image data in a first horizontal time period; arranging the first image data to fifth image data to be output in ascending order, starting from the lowest grayscale image data among the first image data to fifth image data; and arranging switch control signals according to the output order of the first image data to fifth image data to drive the first to fifth switches of a demultiplexer.

[0013] The display device according to the exemplary embodiments of this application determines the switching order of the demultiplexer based on the grayscale of the image data and outputs the image data in ascending order starting from the lowest grayscale data, which helps to prevent or suppress the reduction in brightness caused by insufficient charging time and helps to improve image quality.

[0014] Furthermore, the display device according to the exemplary embodiments of this application controls the switch of the demultiplexer to charge the sub-pixels in ascending order, starting from low grayscale data, to ensure that the sub-pixels are charged to the desired grayscale, which is beneficial to improving image quality.

[0015] Furthermore, the display device according to an exemplary embodiment of this application charges sub-pixels in ascending order, starting from the lowest grayscale image data, by controlling the switch of the demultiplexer. This facilitates charging sub-pixels to the desired grayscale even when there is a significant grayscale difference between adjacent sub-pixels.

[0016] Furthermore, the display device according to the exemplary embodiments of this application determines the switching order of the demultiplexer based on the grayscale of the image data and turns on the switch of the demultiplexer according to the determined switching order, which helps to reduce color shift and line unevenness caused by the difference in charging rate between sub-pixels.

[0017] Furthermore, the display device according to the exemplary embodiments of this application, by adjusting the switching order of the demultiplexer based on the grayscale of the image data and turning on the switch of the demultiplexer to first transmit the data voltage corresponding to the lower grayscale data, facilitates the full charging of sub-pixels to the desired grayscale even if the charging time is insufficient.

[0018] Furthermore, the display device according to the exemplary embodiments of this application controls the switch of the demultiplexer to charge the sub-pixels in ascending order starting from the lowest grayscale sub-pixel, which helps to solve the problem of reduced brightness in the first sub-pixel when a high grayscale is applied to the first sub-pixel in a random pattern.

[0019] Furthermore, the display device according to the exemplary embodiments of this application controls the switch of the demultiplexer to charge sub-pixels in ascending order starting from the lowest grayscale sub-pixel, which helps to reduce color shift and line unevenness even in a one-by-one pattern where high and low grayscale values ​​alternate.

[0020] Furthermore, the display device according to the exemplary embodiments of this application controls the switch of the demultiplexer to charge sub-pixels in ascending order starting from the lowest grayscale sub-pixel, which solves the problem of brightness reduction caused by insufficient charging time due to display panel load and is beneficial to improving image quality.

[0021] In addition to the effects and advantages described above, other beneficial effects of this disclosure will be provided together with the detailed description of this disclosure or may be understood by those skilled in the art from the following description. Attached Figure Description

[0022] The accompanying drawings, which provide a further understanding of this disclosure and are incorporated in and constitute a part of this application, illustrate exemplary embodiments of this disclosure and, together with the specification, explain the principles of this disclosure. In the drawings:

[0023] Figure 1 This is a block diagram illustrating a display device according to an embodiment of this application;

[0024] Figure 2 This is a circuit diagram of the pixels included in a display device according to an embodiment of this application;

[0025] Figure 3 This is a schematic diagram illustrating a demultiplexer for a display device according to an embodiment of this application;

[0026] Figure 4 It shows Figure 3 Operation timing diagram;

[0027] Figure 5 It shows Figure 3 Operation timing diagram based on image pattern;

[0028] Figure 6 The control flow of a display device according to an embodiment of this application is shown;

[0029] Figure 7 This is a flowchart illustrating the control flow of a display device according to an embodiment of this application;

[0030] Figure 8 The control flow of a display device according to another embodiment of this application is shown;

[0031] Figure 9 This is a flowchart illustrating the control flow of a display device according to another embodiment of this application;

[0032] Figure 10 A timing diagram illustrating the operation of a display device according to an embodiment of this application is shown.

[0033] Figure 11 Another timing diagram of operation of a display device according to an embodiment of this application is shown. Detailed Implementation

[0034] The advantages and features disclosed herein, and their implementation methods, can be more readily understood by referring to the detailed description of the embodiments described below with reference to the accompanying drawings. However, this application is not limited to the embodiments disclosed below, but can be implemented in various different forms; these embodiments are provided merely to ensure that the disclosure of this application is complete and to fully inform those skilled in the art of the scope of the invention, which is defined only by the scope of the claims.

[0035] The shapes, dimensions, ratios, angles, quantities, etc., shown in the drawings for the purpose of describing embodiments of this application are merely exemplary, and therefore, this application is not limited thereto. Throughout the specification, the same reference numerals refer to the same parts. Furthermore, detailed descriptions of well-known technologies may be omitted in the specification to avoid obscuring the subject matter of the application. When terms such as "comprising," "having," "including," or "consisting of" are used in this specification, it should be understood that additional elements or steps may be included unless specifically used. Unless otherwise expressly stated, when parts are expressed in the singular, it is intended to also cover the plural forms.

[0036] When interpreting components, even if not explicitly described, it is interpreted as including tolerances.

[0037] When describing positional relationships, for example, when using terms such as “on top of,” “above,” “below,” or “next to” to describe the positional relationship between two parts, one or more other parts may be located between the two parts unless “directly” or “immediately adjacent” is specified.

[0038] When describing temporal relationships, expressions such as “after,” “next,” “next,” or “before” can indicate a sequence of events, and can also include non-continuous cases unless “immediately” or “directly” is used.

[0039] When describing signal flow relationships, for example, in the case of "signal is transmitted from node A to node B", instances of signal transmission from node A to node B via another node may also be included, unless "immediately" or "directly" is specified.

[0040] The terms "first," "second," etc., are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below can be the second component in the technical sense of this application.

[0041] The various features of the embodiments of this disclosure may be combined or assembled in technically different ways, either partially or completely, and each embodiment may be implemented independently or in combination with related embodiments.

[0042] Hereinafter, a display device and its driving method according to an exemplary embodiment of the present application will be described, which can reduce the decrease in brightness caused by insufficient charging time due to display panel load during demultiplexer switching, and reduce color shift and line non-uniformity caused by charging rate differences between sub-pixels.

[0043] Various exemplary embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0044] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present application.

[0045] Reference Figure 1 The display device 10 includes: a display panel 100 having a plurality of pixels P, a controller 200, a gate driver 300 that supplies scan signals SC to the plurality of pixels P, a data driver 400 that supplies data voltage Vdata to the plurality of pixels P, and a power supply 500 that provides the voltage required to drive the plurality of pixels P.

[0046] In the display panel 100, multiple scan lines SCL and multiple data lines DL intersect each other, and each of the multiple pixels P is connected to the scan lines SCL and data lines DL. Specifically, a pixel P receives a scan signal SC via the scan line SCL and a data voltage Vdata via the data line DL, and receives a reference voltage Vref, a high-level drive voltage ELVDD, and a low-level drive voltage ELVSS from the power supply 500.

[0047] The scan line SCL supplies the scan signal SC and the sensing signal to pixel P, and the data line DL supplies the data voltage Vdata to pixel P. Alternatively, according to various embodiments, the scan line SCL and the sensing line supplying the sensing signal can be connected to pixel P separately.

[0048] In addition, multiple pixels P can receive high-potential drive voltage ELVDD and low-potential drive voltage ELVSS via power lines, and can receive reference voltage Vref via reference voltage line RL.

[0049] Each pixel P includes a light-emitting element and a pixel circuit that controls the driving of the light-emitting element. The pixel circuit includes multiple switching elements, driving elements, and capacitors. Here, the switching elements and driving elements can be composed of thin-film transistors. In the pixel circuit, the driving elements control the current supplied to the light-emitting element based on the data voltage, thereby adjusting the amount of light emitted by the light-emitting element. In addition, the multiple switching elements operate the pixel circuit by receiving a scan signal SC provided by multiple scan lines SCL and a reference voltage Vref provided by a reference voltage line RL.

[0050] Display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. Transmissive display panels can be used in transparent display devices, where images are displayed on the screen while allowing background objects to remain visible. Display panel 100 can be manufactured as a flexible display panel. Flexible display panels can be implemented as OLED panels using a plastic substrate.

[0051] Each pixel P can be divided into red, green, and blue sub-pixels for color implementation. Each pixel P may also include a white sub-pixel.

[0052] A touch sensor can be disposed on the display panel 100. Touch input can be sensed using a separate touch sensor or through a pixel P. The touch sensor can be implemented as an on-cell or additional touch sensor disposed on the screen of the display panel, or as an in-cell touch sensor embedded in the display panel 100.

[0053] The controller 200 processes the RGB image data input from the host system to match the size and resolution of the display panel 100, and provides the processed data to the data driver 400. The controller 200 uses synchronization signals input from external sources (such as clock signal CLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) to generate a gate control signal GCS and a data control signal DCS. The controller 200 provides the generated gate control signal GCS and data control signal DCS to the gate driver 300 and the data driver 400 respectively, thereby controlling the gate driver 300 and the data driver 400.

[0054] The voltage level of the gate control signal GCS output from controller 200 can be converted into gate on-voltage and gate off-voltage by a level shifter and provided to gate driver 300. The level shifter converts the low-level voltage of the gate control signal GCS to gate low voltage VGL and the high-level voltage of the gate control signal GCS to gate high voltage VGH. The gate control signal GCS includes a start pulse and a shift clock.

[0055] The gate driver 300 supplies the scan signal SC to the scan line SCL according to the gate control signal GCS. The gate driver 300 can be arranged on one or both sides of the display panel 100 in a gate in panel (GIP) configuration.

[0056] Gate driver 300 sequentially outputs scan signals SC to multiple scan lines SCL. Gate driver 300 can sequentially supply scan signals SC to scan lines SCL by shifting the scan signals SC using a shift register. The scan signals SC may include scan pulses that oscillate between a gate low voltage VGL and a gate high voltage VGH. In various embodiments, gate driver 300 may sequentially output sensing signals to multiple sensing lines. The sensing signals may include scan pulses that oscillate between a gate low voltage VGL and a gate high voltage VGH.

[0057] The gate driver 300 outputs a scan pulse in response to a start pulse and a shift clock from the controller 200, and shifts the scan pulse sequentially according to the shift clock.

[0058] The data driver 400 converts the image data RGB into a data voltage Vdata according to the data control signal DCS, and provides the converted data voltage Vdata to the pixel P through the data line DL.

[0059] exist Figure 1In the diagram, the data driver 400 is shown as a single unit disposed on one side of the display panel 100, but the number and arrangement of the data drivers 400 are not limited thereto. That is, the data driver 400 may consist of multiple integrated circuits (ICs) and may be arranged separately on one side of the display panel 100.

[0060] Power supply 500 generates the direct current (DC) power required to drive the pixel array, gate driver 300, and data driver 400 of display panel 100. Power supply 500 may include a charge pump, regulator, buck converter, boost converter, etc.

[0061] Power supply 500 receives input voltage from the host system and generates DC voltages such as gate high voltage VGH, gate low voltage VGL, high-level drive voltage ELVDD, low-level drive voltage ELVSS, and reference voltage Vref. Gate low voltage VGL and gate high voltage VGH can be supplied to gate driver 300. High-level drive voltage ELVDD, low-level drive voltage ELVSS, and reference voltage Vref can be supplied to pixel P.

[0062] Figure 2 This is a circuit diagram of the pixels included in a display device according to an embodiment of this application.

[0063] refer to Figure 2 Each pixel is defined by a scan line SCL, a data line DL, a power line, and a reference voltage line RL. Each pixel includes a scan transistor SCT, a drive transistor DT, a light-emitting element OLED, a sensing transistor SENT, and a storage capacitor Cst.

[0064] The scan transistor SCT selects the pixel to be driven by applying a data voltage Vdata to the drive transistor DT. The scan transistor SCT is located at the intersection of the scan line SCL and the data line DL. The scan transistor SCT includes a gate electrode, a source electrode, and a drain electrode. The gate electrode is connected to the scan line SCL. The source electrode is connected to the data line DL, and the drain electrode is connected to the drive transistor DT.

[0065] The driving transistor DT drives the light-emitting element OLED of the selected pixel chosen by the scanning transistor SCT. The driving transistor DT includes a gate electrode, a source electrode, and a drain electrode. The gate electrode is connected to the drain electrode of the scanning transistor SCT, the source electrode is connected to the power supply line to which a high-potential driving voltage ELVDD is applied, and the drain electrode is connected to the anode of the light-emitting element OLED.

[0066] The storage capacitor Cst is used to sample the data voltage Vdata. The storage capacitor Cst includes a first electrode and a second electrode. The first electrode of the storage capacitor Cst is connected to the node between the drain electrode of the scan transistor SCT and the gate electrode of the drive transistor DT, and the second electrode of the storage capacitor Cst is connected to the node between the drain electrode of the drive transistor DT and the anode of the light-emitting element OLED.

[0067] An OLED is a self-emissive light-emitting device whose luminous intensity can be adjusted according to the amount of current flowing through it. For example, an OLED can be an organic light-emitting diode. An OLED includes an anode, an emissive layer, and a cathode. The anode of the OLED is connected to the drain electrode of the driving transistor DT and the second electrode of the storage capacitor Cst, the cathode is connected to the power supply line to which a low-potential driving voltage ELVSS is applied, and the emissive layer is placed between the anode and the cathode.

[0068] A sensing transistor (SENT) is used to initialize the anode of the OLED and the second electrode of the storage capacitor Cst to a reference voltage Vref or to sense pixel characteristics. The sensing transistor SENT includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the sensing transistor SENT is connected to the scan line SCL, and the drain electrode of the sensing transistor SENT is connected to the anode of the OLED, the drain electrode of the driving transistor DT, and the second electrode of the storage capacitor Cst. The source electrode of the sensing transistor SENT is connected to the reference voltage line RL. According to various embodiments, the gate electrode of the sensing transistor SENT may be connected to a sensing line supplying a separate sensing signal.

[0069] The driving transistor DT adjusts the current flowing through the light-emitting element OLED according to the magnitude of the data voltage Vdata.

[0070] Furthermore, according to some embodiments, at least one transistor in the pixel circuit can be formed as a P-type thin-film transistor or an N-type thin-film transistor. Each transistor and the driving transistor can be formed from various types of transistors, such as LTPS, oxide, monocrystalline silicon, organic materials, etc. The light-emitting element OLED can use self-emissive diodes, such as organic light-emitting elements or micro-LEDs. The substrate on which the pixels are formed can be made of glass, plastic, flexible plastic, wafers, etc.

[0071] Figure 3 This is a schematic diagram illustrating a demultiplexer for a display device according to an embodiment of this application.

[0072] Reference Figure 3 The display device includes a data driver 400 and a display panel 100.

[0073] The data driver 400 includes a grayscale voltage generator 410, a digital-to-analog converter 420, and an output buffer 430.

[0074] Grayscale voltage generator 410 provides multiple grayscale voltages to digital-to-analog converter 420. For example, grayscale voltage generator 410 can generate 10-bit grayscale voltages and provide them to digital-to-analog converter 420.

[0075] The digital-to-analog converter 420 receives image data and grayscale voltage, and outputs the grayscale voltage (V) corresponding to the image data. GAM (R), V GAM (G), V GAM (B) is used as the data voltage. The digital-to-analog converter 420 can be divided into two parts for outputting red grayscale voltage V. GAM (R) red digital-to-analog converter, used to output green grayscale voltage V GAM (G) green digital-to-analog converter, and for outputting blue grayscale voltage V GAM (B) Blue digital-to-analog converter. For example, based on image data, the digital-to-analog converter 420 can have a 10-bit resolution and output red, green, and blue grayscale voltages in 1024 levels.

[0076] Output buffer 430 outputs the data voltage received from digital-to-analog converter 420 to display panel 100. For example, output buffer 430 may be a unity-gain amplifier. The output terminal of output buffer 430 is connected to display panel 100 via data pin 440. Data pin 440 can be divided into red data pin Pad (R), green data pin Pad (G), and blue data pin Pad (B). In this application, red data pin Pad (R) can be defined as outputting red grayscale voltage V. GAM (R) serves as the data voltage pin. The green data pin Pad(G) can be defined as the output green grayscale voltage V. GAM (G) serves as the data voltage pin. The blue data pin Pad(B) can be defined as the output blue grayscale voltage V. GAM (B) is used as the pin for data voltage.

[0077] Display panel 100 includes a demultiplexer with multiple switches SW1, SW2, SW3, SW4, and SW5, and multiple sub-pixels R1 to R5, G1 to G5, and B1 to B5. Although display panel 100 is shown in this application as including red, green, and blue sub-pixels, it is not limited thereto. Display panel 100 may also include white sub-pixels.

[0078] Multiple switches SW1, SW2, SW3, SW4, and SW5 of the demultiplexer selectively connect the data pin 440 of the data driver 400 to multiple sub-pixels R1 to R5, G1 to G5, and B1 to B5.

[0079] The multiple switches SW1, SW2, SW3, SW4, and SW5 of the demultiplexer can be driven in a time-division manner according to the switch control signals provided from the controller 200. That is, the multiple switches SW1, SW2, SW3, SW4, and SW5 of the demultiplexer can be selectively turned on or off in response to the switch control signals.

[0080] For example, switches SW1, SW2, SW3, SW4, and SW5 of the demultiplexer connected to the red data pin Pad(R) can be driven in a time-division manner according to the switch control signal to convert the red grayscale voltage V GAM (R) is transmitted as data voltage to the first red sub-pixel R1 through the fifth red sub-pixel R5. Switches SW1, SW2, SW3, SW4, and SW5 of the demultiplexer connected to the green data pin Pad(G) are driven in a time-division manner according to the switch control signal to transmit the green grayscale voltage V. GAM (G) is transmitted as data voltage to the first green sub-pixels G1 through G5. Switches SW1, SW2, SW3, SW4, and SW5 of the demultiplexer connected to the blue data pin Pad(B) are driven in a time-division manner according to the switch control signal to transmit the blue grayscale voltage V. GAM (B) is transmitted as data voltage to the first blue sub-pixel B1 to the fifth blue sub-pixel B5.

[0081] The first sub-pixels R1, G1, and B1 can simultaneously receive red, green, and blue data voltages via the first switch SW1. The second sub-pixels R2, G2, and B2 can simultaneously receive red, green, and blue data voltages via the second switch SW2. The third sub-pixels R3, G3, and B3 can simultaneously receive red, green, and blue data voltages via the third switch SW3. The fourth sub-pixels R4, G4, and B4 can simultaneously receive red, green, and blue data voltages via the fourth switch SW4. The fifth sub-pixels R5, G5, and B5 can simultaneously receive red, green, and blue data voltages via the fifth switch SW5. Therefore, the sub-pixels of the first horizontal row of the display panel can receive data voltages using a time-division driving method.

[0082] The demultiplexer technique illustrated in this application is intended to illustrate a method for reducing the number of data pins 440 provided via five data lines to one-fifth, but is not limited thereto. The number of switches in the multiplexer can be two or more.

[0083] Figure 4 It shows Figure 3 The operation timing diagram.

[0084] refer to Figure 4 The display device can sequentially turn on the switches SW1, SW2, SW3, SW4, and SW5 of the demultiplexer during a horizontal time period 1H, thereby allowing data voltage to be transmitted to the first sub-pixel to the fifth sub-pixel. In this case, the first scan signal SC[n] can be enabled during the time period when the data voltage of the first horizontal row is output, and the second scan signal SC[n+1] can be enabled during the time period when the data voltage of the second horizontal row is output.

[0085] Figure 5 It shows Figure 3 The timing diagram of the operation based on the image pattern.

[0086] In demultiplexing technology, when the display devices share the output buffer 430 of the data driver 400, brightness imbalance may occur for a specific image mode, mainly due to the influence of the previously applied image data and the switching order of the demultiplexer.

[0087] When insufficient charging time occurs during demultiplexer switching due to panel load, sub-pixels connected to the first switch SW1 of the demultiplexer may experience insufficient charging, resulting in degraded image quality. Alternatively, when there is a large grayscale difference between adjacent sub-pixels, adjacent sub-pixels may also experience insufficient charging, leading to degraded image quality.

[0088] refer to Figure 5 In Solid PTN mode, for example, when image data corresponding to a first grayscale value of "128" is applied, insufficient charging time occurs because the first switch SW1 is turned off before the first grayscale value of "128" is fully charged. This can result in the brightness of the first sub-pixel being lower than that of the second to fifth sub-pixels. When the brightness of the first sub-pixel is lower than that of the other sub-pixels, line mura may occur.

[0089] Furthermore, in 1-by-1 PTN mode, for example, when image data alternates between a first grayscale "128" and a second grayscale "0", the subpixels representing the first grayscale may be insufficient to represent the desired grayscale due to insufficient charging time. For instance, when the display panel is driven at a high frequency, the duration of the horizontal time interval becomes shorter, further reducing the available charging time and exacerbating the charging problem. Figure 5 In the diagram, the circle indicates the part where a charging problem has occurred.

[0090] Furthermore, in the case of Random PTN, for example, when image data with grayscale values ​​such as 250, 100, 130, 180, 70 is applied, the first sub-pixel may not be able to represent the desired grayscale value of 250 due to insufficient charging time before the first switch SW1 is turned off.

[0091] To address these issues, this application provides a display device that can reduce color shift and line unevenness caused by differences in charging rates, even in a sequential mode where high and low grayscale values ​​are applied alternately.

[0092] Furthermore, this application provides a display device that can solve the problem of brightness reduction of the first sub-pixel when applying high grayscale to the first sub-pixel in random mode.

[0093] Figure 6 The control flow of a display device according to an embodiment of this application is shown.

[0094] refer to Figure 6 The display device includes a controller 200 that determines the output order of image data, such that lower grayscale image data is output to the data driver 400 first, and determines the switching order of the demultiplexer based on this output order. Figure 6 In this implementation, the controller 200 determines the output order of the image data and the corresponding demultiplexer switching order based on the values ​​of the image data; however, this arrangement is not limiting. Alternatively, the output order of the image data can be determined based on the values ​​of the image data, and the switching order of the demultiplexers can be determined based on the output order of the image data. Alternatively, a separate control device (not shown) can determine the output order of the image data based on the values ​​of the image data, and the switching order of the demultiplexers can be determined based on the output order of the image data.

[0095] The controller 200 receives the first to fifth image data Data1, Data2, Data3, Data4, and Data5 from the host system, compares the magnitudes of Data1 to Data5 during the horizontal time period 1H, and determines their output order in ascending order starting from the lowest grayscale value.

[0096] For example, when there are five switches in the demultiplexer, the controller 200 can compare the magnitudes of the five image data values ​​and determine the output order of the image data in ascending order, starting with the data with the lowest grayscale value. For instance, the controller 200 can compare the image data magnitudes by checking each bit in order from the most significant bit to the least significant bit.

[0097] Figure 6The example shows the cases where Data1 has a grayscale value of 250, Data2 has a grayscale value of 100, Data3 has a grayscale value of 130, Data4 has a grayscale value of 180, and Data5 has a grayscale value of 70.

[0098] The controller 200 can determine the output order of the image data as Data5, Data2, Data3, Data4, Data1 based on the size of the first to fifth image data Data1, Data2, Data3, Data4, Data5. The controller 200 can determine the switching order of the demultiplexer to match the output order of the image data.

[0099] The controller 200 can output image data to the data driver 400 based on the output order of the image data, and provide switch control signals to the switches in the order of fifth switch 5SW5, second switch SW2, third switch SW3, fourth switch SW4, and first switch SW1 based on the switching order of the demultiplexer.

[0100] The controller 200 can turn on the demultiplexer switches in ascending order of gray levels, starting from the lowest gray level, thus ensuring that data voltage is delivered to the sub-pixels.

[0101] Reference Figure 6 The fifth switch SW5 is turned on at the first switching time S / W Time1, the second switch SW2 is turned on at the second switching time S / W Time2, the third switch SW3 is turned on at the third switching time S / W Time3, the fourth switch SW4 is turned on at the fourth switching time S / W Time4, and the first switch SW1 is turned on at the fifth switching time S / W Time5.

[0102] By determining the switching order of the demultiplexer based on the grayscale values ​​of the first to fifth image data Data1, Data2, Data3, Data4, and Data5, and outputting image data in ascending order starting from the lowest grayscale, the display device solves the charging rate problem associated with demultiplexer technology.

[0103] That is, the display device can solve the problem of high grayscale charging rate by controlling the first to fifth switches SW1, SW2, SW3, SW4, and SW5 of the demultiplexer to charge the sub-pixels in ascending order of the lower grayscale image data, thereby improving the image quality.

[0104] The controller 200 includes a comparator 210, a first sorting circuit 220, a demultiplexer controller 230, and a second sorting circuit 240.

[0105] Comparator 210 compares the first to fifth image data, Data1, Data2, Data3, Data4, and Data5, within the horizontal time period 1H of the image data. For example, comparator 210 can compare the bits of the first to fifth image data, Data1, Data2, Data3, Data4, and Data5. Assuming the image data is 10 bits, comparator 210 can compare at least the two most significant bits.

[0106] The first sorting circuit 220 can sort the first to fifth image data Data1, Data2, Data3, Data4, and Data5 in ascending order based on the comparison result of the comparator 210.

[0107] The demultiplexer controller 230 can determine the switching order of the demultiplexer based on the comparison result of the comparator 210 to match the output order of the image data. The second sorting circuit 240 can arrange the switch control signals based on the switching order of the demultiplexer to drive the switching of the demultiplexer according to the output order of the image data.

[0108] The data driver 400 can receive image data in the output order adjusted by the controller 200, convert the image data into data voltage through the digital-to-analog converter 420, and output the data voltage to the display panel 100 through the output buffer 430.

[0109] The display panel 100 may include first to fifth switches SW1, SW2, SW3, SW4, and SW5 of a demultiplexer. The first to fifth switches SW1, SW2, SW3, SW4, and SW5 of the demultiplexer can receive switch control signals corresponding to the image data output sequence adjusted by the controller 200, and can transmit data voltages to the corresponding first to fifth sub-pixels in response to the switch control signals. The first to fifth sub-pixels can be charged by data voltages in ascending order, starting from lower gray levels.

[0110] Therefore, the display device of this disclosure can solve the problem of insufficient charging rate of the demultiplexer by charging the sub-pixels in ascending order, starting from image data with lower gray levels.

[0111] Figure 7 This is a flowchart illustrating the control flow of a display device according to an embodiment of this application.

[0112] refer to Figure 7In operation S110, the controller 200 receives row data for a horizontal time period 1H. Here, the row data represents the first to fifth image data to be applied to the first to fifth sub-pixels during the horizontal time period 1H. Although this application exemplifies the controller 200 as a main unit for determining the output order of image data based on the values ​​of the image data and for determining the switching order of the demultiplexer based on the output order of the image data, it is not limited thereto. Alternatively, the data driver 400 can be used as a main unit to perform these functions. In another embodiment, a separate control device can be used as a main unit to perform the same functions.

[0113] In operation S120, the controller 200 compares the size of the first to fifth image data corresponding to the five sub-pixels.

[0114] In operation S130, the controller 200 determines whether the input image is in solid color mode by comparing the values ​​of the first to fifth image data. For example, the controller 200 can determine that the input image is in solid color mode when all the values ​​of the first to fifth image data are the same, and can determine that the input image is not in solid color mode when the values ​​of the first to fifth image data are different.

[0115] When it is determined that the first to fifth image data do not constitute a solid color mode, in operation S140, the controller 200 determines the output order of the image data starting from the image data with the lower gray level from the first to fifth image data in ascending order, and determines the switching order of the demultiplexer to match the output order of the image data.

[0116] When it is determined that some of the first to fifth image data have the same gray level, the output order of the image data and the switching order of the demultiplexer can be adjusted according to the default order. For example, the default order can be set to first image data, second image data, third image data, fourth image data, and fifth image data. For example, when the third and fourth image data have the same gray level, the output order can be determined so that the third image data is output before the fourth image data.

[0117] In operation S150, the controller 200 arranges the first to fifth image data in a determined output order and outputs the arranged first to fifth image data to the data driver 400. In operation S160, the controller 200 also outputs switch control signals to the first to fifth switches SW1, SW2, SW3, SW4, and SW5 of the demultiplexer according to the switching order of the demultiplexer.

[0118] When it is determined that the first to fifth image data constitute a solid color mode, in operation S170, the controller 200 can determine the output order of the image data and the switching order of the demultiplexer according to the default order. For example, the default order can be set to the first image data, the second image data, the third image data, the fourth image data, and the fifth image data.

[0119] When the image data is in solid color mode, the controller 200 can determine the output order of the image data and the switching order of the demultiplexer, so that the first to fifth image data are output in the order of first image data, second image data, third image data, fourth image data, and fifth image data.

[0120] Figure 8 The control flow of a display device according to another embodiment of this application is shown.

[0121] Reference Figure 8 The display device can determine the output order of image data in ascending order from the image data with lower gray levels in the first to fifth image data Data1, Data2, Data3, Data4, and Data5, and can determine the switching order of the demultiplexer based on the output order of the image data.

[0122] The controller 200 can compare the magnitudes of the input first to fifth image data Data1, Data2, Data3, Data4, and Data5, and determine the output order of the first to fifth image data Data1, Data2, Data3, Data4, and Data5 in ascending order, starting with the image data with the lower gray level.

[0123] Figure 8 The diagram illustrates the cases where the first image data Data1 has a gray level of 250, the second image data Data2 has a gray level of 100, the third image data Data3 has a gray level of 130, the fourth image data Data4 has a gray level of 180, and the fifth image data Data5 has a gray level of 70.

[0124] The controller 200 can determine the output order of the image data as Data5, Data2, Data3, Data4, Data1 based on the size of the first to fifth image data Data1, Data2, Data3, Data4, Data5.

[0125] The controller 200 can turn on all the first to fifth switches of the demultiplexer and determine the switching order of the demultiplexer according to the output order of the image data, so that the fifth switch, the second switch, the third switch, and the fourth switch are turned off in sequence.

[0126] Based on the output order of the image data, the controller 200 can output the fifth image data, the second image data, the third image data, the fourth image data, and the first image data to the data driver 400. Based on the switching order of the demultiplexer, the controller 200 can turn on all the first to fifth switches and then turn off the fifth switch SW5, the second switch SW2, the third switch SW3, and the fourth switch SW4 in sequence.

[0127] By turning off the demultiplexer switch based on the switching sequence of the demultiplexer, the controller 200 ensures that the sub-pixels are charged in ascending order starting from the lowest gray level, thereby solving the problem of reduced brightness due to insufficient charging time.

[0128] At the first switching time S / W Time1, all switches 1 through 5 are turned on. At the second switching time S / W Time2, switch 5 SW5 is turned off. At the third switching time S / W Time3, switch 2 SW2 is turned off. At the fourth switching time S / W Time4, switch 3 SW3 is turned off. At the fifth switching time S / W Time5, switch 4 SW4 is turned off.

[0129] By turning off the first to fifth switches SW1, SW2, SW3, SW4, and SW5 of the demultiplexer in this manner, the display device ensures that the sub-pixels are charged in ascending order starting from the lowest gray level, thus solving the problem of high gray level charging rate caused by insufficient charging time.

[0130] The controller 200 includes a comparator 210, a first sorting circuit 220, a demultiplexer controller 230, and a second sorting circuit 240. Descriptions of the same components are replaced by the above explanation.

[0131] The second sorting circuit 240 first arranges the switch control signals for turning on all demultiplexer switches SW1, SW2, SW3, SW4, and SW5, and then arranges the switch control signals for turning off switches SW5, SW2, SW3, and SW4 in sequence according to the data output order. The first to fifth sub-pixels complete data charging in ascending order, starting from the lowest grayscale.

[0132] Therefore, the display device of this disclosure simultaneously turns on all the first to fifth switches of the demultiplexer to charge the first to fifth sub-pixels while outputting the fifth image data with the lowest grayscale among the first to fifth image data, and turns off the switches in ascending order starting from the lowest grayscale image data. By completing the charging in ascending order starting from the sub-pixels displaying the low grayscale image data, the display device can charge the sub-pixels to the desired grayscale regardless of the image data mode.

[0133] In addition, the display device determines the switching order of the demultiplexer based on the grayscale value of the image data and switches the demultiplexer on and off accordingly, thereby reducing color shift and line unevenness caused by differences in charging rate.

[0134] Figure 9 This is a flowchart illustrating the control flow of a display device according to another embodiment of this application.

[0135] Reference Figure 9 In operation S210, the controller 200 receives image data for the horizontal time period 1H.

[0136] In operation S220, the controller 200 compares the size of the first to fifth image data of each group of five sub-pixels from the received image data.

[0137] The controller 200 determines whether the image meets the solid color mode. In operation S230, the controller 200 can determine that the input image is in solid color mode when all the values ​​of the first to fifth image data are the same, and can determine that the input image is not in solid color mode when the values ​​of the first to fifth image data are different.

[0138] When the image is not in solid color mode, in operation S240, the controller 200 determines the output order of the image data in ascending order, starting with the image data with the lowest grayscale. Then, in operation S240, the controller 200 determines the switching order of the demultiplexer based on the output order of the image data to turn off the switch.

[0139] In operation S250, the controller 200 arranges the first to fifth image data in a determined output order and outputs the arranged first to fifth image data to the data driver 400.

[0140] In operation S260, controller 200 turns on all switches SW1, SW2, SW3, SW4, and SW5 of the demultiplexer. In operation S270, controller 200 turns off switches SW1, SW2, SW3, SW4, and SW5 of the demultiplexer according to the switching sequence.

[0141] When the mode is solid color, in operation S280, the controller 200 determines the output order of the image data and the switching order of the demultiplexer according to the default sequence. For example, the default sequence can be set to first image data, second image data, third image data, fourth image data, and fifth image data. In operation S290, the controller 200 outputs switch control signals to the first to fifth switches SW1, SW2, SW3, SW4, and SW5 of the demultiplexer according to the switching order of the demultiplexer.

[0142] In this way, the controller 200 turns on all switches SW1, SW2, SW3, SW4, and SW5 of the demultiplexer, and completes the charging of sub-pixels in ascending order from the lowest gray level to the highest gray level based on the switching order of the demultiplexer, thereby solving the image quality problem caused by insufficient charging time.

[0143] Figure 10 A timing diagram illustrating the operation of a display device according to an embodiment of this application is shown.

[0144] Figure 10 The example shows the Random PTN pattern, where the first image data has a gray level of 250, the second image data has a gray level of 100, the third image data has a gray level of 130, the fourth image data has a gray level of 180, and the fifth image data has a gray level of 70.

[0145] The display device determines the output order of the first to fifth image data as fifth image data, second image data, third image data, fourth image data, and first image data based on the grayscale values ​​of the first to fifth image data, and accordingly determines the switching order of the demultiplexer.

[0146] The first to fifth switches of the demultiplexer can be turned on in the following order: fifth switch, second switch, third switch, fourth switch, and first switch.

[0147] In other words, since the subpixels start charging from image data with a lower grayscale, even when the first image data with a high grayscale value of 250 is input, brightness reduction due to insufficient charging time can be prevented or suppressed.

[0148] Furthermore, by controlling the switch of the demultiplexer, sub-pixels are charged in ascending order, starting from image data with lower gray levels. Even when there is a large difference in gray levels between sub-pixels, the difference in charging rate can be reduced, thereby preventing or suppressing color shift and line inhomogeneity and improving image quality.

[0149] Figure 11 Another timing diagram of operation of a display device according to an embodiment of this application is shown.

[0150] Figure 11 The example shown is a 1-by-1 PTN pattern, where the first image data has 128 gray levels, the second image data has 0 gray levels, the third image data has 128 gray levels, the fourth image data has 0 gray levels, and the fifth image data has 128 gray levels.

[0151] The display device determines the output order of the first to fifth image data based on the gray levels of the first to fifth image data, so that the image data is output in the order of second image data, fourth image data, first image data, third image data, and fifth image data, and determines the switching order of the demultiplexer switch so that it corresponds to the output order.

[0152] The first to fifth switches of the demultiplexer can be turned on in the order of the second switch, the fourth switch, the first switch, the third switch, and the fifth switch. That is, even when high grayscale 128 and low grayscale 0 are alternately applied as image data, the sub-pixels are charged in the order of lower grayscale priority, thereby preventing brightness loss caused by insufficient charging time.

[0153] Therefore, by controlling the switch of the demultiplexer, the sub-pixels are charged in ascending order, starting from image data with lower gray levels. Even when the gray level difference between sub-pixels is large, the difference in charging rate can be reduced, thereby preventing color shift and line unevenness and improving image quality.

[0154] A display device according to an exemplary embodiment of this application includes: a data driver configured to output a data voltage corresponding to image data; a display panel including a demultiplexer configured to selectively transmit the data voltage to a plurality of sub-pixels; and a controller configured to determine the output order of the image data such that low grayscale image data is preferentially output to the data driver, and to determine the switching order of the demultiplexer according to the output order of the image data.

[0155] According to an exemplary embodiment, the controller can compare the size of image data within a horizontal time period and determine the output order of the image data in ascending order, starting from the lowest grayscale data among the image data within the horizontal time period.

[0156] According to an exemplary implementation, based on the fact that the demultiplexer has k switches (k is a natural number of 2 or greater), the controller can compare the size of the image data in k groups and determine the output order of the image data in ascending order, starting from the lowest grayscale data.

[0157] According to an exemplary embodiment, the controller can output the image data to the data driver based on the output order of the image data, and turn the demultiplexer on or off based on the switching order of the demultiplexer.

[0158] According to an exemplary embodiment, the controller can turn on the demultiplexer based on the switching order of the demultiplexer to deliver the data voltage to the sub-pixel in ascending order of grayscale.

[0159] According to an exemplary embodiment, the controller can turn on all the switches of the demultiplexer and turn off the switches of the demultiplexer based on the switching order of the demultiplexer, so as to complete the charging of the sub-pixels in ascending order of grayscale.

[0160] According to an exemplary embodiment, the controller may include: a comparator configured to compare k image data points within a horizontal time period (k is a natural number of 2 or greater); a first sorting circuit configured to sort the image data points of the horizontal time period in ascending order based on the comparison result of the comparator; a demultiplexer controller configured to determine the switching order of the demultiplexer based on the comparison result of the comparator; and a second sorting circuit configured to arrange switch control signals based on the switching order of the demultiplexer to drive the switching of the demultiplexer according to the output order of the image data.

[0161] A display device according to an exemplary embodiment of this application includes: a demultiplexer comprising a first switch to a fifth switch and configured to selectively transmit a data voltage input from a single data pin to a first sub-pixel to a fifth sub-pixel via the first switch to the fifth switch, respectively; and a controller configured to receive first image data to fifth image data within a first horizontal time period, compare the magnitudes of the first image data to the fifth image data, determine the output order of the first image data to the fifth image data in ascending order starting from the lowest grayscale image data among the first image data to the fifth image data, and control the first switch to the fifth switch based on the output order of the first image data to the fifth image data.

[0162] According to an exemplary embodiment, the controller may arrange switch control signals to turn on switches from the first switch to the fifth switch in ascending order, starting with the switch configured to transmit the lowest grayscale data voltage.

[0163] According to an exemplary embodiment, the controller can output the first image data to the fifth image data in ascending order, starting from the lowest grayscale image data, to the data driver, and output the switch control signal to the demultiplexer to turn on the first switch to the fifth switch in ascending order, starting from the switch configured to transmit the voltage of the lowest grayscale data.

[0164] According to an exemplary embodiment, the controller may arrange switch control signals for turning on all the first to fifth switches, and then arrange switch control signals for turning off the switches in ascending order, starting with the switch configured to transmit the lowest grayscale data voltage.

[0165] A method for driving a display device according to an exemplary embodiment of this application includes: receiving first image data to fifth image data within a first horizontal time period; comparing the sizes of the first image data to the fifth image data; determining an output order of the first image data to the fifth image data in ascending order, starting from the lowest grayscale image data among the first image data to the fifth image data; arranging the first image data to be output to the fifth image data in ascending order, starting from the lowest grayscale image data, based on the output order; determining a switching order of a demultiplexer based on the output order of the first image data to the fifth image data; and arranging switch control signals based on the switching order of the demultiplexer to drive a first switch to a fifth switch of the demultiplexer.

[0166] According to an exemplary embodiment, arranging the switch control signals may include arranging the switch control signals for turning on the first to fifth switches of the demultiplexer in ascending order, starting with the switch that transmits the lowest grayscale data voltage.

[0167] According to an exemplary embodiment, the method may further include outputting the first image data to the fifth image data in ascending order, starting from the lowest grayscale image data, and turning on the first to the fifth switches of the demultiplexer in ascending order, starting from the switch that transmits the voltage of the lowest grayscale data.

[0168] According to an implementation, arranging the switch control signals may include arranging the switch control signals for turning on all the first to fifth switches of the demultiplexer, and arranging the switch control signals for turning off the first to fifth switches in ascending order, starting with the switch configured to transmit the lowest grayscale data voltage.

[0169] According to an exemplary embodiment, the method may further include: outputting first image data to fifth image data in ascending order, starting from the lowest grayscale image data; turning on all the first to fifth switches of the demultiplexer; and turning off the first to fifth switches of the demultiplexer in ascending order, starting from the switch configured to transmit the voltage of the lowest grayscale data.

[0170] Although embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, it should be noted that the present disclosure is not necessarily limited to these embodiments, but can be modified in various ways without departing from the scope of the technical concept of the invention. Therefore, the embodiments disclosed in this application are not intended to be limiting, but rather to illustrate the technical idea of ​​the present disclosure, and the scope of the technical idea of ​​the present disclosure is not limited by the embodiments. Therefore, it should be understood that the above embodiments are exemplary and do not limit all aspects of the present disclosure.

Claims

1. A display device, comprising: A data driver configured to output a data voltage corresponding to the image data; The display panel includes a demultiplexer configured to selectively deliver the data voltage to a plurality of sub-pixels; and The controller is configured to determine the output order of the image data to prioritize the output of low grayscale image data to the data driver, and to determine the switching order of the demultiplexer based on the output order of the image data.

2. The display device according to claim 1, wherein, The controller is also configured to compare the size of image data within a horizontal time period and determine the output order of the image data in ascending order, starting with the lowest grayscale data among the image data within the horizontal time period.

3. The display device according to claim 1, wherein, Based on the fact that the demultiplexer has k switches, where k is a natural number greater than or equal to 2, the controller is also configured to compare the size of the image data according to k groups, and determine the output order of the image data in ascending order starting from the lowest grayscale data.

4. The display device according to claim 1, wherein, The controller is also configured to output the image data to the data driver based on the output order of the image data, and to turn the demultiplexer on or off based on the switching order of the demultiplexer.

5. The display device according to claim 4, wherein, The controller is also configured to turn on the demultiplexer based on the switching sequence of the demultiplexer to deliver the data voltage to the sub-pixel in ascending order of grayscale.

6. The display device according to claim 4, wherein, The controller is also configured to turn on all switches of the demultiplexer and turn off the switches of the demultiplexer based on the switching order of the demultiplexer to complete the charging of the sub-pixels in ascending order of grayscale.

7. The display device according to claim 1, wherein, The controller includes: The comparator is configured to compare k image data points within a horizontal time interval, where k is a natural number greater than or equal to 2. A first sorting circuit is configured to sort the image data of the horizontal time segment in ascending order based on the comparison result of the comparator. The demultiplexer controller is configured to determine the switching order of the demultiplexers based on the comparison result of the comparator; and The second sorting circuit is configured to arrange the switch control signals based on the switching order of the demultiplexer, so as to drive the switching of the demultiplexer according to the output order of the image data.

8. A display device, comprising: The demultiplexer includes a first switch to a fifth switch and is configured to selectively pass a data voltage input from a single data pin to a first sub-pixel to a fifth sub-pixel via the first switch to the fifth switch, respectively. and The controller is configured to receive first image data to fifth image data within a first horizontal time period, compare the sizes of the first image data to the fifth image data, determine the output order of the first image data to the fifth image data in ascending order starting from the lowest grayscale image data among the first image data to the fifth image data, and control the first switch to the fifth switch based on the output order of the first image data to the fifth image data.

9. The display device according to claim 8, wherein, The controller is also configured to arrange switch control signals to turn on the first switch to the fifth switch in ascending order, starting with the switch configured to transmit the lowest grayscale data voltage.

10. The display device according to claim 9, wherein, The controller is further configured to output the first image data to the fifth image data in ascending order, starting from the lowest grayscale image data, to the data driver, and to output the switch control signal to the demultiplexer to turn on the first switch to the fifth switch in ascending order, starting from the switch configured to transmit the voltage of the lowest grayscale data.

11. The display device according to claim 8, wherein, The controller is also configured to arrange switch control signals for turning on all the first switches to the fifth switches, and then arrange switch control signals for turning off the first switches to the fifth switches in ascending order, starting with the switch configured to transmit the lowest grayscale data voltage.

12. A method for driving a display device, comprising: Receive the first to fifth image data within the first horizontal time period; Compare the sizes of the first image data to the fifth image data; The output order of the first image data to the fifth image data is determined in ascending order, starting with the lowest grayscale image data among the first image data to the fifth image data; Based on the output order, the first image data to be output, up to the fifth image data, is arranged in ascending order, starting from the lowest grayscale image data; The switching order of the demultiplexer is determined based on the output order of the first image data to the fifth image data. and The switch control signals are arranged according to the switching sequence of the demultiplexer to drive the first to fifth switches of the demultiplexer.

13. The method according to claim 12, wherein, The arrangement of the switch control signals includes arranging the switch control signals for turning on the first switch to the fifth switch of the demultiplexer in ascending order, starting with the switch that transmits the lowest grayscale data voltage.

14. The method of claim 13, further comprising: Starting from the lowest grayscale image data, output the first image data to the fifth image data in ascending order; and Starting with the switch that transmits the lowest grayscale data voltage, the first switch to the fifth switch of the demultiplexer is turned on in ascending order.

15. The method according to claim 12, wherein, The arrangement of the switch control signals includes: Arrange the switch control signals for turning on all the first switches to the fifth switch of the demultiplexer; and The switch control signals are arranged to turn off the first switch to the fifth switch in ascending order, starting with the switch configured to transmit the lowest grayscale data voltage.

16. The method of claim 15, further comprising: Starting from the lowest grayscale image data, output the first image data to the fifth image data in ascending order; Turn on all the first switches to the fifth switch of the demultiplexer; and Starting with the switch configured to transmit the lowest grayscale data voltage, the first to the fifth switches of the demultiplexer are turned off in ascending order.

Images