Scan driving circuit and display device including the same

Abstract

This disclosure provides a scan driving circuit and a display device including the same. The display device includes: a substrate including a display area and a non-display area; a pixel circuit located in the display area and configured to drive light-emitting elements; and a scan driving circuit configured to supply scan signals to the pixel circuit, wherein the scan driving circuit includes: a logic unit configured to receive a plurality of clock signals and output logic signals through a logic output terminal; and an inverter configured to receive the logic signals and output scan signals, inverting their phases through a gating output terminal, the inverter including an n-type first inverter transistor and a p-type second inverter transistor, each having a gate electrode connected to the logic output terminal, and the first and second inverter transistors being positioned such that the gating output terminal is interposed therebetween, and the first inverter transistor including an oxide semiconductor.

Description

Technical Field

[0001] This disclosure relates to an apparatus, and more particularly to, for example, but not limited to, a scan drive circuit and a display device including the scan drive circuit. Background Technology

[0002] Various methods and forms have been used in display devices that display images on TVs, monitors, smartphones, tablets, laptops, etc.

[0003] The display device includes: a display panel having a plurality of light-emitting elements or liquid crystals for realizing images; and transistors for controlling the operation of each light-emitting element or liquid crystal to display images as needed through the plurality of light-emitting elements or liquid crystals.

[0004] Recent display devices include various flat panel display devices, such as electroluminescent display devices including organic light-emitting diode (OLED) display devices, quantum dot light-emitting diode (QLED) display devices, and micro light-emitting diode (microLED) display devices.

[0005] The display device may include a display panel for displaying images and a driving unit for driving the display panel. The display panel includes multiple pixels, each pixel including a light-emitting element, and the driving unit may include multiple driving and switching elements to drive and control the light-emitting elements disposed in each pixel.

[0006] The driving unit may include a scan driving circuit that supplies a scan signal synchronized with the data signal to gate lines disposed in multiple pixels.

[0007] The descriptions provided in the background section should not be assumed to be prior art simply because they are mentioned in or associated with that section. The background section may include information describing one or more aspects of the subject matter art, and the descriptions in that section do not limit this disclosure. Summary of the Invention

[0008] Therefore, this disclosure relates to a scan driving circuit and a display device including the scan driving circuit, which substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0009] The technical objective of the embodiments of this disclosure is to provide a scan drive circuit with improved reliability and a display device including the scan drive circuit.

[0010] The technical objective of the embodiments of this disclosure is to provide a structure for a scan drive circuit that can reduce the number of clock signals and simplify operation.

[0011] The technical objective of embodiments of this disclosure is to provide a structure capable of mitigating operational errors in scan drive circuits that may occur due to positive bias thermal stress (PBTS).

[0012] The technical objective of the embodiments of this disclosure is to achieve ESG by improving the reliability of the display device and reducing power consumption.

[0013] Additional advantages, objects, and features of this disclosure will be set forth in part in the description which follows, and will in part become apparent to those skilled in the art upon examination of the following, or may be learned from practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures specifically pointed out in the specification, its claims, and the accompanying drawings.

[0014] To achieve these objectives and other advantages and in accordance with the purposes of this disclosure, as embodied and broadly described herein, a display device includes: a substrate including a display area and a non-display area; pixel circuitry positioned in the display area and configured to drive light-emitting elements; and a scan driving circuitry configured to supply scan signals to the pixel circuitry, wherein the scan driving circuitry includes: a logic unit configured to receive a plurality of clock signals and output logic signals via a logic output terminal; and an inverter configured to receive the logic signals and output the scan signals, inverting the phase of the logic signals via a gating output terminal, wherein the inverter includes an n-type first inverter transistor and a p-type second inverter transistor, the gate electrode of each of the first and second inverter transistors being connected to the logic output terminal, and the first and second inverter transistors being connected to a gating output terminal, the gating output terminal being interposed between the first and second inverter transistors, and the first inverter transistor comprising an oxide semiconductor.

[0015] The period during which the high voltage of the logic signal is supplied to the gate electrode of the first inverter transistor can be longer than the period during which the low voltage of the logic signal is supplied.

[0016] The second inverter transistor may include a semiconductor formed of low-temperature polycrystalline silicon (LTPS).

[0017] The first inverter transistor may have a gate electrode connected to a logic output terminal, one end supplied with a low gating voltage VGL, and the other end connected to the gating output terminal, and the second inverter transistor may have a gate electrode connected to a logic output terminal, one end supplied with a high gating voltage VGH, and the other end connected to the gating output terminal.

[0018] The first inverter transistor can be turned on by a logic signal with a high gate voltage to output a scan signal with a low gate voltage to the gating output terminal, and the second inverter transistor can be turned on by a logic signal with a low gate voltage to output a scan signal with a high gate voltage to the gating output terminal.

[0019] A logic unit may include multiple logic transistors, and the multiple logic transistors may include semiconductors formed of LTPS.

[0020] The logic unit may include: a first logic transistor having a gate electrode connected to a Q node, one end receiving a first clock signal, and the other end connected to a logic output terminal; a second logic transistor having a gate electrode connected to a QB node, one end receiving a gate high voltage, and the other end connected to a logic output terminal; a third logic transistor having a gate electrode receiving a second clock signal, one end receiving a start signal, and the other end connected to a Q node; a fourth logic transistor having a gate electrode connected to a Q node, one end receiving a second clock signal, and the other end connected to a QB node; and a fifth logic transistor. The fifth logic transistor has a gate electrode for receiving a second clock signal, a terminal for receiving a low-voltage gate, and a terminal connected to the QB node; the sixth logic transistor has a gate electrode connected to the QB node and is configured to output a high-voltage gate supplied at one end to the other end; the seventh logic transistor has a gate electrode for receiving a first clock signal, a terminal connected to the sixth logic transistor, and a terminal connected to the Q node; a first capacitor has a terminal connected to the Q node and a terminal connected to a logic output terminal; and a second capacitor has a terminal connected to the QB node and a terminal supplied with a high-voltage logic gate.

[0021] The logic unit may also include an eighth logic transistor having a gate electrode supplied with a low voltage and connected between the gate electrode of the first logic transistor and the other end of the third logic transistor.

[0022] In the first time period, the start signal and the second clock signal have a logic low voltage, and the first clock signal has a logic high voltage. In the second time period after the first time period, the first clock signal has a logic low voltage, and the second clock signal has a logic high voltage. In the third time period after the second time period, the second clock signal has a logic low voltage, and the first clock signal and the start signal have a logic high voltage. In the fourth time period after the third time period, the first clock signal has a logic low voltage, and the second clock signal has a logic high voltage.

[0023] The first inverter transistor includes a gate electrode located on one side of an oxide semiconductor and a lower electrode located on the other side of the oxide semiconductor, and the display device further includes: a first switch having one end connected to the gate electrode and the other end connected to the lower electrode; and a second switch having one end commonly connected to the lower electrode and the first switch and the other end supplied with a constant voltage.

[0024] When the scan drive circuit outputs a scan signal at a first scan rate or a higher scan rate, the first switch can be turned on and the second switch can be turned off.

[0025] When the scan drive circuit outputs a scan signal at a scan rate less than the first scan rate, the first switch can be turned off and the second switch can be turned on.

[0026] In another aspect of this disclosure, a scan driving circuit includes: a logic unit configured to receive a plurality of clock signals and output logic signals via a logic output terminal to supply scan signals to pixel circuits located in a display area of ​​a substrate; and an inverter configured to receive the logic signals and output scan signals, inverting the phase of the logic signals via a gating output terminal, wherein the inverter includes an n-type first inverter transistor and a p-type second inverter transistor, the first inverter transistor and the second inverter transistor being connected to the gating output terminal, the gating output terminal being interposed between the first inverter transistor and the second inverter transistor, and the first inverter transistor comprising an oxide semiconductor.

[0027] The period during which a logic high voltage of a logic signal is supplied to the gate electrode of the first inverter transistor can be longer than the period during which a logic low voltage of the logic signal is supplied.

[0028] The second inverter transistor may include a semiconductor formed of LTPS.

[0029] The first inverter transistor may have a gate electrode connected to a logic output terminal, one end supplied with a gating low voltage (VGL) and the other end connected to the gating output terminal, and the second inverter transistor may have a gate electrode connected to a logic output terminal, one end supplied with a gating high voltage (VGH) and the other end connected to the gating output terminal.

[0030] The first inverter transistor can be turned on by a logic signal with a high gate voltage to output a scan signal with a low gate voltage to the gating output terminal, and the second inverter transistor can be turned on by a logic signal with a low gate voltage to output a scan signal with a high gate voltage to the gating output terminal.

[0031] The first inverter transistor may include a gate electrode located on one side relative to the oxide semiconductor and a lower electrode located on the other side, and the scan drive circuit may further include a first switch having one end connected to the gate electrode and the other end connected to the lower electrode; and a second switch commonly connected to the lower electrode and the other end of the first switch and configured to control the supply of a constant voltage.

[0032] When the scan drive circuit outputs a scan signal at a first scan rate or a higher scan rate, the first switch can be turned on and the second switch can be turned off.

[0033] When the scan drive circuit outputs a scan signal at a scan rate less than the first scan rate, the first switch can be turned off and the second switch can be turned on.

[0034] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and explanatory, and are intended to provide further explanation of the claimed disclosure.

[0035] Other systems, methods, features, and advantages will be apparent or become apparent to those skilled in the art upon reading the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages are included in this specification, fall within the scope of this disclosure, and are protected by the appended claims. Nothing in this section should be construed as limiting these claims. Further aspects and advantages will be discussed below in conjunction with embodiments of this disclosure. Attached Figure Description

[0036] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and form a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0037] Figure 1 This is a diagram used to describe an example of a display device applicable to this disclosure;

[0038] Figure 2 This is a diagram illustrating an example of an equivalent circuit for a sub-pixel SP of a display device suitable for this disclosure;

[0039] Figure 3 This is a diagram illustrating a scan drive circuit according to a first embodiment of the present disclosure;

[0040] Figure 4 This is an example diagram used to describe a timing diagram applied to a scan drive circuit according to the first embodiment;

[0041] Figures 5 to 8 This is used to describe the scanning drive circuit according to the first embodiment. Figure 4 A diagram illustrating the operation method of a timing diagram;

[0042] Figure 9 This is a diagram illustrating a scan drive circuit according to a second embodiment of the present disclosure;

[0043] Figure 10 This is a diagram illustrating the operation of the scan drive circuit according to the second embodiment during high-speed operation at a first scan rate or a higher scan rate; and

[0044] Figure 11 This is a diagram illustrating the operation of the scan drive circuit according to the second embodiment during low-speed operation at a rate less than the first scan rate.

[0045] Throughout the accompanying drawings and detailed embodiments, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, the relative dimensions and depictions of these elements may be exaggerated. Detailed Implementation

[0046] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions will be omitted or provided briefly where such detail would unnecessarily obscure the gist of the inventive concept. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and can be varied as is known in the art, except where the steps and / or operations must occur in a specific order. The same reference numerals always denote the same elements. The names of the various elements used in the following description are chosen solely for convenience of writing the specification and may therefore differ from the names used in actual products.

[0047] The foregoing objects, features, and advantages of this disclosure will be described in detail with reference to the accompanying drawings to enable those skilled in the art to readily implement the technical concepts of this disclosure. Where a detailed description of prior art related to this disclosure unnecessarily obscures its essence, it will be omitted or may be provided briefly. Hereinafter, embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0048] The same reference numerals refer to the same components. Furthermore, some portions of the figures may be enlarged to effectively depict the thickness, proportions, and dimensions of the components. For ease of description, the scale of the components depicted in the figures differs from the actual scale, and is not limited to the scale depicted in the figures.

[0049] In this disclosure, when a component (or region, layer, section, etc.) is referred to as “on another component,” “connected to another component,” or “linked to another component,” it means that the component can be directly connected to / linked to another component, or a third component can be set therein.

[0050] "And / or" includes all of one or more combinations that can be defined by the associated components. Throughout the specification, unless otherwise stated, the term "A and / or B" means A, B, or both A and B, and unless otherwise stated, the term "C to D" means C or greater and D or less.

[0051] Although terms such as "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. For example, without departing from the scope of this embodiment, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0052] The terms “below,” “lower,” “above,” and “upper,” etc., are used to describe the relationship between components depicted in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings. For example, one or more other components may be located between two components unless “immediately adjacent” or “directly” is used. Spatially relative terms such as “below,” “below,” “lower,” “above,” and “upper” are used to readily describe the relationship between one element or component and another element or component, as depicted in the accompanying drawings. Thus, for example, “below” and “lower” relative to the first component may be in the opposite direction to “above” and “upper” relative to the first component.

[0053] In addition to the directions depicted in the accompanying drawings, spatial relative terms should be understood to include different orientations of the elements during use or operation. For example, when an element depicted in the accompanying drawings is flipped, an element described as being "below" or "below" another element may be placed "above" another element. Thus, the exemplary term "below" can include both the downward direction and the upward direction.

[0054] It should be understood that terms such as “comprising” or “having” are intended to indicate the presence of the features, quantities, steps, operations, components, parts or combinations thereof described in this specification, and do not preclude the possibility of adding or having one or more other features, quantities, steps, operations, components, parts or combinations thereof.

[0055] Unless the context clearly indicates otherwise, singular expressions used in this specification include plural expressions. In this application, terms such as “comprising” or “including” should not be construed as including all components or steps listed in the specification; some components or steps may be excluded, or additional components or steps may be included.

[0056] Furthermore, when referring to any size, relative size, etc., even without a specific description, the numerical values ​​or corresponding information of the component or feature (e.g., level, range, etc.) should be considered to include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "can" fully encompasses all the meanings of the term "can".

[0057] When describing temporal relationships, discontinuous cases may be included when the temporal order is described as such as "after", "following", "next", and "before", unless more restrictive terms such as "only", "immediately after", or "directly" are used.

[0058] Furthermore, when a component or layer is "connected," "joined," or "adhered" to another component or layer, it means that the component or layer can be directly connected or adhered to the other component or layer, or indirectly connected or adhered to the other component or layer, with one or more intermediate components or layers "set" or "intercalated" between these components or layers, unless otherwise stated. It should be understood that components may be arranged to be in direct contact with each other, or they may be arranged not to be in direct contact with each other.

[0059] When describing quantitative or numerical relationships, terms such as "equal" and "identical" generally mean "substantially equal" and "substantially identical," or "similar or equal" and "similar or identical." That is, based on the premise that two elements are equal or identical, a certain margin of error is allowed, such as one percent, five percent, ten percent, etc.

[0060] It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of this disclosure without departing from the technical spirit or scope thereof. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

[0061] Features of each of the several embodiments of this disclosure may be combined or mixed with each other in part or in whole, and may be technically linked and operated in various ways, and the corresponding embodiments may be implemented independently of each other or may be implemented together in an interrelated manner.

[0062] In the following text, the gate on-voltage can be the voltage of a gate signal that enables the transistor to conduct. The gate off-voltage can be the voltage that enables the transistor to turn off. In a P-type transistor, the gate on-voltage can be a logic low voltage VL, and the gate off-voltage can be a logic high voltage VH. In an N-type transistor, the gate on-voltage can be a logic high voltage, and the gate off-voltage can be a logic low voltage.

[0063] The display device of this disclosure will be reviewed below with reference to the accompanying drawings and embodiments.

[0064] Figure 1 This is a diagram used to describe an example of a display device applicable to this disclosure. Figure 2 This is a diagram illustrating an example of an equivalent circuit for a sub-pixel SP suitable for a display device according to this disclosure.

[0065] Reference Figure 1 and Figure 2 According to an example of the present disclosure, the display device 100 includes a display panel 110, and the display panel 110 may include a display area AA and a non-display area NA.

[0066] The display area AA can be an area used to display an image. Multiple subpixels SP are arranged in the display area AA of the display panel 110, and the multiple subpixels SP can be used to display an image. The area with multiple subpixels SP can be the display area AA, and the area other than the display area AA can be a non-display area NA.

[0067] The non-display area NA can be arranged in the boundary region surrounding the display area AA of the displayed image. At least one driving unit (not shown) for driving multiple sub-pixels SP can be arranged in the non-display area NA. The driving unit can be a gate-in-panel (GIP).

[0068] At least one driving unit may include a scan driving circuit for supplying scan signals to a plurality of sub-pixels SP arranged in the display area AA. Additionally, various additional components may be arranged in the non-display area NA to drive the sub-pixels SP in the display area AA.

[0069] However, this disclosure is not limited thereto, and for example, the scan driving circuitry may be distributed within the display area AA. For example, within the display area AA, the pixel area where the pixels are located and the circuit area where the scan driving circuitry is located may be horizontally and alternately positioned.

[0070] In addition, the display device 100 of this disclosure may include a timing controller (not shown) that supplies timing control signals including clock signals (e.g., CLK1 and CLK2) and a start signal GVST to the scan drive circuit, and may include a power supply circuit (not shown) for supplying power (e.g., VGL, VGH, EVDD and EVSS) required to drive the scan drive circuit and sub-pixels.

[0071] Each of the multiple sub-pixels SP can control the emission of the light-emitting element OLED according to the data voltage supplied in sync with the scan signal. The scan signal can be supplied from the scan driving circuit via the gate line GL, and the signal can be supplied in sync with the scan signal via the data line DL.

[0072] For example, such as Figure 2 As shown in (a) or (b), at least one of the plurality of sub-pixels SP can be represented as an equivalent circuit including a first switching transistor ST1, a driving transistor DT, a capacitor Cst, and a light-emitting element OLED.

[0073] The first switching transistor ST1 may have a first electrode (e.g., drain electrode) electrically connected to the data line DL, a second electrode (e.g., source electrode) electrically connected to the first node N1, and a gate electrode electrically connected to the gating line GL. The first switching transistor ST1 may transmit a data signal supplied via the data line DL to the first node N1 in response to a scan signal supplied via the gating line GL.

[0074] The capacitor Cst can be electrically connected to the first node N1 and can be charged with the voltage applied to the first node N1.

[0075] The driving transistor DT may have a first electrode (e.g., drain electrode) electrically connected to a high-potential driving voltage EVDD and a second electrode (e.g., source electrode) electrically connected to a first electrode (e.g., anode) of the light-emitting element OLED. The driving transistor DT may control the amount of driving current flowing to the light-emitting element OLED in response to a voltage applied to the gate electrode.

[0076] The active layer of the first switching transistor ST1 and / or the driving transistor DT may include, but is not limited to, oxides such as IGZO (indium gallium zinc oxide).

[0077] An OLED (Optical Display Panel) can output light corresponding to a driving current. An OLED can output light corresponding to one of the following colors: red (R), green (G), blue (B), and white.

[0078] An OLED (Optical Display Panel) can include an anode, an emitting layer disposed on the anode, and a cathode that supplies a common voltage. The emitting layer can be configured to emit the same color of light, such as white light, for each pixel, or it can be configured to emit different colors of light, such as red (R), green (G), or blue (B), for each sub-pixel (SP).

[0079] The light-emitting element OLED can be a front-emitting diode or a back-emitting diode.

[0080] exist Figure 2 In (a), the case where the driving transistor DT is directly connected to the light-emitting element OLED is shown as an example, but this disclosure is not limited thereto, and as... Figure 2 As shown in (b), the driving transistor DT can be connected to the light-emitting element OLED via the second switching transistor ST2.

[0081] Specifically, such as Figure 2 As shown in (b), a second switching transistor ST2 can be arranged between the driving transistor DT and the light-emitting element OLED, and the first electrode of the second switching transistor ST2 can be connected to the driving transistor DT, and the second electrode of the second switching transistor ST2 can be electrically connected to the light-emitting element OLED. In response to a light emission signal applied to the gate electrode of the driving transistor DT, the on / off state of the driving current applied from the driving transistor DT to the light-emitting element OLED can be controlled.

[0082] Furthermore, although not in Figure 2 As shown, however, a compensation circuit (not shown) for compensating the threshold voltage of the driving transistor DT, which is a driving transistor, can be further provided in the sub-pixel SP. The compensation circuit may include at least one transistor connected to the driving transistor DT and may be provided in the sub-pixel SP.

[0083] In the sub-pixel SP, depending on the configuration, the compensation circuit can be configured in various structures, such as 3T1C including three transistors and one capacitor Cst, 4T2C including four transistors and two capacitors Cst, or 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc.

[0084] The following text will provide information about... Figure 2 The pixel circuit shown is a description of the scan drive circuit that supplies the scan signal.

[0085] Figure 3 This is a diagram illustrating a scan drive circuit according to a first embodiment of the present disclosure, and Figure 4 This is a diagram illustrating an example of a timing diagram applied to a scan drive circuit according to a first embodiment.

[0086] like Figure 3 As shown, the scan drive circuit 200 according to the first embodiment of the present disclosure may include a logic unit 210 and an inverter 220.

[0087] Logic unit 210 can receive multiple clock signals CLK1 and CLK2 and a start signal GVST from a timing controller (not shown), and output logic signals through the logic output terminal OUT_Logic. When the scan drive circuit 200 includes multiple stages, the logic unit 210 included in the first stage that first supplies the scan signal can receive the start signal GVST from the timing controller, and the logic unit 210 included in the second or subsequent stages can receive the carry signal of the previous stage as the start signal GVST.

[0088] To output logic signals, logic unit 210 may include multiple logic transistors and multiple capacitors. The multiple logic transistors included in logic unit 210 may include p-type transistors, which comprise semiconductors formed of LTPS to improve the transistor's response speed characteristics.

[0089] Inverter 220 can receive logic signals and output a scan signal whose phase is inverted through the gating output terminal OUT_AA. That is, the scan signal output by inverter 220 can be a signal whose phase is inverted compared to the logic signal. For example, when a logic signal with a gating high voltage VGH is input from logic unit 210, inverter 220 can output a scan signal with a gating low voltage VGL, and when a logic signal with a gating low voltage VGL is input from logic unit 210, inverter 220 can output a scan signal with a gating high voltage VGH.

[0090] The strobe output terminal OUT_AA can be electrically connected to Figure 1 The gating line GL. The scan signal from inverter 220 can be input to the first switching transistor ST1 of sub-pixel SP through the gating line GL.

[0091] Inverter 220 includes an n-type first inverter transistor T8_O and a p-type second inverter transistor T9. The first inverter transistor T8_O and the second inverter transistor T9 are positioned such that their respective gate electrodes are connected to the logic output terminal OUT_Logic, and the strobe output terminal OUT_AA is interposed between the first inverter transistor T8_O and the second inverter transistor T9. The first inverter transistor T8_O may comprise an oxide semiconductor, and the second inverter transistor T9 may comprise a semiconductor formed of LTPS. In other words, the first inverter transistor T8_O and the second inverter transistor T9 can be transistors of different types.

[0092] Specifically, the first inverter transistor T8_O may have a gate electrode connected to the logic output terminal OUT_Logic, one end supplied with a low selection voltage VGL, and the other end connected to the selection output terminal OUT_AA. The second inverter transistor T9 may have a gate electrode connected to the logic output terminal OUT_Logic, one end supplied with a high selection voltage VGH, and the other end connected to the selection output terminal OUT_AA.

[0093] Therefore, the first inverter transistor T8_O can be turned on by a logic signal with a high gate voltage VGH to output a low gate voltage VGL to the gate output terminal OUT_AA, and the second inverter transistor T9 can be turned on by a logic signal with a low gate voltage VGL to output a high gate voltage VGH to the gate output terminal OUT_AA.

[0094] In the inverter 220 of this disclosure, the first inverter transistor and the second inverter transistor are controlled by a logic signal output through the logic output terminal OUT_Logic, thereby eliminating the need for separate clock signals to control the first and second inverter transistors and reducing the number of clock signals. Therefore, the structure of the inverter 220 of this disclosure can further simplify the circuit structure and reduce the number of clock signal lines arranged on the display panel. For example, since the inverter 220 can use both n-type and p-type transistors, it can be effectively controlled by the same logic signal output through the logic output terminal OUT_Logic.

[0095] Logic unit 210 in Figure 3 The example shown is for illustrative purposes only, but it can be configured in various forms including Q nodes and QB nodes, and can include multiple logic transistors and multiple capacitors, as described above. This disclosure is not limited to... Figure 3 The configuration of logic unit 210 is shown. The configuration of logic unit 210 is not limited, as long as the logic signals for selecting high voltage VGH and selecting low voltage VGL are output through the logic output terminal OUT_Logic.

[0096] For example, such as Figure 3 As shown, the logic unit 210 may include p-type first logic transistors T1 to seventh logic transistors T7, as well as a first capacitor CQ and a second capacitor CQB.

[0097] The first logic transistor T1 may have a gate electrode connected to the Q node, one end receiving the first clock signal CLK1, and the other end connected to the logic output terminal OUT_Logic. The first logic transistor T1 can output the voltage of the first clock signal CLK1 to the logic output terminal OUT_Logic according to the potential of the Q node.

[0098] The second logic transistor T2 may have a gate electrode connected to the QB node, one end supplied with a gating high voltage VGH, and the other end connected to the logic output terminal OUT_Logic. The gating high voltage VGH can be output to the logic output terminal OUT_Logic according to the potential of the QB node.

[0099] The third logic transistor T3 may have a gate electrode connected to the second clock signal CLK2, one end receiving the start signal GVST, and the other end connected to the Q node via the eighth logic transistor TA. The third logic transistor T3 can apply the potential of the start signal GVST to the Q node according to the second clock signal CLK2.

[0100] The fourth logic transistor T4 may have a gate electrode connected to the Q node via the eighth logic transistor TA, one end of which is connected to the input second clock signal CLK2, and the other end connected to the QB node. The fourth logic transistor T4 can apply the potential of the second clock signal CLK2 to the QB node according to the potential of the Q2 node.

[0101] The fifth logic transistor T5 may have a gate electrode that receives the second clock signal CLK2, one end that receives the gating low voltage VGL, and the other end connected to the QB node. The fifth logic transistor T5 can supply the gating low voltage VGL to the QB node according to the second clock signal CLK2.

[0102] The sixth logic transistor T6 may have a gate electrode connected to the QB node and may output the gating high voltage VGH supplied to one end to the other end. The sixth logic transistor T6 may output the gating high voltage VGH to the seventh logic transistor T7 according to the potential of the QB node.

[0103] The seventh logic transistor T7 may have a gate electrode that is input to the first clock signal CLK1, one end connected to the sixth logic transistor T6, and the other end connected to the Q node through the eighth logic transistor TA. The seventh logic transistor T7 may supply the gating high voltage VGH supplied through the sixth logic transistor T6 to the Q node according to the first clock signal CLK1.

[0104] The eighth logic transistor TA has a gate electrode supplied with a low gate voltage VGL and can be connected between the gate electrode of the first logic transistor T1 and the other end of the third logic transistor T3. That is, the eighth logic transistor TA can be located at the Q node.

[0105] exist Figure 3For convenience, one side of the eighth logic transistor TA is designated as the Q2 node, and the other side is designated as the Q node. However, since the eighth logic transistor TA is always supplied with a low gate voltage VGL through its gate electrode and remains in the on state, the potentials of the Q node and the Q2 node can be substantially the same as long as the logic cell 210 is operating normally.

[0106] The eighth logic transistor TA can reduce or prevent damage to the first logic transistor T1 due to overvoltage. Specifically, without the eighth logic transistor TA, the first logic transistor T1 may be damaged when an overvoltage exceeding the drive range is applied to the Q2 node due to circuit malfunction or other reasons.

[0107] However, if an eighth logic transistor TA is provided, when an overvoltage is applied to node Q2, the eighth logic transistor TA is turned off, causing node Q2 and node Q to be electrically isolated from each other, thereby reducing or preventing the overvoltage of node Q2 from being transmitted to node Q, and reducing or preventing damage to the first logic transistor T1.

[0108] The first capacitor CQ may have one end connected to the Q node and the other end connected to the logic output terminal OUT_Logic. The first capacitor CQ can be charged and maintained by the potential applied to the Q node. Therefore, unless the Q node is floated or the currently applied potential to the Q node is different from the previously applied potential, the potential of the Q node can be maintained at the same or substantially the same potential by the first capacitor CQ.

[0109] The second capacitor CQB can have one end connected to the QB node and the other end supplied with a logic high voltage VH. The second capacitor CQB can be charged and maintained at the potential applied to the QB node. Therefore, unless the QB node is floated or the current voltage supplied to the QB node is different from the previously supplied voltage, the potential of the QB node can be maintained at the same or substantially the same potential by the second capacitor CQB.

[0110] Here, the high voltage VGH and the low voltage VGL can be selected from the power supply, and the first clock signal CLK1, the second clock signal CLK2, and the start signal GVST can be supplied from the timing controller.

[0111] like Figure 4 As shown, the timing diagram applied to the scan drive circuit 200 according to the first embodiment may include a first time period P1 to a fourth time period P4 during a cycle.

[0112] During the first time period P1, the start signal GVST and the second clock signal CLK2 can have a logic low voltage VL, and the first clock signal CLK1 can have a logic high voltage VH. Therefore, logic unit 210 can output a gating high voltage VGH through the logic output terminal OUT_Logic, and inverter 220 can output a scan signal with a gating low voltage VGL through the gating output terminal OUT_AA.

[0113] In the second time period P2 following the first time period P1, the first clock signal CLK1 can have a logic low voltage VL, and the second clock signal CLK2 and the start signal GVST can have a logic high voltage VH. Therefore, logic unit 210 can output a low-gating voltage VGL through the logic output terminal OUT_Logic, and inverter 220 can output a scan signal with a high-gating voltage VGH through the gating output terminal OUT_AA.

[0114] In the third time period P3 following the second time period P2, the second clock signal CLK2 can have a logic low voltage VL, and the first clock signal CLK1 and the start signal GVST can have a logic high voltage VH. Therefore, logic unit 210 can output a gating high voltage VGH through the logic output terminal OUT_Logic, and inverter 220 can output a scan signal with a gating low voltage VGL through the gating output terminal OUT_AA.

[0115] In the fourth period P4 following the third period P3, the first clock signal CLK1 can have a logic low voltage VL, and the second clock signal CLK2 and the start signal GVST can have a logic high voltage VH. Therefore, logic unit 210 can output a gating high voltage VGH through the logic output terminal OUT_Logic, and inverter 220 can output a scan signal with a gating low voltage VGL through the gating output terminal OUT_AA.

[0116] In the following text, it will be based on, for example Figure 4 The timing diagrams shown provide a detailed description of the operation method of the scan drive circuit 200 according to the first embodiment.

[0117] Figures 5 to 8 This is used to describe the scanning drive circuit according to the first embodiment. Figure 4 A diagram illustrating the operation method of a timing diagram.

[0118] During the first time period P1 to the fourth time period P4, a low gate voltage VGL is supplied to the gate electrode of the eighth logic transistor TA so that the eighth logic transistor TA can be turned on during the first time period P1 to the fourth time period P4, and the potential of the Q2 node can be the same as the potential of the Q node.

[0119] During the first time period P1, the start signal GVST and the second clock signal CLK2 can have a logic low voltage VL, and the first clock signal CLK1 can have a logic high voltage VH. Therefore, the third logic transistor T3 is turned on by the second clock signal CLK2, so that the logic low voltage VL of the start signal GVST can be supplied to the Q2 node and the Q node, and the Q node can be charged with the logic low voltage VL through the first capacitor CQ.

[0120] In addition, the first logic transistor T1 can be turned on according to the logic low voltage VL of the Q node, so that the logic high voltage VH of the first clock signal CLK1 can be output through the logic output terminal OUT_Logic.

[0121] Additionally, the fourth logic transistor T4 can be turned on according to the logic low voltage VL of the Q2 node, so that the logic low voltage VL of the second clock signal CLK2 can be supplied to the QB node, and the fifth logic transistor T5 can be turned on according to the logic low voltage VL of the second clock signal CLK2, so that the gating low voltage VGL can be supplied to the QB node.

[0122] Therefore, the QB node can be charged using the low gate voltage VGL via the second capacitor CQB. Based on the logic low voltage VL of the QB node, the second logic transistor T2 also conducts, and the high gate voltage VGH can also be output via the second logic transistor T2 through the logic output terminal OUT_Logic.

[0123] Therefore, the first inverter transistor T8_O is turned on by receiving the gating high voltage VGH from the logic output terminal OUT_Logic, and the inverter 220 can output a scan signal with the gating low voltage VGL through the gating output terminal OUT_AA.

[0124] During the second time period P2, the first clock signal CLK1 may have a logic low voltage VL, and the second clock signal CLK2 may have a logic high voltage VH. Therefore, the third logic transistor T3 is turned off, the start signal GVST is blocked, and nodes Q2 and Q can maintain the logic low voltage VL of the first time period P1 through the charging potential of the first capacitor CQ. Therefore, the first logic transistor T1 is turned on, and the logic low voltage VL of the first clock signal CLK1 can be output through the logic output terminal OUT_Logic.

[0125] Additionally, when node Q2 maintains a logic low voltage VL, the fourth logic transistor T4 can be turned on, and the fifth logic transistor T5 can be turned off. Therefore, the logic high voltage VH of the second clock signal CLK2 is applied to node QB, allowing node QB to be charged by the logic high voltage VH through the second capacitor CQB. The logic high voltage VH of node QB can also turn off the second logic transistor T2 and the sixth logic transistor T6.

[0126] Therefore, the second inverter transistor T9 is turned on by receiving the low gating voltage VGL from the logic output terminal OUT_Logic, so that the inverter 220 can output a scan signal with a high gating voltage VGH through the gating output terminal OUT_AA.

[0127] In the third time period P3, the second clock signal CLK2 can have a logic low voltage VL, and the first clock signal CLK1 and the start signal GVST can have a logic high voltage VH.

[0128] The third logic transistor T3 is turned on by the second clock signal CLK2, allowing the logic high voltage VH of the start signal GVST to be provided to nodes Q2 and Q, and node Q can be charged with the logic high voltage VH through the first capacitor CQ. Conversely, the first logic transistor T1 can be turned off according to the logic high voltage VH of node Q.

[0129] Additionally, the fifth logic transistor T5 can be turned on according to the logic low voltage VL of the second clock signal CLK2, so that the gating low voltage VGL can be supplied to the QB node. Therefore, the QB node can be charged by the gating low voltage VGL through the second capacitor CQB. According to the logic low voltage VL of the QB node, the second logic transistor T2 can be turned on, so that the gating high voltage VGH can be output through the logic output terminal OUT_Logic.

[0130] Therefore, the first inverter transistor T8_O can be turned on by receiving the gating high voltage VGH via the logic output terminal OUT_Logic, and the inverter 220 can output a scan signal with the gating low voltage VGL via the gating output terminal OUT_AA.

[0131] In the fourth time period P4, the first clock signal CLK1 can have a logic low voltage VL, and the second clock signal CLK2 can have a logic high voltage VH. Therefore, the seventh logic transistor T7 can be turned on, and the third logic transistor T3 can be turned off.

[0132] The potential of the QB node can be maintained at a logic low voltage VL, equal to the potential in the third time period P3. The logic low voltage VL of the QB node can turn on the second logic transistor T2 and the sixth logic transistor T6. The second logic transistor T2 can be turned on, and a high-gating voltage VGH can be output through the logic output terminal OUT_Logic. Furthermore, the sixth logic transistor T6 can be turned on, and the high-gating voltage VGH can be supplied to the Q node through the seventh logic transistor T7.

[0133] Therefore, the first inverter transistor T8_O is turned on by receiving the gating high voltage VGH via the logic output terminal OUT_Logic, and the inverter 220 can output a scan signal with a gating low voltage VGL via the gating output terminal OUT_AA.

[0134] In this way, the present disclosure can reduce the number of clock signals by connecting the first n-type inverter transistor T8_O and the second p-type inverter transistor T9 together to the logic output terminal OUT_Logic. For example, by using a configuration design that includes a pair of transistors of different types (e.g., one n-type and one p-type) connected to the same output in inverter 220, this particular combination can provide a simpler circuit design and enable it to operate with fewer clock signals.

[0135] Furthermore, the first inverter transistor T8_O comprises an oxide semiconductor, enabling a scan signal with a gating low voltage VGL to be stably supplied to the pixel circuit via the gating output terminal OUT_AA. Therefore, the scan drive circuit 200 of this disclosure can reduce or minimize pixel circuit malfunctions. For example, the oxide semiconductor allows the first inverter transistor T8_O to supply a stable and consistent low voltage signal to the pixel, which can prevent pixel flicker or malfunctions.

[0136] Furthermore, the scan drive circuit 200 according to the first embodiment can supply a scan signal with a gating high voltage VGH for a significantly short period of time during a frame time period of one cycle, and supply a scan signal with a gating low voltage VGL during the remaining period of the frame time period.

[0137] Therefore, the period during which the high gate voltage VGH of the logic signal is supplied from logic cell 210 to the gate electrode of the first inverter transistor T8_O can be longer than the period during which the low gate voltage VGL of the logic signal is supplied. For example, the first inverter transistor T8_O can be turned on during the first period P1, the third period P3, and the fourth period P4, excluding the second period P2.

[0138] In other words, although the scan drive circuit 200 according to the first embodiment outputs a scan signal with a low gate voltage VGL, the first inverter transistor T8_O, which includes an oxide semiconductor, can be continuously turned on.

[0139] When the first inverter transistor T8_O, which includes an oxide semiconductor, is continuously turned on, the first inverter transistor T8_O may be subjected to positive bias thermal stress (PBTS), and the threshold voltage Vth of the first inverter transistor T8_O may be shifted upward due to PBTS.

[0140] This PBTS can become severe when the scan drive circuit 200 is driven at low speed, in a high-temperature environment, or for extended periods. As a result, the first inverter transistor T8_O may malfunction, failing to stably maintain the low gating voltage VGL of the scan signal, leading to drive failure and potentially degrading the reliability of the display device 100.

[0141] With this in mind, this disclosure may include structures to reduce or prevent drive failures of the first inverter transistor T8_O.

[0142] Figure 9 This is a diagram illustrating the scan drive circuit according to a second embodiment of the present disclosure. Figure 10 This is a diagram illustrating the operation of the scan drive circuit according to the second embodiment during high-speed operation at a first scan rate or a higher scan rate, and Figure 11 This is a diagram illustrating the operation of the scan drive circuit according to the second embodiment during low-speed operation at a rate less than the first scan rate.

[0143] exist Figures 9 to 11 In the middle, with reference above Figures 3 to 8 For overlapping descriptions, please refer to [the relevant source]. Figures 3 to 8 The content mainly describes the other parts.

[0144] according to Figure 9 The scanning drive circuit 200 of the second embodiment shown can compensate for the phenomenon that the first inverter transistor T8_O deteriorates and shifts in the positive direction under low-speed driving conditions, high-temperature environmental conditions or long-term driving conditions.

[0145] Specifically, in the scan drive circuit 200 according to the second embodiment of this disclosure, the first inverter transistor T8_O includes a lower electrode BE positioned on the opposite side of the gate electrode relative to the oxide semiconductor, and may also include a first switch SW1 and a second switch SW2. For example, the first inverter transistor T8_O may include a configuration having a sandwich arrangement, wherein the lower electrode is placed on one side of the oxide material and the gate electrode is located on the other side (e.g., the gate may be located above the active layer of T8_O and the lower electrode may be located below the active layer of T8_O). Furthermore, this configuration may be connected to two switches (SW1 and SW2).

[0146] The first switch SW1 may have one end connected to the gate electrode and the other end connected to the lower electrode BE, and the second switch SW2 may have one end connected to both the lower electrode BE and the first switch SW1 and the other end supplied with a constant voltage Vbg. For example, the first switch SW1 and the second switch SW2 may each include a P-type transistor.

[0147] For example, when the scan drive circuit 200 according to the second embodiment is in normal drive or high-speed drive, the first switch SW1 can improve the response speed of the first inverter transistor T8_O by connecting the gate electrode and the lower electrode BE of the first inverter transistor T8_O. For example, during normal or high-speed operation, the first switch SW1 can connect the upper electrode (gate) and the lower electrode of the transistor together, wherein such a direct connection can improve the response speed of the first inverter transistor T8_O. In other words, during normal or high-speed operation, the first switch SW1 can operate as a dual-gate transistor, wherein a stronger electric field can be applied to the opposite side of the source layer to form a better conductive path (e.g., higher drive current and faster response time).

[0148] During low-speed drive, the second switch SW2 can compensate for the degradation and positive offset of the first inverter transistor T8_O by connecting a back-biased power supply with a constant voltage Vbg to the lower electrode BE of the first inverter transistor T8_O. For example, during low-speed drive (which may cause excessive stress on the transistor), the second switch SW2 can be turned on and apply a stable correction voltage (e.g., "reverse bias") to the lower electrode of the first inverter transistor T8_O, which can counteract the stress and prevent the electrical properties of the transistor from shifting.

[0149] More specifically, when the scan drive circuit 200 outputs a scan signal at a first scan rate or a higher rate, the first switch SW1 can be turned on and the second switch SW2 can be turned off, such as... Figure 10 As shown in (a).

[0150] The first scan rate can be set based on, for example, 60 Hz. However, this disclosure is not limited to this, and the standard for the first scan rate can vary. However, for ease of description, the case of a first scan rate of 60 Hz will be used as an example to give the following description.

[0151] Therefore, when the scan drive circuit 200 according to the second embodiment performs a normal drive to output a scan signal at a speed of 60 Hz, or when the scan drive circuit 200 performs a high-speed drive to output a scan signal at a high speed of 120 Hz, the first switch SW1 can be turned on and the second switch SW2 can be turned off. Therefore, for example, as... Figure 10 As shown in (b), during the first time period P1 to the fourth time period P4, a signal with a logic low voltage VL can be applied to the gate electrode of the first switch SW1 to turn on the first switch SW1, and a signal with a logic high voltage VH can be applied to the gate electrode of the second switch SW2 to turn off the second switch SW2.

[0152] Therefore, the gate electrode and lower electrode BE of the first inverter transistor T8_O can be connected to each other through the first switch SW1, thereby improving the response speed of the first inverter transistor T8_O.

[0153] Furthermore, although the scan drive circuit 200 according to the second embodiment outputs a scan signal at a rate less than the first scan rate, however... Figure 11 As shown in (a), the first switch SW1 can be turned off and the second switch SW2 can be turned on.

[0154] Therefore, when the scan drive circuit 200 according to the second embodiment is driven at a low speed to output a scan signal at a speed of, for example, 30 Hz or 1 Hz, which is lower than 60 Hz, the scan drive circuit 200 operates at a first temperature higher than a preset temperature, or the scan drive circuit 200 operates for a long time longer than a preset time, the first switch SW1 can be turned on and the second switch SW2 can be turned off.

[0155] Therefore, for example, such as Figure 11 As shown in (b), during the first time period P1 to the fourth time period P4, a signal with a logic high voltage VH can be applied to the gate electrode of the first switch SW1 to turn off the first switch SW1, and a signal with a logic low voltage VL can be applied to the gate electrode of the second switch SW2 to turn on the second switch SW2.

[0156] Therefore, connecting the back bias power supply to the lower electrode BE of the first inverter transistor T8_O can reduce or prevent the forward bias thermal stress (PBTS) of the first inverter transistor T8_O, thereby improving the reliability of the scan drive circuit 200 and the display device 100. For example, if no reverse bias voltage is applied during low-speed driving, the PBTS stress may cause the threshold voltage of the first inverter transistor T8_O to shift to a higher direction. This means that the minimum voltage at the gate that turns on the transistor increases, which will result in power waste in the long run and may lead to image defects or timing errors.

[0157] In this way, embodiments of the present disclosure can reduce the number of clock signals and simplify operation by using an inverter that includes an n-type first inverter transistor and a p-type second inverter transistor having logic output terminals that are commonly connected to the logic unit of the scan drive circuit.

[0158] In embodiments of this disclosure, the first inverter transistor comprises an oxide semiconductor, thereby preventing the scan signal from becoming unstable due to leakage current of the first inverter transistor and reducing or minimizing pixel circuit failures.

[0159] Embodiments of this disclosure can reduce or prevent PBTS of the first inverter transistor and mitigate operational errors of the scan drive circuit by including a lower electrode and a first switch and a second switch connected to the lower electrode.

[0160] Embodiments of this disclosure can reduce the number of clock signals and simplify operation by using an inverter comprising an n-type first inverter transistor and a p-type second inverter transistor having logic output terminals commonly connected to a logic unit of a scan drive circuit.

[0161] In embodiments of this disclosure, the first inverter transistor comprises an oxide semiconductor, thereby preventing the scan signal from becoming unstable due to leakage current of the first inverter transistor and reducing or minimizing pixel circuit failures.

[0162] The embodiments of this disclosure can reduce or prevent PBTS of the first inverter transistor that may occur during low-speed driving, and mitigate the operational error of the scan drive circuit by including a first switch that connects the gate electrode and the lower electrode of the first inverter transistor during high-speed driving and a second switch that connects the lower electrode of the first inverter transistor and a constant voltage during low-speed driving.

[0163] From the above description, those skilled in the art will understand that various changes and modifications are possible without departing from the technical spirit of this disclosure. Therefore, the technical scope of this disclosure should not be limited to the content described in the specific embodiments of the specification, but should be determined by the scope of the claims.

[0164] Cross-reference to related applications

[0165] This application claims priority to Korean Patent Application No. 10-2024-0188843, filed in Korea on December 17, 2024, the entire contents of which are expressly incorporated herein by reference as if fully set forth herein.

Claims

1. A display device, the display device comprising: A substrate, the substrate including a display area and a non-display area; A pixel circuit, located in the display area and configured to drive light-emitting elements; as well as A scan driving circuit, configured to supply scan signals to the pixel circuit. The scanning drive circuit includes: A logic unit configured to receive multiple clock signals and output logic signals via a logic output terminal; and An inverter configured to receive the logic signal and output the scan signal, wherein the phase of the logic signal is inverted via a gating output terminal. The inverter includes an n-type first inverter transistor and a p-type second inverter transistor. The gate electrode of each of the first inverter transistor and the second inverter transistor is connected to the logic output terminal, and The first inverter transistor and the second inverter transistor are connected to the gating output terminal, which is inserted between the first inverter transistor and the second inverter transistor. The first inverter transistor comprises an oxide semiconductor.

2. The display device according to claim 1, wherein, The period during which the high voltage of the logic signal is supplied to the gate electrode of the first inverter transistor is longer than the period during which the low voltage of the logic signal is supplied.

3. The display device according to claim 1, wherein, The second inverter transistor contains a semiconductor formed of low-temperature polycrystalline silicon (LTPS).

4. The display device according to claim 1, wherein, The first inverter transistor has a gate electrode connected to the logic output terminal, one end supplied with a low gating voltage VGL, and the other end connected to the gating output terminal. The second inverter transistor has a gate electrode connected to the logic output terminal, one end supplied with a gating high voltage VGH, and the other end connected to the gating output terminal.

5. The display device according to claim 1, wherein, The first inverter transistor is turned on by the logic signal having a high gate voltage to output the scan signal having a low gate voltage to the gating output terminal, and The second inverter transistor is turned on by the logic signal having the gating low voltage to output the scan signal having the gating high voltage to the gating output terminal.

6. The display device according to claim 1, wherein, The logic unit includes multiple logic transistors, and The plurality of logic transistors include semiconductors formed of LTPS.

7. The display device according to claim 1, wherein, The logic unit includes: A first logic transistor has a gate electrode connected to a Q node, one end to which a first clock signal is input, and the other end to which the logic output terminal is connected. The second logic transistor has a gate electrode connected to the QB node, one end supplied with a gate high voltage, and the other end connected to the logic output terminal. The third logic transistor has a gate electrode into which a second clock signal is input, one end into which a start signal is input, and the other end connected to the Q node; A fourth logic transistor has a gate electrode connected to the Q node, one end of which is input with the second clock signal, and the other end of which is connected to the QB node; The fifth logic transistor has a gate electrode that is input to the second clock signal, a terminal that is input to a low-voltage gate, and the other terminal that is connected to the QB node; A sixth logic transistor having a gate electrode connected to the QB node and configured to output a gating high voltage supplied at one end to the other end; A seventh logic transistor having a gate electrode into which the first clock signal is input, one end connected to the sixth logic transistor, and the other end connected to the Q node; A first capacitor, the first capacitor having one end connected to the Q node and the other end connected to the logic output terminal; and The second capacitor has one end connected to the QB node and the other end supplied with a logic high voltage.

8. The display device according to claim 7, wherein, The logic unit further includes an eighth logic transistor having a gate electrode supplied with a low voltage and connected between the gate electrode of the first logic transistor and the other end of the third logic transistor.

9. The display device according to claim 7, wherein, During the first time period, the start signal and the second clock signal have a logic low voltage, and the first clock signal has a logic high voltage. In the second time period following the first time period, the first clock signal has a logic low voltage, and the second clock signal has a logic high voltage. In the third period following the second period, the second clock signal has a logic low voltage, and the first clock signal and the start signal have a logic high voltage. In the fourth period following the third period, the first clock signal has a logic low voltage and the second clock signal has a logic high voltage.

10. The display device according to claim 1, wherein, The first inverter transistor includes a lower electrode positioned on the opposite side of the gate electrode relative to the oxide semiconductor, and The display device further includes: A first switch, the first switch having one end connected to the gate electrode and the other end connected to the lower electrode; and A second switch has one end commonly connected to the lower electrode and the first switch, and the other end supplied with a constant voltage.

11. The display device according to claim 10, wherein, When the scan drive circuit outputs the scan signal at a first scan rate or a higher scan rate, the first switch is turned on and the second switch is turned off.

12. The display device according to claim 10, wherein, When the scan drive circuit outputs the scan signal at a scan rate less than the first scan rate, the first switch is turned off and the second switch is turned on.

13. A scan driving circuit, the scan driving circuit comprising: A logic unit configured to receive multiple clock signals and output logic signals through a logic output terminal to supply scan signals to pixel circuits located in the display area of ​​the substrate; as well as An inverter configured to receive the logic signal and output the scan signal, wherein the phase of the logic signal is inverted via a gating output terminal. The inverter includes an n-type first inverter transistor and a p-type second inverter transistor. The first inverter transistor and the second inverter transistor are connected to the gating output terminal, which is inserted between the first inverter transistor and the second inverter transistor. The first inverter transistor comprises an oxide semiconductor.

14. The scanning drive circuit according to claim 13, wherein, The period during which the logic high voltage of the logic signal is supplied to the gate electrode of the first inverter transistor is longer than the period during which the logic low voltage of the logic signal is supplied.

15. The scanning drive circuit according to claim 13, wherein, The second inverter transistor comprises a semiconductor formed of LTPS.

16. The scanning drive circuit according to claim 13, wherein, The first inverter transistor has a gate electrode connected to the logic output terminal, one end supplied with a low gating voltage VGL, and the other end connected to the gating output terminal. The second inverter transistor has a gate electrode connected to the logic output terminal, one end supplied with a gating high voltage VGH, and the other end connected to the gating output terminal.

17. The scanning drive circuit according to claim 13, wherein, The first inverter transistor is turned on by the logic signal having a high gate voltage to output the scan signal having a low gate voltage to the gating output terminal, and The second inverter transistor is turned on by the logic signal having the gating low voltage to output the scan signal having the gating high voltage to the gating output terminal.

18. The scanning drive circuit according to claim 13, wherein, The first inverter transistor includes a gate electrode located on one side of the oxide semiconductor and a lower electrode located on the other side of the oxide semiconductor, and The scanning drive circuit also includes: A first switch, the first switch having one end connected to the gate electrode and the other end connected to the lower electrode; and A second switch is commonly connected to the lower electrode and the other end of the first switch and is configured to control the supply of a constant voltage.

19. The scanning drive circuit according to claim 18, wherein, When the scan drive circuit outputs the scan signal at a first scan rate or a higher scan rate, the first switch is turned on and the second switch is turned off.

20. The scanning drive circuit according to claim 18, wherein, When the scan drive circuit outputs the scan signal at a scan rate less than the first scan rate, the first switch is turned off and the second switch is turned on.

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