Electronic paper display panel and driving method thereof

Abstract

This invention discloses an electronic paper display panel and its driving method, comprising: a first substrate; a plurality of pixel units arranged in an array on the first substrate, each pixel unit including a pixel electrode; a plurality of gate lines extending along a first direction, wherein the gate of each row of pixel units is electrically connected to a gate line; a plurality of data lines extending along a second direction intersecting the first direction; at least one driving chip disposed on or outside the first substrate, the driving chip including a plurality of source output pins; and a multiplexing circuit integrated on the first substrate; wherein the multiplexing circuit includes a plurality of switch unit groups, each switch unit group being electrically connected to a corresponding source output pin. The display panel and its driving method of this application, through time-division multiplexing of the driving channel, reduce the number of required source driving chips while ensuring precise control of the display medium, thereby reducing system cost and power consumption.

Description

Technical Field

[0001] This invention relates to the field of electronic paper display technology, and more particularly to an electronic paper display panel and its driving method. Background Technology

[0002] Electronic paper display technology has been widely used in e-readers, electronic tags, and other fields due to its advantages such as low power consumption, visual comfort, and the ability to maintain static images without continuous refresh. Among them, reflective display technology based on cholesteric liquid crystal (ChLC) is particularly prominent. It utilizes the helical structure of liquid crystal molecules to selectively reflect natural light, eliminating the need for a backlight and making it one of the important solutions for achieving ultra-low power displays.

[0003] Cholesteric liquid crystals exhibit electro-optic properties with various stable or metastable states, which can be actively controlled and switched by applying electric fields of different amplitudes and timings, making them suitable for active matrix driving methods. Common states include: Planar state (P state): In the absence of an external field or a weak field, the helical axis of the liquid crystal molecules is arranged perpendicular to the substrate, presenting a complete helical structure. It can selectively reflect light of a specific wavelength, thereby displaying colors. It is the main working state of reflective displays.

[0004] Focal-conic state (FC state): Under the action of a specific electric field, the helical axis is randomly oriented, the structure is multi-domain distributed, and it scatters light. It usually appears as a turbid or transparent state with weak scattering (depending on the relationship between the pitch and the wavelength), and is often displayed as a black state or intermediate grayscale state.

[0005] Homeotropic state (H state): Under the influence of a strong electric field, the long axes of liquid crystal molecules are aligned vertically along the direction of the electric field, and the helical structure is completely untied. At this time, the material exhibits a transparent state.

[0006] To achieve high-resolution, high-contrast displays, an active matrix driving method is required, where each pixel integrates a thin-film transistor (TFT) as a switching unit. By precisely controlling the voltage amplitude and polarity applied to each pixel electrode, cholesteric liquid crystal can be reversibly switched between P-state, FC-state, and H-state, thereby enabling image writing and retention.

[0007] However, in existing technologies, for active-matrix electronic paper panels using cholesteric liquid crystals, the driving system typically configures an independent source drive channel for each column of data lines. As the resolution of display panels increases, the number of source drive chips and pins required increases significantly, leading to higher module costs, larger bezel sizes, and increased power consumption. This has become one of the key bottlenecks restricting the widespread adoption of this type of display technology in large-size or high-resolution applications.

[0008] Therefore, there is an urgent need for a driving circuit architecture and solution that can significantly reduce the number of source drive channels required while maintaining precise voltage control over each state of cholesteric liquid crystal. Summary of the Invention

[0009] To address the technical problems existing in the background art, the present invention proposes an electronic paper display panel and its driving method.

[0010] The present invention provides an electronic paper display panel, comprising: First substrate; Multiple pixel units are arranged in an array on a first substrate, and each pixel unit includes a pixel electrode. Multiple gate lines extend along a first direction, and the gate of each row of pixel units is electrically connected to one gate line; Multiple data lines extend along a second direction that intersects with the first direction; At least one driver chip is disposed on or outside the first substrate, and the driver chip includes a plurality of source output pins; Multiplexing circuitry is integrated on the first substrate; The multiplexing circuit includes multiple switch unit groups, each switch unit group being electrically connected to a corresponding source output pin; Each switch unit group includes at least two switch units. The control terminal of each switch unit is used to receive an independent gating signal. The first conducting terminals of all switch units in the same switch unit group are connected to the corresponding source output pin, while the second conducting terminal of each switch unit is connected to a different data line. The multiplexing circuit is configured to provide a source output pin with a data voltage signal to at least two data lines in a time-division multiplexing manner by sequentially providing the corresponding gating signal to each switch unit in the same switch unit group.

[0011] Preferably, each switching unit is a thin-film transistor; the gate of the thin-film transistor serves as the control terminal, and the source and drain of the thin-film transistor serve as the first conduction terminal and the second conduction terminal, respectively.

[0012] Preferably, at least two data lines connected to the same source output pin are arranged at equal intervals along the second direction on the display panel.

[0013] Preferably, the column numbers of the data lines connected to the same source output pin form an arithmetic sequence.

[0014] Preferably, the common difference of the arithmetic sequence is equal to the number of switching units connected to the same source output pin.

[0015] The present invention provides an electronic paper display device, comprising an electronic paper display panel as described in any of the preceding claims.

[0016] The present invention proposes a driving method for an electronic paper display panel, comprising the following steps: S1. Provide a gate enable voltage to the currently selected row of gate lines to turn on all pixel units corresponding to that row of gate lines; S2. Provide a first strobe signal to a switching unit in a multiplexing circuit to connect a source output pin to a first target data line and provide a first data voltage to the first target data line through the source output pin; S3. After stopping the first strobe signal, provide a second strobe signal to another switching unit in the multiplexing circuit so that the source output pin is connected to the second target data line and the second data voltage is provided to the second target data line through the source output pin; S4. Repeat the same steps as step S3, sequentially providing the k-th strobe signal and driving the corresponding k-th target data line until all target data lines connected to the source output pin are driven, where k is an integer greater than 2; S5. After completing the driving of all target data lines in the current row, move to the next row of gate lines and repeat steps S1 to S4.

[0017] Preferably, the column numbers of the first target data line, the second target data line, and the kth target data line form an arithmetic sequence; the common difference of the arithmetic sequence is equal to the number of switching units connected to the source output pin.

[0018] Preferably, the effective pulse width of the gate turn-on voltage covers the entire period from the provision of the first strobe signal to the completion of driving all target data lines corresponding to the source output pin.

[0019] Preferably, the first gating signal, the second gating signal, and the kth gating signal are pulse signals provided sequentially and do not overlap in time.

[0020] The proposed electronic paper display panel and its driving method, while maintaining the precise voltage control capability required for each liquid crystal state, achieve time-division multiplexing of the source driving channel by introducing a multiplexing circuit and a timing driving method. This reduces the number of source driving chips and corresponding pin resources required, thereby lowering the overall hardware cost and power consumption of the display module. Attached Figure Description

[0021] Figure 1 A schematic diagram of the driving architecture of an existing electronic paper display panel; Figure 2 This is a schematic diagram of the driving architecture of one embodiment of an electronic paper display panel proposed in this invention; Figure 3 This is a schematic diagram of the driving timing of one embodiment of an electronic paper display panel proposed in this invention; Figure 4 This is a schematic diagram illustrating the workflow of a driving method for an electronic paper display panel proposed in this invention. Detailed Implementation

[0022] Reference Figures 1-3 The present invention provides an electronic paper display panel, comprising: First substrate; Specifically, the first substrate can be made of a transparent insulating material such as glass or flexible plastic.

[0023] Multiple pixel units are arranged in an array on a first substrate, and each pixel unit includes a pixel electrode.

[0024] Specifically, multiple pixel units are arranged in a matrix on a first substrate. Each pixel unit includes a pixel electrode and a thin-film transistor (TFT) as a switching unit. The gate of each TFT is connected to a corresponding gate line, and one of the source and drain of each TFT is connected to a corresponding data line, while the other is connected to the pixel electrode. A liquid crystal capacitor or electrophoretic capsule is formed between the pixel electrode and the common electrode to display different gray levels according to the applied voltage.

[0025] Multiple gate lines extend along a first direction, and the gate of each row of pixel units is electrically connected to one gate line.

[0026] Specifically, multiple gate lines extend parallel to each other along a first direction (e.g., row direction X). The gates of all thin-film transistors in each row of pixel cells are connected to the same gate line.

[0027] Multiple data lines extend along a second direction that intersects with the first direction.

[0028] Specifically, multiple data lines extend parallel to a second direction (e.g., column direction Y) that intersects the first direction. The source (or drain) of the thin-film transistor in each column of pixel cells is connected to the same data line.

[0029] At least one driver chip is disposed on or outside the first substrate, and the driver chip includes multiple source output pins.

[0030] Specifically, the driver chip can be directly bonded to the first substrate using a COG (Chip On Glass) method, or it can be connected to the panel via a flexible printed circuit board (FPC). The driver chip integrates a gate driver unit and a source driver unit. The source driver unit has multiple source output pins for outputting data voltage signals.

[0031] The multiplexing circuit is integrated on the first substrate.

[0032] The multiplexing circuit includes multiple switch unit groups, each of which is electrically connected to a corresponding source output pin.

[0033] Each switch unit group includes at least two switch units. The control terminal of each switch unit is used to receive an independent strobe signal. The first conducting terminal of all switch units in the same switch unit group is connected to the corresponding source output pin, while the second conducting terminal of each switch unit is connected to a different data line.

[0034] In this embodiment, each switching unit is a thin-film transistor; the gate of the thin-film transistor serves as the control terminal, and the source and drain of the thin-film transistor serve as the first conduction terminal and the second conduction terminal, respectively.

[0035] Specifically, at least two data lines connected to the same source output pin are arranged at equal intervals along the second direction on the display panel.

[0036] In this embodiment, the column numbers of the data lines connected to the same source output pin form an arithmetic sequence.

[0037] Specifically, the common difference of an arithmetic sequence is equal to the number of switching units connected to the same source output pin.

[0038] The multiplexing circuit is configured to provide data voltage signals to at least two data lines in a time-division multiplexing manner by sequentially providing the corresponding gating signals to each switch unit in the same switch unit group.

[0039] It should be noted that this multiplexing circuit is integrated on the first substrate (e.g., fabricated in the non-display area of ​​the panel or integrated at the edge of the display area). See reference. Figure 2The multiplexing circuit includes multiple switch unit groups. Each switch unit group is electrically connected to a corresponding source output pin of the driver chip.

[0040] Specifically, each switch unit group includes M switch units, where M is a positive integer greater than 1.

[0041] In this embodiment, each switching unit is also a thin-film transistor. Each switching unit has a control terminal (gate), a first conducting terminal (source), and a second conducting terminal (drain). The key connection is that the first conducting terminals (sources) of all M switching units in the same switching unit group are shorted together and connected to a corresponding source output pin; while the second conducting terminal (drain) of each switching unit is independently connected to a different data line.

[0042] like Figure 1 As shown, in the conventional active-matrix electronic paper display panel driving architecture, each data line typically needs to be directly connected to an independent output pin of the source driver chip (SourceIC). Assuming a source driver chip has 240 output pins, then to drive a display panel with a horizontal resolution of 720 columns and a vertical resolution of 6 rows, a total of 3 source driver chips are required (720 ÷ 240 = 3). This one-to-one connection method causes the number of driver chips to increase linearly with resolution, becoming a major component of system cost.

[0043] For example, such as Figure 2 and Figure 3 As shown, a multiplexed circuit consisting of multiple thin-film transistor (TFT) switches is integrated between each source output pin of the source driver chip and multiple data lines on the panel. Specifically, for a given source output pin (e.g., S1), it is connected to M data lines via a switch unit group (M=3 in the illustration). This switch unit group contains M TFT switches (T1, T2, T3), whose sources are all connected to the source output pin S1, while their drains are connected to the 1st, 4th, 7th... columns of data lines respectively (i.e., the column numbers are arranged in an arithmetic sequence with a common difference of M). The gate of each TFT switch receives an independent gating signal (MUX1, MUX2, MUX3).

[0044] Reference Figures 1-3 The present invention provides an electronic paper display device, comprising an electronic paper display panel as described in any of the above claims.

[0045] Refer to Figures 2-4 The present invention proposes a driving method for an electronic paper display panel, comprising the following steps: S1. Provide a gate enable voltage to the currently selected row of gate lines to turn on all pixel units corresponding to that row of gate lines; S2. Provide a first strobe signal to a switching unit in a multiplexing circuit to connect a source output pin to a first target data line and provide a first data voltage to the first target data line through the source output pin; S3. After stopping the first strobe signal, provide a second strobe signal to another switching unit in the multiplexing circuit so that the source output pin is connected to the second target data line and the second data voltage is provided to the second target data line through the source output pin; S4. Repeat the same steps as step S3, sequentially providing the k-th strobe signal and driving the corresponding k-th target data line until all target data lines connected to the source output pin are driven, where k is an integer greater than 2; S5. After completing the driving of all target data lines in the current row, move to the next row of gate lines and repeat steps S1 to S4.

[0046] In this embodiment, the column numbers of the first target data line, the second target data line, and the kth target data line form an arithmetic sequence; the common difference of the arithmetic sequence is equal to the number of switching units connected to the source output pin.

[0047] In this embodiment, the effective pulse width of the gate turn-on voltage covers the entire period from the provision of the first strobe signal to the completion of driving all target data lines corresponding to the source output pin.

[0048] In this embodiment, the first gating signal, the second gating signal, and the kth gating signal are pulse signals provided sequentially and do not overlap in time.

[0049] Example 1: like Figure 2 and Figure 3 As shown, the process of driving a row of pixels using a specific group of switching units (corresponding to source output pin S1, including switching units T1, T2, and T3) is illustrated below: Row selection stage: During time period t0, the gate drive circuit provides a high-level gate enable voltage to the first row gate line G1, causing the switching transistors of all pixels in that row to be turned on.

[0050] First subframe driving phase: like Figure 3As shown, a high level is provided to the gating control signal line MUX1 simultaneously with (or after) G1 being turned on. At this time, TFT switch T1 is turned on, and the source output pin S1 is connected to the first column of data lines through T1. The source driver chip outputs the first set of data voltages corresponding to the target gray levels of the 1st, 4th, 7th... columns of pixels through the S1 pin, charging the LC of these pixel units.

[0051] Second subframe driving phase: During time period t1, MUX1 is pulled low to turn off T1, while MUX2 is pulled high to turn on T2. ​​At this time, pin S1 is connected to the second column data line through T2. The source driver chip outputs the second set of data voltages corresponding to the 2nd, 5th, 8th... columns of pixels through S1.

[0052] Subsequent subframe driving phase: During time period t2, MUX2 is pulled low while MUX3 is pulled high to enable T3. Pin S1 is connected to the third column data line through T3 and outputs the third set of data voltages corresponding to the 3rd, 6th, 9th... columns of pixels.

[0053] like Figure 3 As shown, the first strobe signal MUX1, the second strobe signal MUX2, and the third strobe signal MUX3 are pulse signals provided sequentially and without temporal overlap. This process continues until all M target data lines connected to the source output pin S1 have been driven. In this embodiment, M is 3 lines.

[0054] Timing correlation and row switching: After driving all columns in the first row, in the next cycle, the gate driving circuit provides an enable voltage to the gate line G2 of the second row, and similarly provides MUX1, MUX2, and MUX3 strobe signals in sequence to drive the pixels in each column of that row.

[0055] Through the timing process described above, where "one source pin drives M columns of data in a time-division multiplexing manner within one row," a system that originally required N source driver chips can theoretically achieve the same resolution driving with only about N / M chips. In this embodiment (M=3), driving 720 columns requires only one source driver chip with 240 output pins, saving 2 / 3 of the number of chips compared to the traditional solution, thereby reducing hardware costs.

[0056] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. An electronic paper display panel, characterized in that, include: First substrate; Multiple pixel units are arranged in an array on a first substrate, and each pixel unit includes a pixel electrode. Multiple gate lines extend along a first direction, and the gate of each row of pixel units is electrically connected to one gate line; Multiple data lines extend along a second direction that intersects with the first direction; At least one driver chip is disposed on or outside the first substrate, and the driver chip includes a plurality of source output pins; Multiplexing circuitry is integrated on the first substrate; The multiplexing circuit includes multiple switch unit groups, each switch unit group being electrically connected to a corresponding source output pin; Each switch unit group includes at least two switch units. The control terminal of each switch unit is used to receive an independent gating signal. The first conducting terminals of all switch units in the same switch unit group are connected to the corresponding source output pin, while the second conducting terminal of each switch unit is connected to a different data line. The multiplexing circuit is configured to provide a source output pin with a data voltage signal to at least two data lines in a time-division multiplexing manner by sequentially providing the corresponding gating signal to each switch unit in the same switch unit group.

2. The electronic paper display panel according to claim 1, characterized in that, Each switching unit is a thin-film transistor; the gate of the thin-film transistor serves as the control terminal, and the source and drain of the thin-film transistor serve as the first conduction terminal and the second conduction terminal, respectively.

3. The electronic paper display panel according to claim 1, characterized in that, At least two data lines connected to the same source output pin are arranged at equal intervals along a second direction on the display panel.

4. The electronic paper display panel according to claim 3, characterized in that, The column numbers of the data lines connected to the same source output pin form an arithmetic sequence.

5. The electronic paper display panel according to claim 4, characterized in that, The common difference of the arithmetic sequence is equal to the number of switching units connected to the same source output pin.

6. An electronic paper display device, characterized in that, Includes an electronic paper display panel as described in any one of claims 1 to 5.

7. A driving method for an electronic paper display panel, characterized in that, Includes the following steps: S1. Provide a gate enable voltage to the currently selected row of gate lines to turn on all pixel units corresponding to that row of gate lines; S2. Provide a first strobe signal to a switching unit in a multiplexing circuit to connect a source output pin to a first target data line and provide a first data voltage to the first target data line through the source output pin; S3. After stopping the first strobe signal, provide a second strobe signal to another switching unit in the multiplexing circuit so that the source output pin is connected to the second target data line and the second data voltage is provided to the second target data line through the source output pin; S4. Repeat the same steps as step S3, sequentially providing the k-th strobe signal and driving the corresponding k-th target data line until all target data lines connected to the source output pin are driven, where k is an integer greater than 2; S5. After completing the driving of all target data lines in the current row, move to the next row of gate lines and repeat steps S1 to S4.

8. The driving method for an electronic paper display panel according to claim 7, characterized in that, The column numbers of the first target data line, the second target data line, and the kth target data line form an arithmetic sequence; the common difference of the arithmetic sequence is equal to the number of switching units connected to the source output pin.

9. The driving method for an electronic paper display panel according to claim 7, characterized in that, The effective pulse width of the gate turn-on voltage covers the entire period from the provision of the first strobe signal to the completion of driving all target data lines corresponding to the source output pin.

10. The driving method for an electronic paper display panel according to claim 7, characterized in that, The first gating signal, the second gating signal, and the kth gating signal are pulse signals provided sequentially and do not overlap in time.

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