Semiconductor device and method of forming the same

Abstract

Embodiments of the present invention provide a semiconductor device comprising: a first semiconductor die including a plurality of first transistors, wherein each first transistor has a first gate component; and a second semiconductor die coupled to the first semiconductor die via a plurality of bump structures, including a plurality of second transistors, wherein each of the plurality of second transistors has a second gate component smaller than the first gate component. At least a subset of the plurality of first transistors is operably used as one or more power switches, configured to receive a first power supply voltage and electrically couple the first power supply voltage to the subset of the plurality of second transistors for a period of time. Embodiments of the present invention also provide a method for forming the semiconductor device.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of semiconductors, and more specifically, to semiconductor devices and methods of forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from the iterative reduction in the smallest feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0003] An embodiment of the present invention provides a semiconductor device comprising: a first semiconductor die including a plurality of first transistors, wherein the plurality of first transistors have first gate components; and a second semiconductor die coupled to the first semiconductor die via a plurality of bump structures and including a plurality of second transistors, wherein each of the plurality of second transistors has a second gate component smaller than the first gate component; wherein at least a subset of the plurality of first transistors is operably used as one or more power switches, configured to receive a first power supply voltage and electrically couple the first power supply voltage to the plurality of second transistors for a period of time.

[0004] Another embodiment of the present invention provides a semiconductor device comprising: a first semiconductor die including a plurality of first transistors, wherein the plurality of first transistors are constructed using a first transistor structure; and a second semiconductor die coupled to the first semiconductor die and including a plurality of second transistors, wherein the plurality of second transistors are all constructed using a second transistor structure; wherein at least a subset of the plurality of first transistors is configured to receive a first power supply voltage and electrically couple the first power supply voltage to the second transistors of the plurality of subsets for a time period satisfying a threshold.

[0005] Another embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming a plurality of first transistors on a first semiconductor die, each first transistor having a first gate component, wherein the plurality of first transistors are configured to receive a power supply voltage; forming a plurality of second transistors on a second semiconductor die, each second transistor having a second gate component smaller than the first gate component, wherein a subset of the plurality of second transistors is configured to receive a power supply voltage from a subset of the first transistors for a period of time; and bonding the first semiconductor die to the second semiconductor die via a plurality of bump structures. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 An example block diagram of a memory circuit according to some embodiments is shown.

[0008] Figure 2 Illustrations are shown according to some embodiments Figure 1 A schematic diagram illustrating an example of a memory cell included in a memory circuit.

[0009] Figure 3 Illustrations are shown according to some embodiments Figure 1 Example block diagram of a memory circuit.

[0010] Figure 4 Illustrations are shown according to some embodiments Figure 1 Another example block diagram of a memory circuit.

[0011] Figure 5 The following are examples of implementations based on... Figure 3 A block diagram illustrating an example of a memory circuit implemented across multiple semiconductor dies.

[0012] Figure 6 The following are examples illustrating the implementation of some embodiments. Figure 5 A schematic diagram illustrating an example of a bump structure formed on a semiconductor die.

[0013] Figure 7 The following are examples of implementations based on... Figure 4 A block diagram illustrating an example of a memory circuit implemented across multiple semiconductor dies.

[0014] Figure 8 The following are examples illustrating the implementation of some embodiments. Figure 7 A schematic diagram illustrating an example of a bump structure formed on a semiconductor die.

[0015] Figure 9 Illustrations are shown according to some embodiments Figure 1 Example circuit diagram of the power switch for a memory circuit.

[0016] Figure 10 The following are examples of implementations based on... Figure 3 This is another example of a block diagram implementation of a memory circuit formed across multiple semiconductor dies.

[0017] Figure 11 An example flowchart of a method for manufacturing memory circuits across multiple dies according to some embodiments is shown. Detailed Implementation

[0018] This invention provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0020] As the pace of advancement towards next-generation nodes accelerates, system input / output (I / O) requirements typically involve transferring signals between integrated circuit dies and connections to components with high capacitance (such as connections associated with printed circuit board traces, cables, etc.). This requires significantly greater drive power and voltage than the signal conduction occurring within the integrated circuit die itself. I / O devices interface faster, smaller signals from the main die to these other, higher-capacitance components, typically transferring signals at higher voltages. As a non-limiting example, memory circuitry (e.g., fuse memory circuitry or one-time programmable (OTP) memory circuitry) often relies on I / O circuitry to provide high voltages for operations of the memory circuitry (e.g., programming, erasing, etc.).

[0021] A voltage supply circuit (sometimes called a power switch) is one of various such I / O circuits operatively coupled to memory circuitry to provide the required operating voltage (e.g., a relatively high operating voltage). Such a power switch typically includes a level shifter that generally shifts the level of the supply voltage from one voltage domain to another. For example, when the memory cells of the memory circuitry are configured in a programmed mode, the power switch typically provides an operating voltage to the memory cells that is shifted from a first supply voltage to a second supply voltage; in other words, from a lower voltage domain to a higher voltage domain. Generally, the power switch continuously receives the higher supply voltage and provides that higher supply voltage to the memory cells as needed.

[0022] However, as memory cells advance to next-generation technology nodes, manufacturing power switches capable of continuously receiving (or "withstanding") high supply voltages can become problematic. For example, in advanced technology nodes, semiconductor dies or wafers tend to have all their transistors formed on a single (e.g., short) gate length. In other words, all transistors on a single die can be configured with small dimensions, allowing them to tolerate relatively low operating voltages. Several approaches have been proposed in this regard, such as stacking multiple such transistors with small dimensions. However, the overall circuit design tends to become complex. For example, for all transistors formed in a stacked structure (multiple transistors coupled in series with each other), one or more additional voltage-providing circuits are generally required in the memory circuitry to provide components of the high supply voltage. Furthermore, the total area occupied by such stacked transistors (and additional circuitry) tends to become unfavorably large. Therefore, existing memory circuitry is not entirely satisfactory in some respects.

[0023] This disclosure provides various embodiments of memory circuits fabricated across multiple semiconductor dies bonded together, each of which may have transistors forming one or more corresponding gate lengths. In some embodiments, a first of the multiple semiconductor dies may have its transistor (first transistor) formed in a FinFET structure or a planar transistor structure, and a second of the multiple semiconductor dies may have its transistor (second transistor) formed in a gate-all-around (GAA) transistor structure or any other advanced transistor structure (e.g., a complementary field-effect transistor structure). Further, the first transistor may have one or more first gate features, while the second transistor may have a single second gate feature, wherein the second gate feature is substantially shorter than any of the one or more first gate features. In this document, the term "gate feature" may refer to a physical dimension of one or more gate components in a gate structure. For example, such a physical dimension may include, for example, the gate length of a (e.g., metal) gate structure, the physical thickness of a gate dielectric layer, and the effective thickness of the gate dielectric layer. Generally, the gate length of a transistor refers to the length of the gate structure of the transistor extending from the source structure of the transistor to the drain structure of the transistor.

[0024] In one aspect of this disclosure, the memory circuit may include a power switch formed by a first transistor (or formed on a first semiconductor die) and all other circuitry, including memory cells, formed by a second transistor (or formed on a second semiconductor die). With this configuration, the memory circuit can operate at substantially high operating (supply) voltages without requiring the memory cells to be formed in a stacked structure. In another aspect of this disclosure, the memory circuit may include a power switch and memory cells formed by a first transistor (or formed on a first semiconductor die) and all other circuitry formed by a second transistor (or formed on a second semiconductor die). With this configuration, the density of memory cells can be significantly increased because memory cells can be formed without a stacked structure.

[0025] Figure 1 A memory circuit 100 according to various embodiments is shown. Figure 1 In the illustrated embodiment, the memory circuit 100 includes a memory array 102, row circuits 104, column circuits 106, input / output (I / O) circuits 108, and control logic circuits 110. Although Figure 1 Not shown, but components in memory circuitry 100 are operably coupled to each other and to control logic circuitry 110. Although for clarity, in Figure 1 The components are displayed as separate squares, but in some other embodiments, Figure 1 Some or all of the components shown can be integrated together. For example, I / O circuitry 108 can be embedded (or integrated) into memory array 102.

[0026] Memory array 102 is a hardware component for storing data. In one aspect, memory array 102 is embodied as a semiconductor memory device. Memory array 102 includes a plurality of memory cells (or other storage cells) 103. Memory array 102 includes a plurality of rows R1, R2, R3, ..., RM, each row extending in a first direction (e.g., the X direction); and a plurality of columns C1, C2, C3, ..., CN, each column extending in a second direction (e.g., the Y direction). Each of the rows / columns may include one or more conductive structures. In some embodiments, each memory cell 103 is disposed at the intersection of a corresponding row and a corresponding column and is operable according to the voltage or current via the corresponding conductive structures of the row and column.

[0027] According to various embodiments of this disclosure, each memory cell 103 may be implemented as a one-time programmable (OTP) memory cell. For example, memory cell 103 may be an efuse cell, which includes at least a series-coupled fuse resistor and an access transistor. However, it should be understood that memory cell 103 may be implemented as any of a variety of other memory configurations, such as static random access memory (SRAM) cells, phase-change random access memory (PCRAM) cells, resistive random access memory (RRAM) cells, magnetoresistive random access memory (MRAM) cells, etc., while still within the scope of this disclosure. Reference will be made below. Figure 2 A detailed description of the memory cell 103 configured as an efuse cell is provided.

[0028] Row circuit 104 is a hardware component that receives the row address of memory array 102 and asserts a conductive structure (e.g., word line) at that row address. Column circuit 106 is a hardware component that receives the column address of memory array 102 and asserts one or more conductive structures (e.g., bit lines, source lines) at that column address. I / O circuit 108 is a hardware component that can access (e.g., read, programmable) each of the memory cells 103 asserted via row circuit 104 and column circuit 106. Control logic circuit 110 is a hardware component that can control the coupled components (e.g., 102 to 108).

[0029] Figure 2 A memory cell 103 configured as an efuse cell (hereinafter referred to as "efuse cell 103") according to some embodiments is shown. Figure 1Example configuration of efuse unit 103. efuse unit 103 is implemented as a 1T1R configuration, for example, where fuse resistor 202 is connected in series with access transistor 204. However, it should be understood that efuse unit 103 may also use any of a variety of other fuse configurations exhibiting fuse characteristics, such as, for example, a 2-diodes-1-resistor (2D1R) configuration, a many-transistors-one-resistor (manyT1R) configuration, etc., while still within the scope of this disclosure.

[0030] The fuse resistor 202 is formed of one or more metal structures. For example, the fuse resistor 202 may be one of many interconnect structures in one of many metallization layers disposed above the access transistor 204. The access transistor 204 may be formed above the main surface of a semiconductor substrate, which is sometimes referred to as a portion of the front-end processing (FEOL) process. Above the FEOL process, a number of metallization layers are typically formed, each of which includes a number of interconnect (e.g., metal) structures, sometimes referred to as a portion of the back-end processing (BEOL) process.

[0031] As the fuse resistor 202 (of efuse cell 103) is embodied as a metallic structure, the fuse resistor 202 can exhibit, for example, an initial resistance value (or resistivity) at the time of manufacture. To program efuse cell 103, access transistor 204 (if embodied as an n-type transistor) is turned on by applying a signal corresponding to a logic high state (e.g., a voltage) to the gate terminal of access transistor 204 via the word line (WL). Simultaneously or subsequently, a sufficiently high voltage (e.g., a programmed voltage) is applied to one of the terminals of fuse resistor 202 via the bit line (BL). As access transistor 204 is turned on to provide an (e.g., programmed) path from BL through resistor 202 and transistor 204 to the source line (SL), such a high voltage signal can burn out a portion of the corresponding metallic structure (fuse resistor 202), thereby transitioning fuse resistor 202 from a first state (e.g., short-circuited) to a second state (e.g., open-circuited). Therefore, the efuse unit 103 can irreversibly transition from a first logic state (e.g., logic 0) to a second logic state (e.g., logic 1), which can be read out by applying a relatively low voltage signal to BL and turning on the access transistor 204 to provide (e.g., read) a path.

[0032] In some embodiments of this disclosure, the power switch of the I / O circuit 108 formed on the first semiconductor die can continuously withstand (or receive) such a high programmed voltage for a period of time, and selectively apply programmed voltages to the efuse cells 103 formed on the second semiconductor die. As the memory array 102 includes multiple (e.g., 4K, 16K, 64K, etc.) efuse cells 103, the time periods applied to each efuse cell 103 can be accumulated. The total number of such time periods for which programmed voltages are applied to the memory array 102 can be a factor in determining whether the access transistors 204 of the efuse cells 103 should be formed in a stacked structure. A stacked structure generally refers to multiple transistors coupled in series with each other. For example, if the total time period is less than or equal to a threshold (e.g., approximately 0.5 seconds for a 16K memory array), the access transistors 204 may not be formed in a stacked structure; on the other hand, if the total time period is longer than this threshold, the access transistors 204 may be formed in a stacked structure. Thus, it can be understood that such a threshold can vary depending on the size of the memory array (e.g., the number of memory cells it includes). In some other embodiments of this disclosure, the efuse unit 103 (including its corresponding access transistor and resistor) may be formed on the first semiconductor die, and is the same as the power switch of the I / O circuit 108.

[0033] Figure 3 and Figure 4 Example block diagrams of memory circuitry 100 according to some embodiments are shown. As a brief overview, Figure 3 The block diagram points to an embodiment that does not implement a stacking structure; Figure 4 The block diagram points to an embodiment implementing the stacked structure. It should be understood that, for illustrative purposes, Figures 3 to 4 The block diagrams have been simplified and are not intended to limit the scope of this disclosure. Therefore, each of the block diagrams may include any of a variety of other suitable components (e.g., level shifters) while still being within the scope of this disclosure.

[0034] First refer to Figure 3 The memory circuit 100 includes a power switch 310, a header circuit 320, a BL selection circuit (or sometimes called BL SEL) 330, a WL selection circuit (or sometimes called WL SEL) 340, a sensing amplifier circuit (or sometimes called SA) 350, and a memory array 360. The memory array 360 may correspond to the memory array 102 ( Figure 1 WL selection circuit 340 can correspond to row circuit 104 ( Figure 1 ); BL selection circuit 330 can correspond to column circuit 106 ( Figure 1The power switch 310, head circuit 320, and sensing amplifier circuit 350 can correspond to the I / O circuit 108. Figure 1 ).

[0035] In some embodiments, the power switch 310 may receive a programmed or supplied voltage (VQPS) and, based on control signals PD and PS, selectively couple VQPS as an operating voltage (VDDQ) to the memory array 360 via the BL selection circuit 330. The following will... Figure 9 The circuit diagram of power switch 310 is described below. Similarly, head circuit 320 can receive supply voltage (VDD) and selectively couple VDD as another operating voltage (VDDHD) to sense amplifier circuit 350 and WL selection circuit 340 based on control signal PD. As a non-limiting example, both control signal PD and control signal PS are provided with a logic low state (i.e., PD=0 and PS=0) to read memory array 360, or to read when memory array 360 is configured in read mode; control signal PD and control signal PS are provided with a logic low state and a logic high state (i.e., PD=0 and PS=1) respectively to program (or write) memory array 360, or to program (or write) memory array 360 when memory array 360 is configured in programmable mode; and control signal PD and control signal PS are provided with a logic high state and a logic low state (i.e., PD=1 and PS=0) respectively to power off memory array 360.

[0036] According to some embodiments, a power switch 310 may be formed on a first semiconductor die 510, while a header circuit 320, a BL selection circuit 330, a WL selection circuit 340, a sensing amplifier circuit 350, and a memory array 360 may be formed on a second semiconductor die 520, such as... Figure 5 As shown. The power switch 310, head circuit 320, BL selection circuit 330, WL selection circuit 340, sensing amplifier circuit 350, or memory array 360 may not be formed in a stacked structure. For example... Figure 6 As shown, the first semiconductor die 510 and the second semiconductor die 520 can be joined to each other via a plurality of bump structures.

[0037] On the first semiconductor die 510, transistors (some of which can be operatively used as power switches 310) may be formed with relatively large gate portions (e.g., long gate lengths) or in a transistor structure that allows the transistors to operate at relatively high operating voltages (e.g., around 1.8V VQPS). On the second semiconductor die 520, transistors (some of which can be operatively used as header circuitry 320, BL select circuitry 330, WL select circuitry 340, sense amplifier circuitry 350, and memory array 360) may be formed with relatively small gate portions (e.g., short gate lengths) or in another transistor structure that allows the transistors to operate at relatively low operating voltages (e.g., around 0.75V VDD) or at VQPS for relatively short periods of time (e.g., less than 0.5 seconds).

[0038] Next, refer to Figure 4 The memory circuit 100 includes a first power switch 410, a head circuit 420, a BL selection circuit 430, a WL selection circuit 440, a sensing amplifier circuit 450, a memory array 460, one or more fractional voltage generators 470, and a second power switch 480. The memory array 460 may correspond to the memory array 102 ( Figure 1 WL selection circuit 440 can correspond to row circuit 104 ( Figure 1 ); BL selection circuit 430 can correspond to column circuit 106 ( Figure 1 ); and the first power switch 410, head circuit 420, sensing amplifier circuit 450, fractional voltage generator 470, and second power switch 480 can correspond to I / O circuit 108 ( Figure 1 ).

[0039] In some embodiments, the power switch 410 may receive a programmed or supplied voltage (VQPS) and, based on control signals PD and PS, selectively couple VQPS as an operating voltage (VDDQ) to the memory array 460 via the BL selection circuit 430. The following will... Figure 9The example circuit diagram of power switch 410 is described below. Similarly, head circuit 420 can receive supply voltage (VDD) and selectively couple VDD as another operating voltage (VDDHD) to sense amplifier circuit 450 and WL selection circuit 440 based on control signal PD. As a non-limiting example, both control signal PD and control signal PS are provided with a logic low state (i.e., PD=0 and PS=0) to read memory array 460, or to read when memory array 460 is configured in read mode; control signal PD and control signal PS are provided with a logic low state and a logic high state (i.e., PD=0 and PS=1) respectively to program (or write) memory array 460, or to program (or write) memory array 460 when memory array 460 is configured in programmable mode; and control signal PD and control signal PS are provided with a logic high state and a logic low state (i.e., PD=1 and PS=0) respectively to power off memory array 460.

[0040] Furthermore, the fractional voltage generator 470 can generate corresponding fractions of VQPS (e.g., 1 / 2 × VQPS, 1 / 3 × VQPS, and 2 / 3 × VQPS) and selectively provide the fractional voltages to at least the BL selection circuit 430, the WL selection circuit 440, the sense amplifier circuit 450, and the memory array 460 via a second power switch 480. These circuits can be formed in a stacked structure. The value of the fraction can be determined based on the number of stacked transistors. For example, in a stacked structure with two transistors in series, the fraction is equal to 1 / 2 (e.g., 1 / 2 × VQPS). In another instance of a stacked structure with three transistors in series, the fraction is equal to 1 / 3 or 2 / 3 (e.g., 1 / 3 × VQPS, 2 / 3 × VQPS).

[0041] According to some embodiments, a power switch 410 not in a stacked structure may be formed on the first semiconductor die 710, while a header circuit 420, BL selection circuit 430, WL selection circuit 440, sensing amplifier circuit 450, memory array 460, fractional voltage generator 470, and second power switch 480 in a stacked structure may be formed on the second semiconductor die 720, such as... Figure 7 As shown. Figure 8 As shown, the first semiconductor die 710 and the second semiconductor die 720 can be joined to each other via a plurality of bump structures.

[0042] On the first semiconductor die 710, transistors (some of which can be operatively used as power switches 410) may be formed with relatively large gate portions (e.g., long gate lengths) or in a transistor structure that allows the transistors to operate at relatively high operating voltages (e.g., around 1.8V VQPS). On the second semiconductor die 720, transistors (some of which can be operatively used as header circuitry 420, BL select circuitry 430, WL select circuitry 440, sense amplifier circuitry 450, memory array 460, fractional voltage generator 470, and second power switch 480) may be formed with relatively small gate portions (e.g., short gate lengths) or in another transistor structure that allows each of the stacked transistors to operate at a relatively low operating voltage (e.g., around 0.75V VDD) or allows the stacked transistors to operate together at VQPS for a relatively long period of time (e.g., greater than 0.5 seconds).

[0043] In particular, Figure 6 In this embodiment, the first semiconductor die 510 and the second semiconductor die 520 are joined together by a plurality of bump structures. The first semiconductor die 510 and the second semiconductor die 520, sometimes referred to as the top die and the bottom die, can be joined together via suitable bonding techniques, such as, for example, hybrid bonding, microbumping, direct bonding, chemically activated bonding, plasma-activated bonding, anodic bonding, eutectic bonding, glass powder bonding, adhesive bonding, thermoforming bonding, reactive bonding, etc. Various electrical connections can be provided between the first semiconductor die 510 and the second semiconductor die 520 via these bump structures.

[0044] For example, in the bump structure, a first (top) semiconductor die 510 (or its bottom surface) may accommodate at least a plurality of bump structures 610, a plurality of bump structures 620, and a plurality of bump structures 630; a second (bottom) semiconductor die 550 (or its top surface) may accommodate at least a plurality of bump structures 660, a plurality of bump structures 670, a plurality of bump structures 680, and a plurality of bump structures 690. In some embodiments, bump structures 610 may be respectively bonded to bump structure 660, thereby allowing a power switch 310 formed on the first semiconductor die 510 to transmit VQPS at least to a column select circuit 330 formed on the second semiconductor die 520. In some embodiments, bump structures 620 may be respectively bonded to bump structure 670, thereby allowing a control signal PS to communicate between the two semiconductor dies. In some embodiments, bump structures 630 may be respectively bonded to bump structure 680, thereby allowing a control signal PD to communicate between the two semiconductor dies. In some embodiments, the bump structure 690 formed on the top surface of the second semiconductor die 520 at least allows the head circuit 320 formed on the second semiconductor die 520 to receive VDD.

[0045] In particular, Figure 8 In this embodiment, the first semiconductor die 710 and the second semiconductor die 720 are joined together by a plurality of bump structures. The first semiconductor die 710 and the second semiconductor die 720, sometimes referred to as the top die and the bottom die, can be joined together via suitable bonding techniques, such as, for example, hybrid bonding, microbumping, direct bonding, chemically activated bonding, plasma-activated bonding, anodic bonding, eutectic bonding, glass powder bonding, adhesive bonding, thermoforming bonding, reactive bonding, etc. Various electrical connections can be provided between the first semiconductor die 710 and the second semiconductor die 720 via these bump structures.

[0046] For example, in the bump structure, a first (top) semiconductor die 710 (or its bottom surface) may accommodate at least a plurality of bump structures 810, a plurality of bump structures 820, and a plurality of bump structures 830; and a second (bottom) semiconductor die 750 (or its top surface) may accommodate at least a plurality of bump structures 860, a plurality of bump structures 870, a plurality of bump structures 880, a plurality of bump structures 890, and a plurality of bump structures 895. In some embodiments, bump structures 810 may be respectively bonded to bump structures 860, thereby allowing a power switch 410 formed on the first semiconductor die 710 to transmit VQPS at least to a column select circuit 430 formed on the second semiconductor die 720. In some embodiments, bump structures 820 may be respectively bonded to bump structures 870, thereby allowing a control signal PS to communicate between the two semiconductor dies. In some embodiments, bump structures 830 may be respectively bonded to bump structures 880, thereby allowing a control signal PD to communicate between the two semiconductor dies. In some embodiments, the bump structure 890 formed on the top surface of the second semiconductor die 720 allows at least the head circuit 420 formed on the second semiconductor die 720 to receive VDD. In some embodiments, the bump structure 895 formed on the top surface of the second semiconductor die 720 allows at least one or more fractional voltage generators 470 formed on the second semiconductor die 720 to receive VQPS.

[0047] Figure 9 A power switch 900 according to some embodiments is shown (e.g., Figure 3 Power switch 310 Figure 4 An example circuit diagram of power switch 410 is provided. Power switch 900 can provide an operating voltage (e.g., VDDQ) configured for programming a plurality of memory cells (e.g., efuse cell 103). Power switch 900 can provide an operating voltage VDDQ offset from a first voltage domain (e.g., from 0V to VDD) to a second voltage domain (e.g., from 0V to VQPS). Figure 9In some examples, the power switch 900 is not formed in a stacked structure, or is formed on a semiconductor die, thereby allowing the formation of multiple gate lengths, relatively long gate lengths, and / or I / O transistors. However, it should be understood that the power switches described above (e.g., 310, 410) are not limited to not being formed in a stacked structure.

[0048] As shown in the figure, the power switch 900 includes an inverter 902, a NAND gate 904, an inverter 906, a level shifter 908, an odd number of inverters 910, a pull-up transistor 912, and a pull-down transistor 914. In some embodiments, the inverter 902, NAND gate 904, and inverter 906 can operate in a first voltage domain (e.g., between 0V and VDD, where VDD can be around 0.75V); the inverter 910, pull-up transistor 912, and pull-down transistor 914 can operate in a second voltage domain (e.g., between 0V and VQPS, where VQPS can be around 1.8V).

[0049] Inverter 902 can receive the control signal PD (e.g., via a first control pin) and provide the inverted control signal PD to one of the inputs of NAND gate 904. NAND gate 904 can also receive the control signal PS (e.g., via a second control pin) and perform a NAND operation on the inverted control signal PD and the control signal PS to provide signal 905 (psvq). Control signals PD and PS with corresponding logic states can be provided in a first voltage domain. For example, when configured in a logic high state, control signals PD / PS are provided at 0.75V; and when configured in a logic low state, control signals PD / PS are provided at 0V. Inverter 906 can invert signal 905 to signal 907 (psvqb). Level shifter 908 can receive signals 905 and 907 as a differential pair of input signals and offset signals 905 / 907 to provide signal 909 (pqb).

[0050] For example, when a level shifter 908 with a logic high state receives signal 907 (psvqb), level shifter 908 can provide signal 909 (pqb) with a logic high state, where signals 907 and 909 are approximately 0.75V and 1.8V respectively. Inverter 910 can provide signal 911 by inverting signal 909. Pull-up transistor 912 can make its gate terminal receive signal 911, and pull-down transistor 914 can make its gate terminal receive signal 911. Further, pull-up transistor 912 (which may be implemented as a p-type transistor) can make its source terminal connected to a second supply voltage VQPS, and pull-down transistor 914 (which may be implemented as an n-type transistor) can make its source terminal connected to ground voltage, where the corresponding drain terminals of transistors 912 and 914 are connected to each other at the output node to provide operating voltage VDDQ.

[0051] In read mode, both control signals PD and PS are logic low (i.e., PD=0 and PS=0). Thus, signal 907 input to level converter 908 is logic low, signal 909 output from level converter 908 is logic low, and signal 911 output from the odd number of inverters 910 is logic high. This allows transistors 912 and 914, which are operably used as inverters, to output an operating voltage VDDQ equal to approximately 0V via transistor 914. In programmable mode, control signals PD and PS are logic low and logic high, respectively (i.e., PD=0 and PS=1). Thus, signal 907 input to level converter 908 is in a logic high state, signal 909 output from level converter 908 is in a logic high state, and signal 911 output from odd number of inverters 910 is in a logic low state. This enables transistors 912 and 914, which are operable as inverters, to output an operating voltage VDDQ equal to approximately 1.8V (VQPS) via transistor 912.

[0052] Compared to Figures 5 to 8 The embodiment shown, Figure 10 Another embodiment of implementing memory circuit 100 is shown (e.g., based on...). Figure 3 (The block diagram). Therefore, it can be used again in the following discussion. Figure 3 Some reference figures. As shown in the figure, the power switch 310 and memory array 360 may be formed on the first semiconductor die 1010, while the header circuit 320, BL selection circuit 330, WL selection circuit 340, and sensing amplifier circuit 350 may be formed on the second semiconductor die 1020. The first semiconductor die 1010 and the second semiconductor die 1020 may be joined to each other via a plurality of bump structures.

[0053] remove Figure 3 , Figure 5 ,or Figure 10 In addition to the implementation in the first semiconductor die, the memory circuit 100 may also be implemented alternatively or additionally. For example, the first semiconductor die may house only one or more memory arrays (e.g., 360), while other circuit components (e.g., 310, 320, 330, 340, and 350) may be formed in the second semiconductor die, and the first semiconductor die and the second semiconductor die are joined to each other via a plurality of bump structures.

[0054] Figure 11 A flowchart of a method 1100 for forming a memory circuit according to one or more embodiments of the present disclosure is shown. The memory circuit includes different dies operably coupled to each other via a plurality of bump structures. For example, at least some operations (or steps) of method 1100 can be used to form the aforementioned memory circuit. It should be noted that method 1100 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that... Figure 11 Additional operations are provided before, during, and / or after Method 1100, and this document may only briefly describe some of these additional operations.

[0055] Method 1100 may begin with operation 1110, forming a plurality of first transistors on a first semiconductor die, each of the plurality of first transistors having a first gate length. In some embodiments, a subset of the plurality of first transistors is used to continuously receive a relatively high supply voltage. The first semiconductor die may be a first semiconductor substrate, such as a bulk silicon semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped.

[0056] On a first semiconductor substrate (die), a first transistor may be formed along the main surface of the first semiconductor substrate. The first transistor may have one or more first gate lengths. The first transistor may be formed as one or more of a FinFET structure or a planar transistor structure. In some embodiments, some of the first transistors may be operatively used as power switches for a memory circuit (e.g., 310, 410), which can sustainably withstand (or receive) relatively high supply voltages, for example, around 1.8V or higher VQPS. As described above (e.g., Figure 9 The power switch can be controlled by one or more control signals (e.g., PS, PD) to selectively couple a high supply voltage to other components of a memory circuit that can be formed on another semiconductor substrate.

[0057] Method 1100 may continue to operation 1120, forming a plurality of second transistors on a second semiconductor die, each of the plurality of second transistors having a second gate length shorter than the first gate length. In some embodiments, a subset of the plurality of second transistors is used to receive a supply voltage from a subset of the first transistors for a period of time. The second semiconductor die may be a second semiconductor substrate, such as a bulk silicon semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped.

[0058] On a second semiconductor substrate (die), a second transistor may be formed along the main surface of the second semiconductor substrate. The second transistor may be formed with a single second gate length, which is substantially shorter than any one of one or more first gate lengths. The second transistor may be formed as one or more of a GAA transistor structure or a complementary field-effect transistor structure. For example, the second transistor may be arranged with a uniform shorter gate length, while the first transistors may be arranged with multiple longer gate lengths. However, it should be understood that during manufacturing, the second transistor may still exhibit various gate lengths, for example, one or more of the various gate lengths may be longer than the gate length of the first transistor due to process variations. In some embodiments, some of the second transistors may be operatively used as header circuitry of a memory circuit (e.g., 320, 420), BL select circuitry (e.g., 330, 430), WL select circuitry (e.g., 340, 440), sense amplifier circuitry (e.g., 350, 450), memory array (e.g., 360, 460), fractional voltage generator (e.g., 470), or fractional voltage switch (e.g., 480). Each of these circuit components formed on the second semiconductor die allows its second transistor to withstand (or receive) a relatively low supply voltage, such as VDD around 0.75V, or to receive a high supply voltage (VQPS) for a period of time. Further, in some embodiments, if the estimated time period is equal to or shorter than a threshold, the second transistor may not be formed in a stacked structure. The threshold may be determined based on the size of the memory array. On the other hand, if the estimated time period is longer than the threshold, the second transistor may be formed in a stacked structure.

[0059] Method 1100 may continue to operation 1130, bonding the first semiconductor die to the second semiconductor die using multiple bump structures. These bump structures may each include solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using electroless nickel-palladium immersion gold (ENEPIG) technology, silicon / substrate vias, combinations thereof (e.g., metal pillars with attached solder balls), etc. As a result, a first transistor formed on the first semiconductor die can communicate with a second transistor formed on the second semiconductor die.

[0060] In one embodiment, the first semiconductor die and the second semiconductor die may be face-to-face (F2F) oriented and bonded to each other. For example, a BEOL process (which includes a plurality of first metallization layers) may be formed over the FEOL process of the first semiconductor die (in which the first transistor is formed). Similarly, a BEOL process (which includes a plurality of second metallization layers) may be formed over the FEOL process of the second semiconductor die (in which the second transistor is formed). A plurality of microbumps may be formed between the topmost of the first metallization layer and the topmost of the second metallization layer.

[0061] In another embodiment, the first semiconductor die and the second semiconductor die may be face-to-back (F2B) oriented and bonded to each other. For example, a BEOL process (including multiple first metallization layers) may be formed over the FEOL process of the first semiconductor die (in which the first transistor is formed). Similarly, a BEOL process (including multiple second metallization layers) may be formed over the FEOL process of the second semiconductor die (in which the second transistor is formed). A plurality of metal pillars (sometimes called silicon through-holes) may be formed to extend through the substrate of the second semiconductor die, thereby connecting at least the topmost of the first metallization layer.

[0062] In one aspect of this disclosure, a semiconductor device is disclosed. The semiconductor device includes a first semiconductor die comprising a plurality of first transistors, each of the plurality of first transistors having a first gate portion; and a second semiconductor die coupled to the first semiconductor die via a plurality of bump structures and including a plurality of second transistors, each of the plurality of second transistors having a second gate portion smaller than the first gate portion. At least a subset of the plurality of first transistors, operably functioning as one or more power switches, is configured to receive a first supply voltage for a time period and electrically couple the first supply voltage to a subset of the plurality of second transistors.

[0063] In some embodiments, the time period is equal to or shorter than a threshold. In some embodiments, each subset of the second transistors is partially operably used as a sense amplifier, level shifter, or memory cell, and wherein none of the subsets of the second transistors has a stacked structure. In some embodiments, the time period is longer than the threshold. In some embodiments, each subset of the second transistors is partially operably used as a sense amplifier, level shifter, or memory cell, and each of the subsets of the second transistors has a stacked structure. In some embodiments, each subset of the first transistors is constructed with a FinFET structure or a planar transistor structure, while each subset of the second transistors is constructed with a gate-all-around (GAA) transistor structure. In some embodiments, at least one of the bump structures is used to receive a control signal to control the time period. In some embodiments, at least one of the bump structures is used to receive a first supply voltage. In some embodiments, at least one of the bump structures is used to receive a second supply voltage supplying power to one or more of the subsets of the second transistors, the second supply voltage being lower than the first supply voltage. In some embodiments, some of the subsets of the second transistors are operably configured to form a memory array comprising a plurality of memory cells, each of the memory cells comprising a resistor series coupled to one or more of the second transistors. In some embodiments, a subset of the first transistors operatively forms a memory array comprising a plurality of memory cells, each of the memory cells including a resistor series coupled to an odd number of the first transistors.

[0064] In another aspect of this disclosure, a semiconductor device is disclosed. The semiconductor device includes a first semiconductor die comprising a plurality of first transistors, each of the plurality of first transistors being configured with a first transistor structure; and a second semiconductor die coupled to the first semiconductor die and comprising a plurality of second transistors, each of the plurality of second transistors being configured with a second transistor structure. At least a subset of the plurality of first transistors is configured to receive a first supply voltage for a time period satisfying a threshold, and electrically couple the first supply voltage to a subset of the plurality of second transistors.

[0065] In some embodiments, the time period is equal to or shorter than the threshold. In some embodiments, a subset of the first transistors is operatively used as one or more power switches, and each subset of the second transistors is operatively used as a sense amplifier, level shifter, or memory cell, wherein none of the subsets of the second transistors has a stacked structure. In some embodiments, the time period is longer than the threshold. In some embodiments, a subset of the first transistors is operatively used as one or more power switches, and each subset of the second transistors is operatively used as a sense amplifier, level shifter, or memory cell, wherein each of the subsets of the second transistors has a stacked structure. In some embodiments, the first transistor structure has one or more first gate lengths, and the second transistor structure has a single second gate length. In some embodiments, the second gate length is shorter than any one of the one or more first gate lengths.

[0066] In another aspect of this disclosure, a method of manufacturing a semiconductor device is disclosed. The method includes forming a plurality of first transistors on a first semiconductor die, each of the plurality of first transistors having a first gate component, wherein a subset of the plurality of first transistors is used to receive a supply voltage. The method includes forming a plurality of second transistors on a second semiconductor die, each of the plurality of second transistors having a second gate component smaller than the first gate component, wherein a subset of the plurality of second transistors is used to receive a supply voltage from a subset of the first transistors for a time period. The method includes bonding the first semiconductor die to the second semiconductor die using a plurality of bump structures.

[0067] In some embodiments, a subset of the first transistors is operatively used as one or more power switches, while each subset of the second transistors is operatively used in part as a sense amplifier, level shifter, or memory cell.

[0068] As used herein, the terms “about” and “approximately” generally indicate a given quantity of value that may vary depending on the specific technology node associated with the target semiconductor device. Based on a specific technology node, the term “about” may indicate a given quantity of value, for example, varying within 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0069] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: A first semiconductor die includes a plurality of first transistors, wherein the plurality of first transistors have a first gate component; and The second semiconductor die is coupled to the first semiconductor die via a plurality of bump structures and includes a plurality of second transistors, wherein each of the plurality of second transistors has a second gate component smaller than the first gate component; In this embodiment, at least a subset of the plurality of first transistors is operably used as one or more power switches, configured to receive a first power supply voltage and electrically couple the first power supply voltage to a subset of the plurality of second transistors during a time period.

2. The semiconductor device according to claim 1, wherein, The time period is configured to be equal to or shorter than the threshold.

3. The semiconductor device according to claim 2, wherein, Each subset of the second transistor is configured to be partially operable as a sense amplifier, level shifter, or memory cell, and none of the subsets of the second transistor has a stacked structure.

4. The semiconductor device according to claim 1, wherein, The time period is configured to be longer than the threshold.

5. The semiconductor device according to claim 4, wherein, Each subset of the second transistor is configured to be partially operatively used as a sense amplifier, level shifter, or memory cell, and each subset of the plurality of first transistors has a stacked structure.

6. A semiconductor device, comprising: A first semiconductor die includes a plurality of first transistors, wherein the plurality of first transistors are configured using a first transistor structure; and A second semiconductor die is coupled to the first semiconductor die and includes a plurality of second transistors, wherein the plurality of second transistors are all composed of a second transistor structure; In this configuration, at least a subset of the plurality of first transistors is configured to receive a first power supply voltage during a time period that satisfies a threshold and to electrically couple the first power supply voltage to a subset of the plurality of second transistors.

7. The semiconductor device according to claim 6, wherein, The time period is configured to be equal to or shorter than the threshold.

8. The semiconductor device according to claim 7, wherein, A subset of the first transistors is configured to be operatively used as one or more power switches, each subset of the second transistors is configured to be partially operatively used as a sense amplifier, level shifter, or memory cell, and none of the subsets of the second transistors have a stacked structure.

9. A method for forming a semiconductor device, comprising: A plurality of first transistors are formed on a first semiconductor die, each of the plurality of first transistors having a first gate component, wherein a subset of the plurality of first transistors is used to receive a power supply voltage; A plurality of second transistors are formed on a second semiconductor die, each of the plurality of second transistors having a second gate portion smaller than the first gate portion, wherein a subset of the plurality of second transistors is configured to receive the power supply voltage from a subset of the plurality of first transistors for a period of time; and The first semiconductor die is bonded to the second semiconductor die using multiple bump structures.

10. The method according to claim 9, wherein, A subset of the plurality of first transistors is configured to be operatively used as one or more power switches, and a subset of the plurality of second transistors is configured to be operatively used in part as a sense amplifier, a level shifter, or a memory cell.

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