An adaptive refresh memory system and an adaptive refresh method thereof

Abstract

This application provides an adaptive refresh memory system and its adaptive refresh method. The system includes a memory array, a control circuit, and at least one detection array integrated on the same chip as the memory array. By writing test data to the detection array through the control circuit and comparing the data after a preset waiting time, the system achieves real-time evaluation of the memory array's retention characteristics. Based on the evaluation results, the refresh cycle applied to the memory array is adaptively adjusted. Compared with existing technologies that use a fixed refresh frequency or a "quasi-static" operation mode, the refresh cycle of this application's memory system follows the current physical state of the chip in real time. While ensuring data reliability, it reduces refresh power consumption to the physical limit, achieving a dynamic optimal balance between energy efficiency and reliability. Furthermore, it does not rely on external testing equipment or offline calibration, exhibiting strong self-adaptability.

Description

Technical Field

[0001] This application relates to the field of memory technology, and specifically to an adaptive refresh memory system and its adaptive refresh method. Background Technology

[0002] With the rapid development of quantum computing technology, the scale of quantum processors is expanding from tens of qubits to thousands and even millions of qubits. To address the "interconnection bottleneck" in this expansion process—namely, how to effectively connect qubits located in a low-temperature environment (millikelvin temperature range) to control electronic devices in a room-temperature environment—industry and academia have proposed a low-temperature circuit control interface scheme. In this scheme, the memory, as the core component of the control chip, undertakes the crucial tasks of storing microinstructions, waveform lookup tables, and quantum error correction data.

[0003] However, the low-temperature environment poses extremely challenging requirements for memory design: First, extremely stringent power consumption constraints, as the cooling power of dilution refrigerators in the 4K temperature range is extremely limited (typically only milliwatts to watts), requiring memory to have extremely high energy efficiency; Second, high bandwidth and low latency, in order to match high-speed quantum error correction algorithms, the memory must eliminate the performance gap between the processor and the memory; Third, high storage density, in order to store a large amount of quantum bit state information and error correction instructions, it is necessary to integrate the largest possible capacity of memory on a limited chip area.

[0004] Current mainstream embedded memory technologies mainly include Static Random Access Memory (SRAM) and Embedded Dynamic Random Access Memory (eDRAM). SRAM uses a 6-transistor latch structure, which is fast and does not require refreshing, but its cell area is large, its storage density is low, and its dynamic power consumption during read and write operations is high, making it difficult to meet the needs of large-capacity caches. Traditional DRAM uses a capacitor to store charge, which has extremely high storage density, but at room temperature, it requires frequent refreshing due to severe subthreshold leakage, resulting in high static power consumption.

[0005] Physics research shows that at low temperatures, the subthreshold slope of transistors improves significantly, and the subthreshold leakage current decreases exponentially. This characteristic allows DRAM data retention time at low temperatures to be extended by several orders of magnitude (e.g., from microseconds to seconds), thereby greatly reducing refresh frequency and standby power consumption. Therefore, gain-cell based embedded DRAM (GC-eDRAM) has become a research hotspot in the field of low-temperature high-performance computing due to its logic process compatibility, high density, and low leakage characteristics at low temperatures.

[0006] Currently, research on GC-eDRAM for low-temperature environments mainly focuses on optimizing cell topology. Existing research attempts to use a four-transistor transmission gate gain cell structure, utilizing parallel NMOS and PMOS transmission gates to improve write performance at low temperatures. However, relying solely on cell topology optimization cannot solve the key problems in low-temperature environments: the threshold voltage dispersion of advanced process nodes increases significantly at 4K temperatures, inevitably resulting in "short-board cells" in the memory array with leakage rates much faster than the average. If a uniform "refresh-free" or fixed low-frequency refresh strategy is adopted, these short-board cells will experience data flipping, leading to calculation errors; the cooling power of dilution refrigerators is limited, and the self-heating effect generated by the high-load operation of quantum chips can cause local temperature fluctuations. Subthreshold leakage is exponentially related to temperature, and even a small increase in temperature can lead to a sharp decrease in hold time. Memory without a real-time monitoring mechanism is extremely prone to data loss during temperature fluctuations; existing solutions mostly set refresh strategies based on simulation models during the design phase, failing to detect real-time physical states such as chip aging and environmental drift, making it difficult to achieve optimal energy efficiency while ensuring data security. Summary of the Invention

[0007] This application provides an adaptive refresh storage system and its adaptive refresh method, which can solve the technical problems in existing low-temperature GC-eDRAM technology, which cannot cope with extreme device mismatch at low temperatures, data loss caused by temperature fluctuations, and lack of real-time physical state perception capabilities due to the use of "quasi-static" or fixed refresh strategies.

[0008] In a first aspect, embodiments of this application provide an adaptive refresh storage system, comprising:

[0009] A storage array, consisting of multiple gain units, is used to store data;

[0010] At least one detection array, integrated on the same chip as the memory array, is used to monitor the retention characteristics of the memory array;

[0011] A control circuit, connected to the storage array and the detection array respectively, is configured to write test data to the detection array, and after a preset waiting time, read the data from the detection array and compare it with the test data to evaluate the retention characteristics of the storage array; and adaptively adjust the refresh cycle applied to the storage array based on the evaluation results.

[0012] In some embodiments, the storage array has a central isolation strip inside and at least one edge buffer strip outside; at least one detection array is disposed on the central isolation strip and at least one detection array is disposed on the edge buffer strip; the detection array has word line control that is independent of the storage array.

[0013] In some embodiments, the number of rows of the edge buffer strip and the central isolation strip is equal to the number of rows of the storage array; virtual arrays are provided on the remaining areas of the edge buffer strip and the central isolation strip, excluding the detection array, to provide uniform pattern density to eliminate proximity effects.

[0014] In some embodiments, the physical structures of the basic units constituting the detection array and the basic units constituting the virtual array are the same as the physical structures of the gain units in the storage array.

[0015] In some embodiments, the gain unit includes a write transmission gate composed of a first transistor and a second transistor, as well as a third transistor and a fourth transistor;

[0016] The control terminal of the first transistor is connected to the write word line WWL, and the first terminal of the first transistor is connected to the write bit line WBL; the control terminal of the second transistor is connected to the complementary write word line WWLB, and the first terminal of the second transistor is connected to the second terminal of the first transistor, and the second terminal of the second transistor is connected to the first terminal of the first transistor; the control terminal of the third transistor is connected to the second terminal of the first transistor, and the second terminal of the third transistor is connected to a preset voltage terminal; the control terminal of the fourth transistor is connected to the read word line RWL, the first terminal of the fourth transistor is connected to the read bit line RBL, and the second terminal of the fourth transistor is connected to the second terminal of the third transistor.

[0017] In some embodiments, the first transistor, the second transistor, and the third transistor have the same aspect ratio, and the physical size of the third transistor is larger than that of the first transistor.

[0018] Secondly, embodiments of this application provide an adaptive refresh method for a storage system, applied to an adaptive refresh storage system as described in any embodiment of the first aspect, comprising:

[0019] Write test data to the detection array and read the data from the detection array after a preset waiting time;

[0020] The read data is compared with the test data, and the current retention characteristics of the storage array are evaluated based on the comparison results;

[0021] Based on the evaluation results, the refresh cycle applied to the storage array is calculated and updated.

[0022] In some embodiments, comparing the read data with the test data and evaluating the current retention characteristics of the storage array based on the comparison result includes:

[0023] If the read data is consistent with the test data, it is determined that the current retention characteristic of the storage array has not exceeded the retention limit, the preset waiting time is increased, and the write, read, and compare operations are repeated.

[0024] If the read data is inconsistent with the test data, it is determined that the current retention characteristic of the storage array has exceeded the retention limit, and the waiting time corresponding to the last time the comparison result was consistent is determined as the current maximum retention time.

[0025] Where there are multiple detection arrays, the current maximum holding time is the minimum value among the maximum holding times corresponding to all detection arrays.

[0026] In some embodiments, calculating and updating the refresh cycle applied to the storage array based on the evaluation results includes:

[0027] Calculate the new refresh cycle applied to the storage array based on the determined maximum hold time and preset safety margin;

[0028] Calculate the difference between the new refresh cycle and the current refresh cycle;

[0029] When the difference does not exceed the preset threshold, the current refresh cycle remains unchanged;

[0030] When the difference exceeds a preset threshold, the refresh cycle applied to the storage array is updated to a new refresh cycle.

[0031] In some embodiments, after updating the refresh cycle applied to the storage array, the method further includes:

[0032] Reset the preset waiting time to the initial preset value.

[0033] The adaptive refresh storage system and method provided in this application introduce a detection array integrated on the same chip as the storage array. A control circuit writes test data to the detection array and reads and compares the data after a preset waiting time, achieving real-time evaluation of the storage array's retention characteristics. Based on the evaluation results, the refresh cycle applied to the storage array is adaptively adjusted. Compared to existing technologies using a fixed refresh frequency or a "quasi-static" operation mode, the refresh cycle of the storage system in this application follows the chip's current physical state in real time. While ensuring data reliability, it reduces refresh power consumption to the physical limit, achieving a dynamic optimal balance between energy efficiency and reliability. Furthermore, it does not rely on external testing equipment or offline calibration, exhibiting strong self-adaptability. Attached Figure Description

[0034] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0035] Figure 1 This is a schematic diagram of the structure of an adaptive refresh storage system provided in one embodiment of this application.

[0036] Figure 2 This is a schematic diagram of the structure of an adaptive refresh storage system provided in another embodiment of this application.

[0037] Figure 3 This is a schematic diagram of the gain unit provided in one embodiment of this application.

[0038] Figure 4 This is a schematic diagram of an adaptive refresh storage system structure provided in another embodiment of this application.

[0039] Figure 5 This is a flowchart of an adaptive refresh method for a storage system provided in one embodiment of this application.

[0040] Figure 6 A flowchart of an adaptive refresh method for a storage system provided in another embodiment of this application.

[0041] Figure 7 A flowchart of an adaptive refresh method for a storage system provided in another embodiment of this application.

[0042] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0043] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. Similar elements in different embodiments are referred to by related similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the present application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present application are not shown or described in the specification. This is to avoid obscuring the core parts of the present application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0044] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0045] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages).

[0046] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0047] Figure 1 This is a schematic diagram of the structure of an adaptive refresh storage system provided in one embodiment of this application. Figure 1 As shown, the adaptive refresh storage system provided in this embodiment includes at least a storage array 110, a detection array 120, and a control circuit 130. The storage array 110 and the detection array 120 are integrated on the same semiconductor chip, and the control circuit 130 is connected to the storage array 110 and the detection array 120 respectively.

[0048] In this embodiment, the storage array 110 consists of multiple gain units for storing data. In typical memory designs, gain units are usually arranged in rows and columns, and addressed and read / write operations are performed via word lines and bit lines. Each gain unit can store binary information in the form of charge, for example, using the gate capacitance of a transistor or a dedicated storage capacitor. The read / write operations of the storage array 110 are completed with the cooperation of peripheral circuitry. For example, a row decoder selects the corresponding word line based on the row address, and a column decoder selects the corresponding bit line based on the column address. The selected gain unit can then be used for data writing or reading.

[0049] The detection array 120 is a dedicated monitoring circuit integrated on the same chip as the main memory array 110. It typically consists of detection units with the same or highly similar physical structure and electrical characteristics as the gain units, but it is not directly used to store user data. Because these detection units maintain consistency with the gain units in physical structure and electrical characteristics, they can accurately reflect the real environment of the memory array 110, such as chip temperature, power supply voltage fluctuations, and process deviations. In this embodiment, the detection array 120 is used to monitor the retention characteristics of the memory array 110 in real time and in situ during the operation of the memory system, such as the retention time of the gain units, i.e., the length of time the gain units can maintain data without loss without external intervention. By simulating the data retention state of the memory array 110, the impact of physical effects such as process deviations, temperature changes, and voltage fluctuations on data retention capability is reflected, providing a basis for refreshing the memory array 110's cycle.

[0050] The control circuit 130 undertakes the routine control tasks of the storage system, including responding to external read / write requests, selecting the corresponding gain units through row and column decoders, and controlling data writing or reading; initiating refresh operations periodically according to the refresh cycle set by the system or the refresh cycle determined by an adaptive algorithm; managing the interface with external processors or systems, performing data exchange and instruction parsing; and handling other auxiliary functions such as power management and error correction.

[0051] In this embodiment, the control circuit 130 is also configured to write test data to the detection array 120, and after a preset waiting time, read the data of the detection array 120 and compare it with the test data to evaluate the retention characteristics of the storage array 110; and adaptively adjust the refresh cycle applied to the storage array 110 according to the evaluation results.

[0052] Because the electronic components in the storage array 110 have leakage current, the data decays over time. Therefore, periodic refresh operations are required, i.e., reading out the data and rewriting it to prevent data loss. The frequency of refresh operations directly affects the power consumption of the memory; the more frequent the refresh, the higher the power consumption; conversely, the longer the refresh interval, the lower the power consumption, but the greater the risk of data loss. Compared to the fixed refresh cycle scheme in the prior art, in this embodiment, the control circuit 130 is also responsible for executing an adaptive refresh strategy. Specifically, firstly, fixed test data (test pattern) is written to the detection array 120. After a preset waiting time, the data in the detection array 120 is read and compared bit by bit to quantitatively evaluate the data retention characteristics of the storage array 110 under the current operating environment. Subsequently, the refresh cycle applied to the storage array 110 is adaptively adjusted based on the evaluation results. The refresh cycle refers to the time interval between two adjacent refresh operations. The refresh operation prevents the gain unit from losing data due to charge leakage by reading out and rewriting the data. By adaptively adjusting the refresh cycle, the refresh frequency can be reduced as much as possible while ensuring data security, thereby reducing power consumption.

[0053] The adaptive refresh storage system provided in this embodiment introduces a detection array integrated on the same chip as the storage array. The control circuit writes test data to the detection array and reads and compares the data after a preset waiting time, achieving real-time evaluation of the storage array's retention characteristics. Based on the evaluation results, the refresh cycle applied to the storage array is adaptively adjusted. Compared to existing technologies using a fixed refresh frequency or a "quasi-static" operation mode, the refresh cycle of the storage system in this embodiment follows the chip's current physical state in real time. While ensuring data reliability, it reduces refresh power consumption to the physical limit, achieving a dynamic optimal balance between energy efficiency and reliability. Furthermore, it does not rely on external testing equipment or offline calibration, exhibiting strong self-adaptability.

[0054] Figure 2 This is a schematic diagram of the structure of an adaptive refresh storage system provided in another embodiment of this application. Figure 2 As shown, in some embodiments, the storage array 110 has a central isolation strip inside and at least one edge buffer strip outside; at least one detection array 120 is provided on the central isolation strip and at least one detection array 120 is provided on the edge buffer strip, and the detection array 120 has word line control that is independent of the storage array 110.

[0055] In practice, transistors located at the array edges are affected by shallow trench isolation stress and diffusion region length effects, causing their electrical characteristics to deviate from those of the central region cells. Simultaneously, the central region of the chip is prone to heat accumulation under high load operations, resulting in more significant temperature changes. To more accurately monitor process deviations and stress distribution across the entire memory chip, the memory array 110 has a central isolation band and edge buffer bands on both sides. These central isolation bands and edge buffer bands are specific physical regions within the memory array 110; these regions themselves are not used to store user data but rather to provide locations for the detection array 120. Specifically, at least one detection array 120 is set on the central isolation band to monitor the retention characteristics of the central region of the memory array 110; at least one detection array 120 is also set on one or both edge buffer bands, such as a 3x3 array, to monitor the retention characteristics of the edge regions of the memory array 110. By setting detection arrays 120 at different locations, the overall retention status of the memory array 110 can be obtained more comprehensively, providing a more accurate basis for adjusting the adaptive refresh cycle. Simultaneously, the array sampling mechanism avoids system misjudgments caused by single-point failures.

[0056] Furthermore, the detection array 120 has word line control that is independent of the storage array 110. This means that the read and write operations of the detection array 120 are completed by an independent word line drive circuit, without occupying the word line resources of the storage array 110. Thus, the detection array 120 can perform independent test data writing and reading operations without affecting the normal data access of the storage array 110, thereby ensuring that the detection process can continue in the background without interfering with the normal read and write tasks of the storage array 110.

[0057] In some embodiments, such as Figure 2 As shown, the number of rows in the edge buffer zone and the center isolation zone of the storage array 110 is equal to the number of rows in the storage array 110; virtual arrays 140 are provided on the remaining areas of the edge buffer zone and the center isolation zone except for the detection array 120, to provide uniform pattern density to eliminate proximity effect.

[0058] In semiconductor photolithography, differences in pattern density can lead to the proximity effect, where densely patterned regions and sparsely patterned regions have different exposure conditions, causing deviations in transistor critical dimensions and drift in electrical characteristics. For memory array 110, the internal cells are densely packed, and if the edge regions are directly adjacent to blank areas, the photolithographic environment of the edge cells will differ from that of the central cells, causing their threshold voltage, leakage current, and other characteristics to deviate from design values, forming the so-called edge effect. In this case, if the environment of the detection array 120 is inconsistent with that of the memory array 110, its monitoring results will lose their reference value. To solve this problem, edge buffer bands are set on the outside of the memory array 110, and a central isolation band is set on the inside, with the number of rows in these buffer bands and isolation bands equal to the number of rows in the memory array 110. On the buffer bands and isolation bands, except for the already set detection array 120, the remaining areas are filled with virtual arrays 140. The virtual array 140 is composed of virtual cells with the same physical structure as the gain cells. These virtual cells do not participate in data storage, but their existence ensures that the buffer bands and isolation bands have the same pattern density as the memory array 110. In this way, from the perspective of photolithography, the entire chip surface maintains a uniform pattern density, eliminating the proximity effect caused by density abrupt changes. This ensures that all cells in the core memory array 110 are in the same photolithographic environment, thereby achieving consistent electrical characteristics. Since the buffer band and isolation band themselves have the same number of rows and pattern density as the memory array 110, the embedded detection array 120 can also operate under process conditions completely consistent with the core cells. The retention characteristics it monitors can truly reflect the actual state of the core array, and also ensure the reliability of the adaptive refresh cycle adjustment.

[0059] Meanwhile, the physical structures of the basic units constituting the detection array 120 and the basic units constituting the virtual array 140 are the same as the physical structures of the gain units in the storage array 110.

[0060] In integrated circuit design and manufacturing, the accuracy of monitoring results highly depends on the consistency between the monitoring device and the target device. If the physical structure (transistor type, size, layout, etc.) of the detection unit differs from that of the gain unit, its response characteristics to environmental factors such as temperature, voltage, and process deviations will deviate from those of the gain unit, causing the monitoring results to fail to accurately reflect the actual state of the memory array 110. Furthermore, virtual units eliminate the lithographic proximity effect by filling sparse regions with the same structure as the gain unit to maintain consistent pattern density across the entire chip surface. If the structure of the virtual unit differs from that of the gain unit, true density compensation cannot be achieved, and the proximity effect will still exist. Therefore, both the detection array 120 and the virtual array 140 are designed with the same physical structure as the gain unit, i.e., they use the same transistor type, size, capacitor structure, and layout. This homogenized physical layout design ensures that the retention characteristic data acquired by the detection array 120 accurately reflects the actual state of the memory array 110, resulting in high-fidelity detection results. Virtual units are also more effective in simulating the lithographic environment of the gain unit.

[0061] Figure 3 This is a schematic diagram of the gain unit provided in one embodiment of this application. Figure 3 As shown, the gain unit provided in this embodiment is composed of four low threshold voltage (LVT) transistors, including a write transmission gate composed of the first transistor M1 and the second transistor M2, and the third transistor M3 and the fourth transistor M4, forming a 4T TGGC architecture.

[0062] Specifically, the control terminal of the first transistor M1 is connected to the write word line WWL, and the first end of the first transistor M1 is connected to the write bit line WBL; the control terminal of the second transistor M2 is connected to the complementary write word line WWLB, and the first end of the second transistor M2 is connected to the second end of the first transistor M1 to form a storage node SN; the second end of the second transistor M2 is connected to the first end of the first transistor M1, i.e., connected to the write bit line WBL; the control terminal of the third transistor M3 is connected to the second end of the first transistor M1, i.e., connected to the storage node SN of the first transistor M1 and the second transistor M2; the second end of the third transistor M3 is connected to a preset voltage terminal, which is usually ground; the control terminal of the fourth transistor M4 is connected to the read word line RWL, the first end of the fourth transistor M4 is connected to the read bit line RBL, and the second end of the fourth transistor M4 is connected to the second end of the third transistor M3.

[0063] In this embodiment, the first transistor M1 is an NMOS transistor and the second transistor M2 is a PMOS transistor. They are connected in parallel to form a complementary transmission gate structure. This cross-connection method allows the write word line WBL and the complementary write word line WWLB to simultaneously control the conduction and cutoff of the transmission gate. When the write word line is high and the complementary write word line is low, the first transistor M1 and the second transistor M2 are simultaneously turned on, transmitting the data voltage on the write bit line to the memory node. Since PMOS transistors can transmit high levels without loss and NMOS transistors can transmit low levels without loss, the complementary transmission gate can achieve full-swing writing from the power supply voltage to ground, solving the problem of write level loss caused by the increase in threshold voltage of single-transistor transmission gates in low-temperature environments. The third transistor M3 is an NMOS transistor, and its control terminal is directly connected to the memory node SN. Its conduction state is determined by the voltage of the memory node SN. Its gate oxide layer capacitance serves as the physical medium for storing charge and is used to sense the data stored in the memory node. The second terminal of the third transistor M3 is connected to the ground terminal, forming the ground branch of the read path. The fourth transistor, M4, is also an NMOS transistor. Its control terminal is connected to the read word line RWL, and its first terminal is connected to the read bit line RBL, used to select the read path during a read operation. When a read operation is performed, the read word line turns on the fourth transistor M4. If the memory node SN is high, the third transistor M3 turns on, and the read bit line discharges to ground through the third transistor M3 and the fourth transistor M4, generating a read signal. If the memory node SN is low, the third transistor M3 is off, and the read bit line remains at a pre-charge high level. By separating the write transmission gate and the read transistor, independent optimization of the write path and the read path is achieved. This ensures reliable writing at low temperatures and provides data storage capability through the gate capacitance of the read transistor. No additional storage capacitors (such as deep trench capacitors in DRAM) or high-voltage devices are required. It is fully compatible with standard logic processes and easy to integrate with quantum control logic circuits.

[0064] It should be noted that, in this embodiment, to clearly describe the connection relationship of the transistor, general terminology is used to define the three electrodes of the transistor: the control terminal refers to the gate of the transistor, used to control the transistor's turn-on and turn-off; the first terminal refers to one active region electrode of the transistor, which can be the drain or source depending on the transistor type and bias conditions; the second terminal refers to the other active region electrode of the transistor, which can correspondingly be the source or drain. For NMOS transistors, the second terminal is the source when the first terminal is the drain, or vice versa; the same applies to PMOS transistors. Due to the symmetry of the MOSFET structure, the roles of the drain and source can be interchanged with the bias voltage direction in actual circuits. Therefore, using the description of the first terminal and the second terminal can accurately cover the connection relationship under various operating states, avoiding limitations on the protection scope due to fixed naming of the drain and source. Those skilled in the art should understand that when the transistor is turned on, current flows between the first terminal and the second terminal, and the voltage at the control terminal controls the magnitude of this current.

[0065] In a deep cryogenic environment of 4.2K, Figure 3 The working principle of the gain unit shown is as follows:

[0066] During writing, the write bit line WBL is set to the corresponding level according to the data to be written: a high level VDD represents writing "1", and a low level 0V represents writing "0". The write word line WWL is set to high level VDD, and the complementary write word line WWLB is set to low level 0V, making the complementary transmission gate composed of the first transistor M1 and the second transistor M2 fully conductive. Since PMOS transistors can transmit high levels without loss and NMOS transistors can transmit low levels without loss, the memory node SN is charged to the same level as WBL, realizing full-swing writing and ensuring that the memory node obtains an accurate initial voltage.

[0067] After writing is complete, WWL is set to low (0V) and WWLB is set to high (VDD), turning off the transmission gate. At a deep cryogenic temperature of 4.2K, the transistor subthreshold slope is extremely steep (typically less than 10mV / dec), and the turn-off leakage current of the first transistor M1 and the second transistor M2 drops below the picoampere level. The charge on the storage node SN leaks slowly mainly through the gate tunneling effect, significantly extending the data retention time.

[0068] Before reading, the read bit line RBL is pre-charged to VDD. Then, the read word line RWL is set to high (VDD), turning on the fourth transistor M4. If the memory node SN is high, the third transistor M3 is in a strongly inverted state, and RBL discharges to ground through the path of the conducting fourth transistor M4 → third transistor M3, causing the RBL voltage to drop. If the memory node SN is low, the third transistor M3 is off, and RBL remains pre-charged high. The data stored in the memory node can be determined by detecting changes in the RBL voltage.

[0069] In some embodiments, the first transistor M1, the second transistor M2, and the third transistor M3 have the same aspect ratio, and the physical size of the third transistor M3 is larger than that of the first transistor M1.

[0070] As described in the background section, innovations in quantum computing technology place higher demands on storage systems in cryogenic environments. To achieve optimal performance of the gain unit at a cryogenic temperature of 4.2K, the dimensions of the first transistor M1, the second transistor M2, and the third transistor M3 are differentiated during the design of the gain unit. The first transistor M1 and the second transistor M2, as components of the write transmission gate, have the same aspect ratio, for example, 4, and both employ a minimum feature size design. This aims to minimize the source-drain junction capacitance of the transistors themselves, thereby reducing parasitic capacitance and leakage paths on the write path, which helps improve write speed and data retention. Simultaneously, the aspect ratios of the first transistor M1 and the second transistor M2 are strictly matched to ensure that the charge injection effects generated by them can cancel each other out when the write operation is turned off, reducing charge errors written to the storage node and improving write accuracy. The third transistor M3, as the read transistor, has the same aspect ratio as the first transistor M1, for example, also set to 4, but its physical dimensions—the absolute values ​​of the channel width W and the channel length L—are significantly larger than those of the first transistor M1, for example, approximately twice that of the first transistor M1. Increasing the physical area of ​​the gate without changing the aspect ratio increases the gate oxide capacitance, which is equivalent to integrating a larger storage capacitor on the memory node. This allows for the storage of more charge and significantly extends data retention time. Furthermore, a larger read transistor size provides a stronger read drive current, enabling faster discharge or charging of the read bit lines during read operations, thus improving read speed and reliability.

[0071] Simulation experiments show that the four-transistor transmission gate gain unit used in this storage system possesses full-swing write characteristics, enabling an initial voltage increase of approximately 150-200mV compared to traditional structures. Since leakage current decays exponentially or linearly with voltage, a higher initial voltage means a significantly longer time required for charge decay to the data flip threshold. Data indicates that the gain unit of this structure can achieve data retention times of tens to hundreds of microseconds at -55°C, and is expected to reach seconds or even longer at a deep cryogenic temperature of 4.2K, representing a cell-level retention performance improvement of more than 10 times compared to existing solutions.

[0072] Simulations also revealed that when the system is in a deep cryogenic environment with extremely low leakage current, the adaptive refresh mechanism extends the refresh cycle to several seconds or even minutes, thereby eliminating a large number of invalid refresh operations. This allows the standby power consumption of the dynamic memory to approach that of the static memory, while maintaining a storage density advantage of more than double. When temperature instability leads to increased leakage current, the system rapidly increases the refresh frequency to ensure data security. This dynamic adjustment mechanism enables the memory to always operate at its optimal energy efficiency point across the entire temperature range, achieving an adaptive balance between power consumption and reliability.

[0073] Figure 4 This is a schematic diagram of an adaptive refresh storage system architecture provided in another embodiment of this application. Figure 4 As shown, based on any of the above embodiments, the adaptive refresh storage system of this embodiment further includes a precharge array 150 and a sensitive amplifier 160.

[0074] In this embodiment, the precharge array 150 is connected to the read bit line of the storage array 110 and is used to precharge the read bit line to a preset voltage before the read operation; the sensitive amplifier 160 is connected to the read bit line of the storage array 110 and is used to amplify the voltage signal on the read bit line and output data.

[0075] Before a read operation is performed, the precharge array 150 precharges all read bit lines to a preset voltage level, typically the power supply voltage VDD, to establish a uniform initial state for the read operation. This ensures that each bit line is at a known reference potential at the start of data reading, thus enabling the sensitive amplifier 160 to accurately detect minute voltage changes. Without the precharge stage, residual charge on the bit lines would lead to uncertain initial voltages, affecting read speed and accuracy. The precharge array 150 typically consists of multiple precharge transistors that simultaneously charge all bit lines under the control of a precharge control signal, ensuring that all bit lines of the entire memory array 110 are in a consistent initial state before the read operation.

[0076] Due to the small size and limited driving capability of the gain unit, during the readout process, the discharge or charging effect of the gain unit on the bit line can only generate a tiny voltage swing of tens to hundreds of millivolts on the bit line, which cannot directly drive the subsequent data output circuit. The function of the sensitive amplifier 160 is to detect this tiny voltage change on the bit line and rapidly amplify it to a full-swing signal of the power supply voltage or ground potential through a positive feedback mechanism, thereby accurately determining whether the data stored in the gain unit is "1" or "0". The sensitive amplifier 160 is usually composed of cross-coupled CMOS transistor pairs, and features high speed, high gain, and low power consumption, making it an indispensable key peripheral circuit in the memory system.

[0077] In summary, the adaptive refresh memory system provided in the above embodiments achieves full-swing writing through a four-transistor transmission gate gain unit, enabling data retention time at a low temperature of 4.2K to reach the second level, which is more than ten times faster than traditional structures. Simultaneously, it utilizes an integrated detection array and control circuit to construct a closed-loop feedback mechanism, allowing the refresh cycle to adaptively adjust according to the chip's physical state. This extends the refresh cycle to reduce power consumption when the drain electrode is low, and shortens the cycle promptly during temperature fluctuations to ensure data security, achieving a dynamic balance between energy efficiency and reliability. Furthermore, by deploying detection arrays at the corners and center of the array, spatial process variability is effectively covered, avoiding single-point misjudgments and significantly improving system robustness. The system is also fully compatible with standard logic processes, easily integrated with quantum control circuits, and combines the advantages of high density, low power consumption, high reliability, and low cost.

[0078] It should be noted that since the main improvement of this embodiment is the control method of the control circuit 130 during the operation of the storage system, other structures of the storage system will not be described in detail here.

[0079] The following section elaborates on the specific implementation process of how the control circuit 130 adjusts the refresh cycle of the storage array 110 based on the detection results of the detection array 120.

[0080] Figure 5 This is a flowchart illustrating an adaptive refresh method for a storage system provided in one embodiment of this application. Figure 5 As shown, the adaptive refresh method for a storage system provided in this application embodiment is applied to the storage system of any of the above embodiments, that is, the storage system is provided with at least a detection array 120, and the refresh method specifically includes the following steps:

[0081] Step S510: Write test data to the detection array and read the data from the detection array after a preset waiting time.

[0082] To ensure absolute data safety in situations where the adaptive algorithm has not yet converged and the system lacks awareness of its current hold characteristics, the control circuit 130 first acquires an initial refresh cycle and applies it to the memory array 110 after system startup or reset. The initial refresh cycle is typically set to an extremely conservative value, such as 0.1 milliseconds, far below the minimum hold time of the gain units in the memory array 110 under the expected operating environment, thus providing sufficient safety buffer for subsequent detection and adjustment processes.

[0083] Based on this, the control circuit 130 begins real-time detection of the retention characteristics of the memory array 110. First, arbitrary preset test data is written to the detection array 120. The test data can be all "1s", all "0s", or a checkerboard pattern; the specific content does not affect the comparison logic, as long as the detection array 120 is in a known state during writing. After writing, the control circuit 130 starts a timing mechanism, waiting for a preset waiting time. The preset waiting time can be initially set according to system requirements, for example, a conservative value much lower than the expected retention time. After the wait, the control circuit 130 reads the currently stored data in the detection array 120. The read data has already undergone the charge decay process throughout the waiting time. Based on the design characteristics of the detection array 120 and the memory array 110 having the same physical structure and consistent environment, the detection result can accurately reflect the retention state of the detection array 120 under the current physical environment. By observing whether the data read from the detection array 120 has flipped, the leakage characteristics of the gain units in the memory array 110 under the current temperature, voltage, and process deviation conditions can be indirectly evaluated.

[0084] Since the detection array 120 has word line control that is independent of the storage array 110, the read and write operations of the detection array 120 during the detection process are completed by an independent word line drive circuit, which does not occupy the word line resources of the storage array 110. The storage array 110 will perform normal read, write and refresh operations at the initial refresh cycle, and the detection process will not interfere with it.

[0085] Step S520: Compare the read data with the test data, and evaluate the current retention characteristics of the storage array based on the comparison results.

[0086] The control circuit 130 reads the data stored in the detection array 120 and compares it bit by bit with the initially written test data. Based on the comparison results, it evaluates the current retention characteristics of the storage array 110. If the read data is completely consistent with the test data, it indicates that no data loss has occurred in the detection array 120 during the current waiting time, meaning that the current retention capability of the storage array 110 is better than the waiting time. Conversely, if there is a discrepancy, it indicates that part of the detection array 120 has flipped, meaning that the current waiting time has exceeded the actual retention capability of the detection array 120 under the current physical conditions. Through this comparison result, the control circuit 130 can qualitatively or quantitatively evaluate the current retention characteristics of the storage array 110, determining whether the data retention capability under the current environment is stronger or weaker than the retention level represented by the preset waiting time. This comparison-based evaluation method is intuitive and reliable, accurately quantifying the real-time retention characteristics of the storage array 110 and providing a quantitative basis for subsequent refresh cycle adjustments.

[0087] Step S530: Calculate and update the refresh cycle applied to the storage array based on the evaluation results.

[0088] Based on the evaluation of the retention characteristics of the memory array 110, the control circuit 130 calculates a new refresh cycle suitable for the current physical state. If the evaluation results indicate that the current retention capability is strong, the refresh cycle can be appropriately extended to reduce refresh power consumption; if the evaluation results indicate that the retention capability is weak, the refresh cycle needs to be shortened to ensure data security. After calculating the new refresh cycle, the control circuit 130 updates it in the refresh control register of the memory array 110, and subsequent refresh operations will be executed according to the new cycle. Through this closed-loop feedback mechanism, the refresh cycle always follows the real-time physical state changes of the chip, achieving the technical effect of reducing refresh power consumption to the physical limit while ensuring data reliability.

[0089] In some embodiments, after updating the refresh cycle applied to the storage array, the method further includes:

[0090] Step S540: Reset the preset waiting time to the initial preset value.

[0091] After completing the refresh cycle update or deciding to maintain the original cycle, the control circuit 130 resets the preset waiting time to the initial preset value, preparing for the next detection cycle. This reset of the waiting time allows the detection process to be executed periodically, forming a continuous closed-loop monitoring mechanism. Each detection starts with a small, absolutely safe waiting time, gradually increasing until the hold limit under the current physical state is found. Through this combination of periodic reset and incremental detection, the system can respond in real time to any fluctuations in ambient temperature. For example, when the temperature is stable, the detection process will stabilize at a relatively long waiting time; when the temperature suddenly rises, causing the hold time to shorten, the next detection will start again from a smaller initial value, rapidly capturing the new hold limit and adjusting the refresh cycle accordingly. This design ensures that the detection process itself does not fall into a local optimum due to the previous detection result, always maintaining sensitivity to changes in the physical environment. This gives the adaptive refresh system the ability to autonomously adjust for long-term stable operation, achieving continuous and dynamic tracking of hold characteristics throughout the entire chip lifecycle.

[0092] Therefore, the adaptive refresh method for the storage system provided in this embodiment is based on a detection array integrated on the same chip as the storage array and having the same structure. By writing test data to the array and comparing it after a preset waiting time, the system dynamically evaluates the retention characteristics of the storage array and adaptively adjusts the refresh cycle accordingly. This closed-loop feedback mechanism ensures that the refresh frequency always follows the current physical state of the chip. Under the premise of ensuring data reliability, it can accurately extend the refresh interval according to the process differences of different chips and real-time changes in operating conditions such as temperature and voltage, thereby significantly reducing the dynamic power consumption caused by excessive refresh. At the same time, this intelligent adjustment mechanism reduces the number of frequent refreshes of the storage array, effectively releasing bandwidth resources, improving the overall access efficiency and performance of the system, and extending the lifespan of the storage system.

[0093] Figure 6 A flowchart illustrating an adaptive refresh method for a storage system provided in another embodiment of this application. Figure 6 As shown in the above embodiment, step S520, comparing the read data with the test data and evaluating the current retention characteristics of the storage array based on the comparison result, specifically includes:

[0094] Step S5201: If the read data is consistent with the test data, it is determined that the current hold characteristics of the storage array have not exceeded the hold limit. The preset waiting time is increased and the write, read and compare operations are repeated.

[0095] After the control circuit 130 reads the data from the detection array 120 and compares it with the test data, if the read data is found to be completely consistent with the test data, it indicates that the detection array 120 has not experienced data loss or errors within the current preset waiting time. This means that the current retention characteristics of the storage array 110 are better than the waiting time, and the current retention characteristics of the storage array 110 have not yet reached their physical limits. At this point, in order to accurately determine the critical point of the retention characteristics, the control circuit 130 determines that the retention characteristics of the storage array 110 have not exceeded the retention limit. It adopts a gradual approximation strategy, appropriately increasing the value of the preset waiting time, and then repeatedly executes the test process of writing test data to the detection array 120, waiting, reading, and comparing. This iterative approach can gradually approach the true limit of data retention in the storage array 110. It can actively detect the maximum retention time boundary that the storage array 110 can achieve under the current physical environment without directly damaging the data. It also avoids missing the precise maximum retention time due to excessively large single test intervals, providing a basis for the precise setting of subsequent refresh cycles.

[0096] Step S5202: If the read data is inconsistent with the test data, it is determined that the current hold characteristic of the storage array has exceeded the hold limit, and the waiting time corresponding to the last comparison result being consistent is determined as the current maximum hold time.

[0097] Conversely, if a discrepancy is found between the read data and the test data in a certain round of testing, it indicates that some or all cells in the memory array 110, which is identical to the detection array 120, have experienced data flipping. In other words, the current preset waiting time has exceeded the actual holding capacity of the memory array 110, and some or all gain cells have experienced bit flipping due to charge leakage. This means the holding characteristics of the memory array 110 have been breached. At this point, the control circuit 130 determines that the holding characteristics of the memory array 110 have exceeded the holding limit and will not use the current error waiting time as a basis. Instead, it will determine the waiting time corresponding to the previous consistent comparison result as the current maximum holding time. This critical value is the true reflection of the longest time that all gain cells in the memory array 110 can reliably hold data under the current temperature, voltage, and process deviation conditions. This "backtracking confirmation" mechanism accurately captures the critical point of the retention characteristic by using the actual error as the boundary, ensuring that the obtained retention time parameter is a true and reliable critical value that has not yet caused data errors. This preserves the necessary safety margin in the setting of subsequent refresh cycles and avoids systemic data reliability risks caused by directly using the duration that has already caused data errors.

[0098] It is important to note that when there are multiple detection arrays 120, the current maximum hold time is the minimum value among the maximum hold times corresponding to all detection arrays 120.

[0099] As described above, to ensure more accurate monitoring of process deviations and stress distribution across the entire memory chip, multiple detection arrays 120 are typically placed in the central isolation zone and edge buffer zone of the memory array 110. When the memory system is configured with multiple detection arrays 120, the maximum hold time measured by each detection array 120 at different physical locations may vary due to differences in process deviations, temperature gradients, or stress distribution. To ensure data integrity across all areas of the entire memory array 110, the control circuit 130 selects the maximum hold time with the smallest data value among all detection arrays 120 as the global current maximum hold time. This ensures that the refresh cycle of the memory array 110 meets the data hold requirements of the weakest area. By using the limit of the weakest array as a benchmark, it is guaranteed that under any location and operating condition, no gain unit will experience data loss or errors due to untimely refresh, thus fundamentally guaranteeing the reliability of the memory system.

[0100] Figure 7A flowchart illustrating an adaptive refresh method for a storage system provided in another embodiment of this application. Figure 7 As shown, in the above embodiment, step S530, calculating and updating the refresh cycle applied to the storage array based on the evaluation results, specifically includes:

[0101] Step S5301: Calculate the new refresh cycle applied to the storage array based on the determined maximum hold time and preset safety margin.

[0102] After the control circuit 130 determines the current maximum hold time based on the comparison results, it proceeds to the refresh cycle calculation stage. Considering the dynamic changes in the storage system's operating environment and the objective existence of process deviations, while the measured maximum hold time reflects the physical limits under current operating conditions, directly using it as the refresh cycle carries a certain risk of data loss. Therefore, a safety margin is introduced. This safety margin is a preset proportional coefficient, such as 20% to 30%, which provides a certain margin based on the maximum hold time to offset uncertainties such as inter-cell differences within the storage array 110, subsequent temperature fluctuations and aging effects, and temperature drift before the next calibration cycle. When calculating the new refresh cycle applied to the storage array 110, the control circuit 130 multiplies the maximum hold time determined through the above steps by a coefficient less than 1 or subtracts a fixed time value to calculate the new refresh cycle. By introducing a safety margin, even if the actual hold time fluctuates slightly, the storage array 110 can still reliably retain data within the new refresh cycle, thus providing additional protection for data security while reducing the refresh frequency.

[0103] Specifically, in some embodiments, the new refresh cycle The calculation expression is:

[0104] ;

[0105] in, This is the current maximum hold time; This is the safety margin coefficient.

[0106] Step S5302: Calculate the difference between the new refresh cycle and the current refresh cycle.

[0107] After calculating the new refresh cycle, considering that directly updating the refresh cycle based on each detection result could lead to frequent refresh frequency fluctuations and affect system stability when environmental fluctuations are small or detection noise is present, hysteresis logic is introduced. Control circuit 130 calculates the difference between the new refresh cycle and the currently used refresh cycle, quantifying the magnitude of the change between the old and new refresh cycles. If the difference is small, it indicates that the system's hold-up characteristics are relatively stable and may not require immediate adjustment; if the difference is significant, it indicates that environmental or aging factors have caused a shift in the system's hold-up characteristics, requiring a response.

[0108] Step S5303: When the difference does not exceed the preset threshold, keep the current refresh cycle unchanged.

[0109] After calculating the difference between the new refresh cycle and the current refresh cycle, the control circuit 130 compares it with a preset threshold, such as 5-15%. If the difference does not exceed the preset threshold, it indicates that the difference between the old and new refresh cycles is small, and the current refresh cycle is already within an optimal range, requiring no frequent adjustments. In this case, the control circuit 130 keeps the current refresh cycle unchanged to avoid invalid refreshes and uncertainties in system timing caused by minor, transient fluctuations (such as noise interference or brief temperature fluctuations). This hysteresis mechanism effectively filters out noise and slight environmental changes during the detection process, improving the stability of refresh cycle adjustment.

[0110] Step S5304: When the difference exceeds a preset threshold, the refresh cycle applied to the storage array is updated to a new refresh cycle.

[0111] If the difference exceeds a preset threshold, it indicates a significant deviation between the current refresh cycle and the optimal cycle calculated based on the latest detection results. Continuing to use the old cycle may lead to decreased energy efficiency or increased data risk. In this case, the control circuit 130 performs an update operation, officially replacing the refresh cycle applied to the memory array 110 with the newly calculated refresh cycle. Through this update mechanism, the system can respond promptly to significant changes in physical state while maintaining stability, ensuring that the refresh cycle always follows the actual operating conditions of the chip, achieving a dynamic balance between energy efficiency and reliability.

[0112] However, if a sharp drop in retention time is detected, such as a surge in leakage current due to sudden temperature runaway, the control circuit 130 will immediately force a refresh cycle update and trigger an emergency refresh operation, no longer subject to the hysteresis threshold. This ensures the fastest possible response under extreme conditions, prioritizing data security and enabling the system to quickly adapt to sudden and severe environments.

[0113] In summary, by writing test data to the detection array integrated on the same chip as the storage array and comparing it after a preset waiting time, an accurate quantitative evaluation of the real-time hold characteristics of the storage array is achieved. Based on this, the refresh cycle is dynamically adjusted according to the comparison results. That is, when the data is consistent, the waiting time is gradually increased to approach the hold limit boundary; when the data is inconsistent, the waiting time of the last successful test is determined as the maximum hold time. In the multi-detection array scenario, the minimum value among all local maximum hold times is used as the overall benchmark. At the same time, a safety margin is introduced to ensure data reliability. Combined with a hysteresis judgment mechanism, updates are only performed when the change exceeds the threshold. This closed-loop feedback mechanism ensures that the refresh frequency always follows the current physical state of the chip. Under the premise of ensuring absolute data security, the refresh power consumption is reduced to the physical limit. Moreover, the detection process runs in the background without interfering with normal read and write operations, achieving synergistic optimization of energy efficiency, reliability, and system stability.

[0114] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement various processes of any embodiment of the adaptive refresh method of the storage system described above, and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0115] The processor can be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0116] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0117] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art, under the guidance of this application, can make several simple deductions, modifications or substitutions based on the spirit of this application and the scope of protection of the claims without departing from the spirit of this application and the claims. All of these are within the protection scope of this application.

Claims

1. A self-adapting refresh storage system, characterized in that, include: A storage array, consisting of multiple gain units, is used to store data; At least one detection array, integrated on the same chip as the memory array, is used to monitor the retention characteristics of the memory array; A control circuit, connected to the storage array and the detection array respectively, is configured to write test data to the detection array, and after a preset waiting time, read the data from the detection array and compare it with the test data to evaluate the retention characteristics of the storage array; and adaptively adjust the refresh cycle applied to the storage array based on the evaluation results.

2. The self-adapting refresh memory system of claim 1, wherein, The storage array has a central isolation zone inside and at least one edge buffer zone outside; at least one detection array is provided on the central isolation zone and at least one detection array is provided on the edge buffer zone; the detection array has word line control that is independent of the storage array.

3. The self-adapting refresh memory system of claim 2, wherein, The number of rows in the edge buffer strip and the central isolation strip is equal to the number of rows in the storage array; virtual arrays are provided on the remaining areas of the edge buffer strip and the central isolation strip, excluding the detection array, to provide uniform pattern density and eliminate proximity effects.

4. The self-refreshed memory system of claim 3, wherein, The physical structures of the basic units constituting the detection array and the basic units constituting the virtual array are the same as the physical structures of the gain units in the storage array.

5. The self-adapting refresh memory system of claim 1, wherein, The gain unit includes a write transmission gate composed of a first transistor and a second transistor, as well as a third transistor and a fourth transistor; The control terminal of the first transistor is connected to the write word line WWL, and the first terminal of the first transistor is connected to the write bit line WBL; the control terminal of the second transistor is connected to the complementary write word line WWLB, and the first terminal of the second transistor is connected to the second terminal of the first transistor, and the second terminal of the second transistor is connected to the first terminal of the first transistor; the control terminal of the third transistor is connected to the second terminal of the first transistor, and the second terminal of the third transistor is connected to a preset voltage terminal; the control terminal of the fourth transistor is connected to the read word line RWL, the first terminal of the fourth transistor is connected to the read bit line RBL, and the second terminal of the fourth transistor is connected to the second terminal of the third transistor.

6. The adaptive refresh storage system according to claim 5, characterized in that, The first transistor, the second transistor, and the third transistor have the same width-to-length ratio, and the physical size of the third transistor is larger than that of the first transistor.

7. An adaptive refresh method for a storage system, applied to the adaptive refresh storage system as described in any one of claims 1 to 6, characterized in that, include: Write test data to the detection array and read the data from the detection array after a preset waiting time; The read data is compared with the test data, and the current retention characteristics of the storage array are evaluated based on the comparison results; Based on the evaluation results, the refresh cycle applied to the storage array is calculated and updated.

8. The adaptive refresh method for a storage system according to claim 7, characterized in that, The step of comparing the read data with the test data and evaluating the current retention characteristics of the storage array based on the comparison result includes: If the read data is consistent with the test data, it is determined that the current retention characteristic of the storage array has not exceeded the retention limit, the preset waiting time is increased, and the write, read, and compare operations are repeated. If the read data is inconsistent with the test data, it is determined that the current retention characteristic of the storage array has exceeded the retention limit, and the waiting time corresponding to the last time the comparison result was consistent is determined as the current maximum retention time. Where there are multiple detection arrays, the current maximum holding time is the minimum value among the maximum holding times corresponding to all detection arrays.

9. The adaptive refresh method for a storage system according to claim 8, characterized in that, The step of calculating and updating the refresh cycle applied to the storage array based on the evaluation results includes: Calculate the new refresh cycle applied to the storage array based on the determined maximum hold time and preset safety margin; Calculate the difference between the new refresh cycle and the current refresh cycle; When the difference does not exceed the preset threshold, the current refresh cycle remains unchanged; When the difference exceeds a preset threshold, the refresh cycle applied to the storage array is updated to a new refresh cycle.

10. The adaptive refresh method for a storage system according to claim 8, characterized in that, Following the update of the refresh cycle applied to the storage array, the process also includes: Reset the preset waiting time to the initial preset value.

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