Memory device including auxiliary circuit for regulating voltage level of word line

Abstract

A storage device includes: a memory cell array comprising a plurality of memory cells; a row decoder that selects one word line from a plurality of word lines connected to the plurality of memory cells based on an address received from a memory controller; and a word line voltage generator that provides a word line voltage to the selected word line. The word line voltage generator includes: a word line driver that outputs the word line voltage, the word line voltage being reduced by a power supply voltage, the power supply voltage being based on a word line drive voltage variation; a bump replication circuit that generates a bump signal having a voltage level that increases or decreases in response to the power supply voltage; and a word line voltage control circuit that outputs a word line drive voltage that increases or decreases complementary to the bump signal.

Description

Technical Field

[0001] This disclosure relates to a storage device. Background Technology

[0002] Semiconductor memories can be mainly divided into volatile memories and non-volatile memories. Volatile memories (such as DRAM or SRAM) have fast read and write speeds, but the data stored in volatile memories is lost when power is turned off. In contrast, non-volatile memories can retain data even when power is off.

[0003] Static random access memory (SRAM) cells may have various disturbance margins depending on process variation. For operational reliability, SRAM can ensure disturbance margins based on worst-case process variation. Furthermore, SRAM with varying supply voltages during operation may have disturbance margins that vary depending on the supply voltage level. Summary of the Invention

[0004] Typically, this disclosure relates to a memory device including auxiliary circuitry for adaptively adjusting the voltage of the drive word lines by tracking process variations based on a variable power supply voltage.

[0005] According to some embodiments, this disclosure relates to a storage device comprising: a memory cell array including a plurality of memory cells; a row decoder that selects one word line from a plurality of word lines connected to the plurality of memory cells based on an address received from a memory controller; and a word line voltage generator that provides a word line voltage to the selected word line. The word line voltage generator includes: a word line driver that outputs a word line voltage, the word line voltage being reduced by a power supply voltage varying based on a word line drive voltage; a bump replication circuit that generates a bump signal having a voltage level that increases or decreases in response to the power supply voltage; and a word line voltage control circuit that outputs a word line drive voltage that increases or decreases complementaryly to the bump signal.

[0006] According to some embodiments, this disclosure relates to a storage device, the storage device comprising: a memory cell array including a plurality of memory cells; a row decoder that selects one word line from a plurality of word lines connected to the plurality of memory cells based on an address received from a memory controller; and a word line voltage generator that provides a word line voltage to the selected word line. The word line voltage generator includes: a word line driver that outputs a word line voltage, the word line voltage being reduced by a power supply voltage varying based on a word line drive voltage; a first voltage control transistor including a source connected to a terminal of the power supply voltage, a drain connected to a first node, and a gate receiving a bulge signal, outputting a word line drive voltage from the first node; a second voltage control transistor including a drain connected to the first node, a source connected to a second node, and a gate receiving a voltage adjustment enable signal; and a third voltage control transistor, the third voltage... The control transistor includes a drain and a gate connected to the second node and a source connected to the third node; an interconnect resistor connected between the third node and a ground terminal; a first bump replication transistor including a drain connected to a power supply voltage terminal, a source connected to a fourth node, and a gate to which the voltage adjustment enable signal is input, and outputting the bump signal from the fourth node; and a second bump replication transistor including a drain connected to the fourth node, a source connected to the ground terminal, and a gate connected to the power supply voltage terminal.

[0007] According to some embodiments, this disclosure relates to a storage device comprising: a memory cell array including a plurality of memory cells configured to operate at a first power supply voltage; input / output circuitry operating at a second power supply voltage lower than the first power supply voltage and performing read or write operations on data via a plurality of bit lines respectively connected to the plurality of memory cells; a row decoder selecting one word line from a plurality of word lines connected to the plurality of memory cells based on an address received from a memory controller; and a word line voltage generator providing a word line voltage to the selected word line. The word line voltage generator includes: a word line driver outputting a word line voltage that is reduced by a power supply voltage varying based on a word line drive voltage; a bump replication circuit generating a bump signal having a voltage level that increases or decreases in response to a difference between the first power supply voltage and the second power supply voltage; and a word line voltage control circuit outputting a word line drive voltage that increases or decreases complementaryly to the bump signal based on the first power supply voltage. Attached Figure Description

[0008] The exemplary embodiments will be more clearly understood in conjunction with the accompanying drawings and the following detailed description.

[0009] Figure 1 This is a block diagram illustrating an example of a storage device according to some embodiments.

[0010] Figure 2 This illustrates according to some embodiments. Figure 1 A block diagram of an example storage device is shown in the figure.

[0011] Figure 3 This illustrates according to some embodiments. Figure 2 The circuit diagram of an example of a memory cell array is shown in the figure.

[0012] Figure 4 This illustrates according to some embodiments. Figure 3 A diagram illustrating an example of the first storage unit MC1.

[0013] Figure 5 This illustrates a connection according to some implementation methods. Figure 3 A diagram showing an example of a word line of a storage cell and a word line driver connected to the word line.

[0014] Figure 6 This illustrates according to some embodiments. Figure 5 A diagram showing an example of an auxiliary circuit.

[0015] Figure 7 This illustrates the basis according to some embodiments. Figure 6 A timing diagram illustrating an example of the word line drive voltage operation of the auxiliary circuit.

[0016] Figure 8 This illustrates according to some embodiments. Figure 5 A diagram showing an example of an auxiliary circuit.

[0017] Figure 9 This illustrates according to some embodiments. Figure 5 A diagram showing an example of an auxiliary circuit.

[0018] Figure 10 This illustrates according to some embodiments. Figure 5 A diagram showing an example of an auxiliary circuit.

[0019] Figure 11 This illustrates according to some embodiments. Figure 8 A diagram showing an example layout of the auxiliary circuit.

[0020] Figure 12 This illustrates according to some embodiments. Figure 5A diagram showing an example of an auxiliary circuit.

[0021] Figure 13 This illustrates according to some embodiments. Figure 5 A diagram showing an example of an auxiliary circuit.

[0022] Figure 14 This illustrates according to some embodiments. Figure 5 A diagram showing an example of an auxiliary circuit. Detailed Implementation

[0023] The following will describe the exemplary embodiments in detail with reference to the accompanying drawings.

[0024] Figure 1 This is a block diagram illustrating an example of a storage device according to some embodiments. Figure 1 In this context, storage device 1000 may include storage device 1100 and storage controller 1200.

[0025] Storage device 1100 can receive input / output signals (IO) from storage controller 1200 via input / output lines, control signals (CTRL) via control lines, and external power supply (PWR) via power lines. Furthermore, storage device 1100 can receive commands (CMD) and addresses (ADDR) from storage controller 1200. Storage device 1000 can store data in storage device 1100 under the control of storage controller 1200.

[0026] Storage device 1100 may include a storage cell array 1110 and peripheral circuitry 1115. The storage cell array 1110 may have a planar two-dimensional (2D) structure or a vertical three-dimensional (3D) structure. The storage cell array may include multiple storage cells. The storage cell array 1110 may be located next to or above the peripheral circuitry 1115.

[0027] The peripheral circuitry 1115 may include analog and / or digital circuitry required to store data in the memory cell array 1110 or to retrieve data stored in the memory cell array 1110. The peripheral circuitry 1115 may receive an external power supply PWR via a power line and generate internal power at various levels based on the external power supply PWR.

[0028] The peripheral circuit 1115 can receive data from the storage controller 1200 via input / output lines. The peripheral circuit 1115 can store data in the storage cell array 1110 according to the control signal CTRL. In some embodiments, the peripheral circuit 1115 can read the data stored in the storage cell array 1110 and provide the read data to the storage controller 1200.

[0029] Figure 2 This illustrates according to some embodiments. Figure 1 A block diagram illustrating an example of a storage device is shown. Figure 2 In the storage device 1100, the storage cell array 1110 and peripheral circuitry 1115 may be included. The peripheral circuitry 1115 may include a row decoder 1120, a column decoder 1130, an input / output circuit 1140, a word line voltage generator 1150, and / or control logic 1160.

[0030] The memory cell array 1110 can be connected to multiple word lines. The memory cell array 1110 can be connected to the word line voltage generator 1150 via multiple word lines.

[0031] The row decoder 1120 can select word lines during write or read operations. The row decoder 1120 can select word lines based on the row address included in the address ADDR.

[0032] Column decoder 1130 can be connected to memory cell array 1110 via multiple bit lines. Column decoder 1130 can select one or more bit lines based on the column address included in address ADDR.

[0033] Input / output circuit 1140 can be internally connected to column decoder 1130 via data lines, and externally connected to memory controller 1200 via input / output lines IO1 to IOn (reference). Figure 1 The input / output circuit 1140 can receive write data from the memory controller 1200 during a write operation.

[0034] The input / output circuit 1140 can provide data read from the memory cell array 1110 to the memory controller 1200 during a read operation. The input / output circuit 1140 can output data via input / output lines IO1 to IOn. The number of input / output lines IO1 to IOn can be determined based on the type of memory device 1000.

[0035] The input / output circuitry 1140 may include multiple sense amplifiers (S / A) 1141 and multiple write drivers (W / D) 1142. The multiple sense amplifiers 1141 can read data from memory cells connected to selected word lines during a read operation. The multiple write drivers 1142 can store data to memory cells connected to selected word lines during a write operation.

[0036] The word line voltage generator 1150 can receive internal power from the control logic 1160 and generate the word line voltage required to read or write data. The word line voltage can be provided to the selected word line via the line decoder 1120.

[0037] Control logic 1160 can use commands CMD, addresses ADDR, and control signals CTRL provided from storage controller 1200 to control operations such as read and / or write operations on storage device 1100. Address ADDR may include a row address for selecting a word line and a column address for selecting a memory cell.

[0038] Control logic 1160 may include auxiliary circuitry 100. Auxiliary circuitry 100 may provide word line drive voltage VDDWL to multiple word line drivers included in word line voltage generator 1150 based on power supply voltage VDD.

[0039] With refined manufacturing processes or reduced operating voltages, read interference may occur where a write operation is performed on a memory cell during a read operation, or a write operation is performed on a memory cell that is not the target of the write operation. The auxiliary circuit 100 can mitigate read interference by reducing the word line drive voltage VDDWL.

[0040] However, when the word line drive voltage VDDWL decreases, the write margin may decrease. Therefore, in order to simultaneously improve read interference and ensure write margin, the word line drive voltage VDDWL needs to be appropriately adjusted according to the fast / slow characteristics of temperature or process variations.

[0041] Control logic 1160 can change the power supply voltage VDD during operation by applying a dynamic voltage and frequency regulation (DVFS) scheme. Auxiliary circuitry 100 can adjust the word line drive voltage VDDWL according to the variable power supply voltage VDD by tracking process variations of the memory cell array 1110.

[0042] As an example, storage device 1100 may use the same power supply voltage VDD in both the storage cell array 1110 and the peripheral circuitry 1115. As another example, storage device 1100 may use different power supply voltages in both the storage cell array 1110 and the peripheral circuitry 1115. Storage device 1100 may use a first power supply voltage VDDCE (e.g., the storage cell power supply voltage) in the storage cell array 1110. Storage device 1100 may use a second power supply voltage VDDPE (e.g., the peripheral circuitry power supply voltage) in the peripheral circuitry 1115.

[0043] Figure 3 This illustrates according to some embodiments. Figure 2 The circuit diagram shows an example of a memory cell array. Figure 3 In this configuration, the storage cell array 1110 may include multiple storage cells (e.g., MC1 to MC2). Each storage cell may be a static random access storage cell.

[0044] The memory cell array 1110 can be connected to the row decoder 1120 and / or the word line voltage generator 1150 via the first word line WL1 to the m-th word line WLm. The memory cell array 1110 can be connected to the column decoder 1130 via the first bit line to the z-th bit line (BL1 to BLz, BLB1 to BLBz). As an example, BLB1 to BLBz can have complementary voltage levels to BL1 to BLz. For example, when BL1 is high, BLB1 can be low.

[0045] Each memory cell in the memory cell array 1110 may include a latch circuit LAT consisting of an inverter and pass gates PG and PGB. For example, the first memory cell MC1 may be connected to a first word line WL1 and a first bit line BL1 and a first complementary bit line BLB1. The first word line WL1 may be connected to the gates of the first pass gate PG and the second pass gate PGB. The first bit line BL1 and the first complementary bit line BLB1 may be connected to the drain or source of the first pass gate PG and the second pass gate PGB.

[0046] Figure 4 This illustrates according to some embodiments. Figure 3 A diagram illustrating an example of the first storage unit MC1. Figure 4 In the first storage unit MC1, a latch circuit LAT and transmission gates PG and PGB may be included.

[0047] The first storage unit MC1 can store one bit. The first storage unit MC1 may include a first inverter INVa and a second inverter INVb. The latch circuit LAT may consist of the first inverter INVa and the second inverter INVb. The output of the first inverter INVa can be connected to the input of the second inverter INVb. The output of the second inverter INVb can be connected to the input of the first inverter INVa.

[0048] A first transmission gate PG can be connected between the first bit line BL1 and the first node Q, and the input of the first inverter INVa is connected to the first node Q. Furthermore, the first transmission gate PG may include a gate connected to the first word line WL1. A second transmission gate PGB can be connected between the first complementary bit line BLB1 and the second node QB, and the second node QB is connected to the input of the second inverter INVb. Furthermore, the second transmission gate PGB may include a gate connected to the first word line WL1.

[0049] Figure 5 This illustrates a connection according to some implementation methods. Figure 3 A diagram illustrating an example of word lines in a memory cell and word line drivers connected to those word lines. Figure 5In this configuration, the memory cell array 1110 may include a plurality of memory cells 1110_1 to 1110_m. For example, the plurality of memory cells 1110_1 to 1110_m may be memory cells connected to a bit line BL.

[0050] Multiple memory cells 1110_1 to 1110_m can each be connected to multiple word lines WL1 to WLm. The multiple word lines WL1 to WLm can transmit the word line voltage to the transmission gate of the connected memory cell. Figure 3 (PG or PGB).

[0051] The word line voltage generator 1150 may include multiple word line drivers WD1 to WDm. The outputs of the multiple word line drivers WD1 to WDm can each be connected to multiple word lines WL1 to WLm. In addition, the inputs of the multiple word line drivers WD1 to WDm can each be connected to multiple complementary word lines WLB1 to WLBm.

[0052] The line decoder 1120 can be based on Figure 2 The row address RA included in the address ADDR selects the word line. For example, the row decoder 1120 can provide a word line drive signal to one of the complementary word lines WLB1 to WLm based on the row address RA. The word line driver connected to the selected complementary word line can invert the word line drive signal based on the word line drive voltage VDDWL and output the word line drive signal to the selected word line.

[0053] The 1130 decoder can be based on Figure 2 The column address CA included in the address ADDR selects one or more bit lines. During a write operation, the write driver 1142 can send data to bit lines BL and BLB. During a read operation, the sense amplifier 1141 can detect the voltage on bit lines BL and BLB.

[0054] Figure 2 The control logic 1160 may include auxiliary circuitry 100. Auxiliary circuitry 100 may provide word line drive voltage VDDWL to multiple word line drivers WD1 to WDm based on the power supply voltage VDD.

[0055] As manufacturing processes become more refined or operating voltages decrease, read interference may occur, such as writing to a memory cell during a read operation or writing to a memory cell that is not the intended target during a write operation. The auxiliary circuit 100 can mitigate read interference by reducing the word line drive voltage VDDWL.

[0056] However, when the word line drive voltage VDDWL decreases, the write margin may decrease. Therefore, in order to simultaneously improve read interference and ensure write margin, it is necessary to appropriately adjust the word line drive voltage VDDWL according to the speed of temperature or process variations.

[0057] Control logic 1160 can change the power supply voltage VDD during operation by applying a dynamic voltage and frequency regulation (DVFS) scheme. Auxiliary circuitry 100 can adjust the word line drive voltage VDDWL according to the variable power supply voltage VDD by tracking process variations of the memory cell array 1110.

[0058] Figure 6 This illustrates according to some embodiments. Figure 5 A diagram illustrating an example of an auxiliary circuit. In Figure 6 In this circuit, the auxiliary circuit 100 may include word line voltage control circuit 110 and bump replication circuit 120 (e.g., an improved circuit for process auto-track read assist (PATA)).

[0059] The word line voltage control circuit 110 may include a first voltage control transistor 111, a second voltage control transistor 112, and a third voltage control transistor 113. As an example, the first voltage control transistor 111 may be implemented as a P-type transistor. The second voltage control transistor 112 and the third voltage control transistor 113 may be implemented as N-type transistors.

[0060] The first voltage-controlled transistor 111 may include a source connected to the power supply voltage VDD terminal, a drain connected to the first node N1, and a gate connected to the third node N3. The second voltage-controlled transistor 112 may include a drain connected to the first node N1, a source connected to the second node N2, and a gate to which a voltage adjustment enable signal PATA_EN (e.g., an enable signal for Process Auto Tracking Read Assist (PATA)) is input. The third voltage-controlled transistor 113 may include a drain and a gate connected to the second node N2, and a source connected to the ground terminal.

[0061] The bump replication circuit 120 may include a first bump replication transistor 121 and a second bump replication transistor 122. As an example, the first bump replication transistor 121 and the second bump replication transistor 122 may be implemented as N-type transistors.

[0062] The first bump replication transistor 121 may include a drain connected to the power supply voltage VDD, a source connected to the third node N3, and a gate to which a voltage adjustment enable signal PATA_EN is input. The second bump replication transistor 122 may include a drain connected to the third node N3, a source connected to the ground terminal, and a gate connected to the power supply voltage VDD terminal.

[0063] The word line voltage control circuit 110 can track the global process corner through the second voltage control transistor 112 and the third voltage control transistor 113, and output a word line drive voltage VDDWL lower than the power supply voltage VDD through the first node N1 according to the global process corner. Therefore, the word line voltage control circuit 110 can improve the memory cell (e.g., Figure 3 The read interference margin of MC1).

[0064] Furthermore, the word line voltage control circuit 110 can receive a bulge signal BUMP to the gate of the first voltage control transistor 111. The bulge signal BUMP is a signal indicating a bit cell bulge phenomenon occurring in the memory cell. Therefore, the word line voltage control circuit 110 can increase the word line drive voltage VDDWL in response to the bulge signal BUMP, which operates according to the DVFS of the power supply voltage VDD. Thus, the word line voltage control circuit 110 can simultaneously improve the read interference margin and write margin of the memory cell.

[0065] The bulge replication circuit 120 can output a bulge signal BUMP to replicate the bit cell bulge phenomenon occurring in the memory cell. The bulge replication circuit 120 can generate the bulge signal BUMP based on the voltage adjustment enable signal PATA_EN. The bulge signal BUMP can be output through the third node N3.

[0066] When the level of the bulge signal BUMP increases, the current flowing through the first voltage control transistor 111 can decrease, and the word line drive voltage VDDWL can decrease significantly. When the level of the bulge signal BUMP decreases, the current flowing through the first voltage control transistor 111 may increase, and the word line drive voltage VDDWL can decrease slightly.

[0067] Figure 7 This illustrates according to some embodiments. Figure 6 A timing diagram illustrating an example of the word line drive voltage operation of the auxiliary circuit. Figure 6 and Figure 7 In this circuit, the auxiliary circuit 100 can adaptively output the word line drive voltage VDDWL according to the change of the power supply voltage VDD.

[0068] At the first time point t1, the voltage adjustment enable signal PATA_EN can be applied to the gate of the second voltage control transistor 112 and the gate of the first bump replication transistor 121. The voltage adjustment enable signal PATA_EN can be... Figure 2The control logic 1160 is generated based on the power supply voltage VDD. The voltage adjustment enable signal PATA_EN can be activated at a first time point t1, a specific time elapsed before the second time point t2 when the word line voltage to the selected word line is supplied. The voltage adjustment enable signal PATA_EN can be deactivated at a fourth time point t4, a specific time elapsed after the third time point t3 when the word line voltage to the selected word line is cut off.

[0069] When the voltage adjustment enable signal PATA_EN is activated, the bulge signal BUMP of the replication bit cell bulge phenomenon can be output from the third node N3 according to the resistance ratio of the first bulge replication transistor 121 and the second bulge replication transistor 122.

[0070] When the bulge signal BUMP is applied to the gate of the first voltage control transistor 111, the resistance of the first voltage control transistor 111 can be increased based on the magnitude of the bulge signal BUMP, and can generate the word line drive voltage VDDWL in a complementary manner with the bulge signal BUMP.

[0071] Between the second time point t2 and the third time point t3, a word line voltage can be provided to the selected word line according to the selection of the row decoder 1120. At this time, the word line voltage can be formed to be lower than the power supply voltage VDD by the word line drive voltage VDDWL. The auxiliary circuit 100 can determine the word line drive voltage VDDWL based on the global process corner of the memory cell. In addition, the auxiliary circuit 100 can change the magnitude of the word line drive voltage VDDWL according to the change of the power supply voltage VDD.

[0072] At the fourth time point t4, after a specified time has elapsed since the third time point t3, control logic 1160 can activate the voltage adjustment enable signal PATA_EN.

[0073] Figure 8 This illustrates according to some embodiments. Figure 5 A diagram showing an example of an auxiliary circuit. Figure 9 This illustrates according to some embodiments. Figure 5 A diagram showing an example of an auxiliary circuit. Figure 10 This illustrates according to some embodiments. Figure 5 A diagram showing an example of an auxiliary circuit.

[0074] exist Figures 8 to 10 In this circuit, the auxiliary circuit 100 may include a first voltage-controlled transistor 111, a second voltage-controlled transistor 112, a third voltage-controlled transistor 113, and an interconnecting resistor RINT. As an example, the first voltage-controlled transistor 111 may be implemented as a P-type transistor. The second voltage-controlled transistor 112 and the third voltage-controlled transistor 113 may be implemented as N-type transistors.

[0075] In the auxiliary circuit 100, the first voltage control transistor 111, the second voltage control transistor 112, and the third voltage control transistor 113 may have effective resistances that vary depending on the magnitude of the power supply voltage VDD. The interconnect resistor RINT may have a fixed resistance value independent of the magnitude of the power supply voltage VDD. The word line drive voltage VDDWL can be output from the first node N1 between the first voltage control transistor 111 and the second voltage control transistor 112. Therefore, the word line drive voltage VDDWL can be determined based on the ratio of the resistance value of the interconnect resistor RINT to the effective resistance of the first voltage control transistor 111, the second voltage control transistor 112, and the third voltage control transistor 113.

[0076] When the power supply voltage VDD decreases, the effective resistance of the first voltage control transistor 111, the second voltage control transistor 112, and the third voltage control transistor 113 can increase exponentially and become much greater than the resistance value of the interconnect resistor RINT. In some embodiments, the word line drive voltage VDDWL can be determined by the ratio between the effective resistances of the first voltage control transistor 111, the second voltage control transistor 112, and the third voltage control transistor 113.

[0077] As the power supply voltage VDD increases, the effective resistance of the first voltage control transistor 111, the second voltage control transistor 112, and the third voltage control transistor 113 can decrease exponentially and become less than the resistance value of the interconnect resistor RINT. In some embodiments, the word line drive voltage VDDWL can be determined by the interconnect resistor RINT.

[0078] Therefore, when the power supply voltage VDD decreases, the ratio of the effective resistance of the first voltage control transistor 111 can increase, thereby reducing the word line drive voltage VDDWL. When the power supply voltage VDD increases, the ratio of the resistance of the discharge path (e.g., the interconnect resistor RINT) can increase, thereby increasing the word line drive voltage VDDWL. Thus, the auxiliary circuit 100 can adjust the word line drive voltage VDDWL according to the global process corner.

[0079] exist Figure 8In the first voltage control transistor 111, a source connected to a terminal of the power supply voltage VDD, a drain connected to a first node N1, and a gate connected to a ground terminal are included. The second voltage control transistor 112 includes a drain connected to the first node N1, a source connected to the second node N2, and a gate to which a voltage adjustment enable signal PATA_EN is input. The third voltage control transistor 113 includes a drain and a gate connected to the second node N2, and a source connected to the fourth node N4. An interconnect resistor RINT can be connected between the fourth node N4 and the ground terminal.

[0080] exist Figure 9 In this configuration, the first voltage-controlled transistor 111 may include a source connected to a terminal of the power supply voltage VDD, a drain connected to a first node N1, and a gate connected to a ground terminal. The second voltage-controlled transistor 112 may include a drain connected to the first node N1, a source connected to a fourth node N4, and a gate to which a voltage adjustment enable signal PATA_EN is input. An interconnect resistor RINT may be connected between the fourth node N4 and the second node N2. The third voltage-controlled transistor 113 may include a drain and a gate connected to the second node N2, and a source connected to a ground terminal.

[0081] exist Figure 10 In this configuration, the first voltage-controlled transistor 111 may include a source connected to a terminal of the power supply voltage VDD, a drain connected to a first node N1, and a gate connected to a ground terminal. An interconnect resistor RINT may be connected between the first node N1 and the fourth node N4. The second voltage-controlled transistor 112 may include a drain connected to the fourth node N4, a source connected to the second node N2, and a gate to which a voltage adjustment enable signal PATA_EN is input. The third voltage-controlled transistor 113 may include a drain and a gate connected to the second node N2, and a source connected to a ground terminal.

[0082] Figure 11 This illustrates according to some embodiments. Figure 8 A diagram illustrating the layout of an auxiliary circuit. Figure 8 and Figure 11 In the auxiliary circuit 100, interconnecting resistors RINT can be achieved through path contacts. Figure 11 In the diagram, solid lines can represent layers M1 or M3, while dashed lines can represent layers M2 or M4.

[0083] Storage devices (e.g., Figure 2The storage device 1100 can use via contacts to connect different metal layers in a semiconductor chip. The via contact process can be performed according to the following steps: First, an interlayer insulating layer can be formed. An insulating layer can be formed between the metal layers to prevent electrical interference. Next, vias can be formed. Small holes can be made in the insulating layer to create vias. Next, metal can be deposited. The vias can be filled with metal to electrically connect the via contacts. For example, tungsten (W) or copper (Cu) can be used as said metal. Next, a chemical mechanical planarization (CMP) operation can be performed. After filling with metal, the surface can be planarized and prepared for the next process.

[0084] The first voltage-controlled transistor 111 can receive the bump signal BUMP through the first metal line ML1 and the path contact. In the first voltage-controlled transistor 111, multiple drive voltage lines VDDWL1 to VDDWL4 can be connected in parallel and output word line drive voltage VDDWL to reduce resistance.

[0085] The value of the interconnect resistor RINT can be determined by the path resistor RVIA. When the path resistor RVIA is connected in parallel to multiple ground lines VSS1 and VSS2, the interconnect resistor RINT can be decreased. Alternatively, or additionally, when the path resistor RVIA is omitted from the second ground line VSS2 and the path resistor RVIA is connected only to the first ground line VSS1, the interconnect resistor RINT can be increased.

[0086] Figure 12 This illustrates according to some embodiments. Figure 5 A diagram illustrating an example of an auxiliary circuit. In Figure 12 In this circuit, the auxiliary circuit 100 may include a word line voltage control circuit 110 and a bump replication circuit 120.

[0087] The word line voltage control circuit 110 may include a first voltage control transistor 111, a second voltage control transistor 112, and a third voltage control transistor 113. As an example, the first voltage control transistor 111 may be implemented as a P-type transistor. The second voltage control transistor 112 and the third voltage control transistor 113 may be implemented as N-type transistors.

[0088] The first voltage-controlled transistor 111 may include a source connected to a terminal of the power supply voltage VDD, a drain connected to a first node N1, and a gate connected to a ground terminal. The second voltage-controlled transistor 112 may include a drain connected to the first node N1, a source connected to the second node N2, and a gate to which a voltage adjustment enable signal PATA_EN is input. The third voltage-controlled transistor 113 may include a drain and a gate connected to the second node N2, and a source connected to the fourth node N4. An interconnect resistor RINT may be connected between the fourth node N4 and the ground terminal. However, as... Figures 8 to 10 As shown, the interconnecting resistor RINT can be arranged in series with voltage control transistors (e.g., first voltage control transistor 111, second voltage control transistor 112, and third voltage control transistor 113) at various locations between the first node N1 and the ground terminal.

[0089] The bump replication circuit 120 may include a first bump replication transistor 121 and a second bump replication transistor 122. As an example, the first bump replication transistor 121 and the second bump replication transistor 122 may be implemented as N-type transistors.

[0090] The first bump replica transistor 121 may include a drain connected to a terminal of the power supply voltage VDD, a source connected to a third node N3, and a gate to which a voltage adjustment enable signal PATA_EN is input. The second bump replica transistor 122 may include a drain connected to the third node N3, a source connected to a ground terminal, and a gate connected to a terminal of the power supply voltage VDD.

[0091] exist Figure 6 In this configuration, when the level of the bulge signal BUMP increases, the current flowing through the first voltage control transistor 111 can decrease, and the word line drive voltage VDDWL can decrease significantly. Conversely, when the level of the bulge signal BUMP decreases, the current flowing through the first voltage control transistor 111 can increase, and the word line drive voltage VDDWL can decrease slightly.

[0092] In addition, Figures 8 to 10 In this configuration, when the power supply voltage VDD decreases through the interconnect resistor RINT, the effective resistance ratio of the first voltage control transistor 111 can increase, and the word line drive voltage VDDWL can decrease. When the power supply voltage VDD increases, the resistance ratio of the discharge path (e.g., the interconnect resistor RINT) can increase, and the word line drive voltage VDDWL can increase.

[0093] Figure 13 This illustrates according to some embodiments. Figure 5 A diagram illustrating an example of an auxiliary circuit. In Figure 13 In this circuit, the auxiliary circuit 100 may include a word line voltage control circuit 110 and a bump replication circuit 120. Figure 13 In this device, storage device 1100 can use different power supply voltages in storage cell array 1110 and peripheral circuitry 1115. For example, storage device 1100 can use a first power supply voltage VDDCE in storage cell array 1110. Storage device 1100 can use a second power supply voltage VDDPE in peripheral circuitry 1115.

[0094] As an example, the first power supply voltage VDDCE can be set to a higher level than the second power supply voltage VDDPE. Therefore, when the second power supply voltage VDDPE varies according to the DVFS scheme and the difference between the first power supply voltage VDDCE and the second power supply voltage VDDPE increases, the interference margin of the memory cell may decrease.

[0095] The word line voltage control circuit 110 may include a first voltage control transistor 111, a second voltage control transistor 112, and a third voltage control transistor 113. The word line voltage control circuit 110 can be coupled with... Figure 6 The word line voltage control circuit 110 is configured in the same manner. The source of the first voltage control transistor 111 can be connected to the terminal of the first power supply voltage VDDCE.

[0096] The bump replication circuit 120 may include a first bump replication transistor 121 and a second bump replication transistor 122. As an example, the first bump replication transistor 121 and the second bump replication transistor 122 may be implemented as N-type transistors.

[0097] The first bump replication transistor 121 may include a drain connected to a terminal of the first power supply voltage VDDCE, a source connected to a third node N3, and a gate to which a voltage adjustment enable signal PATA_EN is input. The second bump replication transistor 122 may include a drain connected to the third node N3, a source connected to a ground terminal, and a gate connected to a terminal of the second power supply voltage VDDPE.

[0098] The second bump replica transistor 122 can be driven by the second power supply voltage VDDPE, and can be driven less weakly than the first bump replica transistor 121. Therefore, Figure 13 The bulge signal BUMP can rise to less than Figure 6 The bulge signal BUMP is generated. Therefore, even if the first power supply voltage VDDCE is different from the second power supply voltage VDDPE, the bulge replication circuit 120 can ensure interference margin by generating the bulge signal BUMP based on the difference between the first power supply voltage VDDCE and the second power supply voltage VDDPE.

[0099] Figure 14 It is shown according to some embodiments Figure 5 A diagram illustrating an example of an auxiliary circuit. In Figure 14 In this circuit, the auxiliary circuit 100 may include a word line voltage control circuit 110, a bump replication circuit 120, and a bump control circuit 130. Figure 14In this device, storage device 1100 can use different power supply voltages in storage cell array 1110 and peripheral circuitry 1115. For example, storage device 1100 can use a first power supply voltage VDDCE in storage cell array 1110. Storage device 1100 can use a second power supply voltage VDDPE in peripheral circuitry 1115.

[0100] As an example, the first power supply voltage VDDCE can be set to a higher level than the second power supply voltage VDDPE. Therefore, when the second power supply voltage VDDPE varies according to the DVFS scheme and the difference between the first power supply voltage VDDCE and the second power supply voltage VDDPE increases, the interference margin of the memory cell can be reduced.

[0101] The word line voltage control circuit 110 may include a first voltage control transistor 111, a second voltage control transistor 112, and a third voltage control transistor 113. The word line voltage control circuit 110 can be coupled with... Figure 13 The word line voltage control circuit 110 is configured in the same manner. The source of the first voltage control transistor 111 can be connected to the terminal of the first power supply voltage VDDCE.

[0102] The bump replication circuit 120 may include a first bump replication transistor 121 and a second bump replication transistor 122. As an example, the first bump replication transistor 121 and the second bump replication transistor 122 may be implemented as N-type transistors.

[0103] The first bump replication transistor 121 may include a drain connected to a terminal of the second power supply voltage VDDPE, a source connected to a third node N3, and a gate to which a voltage adjustment enable signal PATA_EN is input. The second bump replication transistor 122 may include a drain connected to the third node N3, a source connected to a ground terminal, and a gate connected to a fifth node N5.

[0104] The bump control circuit 130 may include a first bump control transistor 131 and a second bump control transistor 132. As an example, the first bump control transistor 131 may be implemented as a P-type transistor. The second bump control transistor 132 may be implemented as an N-type transistor.

[0105] The first bump control transistor 131 may include a source connected to a terminal of the first power supply voltage VDDCE, a drain connected to the fifth node N5, and a gate connected to the third node N3. The second bump control transistor 132 may include a drain connected to the fifth node N5, a source connected to a terminal of the second power supply voltage VDDPE, and a gate to which a voltage adjustment enable signal PATA_EN is input.

[0106] The bump replication circuit 120 can output a voltage based on the second power supply voltage VDDPE with a ratio of Figure 13 The bulge signal BUMP of the bulge replication circuit 120 is at a low level. Furthermore, the second bulge replication transistor 122 can be driven by the voltage level of the fifth node N5. The voltage level of the fifth node N5 can be controlled by the second bulge control transistor 132. The second bulge control transistor 132 can be turned on based on the difference between the voltage adjustment enable signal PATA_EN generated based on the first power supply voltage VDDCE and the second power supply voltage VDDPE.

[0107] Therefore, when the difference between the first power supply voltage VDDCE and the second power supply voltage VDDPE increases by a specified voltage or greater, the second bump replication transistor 122 can be driven. Compared to Figure 13 The second bulge replica transistor 122, Figure 14 The second bulge-replicated transistor 122 can operate less sensitively to the second power supply voltage VDDPE.

[0108] According to this disclosure, the read interference margin and write margin of a storage device can be optimized simultaneously based on a variable power supply voltage.

[0109] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims, their equivalents, and the claims described later. Certain features described in this disclosure in the context of different implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as operating in certain combinations, in some cases, one or more features from the combination may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

Claims

1. A storage device, the storage device comprising: A storage cell array, wherein the storage cell array comprises a plurality of storage cells; A row decoder configured to select one word line from a plurality of word lines connected to the plurality of memory cells based on an address received from the memory controller. as well as A word line voltage generator configured to provide a word line voltage to a selected word line of the plurality of word lines. The word line voltage generator includes: A word line driver configured to output the word line voltage, the word line voltage configured to be reduced by a power supply voltage configured to be based on a word line drive voltage variation; A bump replication circuit, configured to generate a bump signal having a voltage level configured to increase or decrease in response to the power supply voltage; and A word line voltage control circuit is configured to output the word line drive voltage, which is configured to increase or decrease complementaryly to the bulge signal.

2. The storage device according to claim 1, wherein, The word line voltage control circuit includes: A first voltage-controlled transistor, the first voltage-controlled transistor comprising: The source, configured to receive the power supply voltage. The drain is connected to a first node, which is configured to output the word line drive voltage. A gate configured to receive the bump signal; The second voltage control transistor includes a drain connected to the first node, a source connected to the second node, and a gate configured to receive a voltage adjustment enable signal. A third voltage-controlled transistor includes a drain and a gate connected to the second node, and a source connected to a ground terminal. The raised replication circuit includes: A first bump replication transistor includes a drain configured to receive the power supply voltage, a source connected to a third node, and a gate configured to receive the voltage adjustment enable signal, wherein the third node is configured to output the bump signal; and The second bumped replica transistor includes a drain connected to the third node, a source connected to the ground terminal, and a gate configured to receive the power supply voltage.

3. The storage device according to claim 2, wherein, The word line voltage control circuit includes an interconnect resistor connected between the source of the third voltage control transistor and the ground terminal.

4. The storage device according to claim 2, wherein, The word line voltage control circuit includes an interconnect resistor connected between the source of the second voltage control transistor and the second node.

5. The storage device according to claim 2, wherein, The word line voltage control circuit includes an interconnect resistor connected between the first node and the drain of the second voltage control transistor.

6. The storage device according to claim 5, wherein, The interconnecting resistor is configured to be formed by a via contact that is connected to a portion of a plurality of grounding metal wires.

7. The storage device according to claim 5, wherein, The magnitude of the word line drive voltage is based on the resistance value of the interconnect resistor and on the increase of the power supply voltage.

8. The storage device according to claim 5, wherein, The magnitude of the word line drive voltage is based on the effective resistance of the first voltage-controlled transistor and on the reduction of the power supply voltage.

9. The storage device according to claim 2, in, The first voltage-controlled transistor includes a P-type transistor, and The second voltage-controlled transistor, the third voltage-controlled transistor, the first bump replication transistor, and the second bump replication transistor include N-type transistors.

10. A storage device, the storage device comprising: A storage cell array, wherein the storage cell array comprises a plurality of storage cells; A row decoder configured to select one of a plurality of word lines connected to the plurality of memory cells based on an address received from the memory controller; as well as A word line voltage generator configured to provide a word line voltage to a selected word line of the plurality of word lines. The word line voltage generator includes: A word line driver configured to output the word line voltage, the word line voltage configured to be reduced by a power supply voltage configured to be based on a word line drive voltage variation; A first voltage-controlled transistor includes a source configured to receive the power supply voltage, a drain connected to a first node, and a gate configured to receive a bump signal, wherein the first node is configured to output the word line drive voltage. The second voltage control transistor includes a drain connected to the first node, a source connected to the second node, and a gate configured to receive a voltage adjustment enable signal. A third voltage-controlled transistor, the third voltage-controlled transistor including a drain and a gate connected to the second node, and a source connected to the third node; An interconnecting resistor is connected between the third node and the ground terminal; A first bump replication transistor includes a drain configured to receive the power supply voltage, a source connected to a fourth node, and a gate configured to receive the voltage adjustment enable signal, the fourth node being configured to output the bump signal; and The second bump-replicating transistor includes a drain connected to the fourth node, a source connected to the ground terminal, and a gate configured to receive the power supply voltage.

11. The storage device according to claim 10, wherein, The magnitude of the word line drive voltage is based on the resistance value of the interconnect resistor and on the increase of the power supply voltage.

12. The storage device according to claim 10, wherein, The magnitude of the word line drive voltage is based on the effective resistance of the first voltage-controlled transistor and on the reduction of the power supply voltage.

13. The storage device according to claim 10, wherein, The interconnecting resistor is connected to a portion of multiple grounding metal wires via a via contact.

14. The storage device according to claim 10, in, The first voltage-controlled transistor includes a P-type transistor, and The second voltage-controlled transistor, the third voltage-controlled transistor, the first bump replication transistor, and the second bump replication transistor include N-type transistors.

15. A storage device, the storage device comprising: A memory cell array comprising a plurality of memory cells configured to operate at a first power supply voltage; An input / output circuit is configured to operate at a second power supply voltage lower than the first power supply voltage and to perform data read or write operations via multiple bit lines connected to the plurality of memory cells; A row decoder configured to select one word line from a plurality of word lines connected to the plurality of memory cells based on an address received from the memory controller. as well as A word line voltage generator configured to provide a word line voltage to a selected word line of the plurality of word lines. The word line voltage generator includes: A word line driver configured to output the word line voltage, the word line voltage configured to be reduced by a power supply voltage configured to be based on a word line drive voltage variation; A bump replication circuit, configured to generate a bump signal, the bump signal being configured to have a voltage level that increases or decreases based on the difference between a first power supply voltage and a second power supply voltage; and A word line voltage control circuit is configured to output the word line drive voltage based on the first power supply voltage, the word line drive voltage being complementary to or decreasing the bulge signal.

16. The storage device according to claim 15, in, The word line voltage control circuit includes: A first voltage-controlled transistor includes a source configured to receive the first power supply voltage, a drain connected to a first node, and a gate configured to receive the bump signal, wherein the first node is configured to output the word line drive voltage. A second voltage-controlled transistor, the second voltage-controlled transistor including a drain connected to the first node, a source connected to the second node, and a gate configured to receive a voltage adjustment enable signal; and A third voltage-controlled transistor includes a drain and a gate connected to the second node, and a source connected to a ground terminal. The raised replication circuit includes: A first bump replication transistor includes a drain configured to receive the first power supply voltage, a source connected to a third node, and a gate configured to receive the voltage adjustment enable signal. The third node is configured to output the bump signal. The second bump replication transistor includes a drain connected to the third node, a source connected to the ground terminal, and a gate connected to the second power supply voltage.

17. The storage device according to claim 16, wherein, The word line voltage control circuit includes an interconnect resistor connected between the source of the third voltage control transistor and the ground terminal.

18. The storage device according to claim 15, wherein, The word line voltage control circuit includes: A first voltage-controlled transistor includes a source configured to receive the first power supply voltage, a drain connected to a first node, and a gate configured to receive the bump signal. The first node is configured to output the word line drive voltage. The second voltage control transistor includes a drain connected to the first node, a source connected to the second node, and a gate configured to receive a voltage adjustment enable signal. A third voltage-controlled transistor, the third voltage-controlled transistor including a drain and a gate connected to the second node, and a source connected to a ground terminal, The raised replication circuit includes: A first bump replication transistor includes a drain connected to the second power supply voltage, a source connected to a third node, and a gate configured to receive the voltage adjustment enable signal, wherein the third node is configured to output the bump signal; and The second bump control transistor includes a drain connected to the third node, a source connected to the ground terminal, and a gate connected to the fourth node. The bulge control circuit is configured to control the voltage level of the fourth node based on the difference between the first power supply voltage and the second power supply voltage.

19. The storage device according to claim 18, wherein, The protrusion control circuit includes: A first bump control transistor, the first bump control transistor including a source configured to receive the first power supply voltage, a drain connected to the fourth node, and a gate connected to the third node; and The second bump control transistor includes a source configured to receive the second power supply voltage, a drain connected to the fourth node, and a gate configured to receive the voltage adjustment enable signal.

20. The storage device according to claim 19, in, The first bump control transistor includes a P-type transistor, and The second bump control transistor includes an N-type transistor.

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