Communication interface signal receiving circuit, method and energy storage system
By employing a communication interface signal receiving circuit with dual reference voltages in the DDR/LPDDR memory system, the problem of random misjudgment of command address signals under high impedance or uncertain voltage ranges is solved, ensuring the reliability of command determination and system stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- KINGTIGER TESTING TECH (SZ) LTD
- Filing Date
- 2026-05-14
- Publication Date
- 2026-06-19
AI Technical Summary
In DDR/LPDDR memory systems, command address signals are prone to random misjudgments under high impedance or uncertain voltage ranges, leading to illegal commands and system stability issues. Existing single-reference voltage CA receiving schemes cannot guarantee the reliability of command determination.
The communication interface signal receiving circuit adopts dual reference voltage. It confirms the high and low levels of the command address signal twice through the first and second reference signals to ensure that the command address signal is in the same logic state under the judgment conditions of high reference voltage and low reference voltage. It outputs a valid or invalid flag to ensure the reliability of the signal.
It effectively eliminates the problem of random level determination of command address signal under high impedance state, prevents illegal or unexpected commands from being received inside DRAM, has strong compatibility, and is easy to integrate into existing CA receiver architecture.
Smart Images
Figure CN122245366A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of antenna technology, and in particular to a communication interface signal receiving circuit, method, and energy storage system. Background Technology
[0002] In DDR / LPDDR memory systems, the Command / Address (CA) signal is used to transmit memory control and configuration information. Its signal integrity and reliability directly affect the correctness of DRAM functionality. Related technologies also include solutions that improve signal detection capabilities by introducing multiple reference voltages or multiple comparison thresholds. For example, patent CN1618022A, "Input Buffer and Method for Voltage Level Detection," proposes an input buffer structure that identifies the voltage range of the input signal by setting multiple reference voltages and using multiple detection circuits to compare the input voltage, thereby achieving the detection and determination of the input signal state. This solution expands the level detection capability of the input buffer through multiple reference voltage comparisons.
[0003] For example, patent CN119010886B, "Receiver and Communication Interface", proposes a communication interface receiver structure. By setting a first threshold and a second threshold, and using a comparison unit and a logic unit to compare and process the input signal, the corresponding logic result is output when the input signal is in different threshold ranges, thereby improving the anti-interference capability and reliability of the communication interface receiving circuit.
[0004] However, the above solutions mainly address signal detection issues in general communication interfaces or input buffers. They lack a specific mechanism to address the misjudgment problem of CA signals in high-impedance (Hi-Z) or uncertain voltage ranges in DDR / LPDDR memory interfaces. When CA enters a high-impedance or weak-drive state, its line voltage may hover near the reference voltage and fluctuate slightly. If only a single reference voltage is used for comparison and judgment, random misjudgments can easily occur due to noise or offset. Therefore, it is necessary to propose a judgment mechanism more suitable for CA signal reception scenarios to improve the reliability of command address signal reception.
[0005] Although the aforementioned single-reference voltage CA receiving scheme can operate under normal driving conditions, it has significant drawbacks in the following scenarios: When the CA driver is off, enters a high-impedance state, or is in a command idle cycle, the CA line is no longer actively driven, and its voltage is mainly determined by non-ideal factors such as the CTT network, the offset voltage of the receiver input buffer, and leakage current. Since the CTT terminal itself is connected to 0.5×VDDQ, when CA is in Hi-Z or weak drive state, the line voltage may remain near the reference voltage for a long time and produce small fluctuations. Furthermore, when the CA voltage approaches or crosses Vref, the CA receiver may randomly determine it as logic "0" or "1" due to minor noise or offset. Once these misjudgments are sampled by DRAM, they may lead to illegal commands, erroneous state transitions, or even system stability issues. Therefore, when CA enters Hi-Z or an uncertain state, the existing single-reference voltage CA receiving scheme cannot guarantee the reliability of command determination. Summary of the Invention
[0006] The main objective of this invention is to propose a communication interface signal receiving circuit, method, and energy storage system, which aims to improve the reliability of command determination.
[0007] To achieve the above objectives, this invention proposes a communication interface signal receiving circuit for use in a storage system, the storage system including a register clock driver and at least one memory chip, the communication interface signal receiving circuit comprising: The signal output control circuit includes: The first reference signal input terminal is used to connect a first reference signal having a first reference voltage; The second reference signal input terminal is used to connect a second reference signal with a second reference voltage; wherein the first reference voltage is greater than the second reference voltage; The command address signal receiver is used to connect to an external controller to receive command address signals sent by the external controller. The signal validity flag output terminal is connected to the register clock driver and the memory chip, and is used to output the validity indication flag of the command address signal; The command address signal transmitting end is connected to the register clock driver and the memory chip; the signal output control circuit is used to compare the received command address signal with the first reference signal and the second reference signal respectively. When the voltage corresponding to the command address signal is greater than the first reference voltage or less than the second reference voltage, a valid command address signal flag is output to the valid signal flag output terminal, and the path between the command address signal receiver and the command address signal transmitter is connected, so as to output the command address signal to the register clock driver and / or memory chip.
[0008] In one embodiment, the signal output control circuit is further configured to: When the voltage corresponding to the command address signal is greater than the second reference voltage and less than the first reference voltage, a command address signal failure flag is output to the signal validity flag output terminal, and the path between the command address signal receiving terminal and the command address signal transmitting terminal is disconnected, so as to output the command address signal to the register clock driver and / or memory chip.
[0009] In one embodiment, the signal output control circuit includes: The system comprises a first comparison unit, a second comparison unit, and a judgment logic unit. The first input terminal of the first comparison unit is the first reference signal input terminal. The common terminal of the second input terminal of the first comparison unit and the first input terminal of the second comparison unit is the command address signal receiving terminal. The second input terminal of the second comparison unit is the second reference signal input terminal. The output terminals of the first and second comparison units are connected one-to-one with the two input terminals of the judgment logic unit. The first output terminal of the judgment logic unit is the command address signal sending terminal, and the second output terminal of the judgment logic unit is the signal validity flag output terminal. The first comparison unit is used to compare the command address signal with the first reference signal and output the corresponding first comparison result; The first comparison unit is used to compare the command address signal with the second reference signal and output the corresponding second comparison result; The judgment logic unit is used to output a command address signal valid flag to the signal valid flag output terminal when it is determined, based on the first comparison result and the second comparison result, that the voltage corresponding to the command address signal is less than the second reference voltage or the voltage corresponding to the command address signal is greater than the first reference voltage, and to connect the path between the command address signal receiving terminal and the command address signal transmitting terminal, so as to output the command address signal to the register clock driver and / or memory chip.
[0010] In one embodiment, the judgment logic unit is specifically used for: When the first comparison result and the second comparison result are consistent, and the first comparison unit outputs a first result representing a high level, the command address signal is determined to be valid; the command address signal is logically "1", and a command address signal validity flag is output to the signal validity flag output terminal, and a command address signal with logic "1" is output; When the first comparison result and the second comparison result are consistent, and the second comparison unit outputs a second result representing a low level, the command address signal is determined to be valid, and the logic of the command address signal is "0". The command address signal valid flag is output to the signal valid flag output terminal, and the command address signal with logic "0" is output.
[0011] In one embodiment, the judgment logic unit is further configured to, when determining, based on the first comparison result and the second comparison result, that the voltage corresponding to the command address signal is greater than the second reference voltage and less than the first reference voltage, output a command address signal failure flag to the signal validity flag output terminal, and disconnect the path between the command address signal receiving terminal and the command address signal transmitting terminal, so as to shield the command address signal.
[0012] In one embodiment, the judgment logic unit is specifically used for: If the first comparison result and the second comparison result are inconsistent, the command address signal is determined to be invalid, and the path between the command address signal receiving end and the command address signal sending end is disconnected to shield the command address signal; and / or an invalid command address signal flag is output to the valid signal flag output end.
[0013] In one embodiment, the first comparison unit and the second comparison unit are comparators; the judgment logic unit is a multiplexer.
[0014] In one embodiment, the communication interface signal receiving circuit includes: A Schmitt trigger, wherein the signal input terminal of the Schmitt trigger is used to receive the command address signal, and the output terminal of the Schmitt trigger is connected to the register clock driver and the memory chip; the Schmitt trigger is used to compare the received command address signal with the first reference signal and the second reference signal respectively; When the voltage corresponding to the command address signal is less than the second reference voltage, the command address signal is output to the memory chip; when the voltage corresponding to the command address signal is greater than the second reference voltage and less than the first reference voltage, the command address signal with a voltage less than the second reference voltage is maintained to be output to the register clock driver and / or the memory chip. Alternatively, when the voltage corresponding to the command address signal is greater than the first reference voltage, the command address signal is output to the memory chip; when the voltage corresponding to the command address signal is greater than the second reference voltage and less than the first reference voltage, the command address signal with a voltage greater than the first reference voltage is maintained to be output to the register clock driver and / or the memory chip.
[0015] The present invention also proposes an energy storage system, including the communication interface signal receiving circuit described above.
[0016] This invention also proposes a communication interface signal receiving method applied to a storage system, the storage system including a register clock driver, at least one memory chip, and the communication interface signal receiving circuit described above, the communication interface signal receiving method comprising: Upon receiving a command address signal output from an external controller, the received command address signal is compared with a first reference signal and a second reference signal, respectively; wherein, the first reference voltage of the first reference signal is greater than the second reference voltage of the second reference signal; When the voltage corresponding to the command address signal is less than the second reference voltage or the voltage corresponding to the command address signal is greater than the first reference voltage, a valid command address signal flag is output to the valid signal flag output terminal, and the path between the command address signal receiving terminal and the command address signal transmitting terminal is connected, so as to output the command address signal to the register clock driver and / or memory chip; When the voltage corresponding to the command address signal is greater than the second reference voltage and less than the first reference voltage, a command address signal failure flag is output to the signal validity flag output terminal, and the path between the command address signal receiving terminal and the command address signal transmitting terminal is disconnected, so as to output the command address signal to the register clock driver and / or memory chip.
[0017] This invention confirms the command address signal twice, once with a high level and once with a low level, and ensures that the command address signal is in the same logic state under both high and low reference voltage conditions, thus determining that the command address signal is within a defined level range. This invention effectively eliminates the random level determination problem caused by the command address signal being in a high-impedance state, thereby avoiding misjudgments when the command address signal voltage hovers around 0.5×VDDQ, and consequently preventing the DRAM from receiving illegal or unexpected commands. This invention can be implemented without changing the existing CTT terminal structure, has strong compatibility, and is simple to implement, making it easy to integrate into existing CA receiver architectures. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0019] Figure 1 This is a schematic diagram of the structure of an embodiment of the communication interface signal receiving circuit of the present invention; Figure 2 This is a waveform diagram of the command address signal received by the communication interface signal receiving circuit of the present invention; Figure 3 This is a diagram illustrating the actual application of the interface signal receiving circuit of this invention in a storage system. Figure 4 The waveform of the command address signal under a single reference voltage; Figure 5 This is a flowchart illustrating an embodiment of the communication interface signal reception of the present invention.
[0020] Explanation of icon numbers: RX1, First Comparison Unit; RX2, Second Comparison Unit; Ref1, First Reference Signal Input; Ref2, Second Reference Signal Input; CA, Command Address Signal Receiver; VD, Signal Valid Flag Output; D, Command Address Signal Transmitter; 10, Signal Output Control Circuit; 11, Judgment Logic Unit The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0022] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.
[0023] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.
[0024] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.
[0025] This invention proposes a communication interface signal receiving circuit for use in a storage system, which includes a register clock driver and at least one memory chip. The memory chip can be DDR DRAM (Double Data Rate Synchronous Dynamic Random-Access Memory) or LPDDR (Low Power Double Data Rate Dynamic Random-Access Memory). In DDR / LPDDR storage systems, the Command / Address (CA) signal is used to transmit control and configuration information for the memory, and its signal integrity and reliability directly affect the correctness of the DRAM's function. In a typical implementation, according to the JEDEC DDR / LPDDR storage interface specification, the CA line typically uses center tap termination (CTT) for termination matching, with its termination voltage set to 0.5 × VDDQ. Correspondingly, the CA receiver (RX) typically uses a single reference voltage to compare and determine the voltage of the CA signal, which is also generally set to 0.5 × VDDQ. When the command address signal is actively driven by the controller (such as CPU, MCU) as the transmitter (TX), the above structure can realize normal logic "0 / 1" determination, and is therefore widely used in existing memory systems.
[0026] In related technologies, although a determination mechanism for command address signal reception scenarios has been proposed to improve the reliability of command address signal reception, the following problems still exist: the level of the command address signal is unpredictable when it enters the high impedance state (Hi-Z): when the CA driver is off, enters the high impedance state, or is in the command idle cycle, the CA line is no longer actively driven, and its voltage is mainly determined by non-ideal factors such as the CTT network, the offset voltage of the receiver (RX) input buffer, and leakage current.
[0027] The voltage of the command address signal tends to hover around 0.5 × VDDQ: this is because the CTT terminal itself is connected to 0.5 × VDDQ (see...). Figure 3 , Figure 3 (This is a diagram of an actual application system of the interface signal receiving circuit in a storage system). When the command address signal is in a high-impedance or weak-drive state, the line voltage may remain near the reference voltage for a long time and produce small fluctuations (see...). Figure 4 The single reference voltage determination is prone to random misjudgments. When the voltage of the command address signal is close to or exceeds the reference voltage, the receiver CA may randomly determine the logic as "0" or "1" due to slight noise or offset.
[0028] This could trigger illegal or unexpected commands within the DRAM. Once these misjudgments are sampled by the DRAM, they could lead to illegal commands, erroneous state transitions, or even system stability issues. Therefore, existing single-reference voltage CA signal receiving schemes cannot guarantee the reliability of command determination when the CA signal enters a high-impedance or uncertain state.
[0029] To address the aforementioned problems, this invention proposes a communication interface signal receiving circuit that can identify and filter erroneous judgments of command address signals in high-impedance states or uncertain voltage ranges. (Refer to...) Figure 1 and Figure 2 In one embodiment of the present invention, the communication interface signal receiving circuit includes: Signal output control circuit 10, the signal output control circuit 10 includes: The first reference signal input terminal Ref1 is used to connect a first reference signal with a first reference voltage; The second reference signal input terminal Ref2 is used to connect a second reference signal with a second reference voltage; wherein, the first reference voltage is greater than the second reference voltage; The command address signal receiver (CA) is used to connect to an external controller to receive command address signals sent by the external controller. The signal validity flag output terminal VD is connected to the memory chip and is used to output a validity indicator flag for the command address signal. The command address signal transmitter D is connected to the memory chip; the signal output control circuit 10 is used to compare the received command address signal with the first reference signal and the second reference signal respectively. When the voltage corresponding to the command address signal is greater than the first reference voltage or less than the second reference voltage, the command address signal valid flag is output to the signal valid flag output terminal VD, and the path between the command address signal receiving terminal CA and the command address signal transmitting terminal is connected so as to output the command address signal to the memory clock driver and / or memory chip.
[0030] When the voltage corresponding to the command address signal is greater than the second reference voltage and less than the first reference voltage, the command address signal failure flag is output to the signal validity flag output terminal VD, and the path between the command address signal receiving terminal CA and the command address signal transmitting terminal is disconnected so that the command address signal is output to the memory chip.
[0031] In this embodiment, the voltage of the first reference signal is set to be higher than the voltage of the command address signal receiving terminal. The voltage of the second reference signal is set to be lower than the voltage of the command address signal receiving terminal. That is, the first reference signal and the second reference voltage can avoid the voltage of the command address signal receiving terminal, so as to avoid the line voltage from staying around 0.5×VDDQ for a long time and producing small fluctuations when the command address signal is in Hi-Z or weak drive state.
[0032] The storage system has a CA terminal and an RX terminal. The CA terminal is used to receive command address signals, and the RX terminal is used to receive data. When the external master controller needs to access the data of the corresponding storage chip in the storage system, it sends a command address signal to the CA terminal of the storage system through the TX terminal (transmitter) of the external master controller. When the storage system determines that the command address signal is valid, it sends the command address signal to the corresponding CTT terminal. The command address signal is input to the signal output control circuit 10, which compares the command address signal with the first reference signal and the second reference signal respectively. When the voltage of the command address signal is higher than the voltage of the first reference signal and the second reference signal at the same time, or when the voltage of the command address signal is lower than the voltage of the first reference signal and the second reference signal at the same time, the signal output control circuit 10 can determine that the command address signal is in the same logic state under the conditions of high reference voltage and low reference voltage, indicating that the command address signal is in the level determination range.
[0033] When the voltage of the command address signal is lower than the voltage of the first reference signal but higher than the voltage of the second reference signal, the signal output control circuit 10 can determine that the logic state of the command address signal is different under the conditions of high reference voltage and low reference voltage. This indicates that the command address signal is in the level uncertainty range. The CA voltage in this range may be affected by factors such as high impedance, terminal network or noise, and its logic state is not reliable.
[0034] When the signal output control circuit 10 determines that the command address signal is within a defined level range, it outputs a command address signal at the corresponding logic level from the command address signal transmitting terminal D, depending on whether the voltage of the command address signal is simultaneously higher than the voltages of the first and second reference signals, or simultaneously lower than the voltages of the first and second reference signals. Simultaneously, the signal validity flag output terminal VD outputs an indication flag indicating that the command address signal is valid (logic "1"). Specifically, when the voltage of the command address signal is simultaneously higher than the voltages of the first and second reference signals, a command address signal with logic "1" is output. When the voltage of the command address signal is simultaneously lower than the voltages of the first and second reference signals, a command address signal with logic "0" is output. When the signal output control circuit 10 determines that the command address signal is within an uncertain level range, the signal validity flag output terminal VD outputs an indication flag indicating that the command address signal is invalid (logic "0"), and the signal output control circuit 10 does not output the command address signal, i.e., it masks the command address signal. Thus, the back-end circuitry in the storage system, such as the RCD (Registering Clock Driver), can be connected to the signal validity flag output terminal VD and the command address signal transmitting terminal D of the signal output control circuit 10. The RCD can receive the command address signal when it determines the command address signal is valid based on the signal validity flag output terminal VD. When it determines the command address signal is invalid based on the signal validity flag output terminal VD, it can choose not to receive the command address signal.
[0035] This invention confirms the command address signal twice, once with a high level and once with a low level, and ensures that the command address signal is in the same logic state under both high and low reference voltage conditions, thus determining that the command address signal is within a defined level range. This invention effectively eliminates the random level determination problem caused by the high impedance state of the CA (Command Address) terminal, thereby avoiding misjudgments when the CA voltage hovers around 0.5×VDDQ, and preventing the DRAM from receiving illegal or unexpected commands. This invention can be implemented without changing the existing CTT (Content Toll Collection) terminal structure, has strong compatibility, and is simple to implement, making it easy to integrate into existing CA receiver architectures.
[0036] In one embodiment, the signal output control circuit 10 includes: The system comprises a first comparison unit RX1, a second comparison unit RX2, and a judgment logic unit 11. The first input terminal of the first comparison unit RX1 is a first reference signal input terminal Ref1. The common terminal of the second input terminal of the first comparison unit RX1 and the first input terminal of the second comparison unit RX2 is a command address signal receiving terminal CA. The second input terminal of the second comparison unit RX2 is a second reference signal input terminal Ref2. The output terminals of the first comparison unit RX1 and the second comparison unit RX2 are connected one-to-one with the two input terminals of the judgment logic unit 11. The first output terminal of the judgment logic unit 11 is a command address signal transmitting terminal D, and the second output terminal of the judgment logic unit 11 is a signal validity flag output terminal VD. The first comparison unit RX1 is used to compare the command address signal with the first reference signal and output the corresponding first comparison result. The first comparison unit RX1 is used to compare the command address signal with the second reference signal and output the corresponding second comparison result; The judgment logic unit 11 is used to output a command address signal valid flag to the signal valid flag output terminal VD when it is determined, based on the first comparison result and the second comparison result, that the voltage corresponding to the command address signal is less than the second reference voltage or the voltage corresponding to the command address signal is greater than the first reference voltage, and to connect the path between the command address signal receiving terminal CA and the command address signal transmitting terminal, so as to output the command address signal to the register clock driver and / or memory chip.
[0037] In this embodiment, the first comparison unit RX1 and the second comparison unit RX2 are comparators. The inverting input of the first comparison unit RX1 is connected to a first reference signal, and the non-inverting input is connected to a command address signal. The non-inverting input of the second comparison unit RX2 is connected to a second reference signal, and the inverting input is connected to the command address signal. The first comparison unit RX1 compares the voltage of the command address signal with the voltage of the first reference voltage and outputs a first comparison result. The first reference voltage is set to a reference level higher than the voltage of the command address signal receiving terminal. When the command address signal voltage is higher than the first reference voltage, the first comparison unit RX1 outputs a first comparison result indicating a high level, signifying that the command address signal is within a defined high-level range. When the command address signal is lower than the first reference voltage, the first comparison unit RX1 outputs the opposite first comparison result (flipping to a low level). Refer to Table 1, which shows the comparison results of the first comparison unit RX1 and the second comparison unit RX2, the validity flag output of the valid flag output terminal VD of the judgment logic unit 11 ((1) indicates valid, (0) indicates invalid), and the logic of the command address signal output by the command address signal output terminal D.
[0038] Table 1
[0039] Using this comparison method, the first comparison unit RX1 can determine from the high-level perspective whether the command address signal has a clear logical "1" characteristic.
[0040] The second comparison unit RX2 compares the command address signal with the level relationship of the second reference voltage and outputs a second comparison result. The second reference voltage is set to a reference level lower than the CA terminal voltage. When the command address signal voltage is lower than the second reference voltage, the second comparison unit RX2 outputs a comparison result representing a low level, indicating that the command address signal is within a defined low-level range. When the command address signal is higher than the second reference voltage, the second comparison unit RX2 outputs the opposite comparison result (flipping to a high level). Through this comparison method, the second comparison unit RX2 can determine whether the command address signal has a clear logic "0" characteristic from a low-level perspective.
[0041] In summary, when the voltage of the command address signal is higher than the first reference signal, the first comparison unit RX1 outputs a high level (1) first comparison result. Since the first reference voltage is greater than the second reference voltage, the command address signal also satisfies the condition of being higher than the second reference voltage. The second comparison unit RX2 simultaneously outputs a high level (1) second comparison result. Therefore, the comparison results of the first comparison unit RX1 and the second comparison unit RX2 are consistent (both are high level (1)).
[0042] When the voltage of the command address signal is lower than the voltage of the second reference signal, the second comparison unit RX2 outputs a high level (1) second comparison result. Since the first reference voltage is greater than the second reference voltage, the command address signal also meets the condition of being lower than the voltage of the first reference signal. The first comparison unit RX1 outputs a low level (0) first comparison result at the same time. Therefore, the comparison results of the first comparison unit RX1 and the second comparison unit RX2 are consistent (both are high level (1)).
[0043] The decision logic unit is connected to the outputs of the first comparison unit RX1 and the second comparison unit RX2, and is used to determine the consistency between the first comparison result and the second comparison result. When the first comparison result and the second comparison result are consistent, it indicates that the command address signal is in the same logic state under both high reference voltage and low reference voltage conditions, indicating that the command address signal is in the level-determined range.
[0044] In this embodiment, when the comparison results of the first comparison unit RX1 and the second comparison unit RX2 are consistent, the decision logic unit outputs a valid flag signal to the valid flag output terminal to indicate that the current command address signal is valid; when both are high level (1), the corresponding command address signal terminal outputs a command address signal with logic "1". When both are low level (0), the corresponding command address signal terminal outputs a command address signal with logic "0".
[0045] Optionally, when the first comparison result and the second comparison result are consistent, and the first comparison unit RX1 outputs the first comparison result representing a high level, the decision logic unit determines that the command address signal is valid and the logic of the command address signal is "1", and outputs the command address signal valid flag to the signal valid flag output terminal VD, and outputs the command address signal with logic "1". When the first comparison result and the second comparison result are consistent, and the second comparison unit RX2 outputs a second result representing a low level, the decision logic unit determines that the command address signal is valid and the logic of the command address signal is "0", and outputs the command address signal valid flag to the signal valid flag output terminal VD, and outputs the command address signal with logic "0".
[0046] Reference Figure 1 In one embodiment, the judgment logic unit 11 is further configured to, when it is determined based on the first comparison result and the second comparison result that the voltage corresponding to the command address signal is greater than the second reference voltage and less than the first reference voltage, output a command address signal failure flag to the signal validity flag output terminal VD, and disconnect the path between the command address signal receiving terminal CA and the command address signal sending terminal to shield the command address signal.
[0047] In this embodiment, the command address signal voltage is located in an uncertain range between the first reference voltage and the second reference voltage. The CA voltage within this range may be affected by factors such as high impedance, terminal network, or noise, and its logic state is not reliable. The decision logic unit performs a consistency determination on the first comparison result and the second comparison result. When the voltage of the command address signal is lower than the voltage of the first reference signal but higher than the voltage of the second reference signal, since the voltage of the command address signal is lower than the first reference signal, the first comparison unit RX1 outputs a low level (0) first comparison result, and since the voltage of the command address signal is higher than the voltage of the second reference signal, the second comparison unit RX2 outputs a high level (1) second comparison result. Therefore, the comparison results of the first comparison unit RX1 and the second comparison unit RX2 are inconsistent. Optionally, when the first comparison result and the second comparison result are inconsistent, the decision logic unit determines that the command address signal is invalid and disconnects the path between the command address signal receiving end CA and the command address signal sending end to shield the command address signal; and / or outputs a command address signal invalid flag to the signal valid flag output end VD. At this time, the decision logic unit 11 can output a command address signal with logic "1". Since the valid flag output end outputs a command address signal invalid flag, the back-end circuit chooses not to read the current command address signal when the valid flag output end outputs a command address signal invalid flag.
[0048] Reference Figure 1 In one embodiment, when the first comparison unit RX1 and the second comparison unit RX2 are implemented using comparators (labeled as the first comparator and the second comparator, respectively), the inverting input of the first comparator is connected to the first reference signal, and the non-inverting input of the first comparator is connected to the command address signal. The non-inverting input of the second comparator is connected to the second reference signal, and the inverting input of the second comparator is connected to the command address signal. The judgment logic unit 11 is implemented using a multiplexer. The two inputs of the multiplexer are respectively connected to the outputs of the two comparators one-to-one. The first output of the multiplexer is used to output a valid command address signal flag, and the second output is used to output the command address signal.
[0049] When the voltage of the command address signal is higher than that of the first reference signal, the output of the first comparator outputs a high level (1) first comparison result, and when the voltage of the command address signal is lower than that of the first reference signal, the output of the first comparator outputs a low level (0) first comparison result.
[0050] When the voltage of the command address signal is lower than that of the second reference signal, the output of the second comparator outputs a low level (0) second comparison result, and when the voltage of the command address signal is higher than that of the second reference signal, the output of the second comparator outputs a high level (1) second comparison result.
[0051] When both the first comparator and the second comparator output a high level, the first output terminal outputs a command address signal valid flag to the signal valid flag output terminal VD, and the second output terminal outputs a command address signal with logic "1". When both the first comparator and the second comparator output a low level, the first output terminal outputs a command address signal valid flag (1) to the signal valid flag output terminal VD, and the second output terminal outputs a command address signal with logic "0". When the first comparator outputs a low level and the second comparator outputs a high level, the first output terminal outputs a command address signal invalid flag (0) to the signal valid flag output terminal VD, and the second output terminal does not output a command address signal.
[0052] In one embodiment, the communication interface signal receiving circuit includes: The Schmitt trigger has a signal input terminal for receiving a command address signal and an output terminal connected to the memory chip. The Schmitt trigger is used to compare the received command address signal with a first reference signal and a second reference signal, respectively. When the voltage corresponding to the command address signal is less than the second reference voltage, the command address signal is output to the memory chip; when the voltage corresponding to the command address signal is greater than the second reference voltage and less than the first reference voltage, the command address signal with a voltage less than the second reference voltage is maintained to be output to the register clock driver and / or the memory chip. Alternatively, when the voltage corresponding to the command address signal is greater than the first reference voltage, the command address signal is output to the memory chip; when the voltage corresponding to the command address signal is greater than the second reference voltage and less than the first reference voltage, the command address signal with a voltage greater than the first reference voltage is maintained and output to the register clock driver and / or the memory chip.
[0053] In this embodiment, a Schmitt trigger structure is introduced at the command address signal receiving terminal CA. Positive feedback forms upper and lower threshold intervals (the upper threshold of this interval is the first reference voltage, and the lower threshold is the second reference voltage). When the command address signal is outside the upper and lower threshold intervals, i.e., when the voltage of the command address signal is higher than the voltage of the first reference signal or lower than the voltage of the second reference signal, it is determined that the command address signal is in a level-determined interval. At this time, depending on whether the voltage of the command address signal is simultaneously higher than the voltages of the first and second reference signals, or simultaneously lower than the voltages of the first and second reference signals, the output terminal of the Schmitt trigger outputs a command address signal with the corresponding logic level. When the command address signal is within the upper and lower threshold intervals, and it is determined that the command address signal is in a level-determined interval, the Schmitt trigger maintains the logic level output of the previous determined interval. For example, if the logic of the previous command address signal was "1", then it continues to output a command address signal with logic "1". If the logic of the previous command address signal is "0", then the command address signal with logic "0" will continue to be output. Thus, when the voltage of the command address signal is within the upper and lower threshold range, the output logic state of the command address signal remains unchanged, thereby improving the noise immunity.
[0054] This invention also proposes a communication interface signal receiving method applied to a storage system, the storage system including a register clock driver, at least one memory chip, and the communication interface signal receiving circuit described above, with reference to... Figure 5 The communication interface signal receiving method includes: Step S100: Upon receiving a command address signal output from an external controller, the received command address signal is compared with a first reference signal and a second reference signal, respectively; wherein, the first reference voltage of the first reference signal is greater than the second reference voltage of the second reference signal. Step S200: When the voltage corresponding to the command address signal is less than the second reference voltage or the voltage corresponding to the command address signal is greater than the first reference voltage, output a valid command address signal flag to the valid signal flag output terminal, and connect the path between the command address signal receiving terminal and the command address signal transmitting terminal, so as to output the command address signal to the register clock driver and / or memory chip; Step S300: When the voltage corresponding to the command address signal is greater than the second reference voltage and less than the first reference voltage, output a command address signal failure flag to the signal validity flag output terminal, and disconnect the path between the command address signal receiving terminal and the command address signal transmitting terminal, so as to output the command address signal to the register clock driver and / or memory chip.
[0055] In this embodiment, the voltage of the first reference signal is set to be higher than the voltage of the command address signal receiving terminal. The voltage of the second reference signal is set to be lower than the voltage of the command address signal receiving terminal. That is, the first reference signal and the second reference voltage can avoid the voltage of the command address signal receiving terminal, so as to prevent the line voltage from staying near 0.5×VDDQ for a long time and producing small fluctuations when the command address signal is in a high impedance state or a weak drive state.
[0056] When the external main controller needs to access the data of the corresponding storage chip in the storage system, it sends a command address signal to the storage system. This command address signal is input to the output control circuit, which compares the command address signal with the first reference signal and the second reference signal respectively. If the voltage of the command address signal is simultaneously higher than the voltages of the first reference signal and the second reference signal, or if the voltage of the command address signal is simultaneously lower than the voltages of the first reference signal and the second reference signal, it can be determined that the command address signal is in the same logic state under both high and low reference voltage conditions, indicating that the command address signal is in the level determination range.
[0057] When the voltage of the command address signal is lower than the voltage of the first reference signal but higher than the voltage of the second reference signal, it can be determined that the logic state of the command address signal is different under the conditions of high reference voltage and low reference voltage. This indicates that the command address signal is in the level uncertainty range. The CA voltage in this range may be affected by factors such as high impedance state, terminal network or noise, and its logic state is not reliable.
[0058] When the command address signal is determined to be within a defined level range, the command address signal transmitter outputs a command address signal of the corresponding logic level, depending on whether the voltage of the command address signal is simultaneously higher than the voltages of the first and second reference signals, or simultaneously lower than the voltages of the first and second reference signals. Simultaneously, the signal validity flag output terminal outputs a flag indicating that the command address signal is valid (logic "1"). Specifically, when the voltage of the command address signal is simultaneously higher than the voltages of the first and second reference signals, a command address signal of logic "1" is output. When the voltage of the command address signal is simultaneously lower than the voltages of the first and second reference signals, a command address signal of logic "0" is output. When the command address signal is determined to be within an indeterminate level range, the signal validity flag output terminal outputs a flag indicating that the command address signal is invalid (logic "0"), and no command address signal is output, i.e., the command address signal is masked. Thus, back-end circuitry in the storage system, such as an RCD (Registering Clock Driver), can be connected to the signal validity flag output terminal and the command address signal transmitter. The RCD can receive the command address signal when the signal validity flag output terminal determines that the command address signal is valid. If the command address signal is determined to be invalid based on the signal validity flag output, the command address signal can be ignored.
[0059] This invention confirms the command address signal twice, once with a high level and once with a low level, and ensures that the command address signal is in the same logic state under both high and low reference voltage conditions, thus determining that the command address signal is within a defined level range. This invention effectively eliminates the random level determination problem caused by the high impedance state of the CA (Capacitor Receiver), thereby avoiding misjudgments where the CA voltage hovers at 0.5 × VDDQ, and preventing the DRAM from receiving illegal or unexpected commands. This invention can be implemented without changing the existing CTT (Cellular Telephone Terminal) terminal structure, has strong compatibility, and is simple to implement, making it easy to integrate into existing CA receiver architectures.
[0060] The present invention also proposes an energy storage system, which includes the communication interface signal receiving circuit described above.
[0061] The detailed structure of the communication interface signal receiving circuit can be referred to the above embodiments, and will not be repeated here. It is understood that since the above communication interface signal receiving circuit is used in the energy storage system of the present invention, the embodiments of the energy storage system of the present invention include all the technical solutions of all the embodiments of the above communication interface signal receiving circuit, and the technical effects achieved are exactly the same, and will not be repeated here.
[0062] The above description is merely an optional embodiment of the present invention and does not limit the scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the scope of protection of the present invention.
Claims
1. A communication interface signal receiving circuit, characterized in that, Applied to a storage system, the storage system includes a register clock driver and at least one memory chip, and the communication interface signal receiving circuit includes: The signal output control circuit includes: The first reference signal input terminal is used to connect a first reference signal having a first reference voltage; The second reference signal input terminal is used to connect a second reference signal with a second reference voltage; wherein the first reference voltage is greater than the second reference voltage; The command address signal receiver is used to connect to an external controller to receive command address signals sent by the external controller. The signal validity flag output terminal is connected to the register clock driver and the memory chip, and is used to output the validity indication flag of the command address signal; The command address signal transmitting end is connected to the register clock driver and the memory chip; the signal output control circuit is used to compare the received command address signal with the first reference signal and the second reference signal respectively. When the voltage corresponding to the command address signal is greater than the first reference voltage or less than the second reference voltage, a valid command address signal flag is output to the valid signal flag output terminal, and the path between the command address signal receiver and the command address signal transmitter is connected, so as to output the command address signal to the register clock driver and / or memory chip.
2. The communication interface signal receiving circuit as described in claim 1, characterized in that, The signal output control circuit is also used for: When the voltage corresponding to the command address signal is greater than the second reference voltage and less than the first reference voltage, a command address signal failure flag is output to the signal validity flag output terminal, and the path between the command address signal receiving terminal and the command address signal transmitting terminal is disconnected, so as to output the command address signal to the register clock driver and / or memory chip.
3. The communication interface signal receiving circuit as described in claim 2, characterized in that, The signal output control circuit includes: The system comprises a first comparison unit, a second comparison unit, and a judgment logic unit. The first input terminal of the first comparison unit is the first reference signal input terminal. The common terminal of the second input terminal of the first comparison unit and the first input terminal of the second comparison unit is the command address signal receiving terminal. The second input terminal of the second comparison unit is the second reference signal input terminal. The output terminals of the first and second comparison units are connected one-to-one with the two input terminals of the judgment logic unit. The first output terminal of the judgment logic unit is the command address signal sending terminal, and the second output terminal of the judgment logic unit is the signal validity flag output terminal. The first comparison unit is used to compare the command address signal with the first reference signal and output the corresponding first comparison result; The first comparison unit is used to compare the command address signal with the second reference signal and output the corresponding second comparison result; The judgment logic unit is used to output a command address signal valid flag to the signal valid flag output terminal when it is determined, based on the first comparison result and the second comparison result, that the voltage corresponding to the command address signal is less than the second reference voltage or the voltage corresponding to the command address signal is greater than the first reference voltage, and to connect the path between the command address signal receiving terminal and the command address signal transmitting terminal, so as to output the command address signal to the register clock driver and / or memory chip.
4. The communication interface signal receiving circuit as described in claim 3, characterized in that, The judgment logic unit is specifically used for: When the first comparison result and the second comparison result are consistent, and the first comparison unit outputs a first result representing a high level, the command address signal is determined to be valid; the command address signal is logically "1", and a command address signal validity flag is output to the signal validity flag output terminal, and a command address signal with logic "1" is output; When the first comparison result and the second comparison result are consistent, and the second comparison unit outputs a second result representing a low level, the command address signal is determined to be valid, and the logic of the command address signal is "0". The command address signal validity flag is output to the signal validity flag output terminal, and the command address signal with logic "0" is output.
5. The communication interface signal receiving circuit as described in claim 3, characterized in that, The judgment logic unit is further configured to, based on the first comparison result and the second comparison result, determine that when the voltage corresponding to the command address signal is greater than the second reference voltage and less than the first reference voltage, output a command address signal failure flag to the signal validity flag output terminal, and disconnect the path between the command address signal receiving terminal and the command address signal transmitting terminal, so as to shield the command address signal.
6. The communication interface signal receiving circuit as described in claim 5, characterized in that, The judgment logic unit is specifically used for: If the first comparison result and the second comparison result are inconsistent, the command address signal is determined to be invalid, and the path between the command address signal receiving end and the command address signal sending end is disconnected to shield the command address signal; and / or an invalid command address signal flag is output to the valid signal flag output end.
7. The communication interface signal receiving circuit as described in any one of claims 3 to 6, characterized in that, The first comparison unit and the second comparison unit are comparators; the judgment logic unit is a multiplexer.
8. The communication interface signal receiving circuit as described in any one of claims 1 to 6, characterized in that, The communication interface signal receiving circuit includes: A Schmitt trigger, wherein the signal input terminal of the Schmitt trigger is used to receive the command address signal, and the output terminal of the Schmitt trigger is connected to the register clock driver and the memory chip; the Schmitt trigger is used to compare the received command address signal with the first reference signal and the second reference signal respectively; When the voltage corresponding to the command address signal is less than the second reference voltage, the command address signal is output to the memory chip; when the voltage corresponding to the command address signal is greater than the second reference voltage and less than the first reference voltage, the command address signal with a voltage less than the second reference voltage is maintained to be output to the register clock driver and / or the memory chip. Alternatively, when the voltage corresponding to the command address signal is greater than the first reference voltage, the command address signal is output to the memory chip; when the voltage corresponding to the command address signal is greater than the second reference voltage and less than the first reference voltage, the command address signal with a voltage greater than the first reference voltage is maintained to be output to the register clock driver and / or the memory chip.
9. An energy storage system, characterized in that, Includes the communication interface signal receiving circuit as described in any one of claims 1 to 8.
10. A method for receiving signals from a communication interface, characterized in that, Applied to a storage system, the storage system including at least one memory chip and a communication interface signal receiving circuit as described in any one of claims 1 to 8, the communication interface signal receiving method comprising: Upon receiving a command address signal output from an external controller, the received command address signal is compared with a first reference signal and a second reference signal, respectively; wherein, the first reference voltage of the first reference signal is greater than the second reference voltage of the second reference signal; When the voltage corresponding to the command address signal is less than the second reference voltage or the voltage corresponding to the command address signal is greater than the first reference voltage, a valid command address signal flag is output to the valid signal flag output terminal, and the path between the command address signal receiving terminal and the command address signal transmitting terminal is connected, so as to output the command address signal to the register clock driver and / or memory chip; When the voltage corresponding to the command address signal is greater than the second reference voltage and less than the first reference voltage, a command address signal failure flag is output to the signal validity flag output terminal, and the path between the command address signal receiving terminal and the command address signal transmitting terminal is disconnected, so as to output the command address signal to the register clock driver and / or memory chip.