Semiconductor memory device and memory package including semiconductor memory device

Abstract

A semiconductor memory device and a memory package including the semiconductor memory device are disclosed. An example semiconductor memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array. The memory cell array includes memory cells for storing data. The second semiconductor layer is below the first semiconductor layer and includes peripheral circuitry for controlling the memory cell array. The peripheral circuitry includes one or more sub-word line drivers and a sub-word line decoder. The one or more sub-word line drivers drive word lines. The sub-word line decoder applies word line enable signals to the one or more sub-word line drivers based on a first intermediate word line enable signal and a second intermediate word line enable signal. The regions of the one or more sub-word line drivers and sub-word lines in the second semiconductor layer are below the regions of the plurality of memory cells in the first semiconductor layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0187933, filed on December 17, 2024, with the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to semiconductor memory devices and memory packages that include semiconductor memory devices. Background Technology

[0003] Semiconductor memory devices can be categorized into two types based on whether they retain stored data when disconnected from power. These categories include volatile memory devices, which lose stored data when disconnected from power, and non-volatile memory devices, which retain stored data when disconnected from power.

[0004] Various structures are being employed to increase the integration density and reduce the size of memory devices. However, the reduction in size is limited because memory devices must still include peripheral circuitry for driving the memory cell array and wiring structures for electrically connecting the memory cell array to the peripheral circuitry. Recently, methods have been used in which components included in the memory device are fabricated on separate wafers (rather than on a single wafer) and then bonded together. Summary of the Invention

[0005] This disclosure relates to semiconductor memory devices that can effectively reduce size and enhance performance, and memory packages that include semiconductor memory devices.

[0006] Generally, according to some aspects, a semiconductor memory device includes: a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes an array of memory cells connected to a plurality of word lines and a plurality of bit lines. The memory cell array includes a plurality of memory cells for storing data, the plurality of word lines extending in a first direction, and the plurality of bit lines extending in a second direction intersecting the first direction. The second semiconductor layer is below the first semiconductor layer in a third direction and includes peripheral circuitry for controlling the memory cell array, the third direction being perpendicular to both the first and second directions. The peripheral circuitry includes one or more sub-word line drivers and a sub-word line decoder. The one or more sub-word line drivers drive the plurality of word lines. The sub-word line decoder applies word line enable signals to the one or more sub-word line drivers based on a first intermediate word line enable signal and a second intermediate word line enable signal. In a plan view, a first region in the second semiconductor layer is below a memory region in the first semiconductor layer, the one or more sub-word line drivers and sub-word line decoder are in the first region, and the plurality of memory cells are in the memory region.

[0007] Generally, according to some aspects, a memory package includes: a substrate; and a plurality of memory chips stacked on the substrate. Each of the plurality of memory chips includes: a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array connected to a plurality of word lines and a plurality of bit lines. The memory cell array includes a plurality of memory cells for storing data, the plurality of word lines extending in a first direction, and the plurality of bit lines extending in a second direction intersecting the first direction. The second semiconductor layer is below the first semiconductor layer in a third direction and includes peripheral circuitry for controlling the memory cell array, the third direction being perpendicular to both the first and second directions. The peripheral circuitry includes one or more sub-word line drivers and sub-word line decoders. The one or more sub-word line drivers drive the plurality of word lines. The sub-word line decoders apply word line enable signals to the one or more sub-word line drivers based on a first intermediate word line enable signal and a second intermediate word line enable signal. In a plan view, a first region in the second semiconductor layer is below a memory region in the first semiconductor layer, the one or more sub-word line drivers and sub-word line decoders are in the first region, and the plurality of memory cells are in the memory region.

[0008] Generally, according to some aspects, a semiconductor memory device includes: a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes an array of memory cells connected to a plurality of word lines and a plurality of bit lines. The memory cell array includes a plurality of memory cells for storing data, the plurality of word lines extending in a first direction, and the plurality of bit lines extending in a second direction intersecting the first direction. The second semiconductor layer is below the first semiconductor layer in a third direction and includes peripheral circuitry for controlling the memory cell array, the third direction being perpendicular to both the first and second directions. The peripheral circuitry includes one or more sub-word line drivers and a sub-word line decoder. The one or more sub-word line drivers drive the plurality of word lines. The sub-word line decoder applies a word line enable signal to the one or more sub-word line drivers based on a first intermediate word line enable signal and a second intermediate word line enable signal. In a plan view, a first region in the second semiconductor layer is below a memory region in the first semiconductor layer, the one or more sub-word line drivers and the sub-word line decoder are in the first region, and the plurality of memory cells are in the memory region. The sub-word line decoder generates the word line enable signal based on the first intermediate word line enable signal and the second intermediate word line enable signal. Each of the first intermediate word line enable signal and the second intermediate word line enable signal oscillates between the power supply voltage and the ground voltage. The word line enable signal oscillates between the power supply voltage and a negative voltage.

[0009] In general, depending on some aspects, semiconductor memory devices and memory packages may have or employ a structure in which peripheral circuitry and memory cell arrays are stacked (e.g., a COP structure in which peripheral circuitry is formed below and then the memory cell array is stacked on top of the peripheral circuitry). Therefore, memory devices and memory packages can have relatively small dimensions.

[0010] Furthermore, semiconductor memory devices and memory packages can reduce wiring by arranging a sub-word line decoder adjacent to the sub-word line driver below the memory cell array, and because the sub-word line decoder applies a word line enable signal that swings between the supply voltage and the negative voltage to the sub-word line driver, the NBTI occurring in the PMOS transistors of the sub-word line driver and the PBTI occurring in the NMOS transistors of the sub-word line driver can be reduced. Attached Figure Description

[0011] Exemplary, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 This is a perspective view of an example of a semiconductor memory device.

[0013] Figure 2A This is a cross-sectional view of an example of a semiconductor memory device.

[0014] Figure 2B This is a cross-sectional view of an example of a semiconductor memory device.

[0015] Figure 3A and Figure 3B Show Figure 2A or Figure 2B Example of the first region in the text.

[0016] Figure 4 This is a schematic diagram illustrating an example of the structure of the memory cell region and the peripheral circuit region of a semiconductor memory device.

[0017] Figure 5 This is a block diagram illustrating an example of a semiconductor memory device.

[0018] Figure 6 Show Figure 5 An example of a first memory bank array in a semiconductor memory device.

[0019] Figure 7 It is shown Figure 5 A block diagram of an example of a first-line decoder in a semiconductor memory device.

[0020] Figure 8 It is shown Figure 7 The circuit diagram of an example main word line driver among multiple main word line drivers.

[0021] Figure 9 This shows an example of a subword line decoder and one or more sample subword line drivers.

[0022] Figure 10 It is shown Figure 9 The circuit diagram of an example sub-word line decoder.

[0023] Figure 11 It is shown Figure 9 The circuit diagram of an example sub-word line driver.

[0024] Figure 12A It is shown Figure 10 A waveform diagram illustrating an example of the operation of the sub-word line decoder.

[0025] Figure 12B It is shown Figure 11 A waveform diagram illustrating an example of the operation of a sub-word line driver.

[0026] Figure 13 It is used to describe Figure 2A An example diagram of a semiconductor memory device.

[0027] Figure 14 It is shown Figure 3A or Figure 3B A circuit diagram of an example bit-line sense amplifier.

[0028] Figure 15 and Figure 16 This is a perspective view of an example of a semiconductor memory device.

[0029] Figure 17 and Figure 18 This is a cross-sectional view of an example memory package.

[0030] Figure 19 This is a block diagram illustrating an example of a memory system.

[0031] Figure 20 It is shown Figure 19 A block diagram of an example memory controller.

[0032] Figure 21 This is a flowchart illustrating an example of a method for manufacturing a semiconductor memory device.

[0033] Figure 22 This is a diagram illustrating an example of the manufacturing process of a semiconductor device. Detailed Implementation

[0034] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, the same reference numerals denote the same elements.

[0035] Figure 1 This is a perspective view of an example of a semiconductor memory device.

[0036] exist Figure 1 In the figure, two directions that are parallel or substantially parallel to the first surface (e.g., the top surface) of the substrate and intersect each other are called the first direction DR1 (e.g., the X-axis direction) and the second direction DR2 (e.g., the Y-axis direction). Furthermore, a direction perpendicular or substantially perpendicular to the first surface of the substrate is called the third direction VD (e.g., the Z-axis direction). The third direction VD can be referred to as the vertical direction. For example, the first direction DR1 and the second direction DR2 can be perpendicular or substantially perpendicular to each other. Furthermore, the third direction VD can be perpendicular or substantially perpendicular to both the first direction DR1 and the second direction DR2. Additionally, the directions indicated by the arrows in the figure and their opposite directions are considered to be the same direction. The definitions of the first direction DR1, the second direction DR2, and the third direction VD are the same in the following figures.

[0037] Reference Figure 1 The semiconductor memory device 100 may include a first semiconductor layer L1 and a second semiconductor layer L2.

[0038] The first semiconductor layer L1 and the second semiconductor layer L2 may be disposed or stacked on a third-direction VD. For example, the first semiconductor layer L1 may be stacked on the second semiconductor layer L2 on the third-direction VD, and the second semiconductor layer L2 may be disposed on the third-direction VD below the first semiconductor layer L1 (e.g., directly or indirectly below the first semiconductor layer L1). However, the example implementation is not limited to this. For example, the semiconductor memory device 100 may be flipped during the manufacturing process, and therefore the second semiconductor layer L2 may be stacked on the first semiconductor layer L1 on the third-direction VD. In some implementations, reference will be made to... Figure 15 and Figure 16 As described, three or more semiconductor layers can be stacked on a third-party VD.

[0039] The first semiconductor layer L1 may include multiple word lines (WL), multiple bit lines (BTL), and a memory cell array (MCA). Therefore, the first semiconductor layer L1 may be referred to as a memory cell region or a cell wafer.

[0040] For example, if referencing Figure 2A and Figure 2B As described, the first semiconductor layer L1 may include a first substrate. Multiple word lines WL, multiple bit lines BTL, and a memory cell array MCA may be disposed and / or formed on the first substrate. For example, each of the multiple word lines WL may extend in a first direction DR1, and the multiple word lines WL may be arranged along a second direction DR2. For example, each of the multiple bit lines BTL may extend in the second direction DR2, and the multiple bit lines BTL may be arranged along the first direction DR1. For example, the memory cell array MCA may be connected to the multiple word lines WL and the multiple bit lines BTL.

[0041] The second semiconductor layer L2 may include a peripheral circuit PCKT, which controls the memory cell array MCA. Therefore, the second semiconductor layer L2 may be referred to as the peripheral circuit region or the peripheral wafer.

[0042] For example, if referencing Figure 2A and Figure 2B As described, the second semiconductor layer L2 may include a second substrate. Peripheral circuitry PCKT may be disposed and / or formed on the second substrate. For example, the peripheral circuitry PCKT may control a memory cell array MCA.

[0043] In some embodiments, the first semiconductor layer L1 and the second semiconductor layer L2 can be fabricated separately, and then the first semiconductor layer L1 and the second semiconductor layer L2 can be connected to each other by a bonding scheme (or method). For example, as will be referred to Figure 2A and Figure 2BDescribed, the first semiconductor layer L1 may include a first bonding pad (or solder pad), the second semiconductor layer L2 may include a second bonding pad, and the bonding scheme may refer to a method of electrically or physically connecting a bonding metal pattern (e.g., the first bonding pad) formed in the first semiconductor layer L1 to a bonding metal pattern (e.g., the second bonding pad) formed in the second semiconductor layer L2. For example, the bonding pad may be formed of copper (Cu), and the bonding scheme may be a Cu-Cu bonding scheme. Alternatively, the bonding pad may be formed of aluminum (Al) or tungsten (W).

[0044] The memory cell array (MCA) may include multiple general-purpose memory cells. The peripheral circuitry (PCKT) may include a sub-word line decoder (SDEC). The SDEC provides a word line enable signal that swings between a power supply voltage and a negative voltage to one or more sub-word line drivers. The multiple memory cells in the first semiconductor layer L1 and the SDEC in the second semiconductor layer L2 may be arranged to be partially and / or completely stacked in a planar view or on a plane, which will refer to... Figure 2A and Figure 2B The description is as follows: That is, the first region in the second semiconductor layer L2 may be below the memory region in the first semiconductor layer L1, the sub-word line decoder (SDEC) is in the first region, and the memory cell array (MCA) is in the memory region. For example, the memory region may be superimposed on the first region.

[0045] Figure 2A This is a cross-sectional view of an example of a semiconductor memory device.

[0046] Reference Figure 1 and Figure 2A The semiconductor memory device 100a may include a first semiconductor layer L1 and a second semiconductor layer L2.

[0047] The first semiconductor layer L1 may include a first substrate SUB1, a memory cell array MCAa, a first bonding pad PD_L1, a first contact CT_L1, and a first insulating layer IL1. The second semiconductor layer L2 may include a second substrate SUB2, peripheral circuitry PCKT, a second bonding pad PD_L2, a second contact CT_L2, and a second insulating layer IL2.

[0048] The first substrate SUB1 may be a support layer for components (or elements) supporting the first semiconductor layer L1, and the second substrate SUB2 may be a support layer for components supporting the second semiconductor layer L2. For example, each of the first substrate SUB1 and the second substrate SUB2 may be a silicon substrate and may be referred to as a substrate. The first insulating layer IL1 may cover the components of the first semiconductor layer L1, and the second insulating layer IL2 may cover the components of the second semiconductor layer L2.

[0049] The memory cell array MCAa may include multiple general-purpose memory cells (NMCs). The peripheral circuitry PCKT may include a row decoder (RDEC), a bit line sense amplifier (BLSA), a sub-word line driver (SWD), a sub-word line decoder (SDEC), and a column decoder (CDEC), etc.

[0050] The bit line sense amplifier (BLSA), sub-word line driver (SWD), and sub-word line decoder (SDEC) can be disposed in a first region RG11 in the second semiconductor layer L2. The row decoder (RDEC) can be disposed in a second region RG12 in the second semiconductor layer L2 adjacent to the first region RG11, and the column decoder (CDEC) can be disposed in a third region RG13 in the second semiconductor layer L2 adjacent to the first region RG11. The first region RG11, which houses the bit line sense amplifier (BLSA), sub-word line driver (SWD), and sub-word line decoder (SDEC), is located below the memory region of the memory cell array (MCAa) in the first semiconductor layer L1 in the vertical direction VD. That is, the first region RG11 is located below the memory cell array (MCAa) (e.g., the memory region) in a plan view.

[0051] The memory cell array MCAa and the peripheral circuit PCKT can be electrically connected to each other via a first contact CT_L1 and a second contact CT_L2, and a first bonding pad PD_L1 and a second bonding pad PD_L2. For example, the memory cell array MCAa can be electrically connected to the first contact CT_L1 and the first bonding pad PD_L1, and the peripheral circuit PCKT can be electrically connected to the second contact CT_L2 and the second bonding pad PD_L2. Furthermore, the memory cell array MCAa and the peripheral circuit PCKT can be electrically connected to each other by electrically connecting the first bonding pad PD_L1 and the second bonding pad PD_L2. Although not shown in detail, at least one conductive line and / or contact can also be formed to connect the memory cell array MCAa to the first bonding pad PD_L1, and at least one conductive line and / or contact can also be formed to connect the peripheral circuit PCKT to the second bonding pad PD_L2.

[0052] In some embodiments, the first semiconductor layer L1 can be fabricated by forming a memory cell array MCAa, a first bonding pad PD_L1, a first contact CT_L1, and a first insulating layer IL1 in and / or on the first substrate SUB1. The second semiconductor layer L2 can be fabricated by forming a peripheral circuit PCKT, a second bonding pad PD_L2, a second contact CT_L2, and a second insulating layer IL2 in and / or on the second substrate SUB2. The first semiconductor layer L1 can be flipped, and bonding pads PD_L1 and PD_L2 can be connected using a bonding scheme. Therefore, the first semiconductor layer L1 and the second semiconductor layer L2 can be electrically connected to a third-party VD.

[0053] although Figure 2A An example is shown where semiconductor layers L1 and L2 include a pair of bonding pads PD_L1 and PD_L2 and a pair of contacts CT_L1 and CT_L2. However, the example implementation is not limited to this, and the number of bonding pads and contacts included in semiconductor layers L1 and L2 may be determined differently.

[0054] Semiconductor memory device 100a may have or employ a structure in which peripheral circuitry PCKT and memory cell array MCAa are stacked (e.g., a cell-on-periphery (COP) structure in which peripheral circuitry PCKT is formed below and then memory cell array MCAa is stacked on top of peripheral circuitry PCKT). Therefore, semiconductor memory device 100a may have a relatively small size.

[0055] Figure 2B This is a cross-sectional view of an example of a semiconductor memory device.

[0056] exist Figure 2B For the sake of brevity, the ellipsis and Figure 2A The description is repetitive or overlapping.

[0057] Reference Figure 1 and Figure 2B The semiconductor memory device 100b may include a first semiconductor layer L1 and a second semiconductor layer L2.

[0058] The first semiconductor layer L1 may include a first substrate SUB1, a memory cell array MCAb, a first bonding pad PD_L1, a first contact CT_L1, and a first insulating layer IL1. The second semiconductor layer L2 may include a second substrate SUB2, peripheral circuitry PCKT, a second bonding pad PD_L2, a second contact CT_L2, and a second insulating layer IL2.

[0059] The memory cell array MCAb may include multiple general-purpose memory cells (NMCs) and multiple error-correcting code (ECC) memory cells (EMCs). The multiple general-purpose memory cells (NMCs) may store general-purpose data (e.g., user data), and the multiple ECC memory cells (EMCs) may store ECC data (e.g., parity data) that is associated with or related to the general-purpose data.

[0060] In computing, telecommunications, information theory, and coding theory, forward error correction (FEC), or channel coding, is a technique used to control errors in data transmission over unreliable or noisy communication channels. For example, a transmitter encodes a message in a redundant manner (most commonly by using error-correcting codes or ECC). Redundancy allows the receiver not only to detect errors occurring anywhere in the message but also to often correct a limited number of errors. Therefore, a reverse channel for requesting retransmissions is not required.

[0061] For example, when ordinary data is written to multiple ordinary memory cells (NMCs), ECC data associated with the ordinary data to be written can be generated using an ECC encoder and an ECC. The ordinary data and ECC data can be stored in the multiple ordinary memory cells (NMCs) and multiple ECC memory cells (EMCs), respectively. For example, when reading ordinary data from the multiple ordinary memory cells (NMCs), an ECC decoder and an ECC can be used to perform ECC decoding on the ordinary data based on the ECC data. When the result of the ECC decoding determines that the ordinary data includes at least one error bit, the ECC decoder can perform error correction and output corrected ordinary data in the case of correctable errors (CE), and the ECC decoder can declare that ECC decoding is impossible in the case of uncorrectable errors (UE). For example, the ECC can be a single error-correcting (SEC) code or a single error-correcting and double error-detecting (SECDED) code, but the example implementation is not limited to this.

[0062] The bit line sense amplifier (BLSA), sub-word line driver (SWD), and sub-word line decoder (SDEC) can be disposed in a first region RG11 in the second semiconductor layer L2. The row decoder (RDEC) can be disposed in a second region RG12 in the second semiconductor layer L2 adjacent to the first region RG11, and the column decoder (CDEC) can be disposed in a third region RG13 in the second semiconductor layer L2 adjacent to the first region RG11. The first region RG11, where the bit line sense amplifier (BLSA), sub-word line driver (SWD), and sub-word line decoder (SDEC) are disposed, is located below the memory region in the vertical direction VD where the memory cell array (MCAb) is disposed. That is, the first region RG11 is located below the memory cell array (MCAb) (e.g., the memory region) in a plan view.

[0063] The memory cell array MCAb and the peripheral circuit PCKT can be electrically connected to each other via the first contact CT_L1 and the second contact CT_L2, as well as the first bonding pad PD_L1 and the second bonding pad PD_L2.

[0064] Figure 3A and Figure 3B Show Figure 2A or Figure 2B Example of the first region in the text.

[0065] Reference Figure 3A The bit line sense amplifier (BLSA), sub-word line decoder (SDEC), and one or more sub-word line drivers (SWDs) may be disposed in the first region RG11a and may be arranged in the first direction DR1. The one or more sub-word line drivers (SWDs) may be disposed adjacent to the first side of the sub-word line decoder (SDEC) extending in the second direction DR2.

[0066] Reference Figure 3B The bit line sense amplifier (BLSA), one or more sub-word line drivers (SWDs), and the sub-word line decoder (SDEC) may be disposed in the first region RG11b and may be arranged in the first direction DR1. The one or more sub-word line drivers (SWDs) may be positioned adjacent to a second side of the sub-word line decoder (SDEC) extending in the second direction DR2. This second side may be opposite to the first side of the sub-word line decoder (SDEC). That is, the one or more sub-word line drivers (SWDs) may be disposed between the bit line sense amplifier (BLSA) and the sub-word line decoder (SDEC).

[0067] Figure 4 This is a schematic diagram illustrating an example of the structure of the memory cell region and the peripheral circuit region of a semiconductor memory device.

[0068] Reference Figure 4 The memory cell region MCR may include multiple sub-array regions SCA and multiple contact regions CON. Multiple memory cells may be formed in each of the sub-array regions SCA. In this case, the memory cell may include a cell transistor and a cell capacitor, and each memory cell formed in the sub-array region SCA may include a cell capacitor and a cell transistor connected to the bit line and word line. Figure 4 The memory cell region MCR in the memory can be compared with Figure 1 The memory cell array (MCA) corresponds to this.

[0069] Figure 1 The memory cell array (MCA) can include multiple memory blocks. Memory cells connected to word lines (WL) can form a single memory block. Each subarray region (SCA) can be included in a single memory block and can be a cell array region. At least one surface of each subarray region (SCA) can be configured to be separate from the other subarray regions (SCA).

[0070] Each of the contact regions CON can be located between two different subarray regions SCA. Multiple contact elements CT can be located in each of the contact regions CON. The contact elements CT electrically connect the word line WL to the sub-word line driver SWD formed in the peripheral circuit region PCR.

[0071] Multiple word lines WL extending in the first direction DR1 may be located in the memory cell region MCR. For example, word lines WL may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2 so as to be parallel to each other.

[0072] In some implementations, the word line WL may extend across the subarray region SCA and the contact region CON.

[0073] Multiple contact elements (CTs) connected to all word lines WL intersecting with the contact region CON can be formed in each of the contact regions CON. That is, all word lines WL located in two subarray regions SCA set adjacent to the contact region CON can be driven by contact elements (CTs) formed in one contact region CON.

[0074] The peripheral circuit region PCR may include multiple sub-word line drivers (SWDs), multiple sub-word line decoders (SDECs), and multiple bit line sense amplifiers (BLSAs). For example, the sub-word line drivers (SWDs), sub-word line decoders (SDECs), and bit line sense amplifiers (BLSAs) corresponding to a subarray region SCA may be arranged sequentially on a plane extending from the first direction DR1 and the second direction DR2.

[0075] In some implementations, each of the sub-word line drivers SWD may (e.g., in the vertical direction VD) be located (e.g., positioned) below the corresponding one in the contact area CON and may be electrically connected to the contact CT.

[0076] The sub-word line decoder SDEC can generate a word line enable signal that swings between the power supply voltage and the negative voltage by decoding the first intermediate word line enable signal and the second intermediate word line enable signal, and can provide the word line enable signal to the adjacent sub-word line driver SWD, each of the first intermediate word line enable signal and the second intermediate word line enable signal swinging between the power supply voltage and the ground voltage.

[0077] Bit line sense amplifier (BLSA) can be connected to bit lines formed in subarray region SCA and can be configured to read data from or write data to memory cells formed in subarray region SCA.

[0078] Figure 5 This is a block diagram illustrating an example of a semiconductor memory device.

[0079] Reference Figure 5 The semiconductor memory device 200 may include peripheral circuitry 201 and a memory cell array 310.

[0080] The peripheral circuitry 201 may include control logic circuitry 210, address register 220, memory control logic 230, refresh control circuitry 400, row address multiplexer 240, column address latch 250, row decoder 260, column decoder 270, sense amplifier unit 285, input / output (I / O) gating circuitry 290, error correction code (ECC) engine 350, clock buffer 225, strobe signal generator 235, voltage generator 385, negative voltage (NV) generator 387, and data I / O buffer 320.

[0081] The memory cell array 310 may include a first memory array 310a to a sixteenth memory array 310p. The row decoder 260 may include a first row decoder 260a to a sixteenth row decoder 260p respectively coupled to the first memory array 310a to the sixteenth memory array 310p, the column decoder 270 may include a first column decoder 270a to a sixteenth column decoder 270p respectively coupled to the first memory array 310a to the sixteenth memory array 310p, and the sense amplifier unit 285 may include a first sense amplifier 285a to a sixteenth sense amplifier 285p respectively coupled to the first memory array 310a to the sixteenth memory array 310p.

[0082] The first memory arrays 310a to 16th memory arrays 310p, the first row decoders 260a to 16th row decoders 260p, the first column decoders 270a to 16th column decoders 270p, and the first sense amplifiers 285a to 16th sense amplifiers 285p can form the first to sixteenth memory arrays. Each of the first memory arrays 310a to 16th memory arrays 310p includes a plurality of memory cells MC formed at the intersection of multiple word lines WL and multiple bit lines BTL.

[0083] Address register 220 can receive address ADDR, including bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from the external memory controller. Address register 220 can provide the received bank address BANK_ADDR to the bank control logic 230, the received row address ROW_ADDR to the row address multiplexer 240 and the refresh control circuit 400, and the received column address COL_ADDR to the column address latch 250.

[0084] The memory bank control logic 230 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. One of the first row decoders 260a to the sixteenth row decoders 260p corresponding to the memory bank address BANK_ADDR is activated in response to the memory bank control signal, and one of the first column decoders 270a to the sixteenth column decoders 270p corresponding to the memory bank address BANK_ADDR is activated in response to the memory bank control signal.

[0085] The row address multiplexer 240 can receive the row address ROW_ADDR from the address register 220 and the refresh row address REF_ADDR from the refresh control circuit 400. The row address multiplexer 240 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address SRA. The row address SRA output from the row address multiplexer 240 is applied to the first row decoder 260a through the sixteenth row decoder 260p.

[0086] The refresh control circuit 400 can sequentially increase or decrease the refresh row address REF_ADDR in response to the third control signal CTL3 from the control logic circuit 210.

[0087] The row decoders activated by the memory bank control logic 230 in the first row decoder 260a to the sixteenth row decoder 260p can decode the row address SRA output from the row address multiplexer 240 and can activate the word line corresponding to the row address SRA. For example, the activated row decoder applies a word line drive voltage to the word line corresponding to the row address.

[0088] Column address latch 250 can receive column address COL_ADDR from address register 220 and can temporarily store the received column address COL_ADDR. In some embodiments, in burst mode, column address latch 250 can generate a column address COL_ADDR' incremented from the received column address COL_ADDR. Column address latch 250 can apply the temporarily stored or generated column address COL_ADDR' to the first column decoder 270a through the sixteenth column decoder 270p.

[0089] The activated column decoders in the first column decoder 270a to the sixteenth column decoder 270p can activate the sense amplifiers corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I / O gate circuit 290.

[0090] I / O gate circuit 290 may include circuitry for gating input / output data, and may also include input data masking logic, a read data latch for storing data output from the first memory array 310a to the sixteenth memory array 310p, and a write driver for writing data to the first memory array 310a to the sixteenth memory array 310p.

[0091] A codeword CW read from a selected memory array from the first memory array 310a to the sixteenth memory array 310p can be sensed by a sense amplifier coupled to the selected memory array from which data will be read, and can be stored in a read data latch. After ECC decoding of the codeword CW by the ECC engine 350, the codeword CW stored in the read data latch can be provided to the data I / O buffer 320 as data DTA. The data I / O buffer 320 can convert the data DTA into a data signal DQ, and can send the data signal DQ together with the data strobe signal DQS to the external memory controller.

[0092] A data signal DQ, which can be written to a selected memory array from the first memory array 310a to the sixteenth memory array 310p, can be provided from an external memory controller to a data I / O buffer 320. The data I / O buffer 320 can convert the data signal DQ into a data DTA and provide the data DTA to an ECC engine 350. The ECC engine 350 can perform ECC encoding on the data DTA to generate parity bits, and the ECC engine 350 can provide a codeword CW, including the data DTA and the parity bits, to an I / O gate circuit 290. The I / O gate circuit 290 can write the codeword CW to a subpage in the selected memory array via a write driver.

[0093] The data I / O buffer 320 can provide the data signal DQ to the ECC engine 350 by converting the data signal DQ from the external memory controller into the data DTA during the write operation of the semiconductor memory device 200, and can convert the data DTA from the ECC engine 350 into the data signal DQ during the read operation of the semiconductor memory device 200, and can send the data signal DQ and the data strobe signal DQS to the external memory controller.

[0094] ECC engine 350 can perform ECC encoding on data DTA and can perform ECC decoding on codeword CW based on the second control signal CTL2 from control logic circuit 210.

[0095] Clock buffer 225 can receive clock signal CK, generate internal clock signal ICK by buffering clock signal CK, and provide internal clock signal ICK to circuit components that process command CMD and address ADDR.

[0096] The strobe signal generator 235 can receive a clock signal CK, generate a data strobe signal DQS based on the clock signal CK, and provide the data strobe signal DQS to the data I / O buffer 320.

[0097] The voltage generator 385 can generate a power supply voltage VPP based on the external voltage VDD received from an external device, and can provide the power supply voltage VPP to the sub-word line decoder, sub-word line driver, etc.

[0098] The negative voltage generator 387 can generate a negative voltage DVBB2 and can provide the negative voltage DVBB2 to sub-word line decoders, sub-word line drivers, etc.

[0099] Although not shown, the sub-word line decoder and sub-word line driver may be located below the memory cell array 310.

[0100] Control logic circuitry 210 controls the operation of semiconductor memory device 200. For example, control logic circuitry 210 generates control signals for semiconductor memory device 200 to perform write operations, read operations, and refresh operations. Control logic circuitry 210 includes command decoder 211 and mode register 212. Command decoder 211 decodes commands (CMD) received from an external memory controller, and mode register 212 sets the operating mode of semiconductor memory device 200.

[0101] For example, the command decoder 211 can generate control signals corresponding to the command CMD by decoding the write enable signal, row address strobe signal, column address strobe signal, chip select signal, etc. The control logic circuit 210 can generate a first control signal CTL1 for controlling the I / O gate circuit 290, a second control signal CTL2 for controlling the ECC engine 350, and a third control signal CTL3 for controlling the refresh control circuit 400.

[0102] Figure 6 Show Figure 5 An example of a first memory bank array in a semiconductor memory device.

[0103] Reference Figure 6The first memory bank array 310a may include multiple word lines WL0 to WLm-1 (where m is a natural number greater than 2), multiple bit lines BL0 to BLn-1 (where n is a natural number greater than 2), and multiple memory cells MC disposed at the intersections of the word lines WL0 to WLm-1 and the bit lines BL0 to BLn-1. Each memory cell MC includes a cell transistor coupled to each of the word lines WL0 to WLm-1 and each of the bit lines BL0 to BLn-1, and a cell capacitor coupled to the cell transistor.

[0104] Each of the memory cells MC may have a DRAM cell structure. Each of the word lines WL0 to WLm-1 extends in a first direction DR1, and each of the bit lines BL1 to BLn-1 extends in a second direction DR2 that intersects the first direction DR1.

[0105] Word lines WL0 to WLm-1, which are associated with multiple memory cells MC, can be referred to as rows of the first memory bank array 310a, and bit lines BL0 to BLn-1, which are associated with multiple memory cells MC, can be referred to as columns of the first memory bank array 310a.

[0106] Although semiconductor memory devices are described based on DRAM, semiconductor memory devices can be any volatile memory device and / or any non-volatile memory device (e.g., static random access memory (SRAM), flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), etc.).

[0107] Figure 7 It is shown Figure 5 A block diagram of an example of a first-line decoder in a semiconductor memory device.

[0108] Reference Figure 7 The first line decoder 260a may include a pre-decoder 330 and multiple main word line drivers 340a, 340b, ..., 340g. Here, g can be an integer greater than 2.

[0109] The predecoder 330 can generate a decoded row address DRA by decoding the row address SRA, and can provide the decoded row address DRA to multiple master word line drivers 340a, 340b, ..., 340g.

[0110] Each of the plurality of master word line drivers 340a, 340b, ..., 340g can generate a corresponding intermediate word line enable signal NWEIB0, NWEIB1, ..., NWEIBf based on the decoded row address DRA, and can provide at least a portion of the intermediate word line enable signals NWEIB0, NWEIB1, ..., NWEIBf to the corresponding sub-word line decoder. Here, g can be an integer greater than 1. In one example, the row decoder RDEC can generate a first intermediate word line enable signal NWEIB0 and a second intermediate word line enable signal NWEIB1 based on the decoded row address DRA.

[0111] Figure 8 It is shown Figure 7 The circuit diagram of an example main word line driver among multiple main word line drivers.

[0112] Despite Figure 8 The configuration of main word line driver 340a is shown for ease of explanation, but each of the main word line drivers 340b, ..., 340g may have a configuration that is substantially the same as that of main word line driver 340a.

[0113] Reference Figure 8 The main word line driver 340a may include inverters INV1, INV2 and INV3, n-channel metal-oxide-semiconductor (NMOS) transistors 343, 344, 345 and 346, and a keeper transistor 347.

[0114] Inverter INV1 may include a p-channel metal-oxide-semiconductor (PMOS) transistor 341a and an NMOS transistor 341b. PMOS transistor 341a may be connected between a power supply voltage VPP and a first node N11, and may have a gate for receiving a block access signal PDPXIP (or PDPXIPD). NMOS transistor 341b may be connected between the first node N11 and an NMOS transistor 343, and may also have a gate for receiving the block access signal PDPXIP. NMOS transistors 343, 344, 345, and 346 may be connected in series between NMOS transistor 341b and ground voltage VSS.

[0115] NMOS transistor 343 may have a gate for receiving control signal VPP_VT, NMOS transistor 344 may have a gate for receiving decoded row address DRA345, NMOS transistor 345 may have a gate for receiving decoded row address DRA678, and NMOS transistor 346 may have a gate for receiving block select signal BSEL.

[0116] Each of the NMOS transistors 341b, 343, 344, 345, and 346 can form a pull-down network to discharge the first node N11 using the ground voltage VSS when each of the NMOS transistors 341b, 343, 344, 345, and 346 is turned on based on the block access signal PDPXIP, the control signal VPP_VT, the decoded row address DRA345, the decoded row address DRA678, and the block select signal BSEL.

[0117] Inverter INV2 may include a PMOS transistor 348a and an NMOS transistor 348b. PMOS transistor 348a may be connected between the power supply voltage VPP and the second node N12, and may have a gate coupled to the first node N11. NMOS transistor 348b may be connected between the second node N12 and the ground voltage VSS, and may also have a gate coupled to the first node N11. Therefore, inverter INV2 can invert the logic level of the first node N11 and output the inverted logic level to the second node N12.

[0118] Inverter INV3 may include a PMOS transistor 349a and an NMOS transistor 349b. PMOS transistor 349a may be connected between the power supply voltage VPP and the third node N13, and may have a gate coupled to the second node N12. NMOS transistor 349b may be connected between the third node N13 and the ground voltage VSS, and may also have a gate coupled to the second node N12. Therefore, inverter INV3 can invert the logic level of the second node N12 and output a first intermediate word line enable signal NWEIB0 at the third node N13, swinging between the power supply voltage VPP and the ground voltage VSS.

[0119] The retainer transistor 347 may be connected between the power supply voltage VPP and the first node N11, and may have a gate coupled to the second node N12. Therefore, the retainer transistor 347 may maintain the logic level of the first node N11 at a logic high level based on the logic level of the second node N12.

[0120] Each of the main word line drivers 340b, ..., 340g can generate a corresponding intermediate word line enable signal NWEIB1, ..., NWEIBf, each of which swings between the power supply voltage VPP and the ground voltage VSS. In one example, the line decoder RDEC may include a first main word line driver and a second main word line driver. The first main word line driver may be configured to generate a first intermediate word line enable signal NWEIB0 based on the decoded line address DRA, the block access signal PDPXIP, and the block select signal BSEL, and the second main word line driver may be configured to generate a second intermediate word line enable signal NWEIB1 based on the decoded line address DRA, the block access signal PDPXIP, and the block select signal BSEL.

[0121] Figure 9 This shows an example of a subword line decoder and one or more sample subword line drivers.

[0122] Reference Figure 9 The sub-word line decoder 410 can apply the word line enable signal NWEIB to one or more sub-word line drivers 420, 430, 440 and 450.

[0123] Sub-word line decoder 410 can be used with Figure 2A or Figure 2B The sub-word line decoder corresponds to SDEC, and one or more sub-word line drivers 420, 430, 440, and 450 can be used with... Figure 2A or Figure 2B The sub-word line driver SWD corresponds to this.

[0124] Sub-word line decoder 410 can be coupled to power supply voltage VPP and negative voltage DVBB2, can receive a first intermediate word line enable signal NWEIB0 and a second intermediate word line enable signal NWEIB1, can generate a word line enable signal NWEIB that swings between power supply voltage VPP and negative voltage DVBB2 by decoding the first intermediate word line enable signal NWEIB0 and the second intermediate word line enable signal NWEIB1, and can apply (e.g., provide) the word line enable signal NWEIB to sub-word line drivers 420, 430, 440 and 450.

[0125] Each of the first intermediate word line enable signal NWEIB0 and the second intermediate word line enable signal NWEIB1 can swing between the power supply voltage VPP and the ground voltage VSS.

[0126] Sub-word line driver 420 can drive the corresponding word line WL0 using power supply voltage VPP or negative voltage DVBB2 based on word line enable signal NWEIB, first drive signal PXID0, and second drive signal PXIB0. Sub-word line driver 430 can drive the corresponding word line WL2 using power supply voltage VPP or negative voltage DVBB2 based on word line enable signal NWEIB, first drive signal PXID2, and second drive signal PXIB2.

[0127] Sub-word line driver 440 can drive the corresponding word line WL4 using power supply voltage VPP or negative voltage DVBB2 based on word line enable signal NWEIB, first drive signal PXID4, and second drive signal PXIB4. Sub-word line driver 450 can drive the corresponding word line WL6 using power supply voltage VPP or negative voltage DVBB2 based on word line enable signal NWEIB, first drive signal PXID6, and second drive signal PXIB6.

[0128] The first drive signals PXID0, PXID2, PXID4, and PXID6, and the second drive signals PXIB0, PXIB2, PXIB4, and PXIB6 can be generated by a drive signal generator or Figure 5 It is generated by the line decoder 260 in the middle.

[0129] The voltage level of the negative voltage DVBB2 is lower than the voltage level of the ground voltage VSS, and the amplitude of the negative voltage DVBB2 may be less than the amplitude of the negative voltage used to drive word lines in a conventional semiconductor memory device. Furthermore, the amplitude of the power supply voltage VPP may be less than the amplitude of the power supply voltage used to drive word lines in a conventional semiconductor memory device. Each of the sub-word line drivers 420, 430, 440, and 450 may include at least one PMOS transistor and one or more NMOS transistors.

[0130] When a high electric field is applied to the gate of a PMOS transistor for an extended period, the negative bias used in the semiconductor device becomes unstable with temperature variations. This is called negative bias temperature instability (NBTI). When NBTI occurs, the threshold voltage of the PMOS transistor increases, and the performance of the semiconductor memory device can degrade. Conversely, an increase in the threshold voltage of an NMOS transistor is called positive bias temperature instability (PBTI), and when PBTI occurs, the threshold voltage Vth of the NMOS transistor increases.

[0131] As mentioned above, because the sub-word line decoder 410 applies a word line enable signal NWEIB, which swings between the power supply voltage VPP and the negative voltage DVBB2, to the sub-word line drivers 420, 430, 440, and 450, the NBTI occurring in the PMOS transistors of the sub-word line drivers 420, 430, 440, and 450, and the PBTI occurring in the NMOS transistors of the sub-word line drivers 420, 430, 440, and 450, can be reduced. Therefore, the performance of the semiconductor memory device 200 can be enhanced.

[0132] Figure 10 It is shown Figure 9 The circuit diagram of an example sub-word line decoder.

[0133] Reference Figure 10 The sub-word decoder 410 may include a first PMOS transistor 411, a second PMOS transistor 412, a first NMOS transistor 413, a second NMOS transistor 414, and an inverter 415.

[0134] A first PMOS transistor 411 may be connected between a power supply voltage VPP and a first node N21, and may have a gate for receiving a first intermediate word line enable signal NWEIB0. A second PMOS transistor 412 may be connected between the first node N21 and the second node N22, and may have a gate for receiving a second intermediate word line enable signal NWEIB1.

[0135] The first NMOS transistor 413 may be connected between the second node N22 and the negative voltage DVBB2, and may have a gate for receiving the block access signal PDPXIPD. The second NMOS transistor 414 may be connected in parallel with the first NMOS transistor 413 between the second node N22 and the negative voltage DVBB2, and may have a gate for receiving the word line enable signal NWEIB.

[0136] Inverter 415 can output a word line enable signal NWEIB that swings between the supply voltage VPP and the negative voltage DVBB2 by inverting the logic level (e.g., voltage level) at the second node N22.

[0137] When each of the first intermediate word line enable signal NWEIB0, the second intermediate word line enable signal NWEIB1, and the block access signal PDPXIPD has a power supply voltage level VPP, the first PMOS transistor 411 and the second PMOS transistor 412 are turned off, the first NMOS transistor 413 is turned on, and the second node N22 is driven at a negative voltage level DVBB2. The inverter 415 can output a word line enable signal NWEIB with a power supply voltage level VPP by inverting the negative voltage level DVBB2 at the second node N22. In other words, based on the power supply voltage level VPP of each of the first intermediate word line enable signal NWEIB0, the second intermediate word line enable signal NWEIB1, and the block access signal PDPXIPD, the inverter 415 can output a word line enable signal NWEIB with a power supply voltage level VPP. Furthermore, based on the word line enable signal NWEIB having a power supply voltage VPP, the second NMOS transistor 414 can be turned on and provides an additional current path between the second node N22 and the negative voltage DVBB2.

[0138] When each of the first intermediate word line enable signal NWEIB0, the second intermediate word line enable signal NWEIB1, and the block access signal PDPXIPD has a voltage level of ground VSS (or, when each of the first intermediate word line enable signal NWEIB0 and the second intermediate word line enable signal NWEIB1 has a voltage level of ground VSS and the block access signal PDPXIPD has a voltage level of negative DVBB2), the first PMOS transistor 411 and the second PMOS transistor 412 are turned on, the first NMOS transistor 413 is turned off, and the second node N22 is driven at the voltage level of the power supply voltage VPP. The inverter 415 can output a word line enable signal NWEIB with a voltage level of negative DVBB2 by inverting the voltage level of the power supply voltage VPP at the second node N22. In other words, based on the voltage level of each of the first intermediate word line enable signal NWEIB0, the second intermediate word line enable signal NWEIB1, and the block access signal PDPXIPD having a ground voltage VSS (or, based on the voltage level of each of the first intermediate word line enable signal NWEIB0 and the second intermediate word line enable signal NWEIB1 having a ground voltage VSS and the block access signal PDPXIPD having a negative voltage DVBB2), the inverter 415 can output a word line enable signal NWEIB having a negative voltage DVBB2. Furthermore, based on the word line enable signal NWEIB having a negative voltage DVBB2, the second NMOS transistor 414 can be turned off and disconnect the current path between the second node N22 and the negative voltage DVBB2.

[0139] Although not shown, the power supply voltage VPP and the negative voltage DVBB2 can be supplied to the inverter 415.

[0140] Figure 11 It is shown Figure 9 The circuit diagram of an example sub-word line driver.

[0141] Despite Figure 11 The configuration of sub-word line driver 420 is shown for ease of explanation, but each of the configurations of sub-word line drivers 430, 440 and 450 may be substantially the same as the configuration of sub-word line driver 420.

[0142] Reference Figure 11 The sub-word driver 420 may include a PMOS transistor PT11, a first NMOS transistor NT11, and a second NMOS transistor NT12.

[0143] The PMOS transistor PT11 may be connected between the first node N31 and the first (power) terminal that receives the first drive signal PXID0, and may have a gate for receiving the word line enable signal NWEIB.

[0144] A first NMOS transistor NT11 may be connected between the first node N31, which is bonded to word line WL0, and the negative voltage DVBB2, and may have a gate for receiving the word line enable signal NWEIB. A second NMOS transistor NT12 may be connected in parallel with the first NMOS transistor NT11 between the first node N31, which is bonded to word line WL0, and the negative voltage DVBB2, and may have a gate for receiving the second drive signal PXIB0. The first drive signal PXIB0 and the second drive signal PXIB0 may be complementary to each other.

[0145] Based on the word line enable signal NWEIB having a power supply voltage VPP, PMOS transistor PT11 can be turned off, thus cutting off the current path from the first terminal to the first node N31. Based on the word line enable signal NWEIB and the second drive signal PXIB0 each having a power supply voltage VPP, the first NMOS transistor NT11 and the second NMOS transistor NT12 can be turned on, thus driving the word line WL0 using the negative voltage DVBB2.

[0146] Based on the first drive signal PXID0 having a power supply voltage VPP and the word line enable signal NWEIB having a negative voltage DVBB2, PMOS transistor PT11 can be turned on, providing the power supply voltage VPP to the first node N31, and the word line WL0 can be driven using the power supply voltage VPP. Based on the word line enable signal NWEIB having a negative voltage DVBB2, the first NMOS transistor NT11 can be turned off, cutting off the first current path from the first node N31 to the negative voltage DVBB2. Based on the second drive signal PXIB0 having a ground voltage VSS (or a negative voltage DVBB2), the second NMOS transistor NT12 can be turned off, cutting off the second current path from the first node N31 to the negative voltage DVBB2.

[0147] Figure 12A It is shown Figure 10 A waveform diagram illustrating an example of the operation of the sub-word line decoder.

[0148] Reference Figure 10 and Figure 12A Before the first time point T11, when each of the first intermediate word line enable signal NWEIB0, the second intermediate word line enable signal NWEIB1, and the block access signal PDPXIPD has a power supply voltage VPP level, the first PMOS transistor 411 and the second PMOS transistor 412 are turned off, the first NMOS transistor 413 is turned on, and the second node N22 is driven at a negative voltage DVBB2 level. Therefore, the inverter 415 can output a word line enable signal NWEIB with a power supply voltage VPP level by inverting the negative voltage DVBB2 level at the second node N22.

[0149] After time point T11, when each of the first intermediate word line enable signal NWEIB0, the second intermediate word line enable signal NWEIB1, and the block access signal PDPXIPD transitions to ground voltage VSS (or, when each of the first intermediate word line enable signal NWEIB0 and the second intermediate word line enable signal NWEIB1 transitions to ground voltage VSS and the block access signal PDPXIPD transitions to negative voltage DVBB2), the first PMOS transistor 411 and the second PMOS transistor 412 turn on, the first NMOS transistor 413 turns off, and the second node N22 is driven at the voltage level of the power supply voltage VPP.

[0150] When each of the first intermediate word line enable signal NWEIB0, the second intermediate word line enable signal NWEIB1, and the block access signal PDPXIPD has a ground voltage VSS level between time points T11 and T12 (or, when each of the first intermediate word line enable signal NWEIB0 and the second intermediate word line enable signal NWEIB1 has a ground voltage VSS level between time points T11 and T12 and the block access signal PDPXIPD has a negative voltage DVBB2 level between time points T11 and T12), the first PMOS transistor 411 and the second PMOS transistor 412 are turned on, the first NMOS transistor 413 is turned off, and the second node N22 is driven at the power supply voltage VPP level. Therefore, the inverter 415 can output a word line enable signal NWEIB with a negative voltage DVBB2 level by inverting the power supply voltage VPP level at the second node N22. Furthermore, based on the word line enable signal NWEIB having a negative voltage level of DVBB2, the second NMOS transistor 414 can be turned off and cut off the current path between the second node N22 and the negative voltage DVBB2.

[0151] The operations after time point T12 are basically the same as those before time point T11.

[0152] Figure 12B It is shown Figure 11 A waveform diagram illustrating an example of the operation of a sub-word line driver.

[0153] Reference Figure 11 and Figure 12B The sub-word line driver 420 can drive the word line WL0 using either the power supply voltage VPP or the negative voltage DVBB2 based on the word line enable signal NWEIB. For example, the word line enable signal NWEIB may have a voltage level of the power supply voltage VPP corresponding to the deactivation state before the first time point T1, and may have a voltage level of the negative voltage DVBB2 corresponding to the activation state between the first time point T1 and the second time point T2.

[0154] Before the first time point T1, the first drive signal PXID0 may have a logic low level (e.g., the voltage level of ground voltage VSS), and the second drive signal PXIB0 may have a logic high level (e.g., the voltage level of power supply voltage VPP).

[0155] When a memory cell is accessed, the word line enable signal NWEIB and the first drive signal PXID0 corresponding to the memory cell can be activated. Since the word line enable signal NWEIB is activated at a negative voltage level DVBB2, the sub-word line driver 420 can supply the power supply voltage (e.g., a boost voltage) VPP provided by the first drive signal PXID0 to the word line WL0. Therefore, the sub-word line driver 420 can use the power supply voltage VPP to drive the word line WL0.

[0156] For example, when the word line enable signal NWEIB is activated to the voltage level of the negative voltage DVBB2 after the first time point T1, the first drive signal PXID0 can be switched to the power supply voltage VPP, and the second drive signal PXIB0 can be switched to the logic low level (e.g., ground voltage VSS).

[0157] After the memory cell access operation is completed, the sub-word line driver 420 can drive the word line WL0 using the voltage level of the negative voltage DVBB2.

[0158] For example, when the word line enable signal NWEIB is deactivated to the power supply voltage VPP level after the second time point T2, the first drive signal PXID0 can be switched to the ground voltage VSS level, and the second drive signal PXIB0 can be switched to the power supply voltage VPP level. Therefore, the word line WL0 can be reduced to the negative voltage DVBB2 level.

[0159] The second NMOS transistor NT2 can maintain the word line WL0 at the negative voltage DVBB2 after the second time point T2.

[0160] Figure 13 It is used to describe Figure 2A An example diagram of a semiconductor memory device.

[0161] Reference Figure 13 The first semiconductor layer L1a may include a first general memory cell NMC1' and a first ECC memory cell EMC1', and the second semiconductor layer L2a may include a sub-word line decoder SDEC', a first sub-word line driver SWD1 and a second sub-word line driver SWD2 arranged in region RGa.

[0162] Figure 13 Examples of the connections between the first general-purpose memory cell NMC1' and the first sub-word line driver SWD1, and between the first ECC memory cell EMC1' and the second sub-word line driver SWD2 are shown.

[0163] The first general-purpose memory cell NMC1' in the first memory array region R_BA1a in the first semiconductor layer L1a and the first sub-word line driver SWD1 in the region RGa in the second semiconductor layer L2a can be electrically connected to each other via a vertical line (or wire) VL_WN1 extending in the vertical direction VD and a word line WL_N1 extending in the first direction DR1.

[0164] The first ECC memory cell EMC1' in the first ECC cell region R_EC1a of the first semiconductor layer L1a and the second sub-word line driver SWD2 in the region RGa of the second semiconductor layer L2a can be electrically connected to each other via a vertical line VL_WE1 extending in the vertical direction VD and a word line WL_E1 extending in the first direction DR1.

[0165] In some implementations, each of the vertical lines VL_WN1 and VL_WE1 may include Figure 2B The bonding pads PD_L1 and PD_L2 and the contacts CT_L1 and CT_L2 are in the middle.

[0166] The first general-purpose memory cell NMC1', the first ECC memory cell EMC1', and the sub-word line drivers SWD1 and SWD2 can be respectively included in Figure 2B The ordinary memory cell NMC, the ECC memory cell EMC, and the sub-word line driver SWD are located in the memory. Sub-word line drivers SWD1 and SWD2 can provide word line enable signals NWEIB, which swing between the power supply voltage and the negative voltage, to the first ordinary memory cell NMC1' and the first ECC memory cell EMC1' through vertical lines VL_WN1 and VL_WE1.

[0167] Figure 14 It is shown Figure 3A or Figure 3B A circuit diagram of an example bit-line sense amplifier.

[0168] Reference Figure 14 The bit line sense amplifier 460 can be connected to the bit line BTL and can have a circuit structure for driving the bit line BTL. For example, the bit line sense amplifier 460 may include transistors PT21, PT22, NT21, and NT22, which are connected to the control line LA and the complementary control line LAB through nodes ND21 and ND22, and to the bit line BTL and the complementary bit line BTLB through nodes ND23 and ND24.

[0169] Transistor PT21 may be connected between nodes ND23 and ND21, and may have a gate connected to node ND24. Transistor PT22 may be connected between nodes ND21 and ND24, and may have a gate connected to node ND23. Transistor NT21 may be connected between nodes ND23 and ND22, and may have a gate connected to node ND24. Transistor NT22 may be connected between nodes ND22 and ND24, and may have a gate connected to node ND23. Depending on the operation of turning on and / or turning off transistors PT21, PT22, NT21, and NT22 included in the bit line sense amplifier 460, various operations for bit line BTL (such as precharge operation, offset cancellation operation, charge sharing operation, development operation, and sensing operation, etc.) can be performed.

[0170] Furthermore, the bit line BTL and complementary bit line BTLB can be connected to the local I / O line LIO and complementary local I / O line LIOB respectively via transistors NT23 and NT24. The gates of transistors NT23 and NT24 can be connected to the column select line CSL. When transistors NT23 and NT24 are turned on, detection data can be output.

[0171] In some implementations, each of transistors PT21 and PT22 may be a PMOS transistor, and each of transistors NT21, NT22, NT23 and NT24 may be an NMOS transistor.

[0172] However, the example implementation is not limited to this, and the bit line sensing amplifier is not limited to this. Figure 14 The structure shown.

[0173] Figure 15 and Figure 16 This is a perspective view of an example semiconductor memory device. For the sake of brevity, [the following will be omitted]. Figure 1 The description is repetitive or overlapping.

[0174] Reference Figure 15 The semiconductor memory device 100c may include a first semiconductor layer L1, a second semiconductor layer L2, and a third semiconductor layer L3. In addition to the third semiconductor layer L3, the semiconductor memory device 100c also includes... Figure 15 Examples can be compared with Figure 1 The examples are basically the same.

[0175] The first semiconductor layer L1, the second semiconductor layer L2, and the third semiconductor layer L3 are disposed or stacked in the vertical direction VD. Although Figure 15An example is shown where a first semiconductor layer L1 and a third semiconductor layer L3 are respectively disposed on and below a second semiconductor layer L2, but the example implementation is not limited thereto. For example, both the first semiconductor layer L1 and the third semiconductor layer L3 may be disposed on or below the second semiconductor layer L2.

[0176] Similar to the first semiconductor layer L1, the third semiconductor layer L3 may include a memory cell array MCA2 and may be referred to as a memory cell region or a cell wafer. For example, the memory cell array MCA1 included in the first semiconductor layer L1 may be referred to as the first memory cell array, and the memory cell array MCA2 included in the third semiconductor layer L3 may be referred to as the second memory cell array.

[0177] Each of the memory cell array MCA1 in the first semiconductor layer L1 and the memory cell array MCA2 in the third semiconductor layer L3 may respectively include multiple ordinary memory cells (NMCs) and multiple ECC memory cells (EMCs). The multiple ordinary memory cells (NMCs) and multiple ECC memory cells (EMCs) in the first semiconductor layer L1 and the third semiconductor layer L3, as well as the sub-word line decoder (SDEC) and sub-word line driver (SWD) in the second semiconductor layer L2, may be arranged to be partially and / or completely stacked in a planar view or on a plane.

[0178] Reference Figure 16 The semiconductor memory device 100d may include a first semiconductor layer L1, a second semiconductor layer L2, and a fourth semiconductor layer L4. In addition to the fourth semiconductor layer L4, the semiconductor memory device 100d also includes... Figure 16 Examples can be compared with Figure 1 The examples are basically the same.

[0179] The first semiconductor layer L1, the second semiconductor layer L2, and the fourth semiconductor layer L4 are disposed or stacked in the vertical direction VD. Although Figure 16 An example is shown where the fourth semiconductor layer L4 and the second semiconductor layer L2 are respectively disposed on and below the first semiconductor layer L1, but the example implementation is not limited thereto. For example, both the second semiconductor layer L2 and the fourth semiconductor layer L4 may be disposed on or below the first semiconductor layer L1.

[0180] Similar to the second semiconductor layer L2, the fourth semiconductor layer L4 may include peripheral circuitry PCKT2 and may be referred to as a peripheral circuitry region or peripheral wafer. For example, peripheral circuitry PCKT1 included in the second semiconductor layer L2 may be referred to as the first peripheral circuitry, and peripheral circuitry PCKT2 included in the fourth semiconductor layer L4 may be referred to as the second peripheral circuitry.

[0181] Each of the peripheral circuits PCKT1 of the second semiconductor layer L2 and PCKT2 of the fourth semiconductor layer L4 may respectively include a sub-word line decoder (SDEC) and a sub-word line driver (SWD). The plurality of general-purpose memory cells (NMC) and the plurality of ECC memory cells (EMC) in the first semiconductor layer L1, as well as the sub-word line decoders (SDEC) and sub-word line drivers (SWD) in the second semiconductor layer L2 and the fourth semiconductor layer L4, may be arranged to be partially and / or completely stacked in a planar view or on a plane.

[0182] Although not shown in detail, memory devices may include four or more stacked semiconductor layers.

[0183] Figure 17 and Figure 18 This is a cross-sectional view of an example memory package.

[0184] Reference Figure 17 The memory package 700 includes a substrate 710 and a plurality of memory chips CHP1, CHP2 and CHP3 stacked on the substrate 710.

[0185] Each of the memory chips CHP1, CHP2, and CHP3 may include a memory cell layer CLY and a peripheral circuit layer PLY, and may also include multiple I / O pads IOPAD. The memory cell layer CLY and the peripheral circuit layer PLY may be respectively connected to a reference... Figure 1 The first semiconductor layer L1 and the second semiconductor layer L2 described correspond to each other, and according to any example implementation described herein, elements described herein that would be included in the first semiconductor layer L1 and the second semiconductor layer L2 may also be included. Each of the memory chips CHP1, CHP2 and CHP3 may include a semiconductor memory device and may be implemented such that the memory cells included in the different semiconductor layers, as well as the sub-word line decoder and sub-word line driver, are arranged to be partially and / or completely stacked in a planar view or on a plane.

[0186] In some embodiments, memory chips CHP1, CHP2, and CHP3 may be stacked on substrate 710 such that the surfaces on which a plurality of I / O pads (IOPADs) are formed are facing upwards. In some embodiments, for each of memory chips CHP1, CHP2, and CHP3, the plurality of I / O pads (IOPADs) may be arranged near one side of the semiconductor substrate. Thus, memory chips CHP1, CHP2, and CHP3 may be stacked in a ladder-like manner (i.e., in a stepped arrangement), exposing the plurality of I / O pads (IOPADs) of each memory chip. In this stacked configuration, memory chips CHP1, CHP2, and CHP3 may be electrically connected to substrate 710 via multiple bonding wires (BW).

[0187] Stacked memory chips CHP1, CHP2, and CHP3, along with multiple bonding wires BW, can be secured by a sealing member 740, and an adhesive member 730 can be positioned between the substrate 710 and the memory chips CHP1 to CHP3. Conductive bumps 720 can be formed on the bottom surface of the substrate 710 for electrical connection to external devices.

[0188] Reference Figure 18 The memory package 800 includes a substrate 810 and a plurality of memory chips CHP1, CHP2, and CHP3 stacked on the substrate 810. For brevity, the components will be omitted. Figure 17 The description is repetitive or overlapping.

[0189] Each of the memory chips CHP1, CHP2 and CHP3 may include a memory cell layer CLY and a peripheral circuit layer PLY, and may also include multiple through-silicon vias (TSVs, or through-silicon vias) 830.

[0190] In some embodiments, for each of the memory chips CHP1, CHP2, and CHP3, a plurality of TSVs 830 may be arranged at the same location in each memory chip. Thus, the memory chips CHP1, CHP2, and CHP3 can be stacked such that the plurality of TSVs 830 of each memory chip can be completely stacked (e.g., the arrangement of the plurality of TSVs 830 can perfectly match the memory chips CHP1 through CHP3). In this stacked state, the memory chips CHP1, CHP2, and CHP3 are electrically connected to each other and to the substrate 810 via the plurality of TSVs 830 and the conductive material 840.

[0191] The conductive bump 820 and the sealing member 850 can be used with Figure 17 The conductive bump 720 and the sealing member 740 are basically the same.

[0192] Figure 19 This is a block diagram illustrating an example of a memory system.

[0193] Reference Figure 19 The memory system 20 may include a memory controller 30 and a semiconductor memory device 200.

[0194] The memory controller 30 controls the overall operation of the memory system 20. The memory controller 30 also controls the overall data exchange between the external host and the semiconductor memory device 200. For example, the memory controller 30 can write data to or read data from the semiconductor memory device 200 in response to a request from the host.

[0195] Furthermore, the memory controller 30 can issue operation commands to the semiconductor memory device 200 for controlling the semiconductor memory device 200. In some embodiments, the semiconductor memory device 200 is a memory device that includes dynamic memory cells, such as dynamic random access memory (DRAM), double data rate (DDR) synchronous DRAM (SDRAM), low power (LP) DDR SDRAM, etc.

[0196] The memory controller 30 can send a clock signal CK (which may be referred to as a command clock signal), a command CMD, and an address (signal) ADDR to the semiconductor memory device 200. For ease of description, the terms clock signal CK, command CMD, and address ADDR are used interchangeably with those used for other purposes. When the memory controller 30 writes a data signal DQ to the semiconductor memory device 200, the memory controller 30 can send a data strobe signal DQS to the semiconductor memory device 200. When the memory controller 30 reads a data signal DQ from the semiconductor memory device 200, the semiconductor memory device 200 can send a data strobe signal DQS to the memory controller 30. The address ADDR may be accompanied by a command CMD, and the address ADDR may be referred to as the access address.

[0197] The memory controller 30 may include a central processing unit (CPU) 35 and refresh management (RFM) control logic 90. The CPU 35 controls the overall operation of the memory controller 30, and the refresh management (RFM) control logic 90 generates refresh management commands associated with row hammers of multiple memory cell rows of the semiconductor memory device 200.

[0198] The semiconductor memory device 200 may include a memory cell array 310 and peripheral circuitry 201. The memory cell array 310 stores a data signal DQ. The peripheral circuitry 201 may include control logic circuitry 210, a sub-word line decoder 410, and a sub-word line driver 420. The sub-word line decoder 410 and the sub-word line driver 420 are located below the memory cell array 310.

[0199] Control logic circuitry 210 controls the operation of semiconductor memory device 200. Memory cell array 310 may include multiple rows of memory cells, and each row of memory cells may include multiple (volatile) memory cells.

[0200] As described above, the sub-word line decoder 410 can generate a word line enable signal that oscillates between a power supply voltage and a negative voltage by decoding the first intermediate word line enable signal and the second intermediate word line enable signal, and can apply the word line enable signal to the sub-word line driver 420, each of the first intermediate word line enable signal and the second intermediate word line enable signal oscillating between a power supply voltage and a ground voltage. The sub-word line driver 420 can use either the power supply voltage or the negative voltage to drive the corresponding word line.

[0201] Therefore, because the sub-word line driver 420 is located below the memory cell array 310, the semiconductor memory device 200 can reduce the chip size and wiring associated with transmitting word line enable signals. Furthermore, since the voltage levels of each of the power supply voltage and the negative voltage are lower than those of each of the conventional power supply voltage and the conventional negative voltage, the NBTI occurring in the PMOS transistor in the sub-word line driver 420 and the PBTI occurring in the NMOS transistor in the sub-word line driver 420 can be reduced.

[0202] Figure 20 It is shown Figure 19 A block diagram of an example memory controller.

[0203] Reference Figure 20 The memory controller 30 may include a CPU 35, RFM control logic 90, refresh logic 40, host interface 50, scheduler 55 and memory interface 60 connected to each other via a bus 31.

[0204] The CPU 35 controls the overall operation of the memory controller 30. The CPU 35 can control the RFM control logic 90, refresh logic 40, host interface 50, scheduler 55 and memory interface 60 via bus 31.

[0205] The refresh logic 40 can generate an automatic refresh command for refreshing memory cells of multiple memory cell rows based on the refresh interval of the semiconductor memory device 200.

[0206] The host interface 50 can perform an interface connection with a host. The memory interface 60 can perform an interface connection with the semiconductor memory device 200.

[0207] Scheduler 55 manages the scheduling and transmission of command sequences generated in memory controller 30. Scheduler 55 can send automatic refresh commands and refresh management commands to the semiconductor memory device via memory interface 60.

[0208] Figure 21 This is a flowchart illustrating an example of a method for manufacturing a semiconductor memory device.

[0209] Figure 21 The manufacturing method can be applied to manufacturing Figure 1 Semiconductor memory device 100.

[0210] Reference Figure 21 A method for manufacturing a semiconductor memory device including a first chip and a second chip is provided. The first chip includes a memory cell region and is disposed on a first wafer, and the second chip includes a peripheral circuit region having a sub-word line decoder and is disposed on a second wafer, the second wafer being different from the first wafer.

[0211] According to this method, a second chip including a peripheral circuit region with a sub-word line decoder is formed (set) on a second wafer (operation S510). A first test is performed on the second chip (operation S520). Based on the result of the first test, it is determined whether the second chip passes the first test (operation S530). When the second chip fails the first test (no in operation S530), it is determined that the second chip is defective (operation S540).

[0212] A first chip, including a memory cell region, is formed (set) on the first wafer separately from the formation and testing of the second chip (operation S520) (operation S610). A second test is performed on the first chip (operation S620). Based on the result of the second test, it is determined whether the first chip passes the second test (operation S630). When the first chip fails the second test (no in operation S630), it is determined that the first chip is defective (operation S640).

[0213] When the second chip passes the first test (Yes in operation S530) and the first chip passes the second test (Yes in operation S630), the first chip and the second chip are joined (operation S650) and the semiconductor memory device is provided as a qualified product (operation S660).

[0214] Figure 22 This is a diagram illustrating an example of the manufacturing process of a semiconductor device.

[0215] Reference Figure 22 The corresponding integrated circuits can be formed on the first wafer WF1 and the second wafer WF2. The memory cell array can be formed in the first wafer WF1, and the peripheral circuits can be formed in the second wafer WF2.

[0216] After various integrated circuits have been formed on the first wafer WF1 and the second wafer WF2 respectively, the first wafer WF1 and the second wafer WF2 can be bonded together. The bonded wafers WF1 and WF2 can then be diced (or divided) into individual chips, each corresponding to a semiconductor device (such as, for example, a semiconductor memory device 3000 comprising vertically stacked first semiconductor dies SD1 and second semiconductor dies SD2 (e.g., the first semiconductor die SD1 is stacked on the second semiconductor die SD2, etc.)). Each cut portion of the first wafer WF1 corresponds to the first semiconductor die SD1, and each cut portion of the second wafer WF2 corresponds to the second semiconductor die SD2. For example, based on... Figure 21 Manufacturing process Figure 22 Semiconductor memory device 3000.

[0217] The example implementations can be applied to a variety of electronic devices and systems, including semiconductor memory devices. For example, the example implementations can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, automobiles, and the like.

[0218] While this specification contains numerous specific details of implementation, these should not be construed as limiting the scope or claimable scope of any invention, but rather as descriptions of features specific to particular embodiments of a particular invention. Specific features described in the context of individual embodiments in this specification may also be implemented in combination within a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a specific combination, in some cases, one or more features from the combination may be removed from the combination, and the combination may refer to a sub-combination or a variation of the sub-combination.

[0219] The foregoing is exemplary and should not be construed as limiting. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims.

Claims

1. A semiconductor memory device, comprising: A first semiconductor layer includes a memory cell array connected to multiple word lines and multiple bit lines. The memory cell array includes multiple memory cells configured to store data. The multiple word lines extend in a first direction, and the multiple bit lines extend in a second direction intersecting the first direction. as well as A second semiconductor layer, located below the first semiconductor layer in a third direction and perpendicular to both the first and second directions, includes peripheral circuitry configured to control an array of memory cells. This peripheral circuitry includes one or more sub-word line drivers and sub-word line decoders. The one or more sub-word line drivers are configured to drive the plurality of word lines. The sub-word line decoder is configured to apply word line enable signals to the one or more sub-word line drivers based on a first intermediate word line enable signal and a second intermediate word line enable signal. In the plan view, the one or more sub-word line drivers and sub-word line decoders are located in a first region of a second semiconductor layer, the plurality of memory cells are located in a memory region of the first semiconductor layer, and the memory region is superimposed on the first region.

2. The semiconductor memory device of claim 1, wherein, Each of the first intermediate word line enable signal and the second intermediate word line enable signal is configured to swing between the power supply voltage and the ground voltage, and The word line enable signal is configured to oscillate between the power supply voltage and a negative voltage.

3. The semiconductor memory device of claim 1, wherein, The sub-word line decoder is configured to generate the word line enable signal based on decoding the first intermediate word line enable signal and the second intermediate word line enable signal. Each of the first intermediate word line enable signal and the second intermediate word line enable signal is configured to oscillate between the power supply voltage and the ground voltage, and The word line enable signal is configured to oscillate between the power supply voltage and a negative voltage.

4. The semiconductor memory device of claim 1, wherein, The sub-word decoder includes: A first p-channel metal-oxide-semiconductor (PMOS) transistor is connected between a power supply voltage and a first node. The first PMOS transistor has a gate configured to receive a first intermediate word line enable signal, which is configured to oscillate between a power supply voltage and a ground voltage. A second PMOS transistor is connected between the first node and the second node. The second PMOS transistor has a gate configured to receive a second intermediate word line enable signal, which is configured to oscillate between a power supply voltage and a ground voltage. A first n-channel metal-oxide-semiconductor (NMOS) transistor is connected between a second node and a negative voltage. The first NMOS transistor has a gate configured to receive a block access signal. A second NMOS transistor, connected in parallel with the first NMOS transistor between the second node and the negative voltage, has a gate configured to receive the word line enable signal; and An inverter is configured to output the word line enable signal based on inverting the voltage level at the second node, the word line enable signal being configured to oscillate between the power supply voltage and a negative voltage.

5. The semiconductor memory device of claim 4, wherein, Based on the first intermediate word line enable signal having a power supply voltage level, the second intermediate word line enable signal having a power supply voltage level, and the block access signal having a power supply voltage level, the inverter is configured to invert the voltage level of the negative voltage at the second node in order to output the word line enable signal having a power supply voltage level. and Based on the fact that the first intermediate word line enable signal has a ground voltage level, the second intermediate word line enable signal has a ground voltage level, and the block access signal has a ground voltage level, the inverter is configured to invert the voltage level of the power supply voltage at the second node in order to output the word line enable signal with a negative voltage level.

6. The semiconductor memory device of claim 4, wherein, Based on the voltage level of the word line enable signal having the power supply voltage, the second NMOS transistor is configured to provide an additional current path between the second node and the negative voltage.

7. The semiconductor memory device of claim 1, wherein, Each of the one or more sub-word line drivers is configured to drive a corresponding word line among the plurality of word lines using a power supply voltage or a negative voltage, based on the word line enable signal, a first drive signal, and a second drive signal.

8. The semiconductor memory device of claim 7, wherein, Each of the one or more sub-word line drivers includes: A p-channel metal-oxide-semiconductor (PMOS) transistor is connected between a first terminal and a first node, the first terminal being configured to receive a first drive signal, and the PMOS transistor having a gate configured to receive the word line enable signal. A first n-channel metal-oxide-semiconductor (NMOS) transistor is connected between a first node and a negative voltage, the first node being coupled to the corresponding word line. The first NMOS transistor has a gate configured to receive an enable signal for the word line. A second NMOS transistor is connected between the first node and the negative voltage, and the second NMOS transistor has a gate configured to receive a second drive signal.

9. The semiconductor memory device of claim 8, wherein, Based on the word line enable signal having a power supply voltage level, the PMOS transistor is configured to cut off the current path from the first terminal to the first node. and Based on the word line enable signal having a power supply voltage level and the second drive signal having a power supply voltage level, the first NMOS transistor and the second NMOS transistor are configured to drive the corresponding word line using a negative voltage level.

10. The semiconductor memory device of claim 8, wherein, Based on the first drive signal having a power supply voltage level and the word line enable signal having a negative voltage level, the PMOS transistor is configured to drive the corresponding word line using the power supply voltage level. Based on the negative voltage level of the word line enable signal, the first NMOS transistor is configured to: cut off the first current path from the first node to the negative voltage; and Based on the voltage level of the second drive signal having a ground voltage, the second NMOS transistor is configured to cut off the second current path from the first node to the negative voltage.

11. The semiconductor memory device of claim 1, wherein, Each of the one or more sub-word line drivers is electrically connected to a corresponding word line among the plurality of word lines via a vertical line extending upward from a third party.

12. The semiconductor memory device of claim 1, wherein, The peripheral circuit includes: The first region includes a sub-word line decoder and the one or more sub-word line drivers; and The second region includes a line decoder, wherein the second region is adjacent to the first region in a first direction, and the line decoder is configured to generate a first intermediate word line enable signal and a second intermediate word line enable signal based on the decoded line address.

13. The semiconductor memory device of claim 12, wherein, The line decoder includes: The first main word line driver is configured to generate a first intermediate word line enable signal based on the decoded row address, block access signal, and block select signal; and The second master word line driver is configured to generate a second intermediate word line enable signal based on the decoded row address, block access signal, and block select signal.

14. The semiconductor memory device of claim 12, wherein, The bit line sense amplifier is disposed in the first region and is connected to the first bit line and the first complementary bit line among the plurality of bit lines.

15. The semiconductor memory device of claim 12, wherein, The one or more sub-word line drivers are disposed on a first side of the sub-word line decoder, and the first side extends in a second direction.

16. The semiconductor memory device of claim 12, wherein, The one or more sub-word line drivers are disposed on the second side of the sub-word line decoder, and the second side extends in a second direction and is opposite to the first side of the sub-word line decoder.

17. The semiconductor memory device according to any one of claims 1 to 16, wherein, Each of the plurality of memory cells includes a unit transistor and a unit capacitor.

18. The semiconductor memory device according to any one of claims 1 to 16, in, The first semiconductor layer includes a first bonding pad. The second semiconductor layer includes a second bonding pad electrically connected to the first bonding pad. The first semiconductor layer and the second semiconductor layer are electrically connected in the third direction through the first bonding pad and the second bonding pad.

19. A memory package, comprising: Substrate, and Multiple memory chips are stacked on a substrate. Each of the plurality of memory chips includes: A first semiconductor layer includes a memory cell array connected to a plurality of word lines and a plurality of bit lines. The memory cell array includes a plurality of memory cells configured to store data, wherein the plurality of word lines extend in a first direction and the plurality of bit lines extend in a second direction intersecting the first direction; and A second semiconductor layer is located below the first semiconductor layer in a third direction, which is perpendicular to both the first and second directions. The second semiconductor layer includes peripheral circuitry configured to control an array of memory cells. This peripheral circuitry includes one or more sub-word line drivers and sub-word line decoders. The one or more sub-word line drivers are configured to drive the plurality of word lines. The sub-word line decoder is configured to apply word line enable signals to the one or more sub-word line drivers based on a first intermediate word line enable signal and a second intermediate word line enable signal. In the plan view, the one or more sub-word line drivers and sub-word line decoders are located in a first region of a second semiconductor layer, the plurality of memory cells are located in a memory region of the first semiconductor layer, and the memory region is superimposed on the first region.

20. A semiconductor memory device, comprising: A first semiconductor layer includes a memory cell array connected to a plurality of word lines and a plurality of bit lines. The memory cell array includes a plurality of memory cells configured to store data. The plurality of word lines extend in a first direction, and the plurality of bit lines extend in a second direction intersecting the first direction. as well as A second semiconductor layer, located below the first semiconductor layer in a third direction, perpendicular to both the first and second directions, includes peripheral circuitry configured to control a memory cell array. This peripheral circuitry includes one or more sub-word line drivers and sub-word line decoders. The one or more sub-word line drivers are configured to drive the plurality of word lines. The sub-word line decoders are configured to apply word line enable signals to the one or more sub-word line drivers based on a first intermediate word line enable signal and a second intermediate word line enable signal. In a plan view, the one or more sub-word line drivers and sub-word line decoders are located in a first region of the second semiconductor layer, and the plurality of memory cells are located in a memory region of the first semiconductor layer, with the memory region overlapping the first region. The sub-word line decoder is configured to generate the word line enable signal based on the first intermediate word line enable signal and the second intermediate word line enable signal. Each of the first intermediate word line enable signal and the second intermediate word line enable signal is configured to oscillate between the power supply voltage and the ground voltage, and The word line enable signal is configured to oscillate between the power supply voltage and a negative voltage.

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