Method for erasing memory and memory

Abstract

This application discloses a memory erasure method and a memory. The memory erasure method includes: acquiring programming data and performing programming operations on the memory based on the programming data until programming is completed; acquiring programming data again and using the programming data to perform data verification on the memory to obtain the address of the memory cell where the memory flipped; in response to the number of errors of the memory cell where the memory flipped being greater than or equal to a preset target threshold, performing at least one erase operation on the corresponding memory cell based on the address until the number of errors is less than the preset target threshold. Through the above method, the memory erasure method of this application allows memory erasure to no longer be limited to memory blocks, enabling precise erasure of memory cells to meet the needs of flexible erasure and thus improve programming interference.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a method for erasing a memory and a memory. Background Technology

[0002] During memory operation, numerous interference effects occur, with programming interference and read interference being two typical examples. When programming a memory, a higher voltage is applied to the word lines used for programming, while the remaining word lines are subjected to a conduction voltage. Therefore, for memory cells requiring programming, a significant voltage difference exists between the gate voltage and the substrate channel, resulting in the FN tunneling effect of electrons. For memory cells not requiring programming, the channel voltage is raised by the conduction voltage, creating programming suppression. In this case, the difference between the gate voltage and the channel voltage is less than the minimum voltage difference required for programming. When the channel voltage is low, the difference between the gate voltage and the channel voltage increases, ultimately leading to programming interference. On the other hand, read interference occurs because a high conduction voltage is continuously applied to the gate of the memory cell during the read cycle, similarly causing a weak programming effect and resulting in data flipping. Generally, because the difference between the gate voltage and the channel voltage is small, these interferences will only cause a small number of memory cells on a few word lines to flip data. However, this interference is currently irreversible. Once interference occurs, it may cause data reading errors. Therefore, there is an urgent need for a method to erase these few memory cells that are affected by the interference. Summary of the Invention

[0003] To address the aforementioned problems, this application provides a method for erasing a memory and a memory in general, aiming to resolve these issues.

[0004] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a memory erasure method, the memory erasure method comprising: acquiring programming data, and performing programming operations on the memory based on the programming data until programming ends; acquiring programming data again, and using the programming data to perform data verification on the memory to obtain the address of the memory cell in which the memory has flipped; in response to the number of errors of the memory cell in which the memory has flipped being greater than or equal to a preset target threshold, performing at least one erase operation on the corresponding memory cell in the memory based on the address until the number of errors is less than the preset target threshold.

[0005] The step of verifying the memory using programming data includes: obtaining the address of the memory cell that needs to be programmed during the programming operation based on the programming data; adjusting the voltage of the bit line corresponding to the memory cell that needs to be programmed to a first verification voltage; adjusting the voltage of the bit line corresponding to the memory cell that does not need to be programmed to a second verification voltage, wherein the first verification voltage is less than the second verification voltage; performing a data verification operation on the memory to obtain the address of the memory cell whose bit line voltage is still the second verification voltage as the address of the memory cell that has flipped.

[0006] The steps for performing data verification on the memory include: enabling the word lines of the memory and performing a data read operation.

[0007] The step of performing at least one erase operation on the corresponding memory cell in the memory based on the address until the number of errors is less than a preset target threshold includes: performing an erase operation on the memory cell corresponding to the address, and after the erase operation, determining whether the number of errors is less than the preset target threshold; in response to the number of errors being greater than the preset target threshold, incrementing the loop count of the erase operation by one, and performing the erase operation again until the number of errors is less than the preset target threshold.

[0008] The steps for erasing the memory cell corresponding to the address include: obtaining the number of cycles for the erasure operation; adjusting the voltage of the word line, the voltage of the bit line, and the voltage of the gate select line on the drain side based on the number of cycles to boost the channel of the memory cell corresponding to the address, thereby erasing the memory cell corresponding to the address.

[0009] The step of adjusting the voltage of the word line corresponding to the address based on the number of loops includes: obtaining the first step increment voltage and the initial erase voltage of the erase operation, and calculating the first erase voltage based on the first step increment voltage, the initial erase voltage and the number of loops; adjusting the voltage of the word lines other than the word line corresponding to the address to the first erase voltage, and adjusting the voltage of the word line corresponding to the address to the second erase voltage, wherein the second erase voltage is less than the first erase voltage.

[0010] The step of adjusting the voltage of the bit line corresponding to the address based on the number of loops includes: obtaining the second step boost voltage, the first initial suppression voltage, and the second initial suppression voltage of the erase operation, wherein the first initial suppression voltage is greater than the second initial suppression voltage; calculating and obtaining the first suppression voltage based on the second step boost voltage, the first initial suppression voltage, and the number of loops; calculating and obtaining the second suppression voltage based on the second step boost voltage, the second initial suppression voltage, and the number of loops; adjusting the voltage of the bit line corresponding to the address to the first suppression voltage, and adjusting the voltage of other bit lines besides the bit line corresponding to the address to the second suppression voltage.

[0011] The step of adjusting the voltage of the drain-side gate line corresponding to the address based on the number of cycles includes: obtaining the third step boost voltage and the initial selection voltage of the erase operation, and calculating the first selection voltage based on the third step boost voltage, the initial selection voltage and the number of cycles; adjusting the voltage of the drain-side gate line corresponding to the address to the first selection voltage, and adjusting the voltage of the source-side gate line corresponding to the address to the second selection voltage, wherein the second selection voltage is less than the first selection voltage.

[0012] The erasure method further includes: when a read operation is performed on the memory, if an error occurs in the read data, an erasure operation is performed on the memory page corresponding to the read operation.

[0013] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a memory, which includes a memory array and peripheral circuits. The memory array includes multiple word lines, multiple pairs of bit lines, source-side select gate lines, drain-side select gate lines, and multiple memory cells. The peripheral circuits are connected to the memory array and are used to execute any of the above-mentioned memory erasure methods. The source-side select gate lines and drain-side select gate lines are respectively disposed on both sides of the multiple word lines and connected to the multiple pairs of bit lines. Each memory cell is connected to one word line and one pair of bit lines.

[0014] Unlike existing technologies, the memory erasure method of this application includes: acquiring programming data and performing programming operations on the memory based on the programming data until programming is completed; acquiring programming data again and using the programming data to perform data verification on the memory to obtain the address of the memory cell where the memory flipped; in response to the number of errors of the memory cell where the memory flipped being greater than or equal to a preset target threshold, performing at least one erase operation on the corresponding memory cell based on the address until the number of errors is less than the preset target threshold. Through the above method, the memory erasure method of this application allows memory erasure to no longer be limited to memory blocks, enabling precise erasure of memory cells to meet the needs of flexible erasure and thus improve programming interference. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0016] Figure 1 This is a flowchart illustrating the first embodiment of the memory erasure method provided in this application;

[0017] Figure 2 yes Figure 1 A flowchart illustrating an embodiment of step S102;

[0018] Figure 3 yes Figure 1 A flowchart illustrating an embodiment of step S103;

[0019] Figure 4 yes Figure 3 A flowchart illustrating an embodiment of step S301;

[0020] Figure 5 yes Figure 4 A flowchart illustrating step S402 of the first embodiment;

[0021] Figure 6 yes Figure 4 A flowchart illustrating the second embodiment of step S402;

[0022] Figure 7 yes Figure 4 A flowchart illustrating step S402 of the third embodiment;

[0023] Figure 8 This is a schematic diagram of the voltage waveform during the erasure process provided in this application;

[0024] Figure 9 This is a schematic diagram of the structure of an embodiment of the memory provided in this application;

[0025] Figure 10 This is a schematic diagram of another embodiment of the memory in this application. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0027] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0028] During memory operation, numerous interference effects occur, with programming interference and read interference being two typical examples. When programming a memory, a higher voltage is applied to the word lines used for programming, while the remaining word lines are subjected to a conduction voltage. Therefore, for memory cells requiring programming, a significant voltage difference exists between the gate voltage and the substrate channel, resulting in the FN tunneling effect of electrons. For memory cells not requiring programming, the channel voltage is raised by the conduction voltage, creating programming suppression. In this case, the difference between the gate voltage and the channel voltage is less than the minimum voltage difference required for programming. When the channel voltage is low, the difference between the gate voltage and the channel voltage increases, ultimately leading to programming interference. On the other hand, read interference occurs because a high conduction voltage is continuously applied to the gate of the memory cell during the read cycle, similarly causing a weak programming effect and resulting in data flipping. Generally, because the difference between the gate voltage and the channel voltage is small, these interferences will only cause a small number of memory cells on a few word lines to flip data. However, this interference is currently irreversible. Once interference occurs, it may cause data reading errors. Therefore, there is an urgent need for a method to erase these few memory cells that are affected by the interference.

[0029] In existing technologies, the current solutions generally involve read retry operations. That is, when the first read data shows an error, increasing the read-sensing voltage during the read might cause the flipped memory cell to be read correctly. However, this operation can only mitigate errors caused by interference during the data reading process; it cannot fundamentally erase the flipped memory cell from being read correctly. Therefore, to fundamentally eliminate memory cell flipping errors, the data in the flipped memory cell must be erased. Currently, memory erasure operations typically erase data on a block-by-block basis. During the erasure process, all data in the selected memory block is erased. Obviously, if there is read interference or programming interference, directly erasing using traditional methods will affect all data in the selected memory block, which is clearly undesirable for normal memory cells.

[0030] Therefore, in order to solve the above problems, this application first proposes a memory erasure method, please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the memory erasure method provided in this application. Figure 1 As shown, the memory erasure method of this embodiment includes steps S101 to S103:

[0031] Step S101: Obtain programming data and perform programming operations on the memory based on the programming data until programming is complete.

[0032] In this embodiment, the improvement is made to the interference generated during the programming process. When the user instruction is a programming instruction, programming data can be obtained, and programming operations can be performed on the memory based on the programming data until the programming is completed.

[0033] In this embodiment, when programming the memory, programming data needs to be loaded into the memory register. Before programming the memory, a pre-charge operation is also required. The pre-charge operation is to pre-charge the bit line corresponding to the memory cell. After the pre-charge operation, the voltage on the bit line of the memory cell corresponding to "1" in all programming data is a suppression voltage, and the voltage on the bit line of the memory cell corresponding to "0" in all programming data is zero voltage or a low voltage close to zero.

[0034] Furthermore, when programming the memory, the memory cells in the word line are programmed based on the programming data in the register. The programming is considered complete when all the data in the register has been converted to "1".

[0035] Step S102: Obtain the programming data again and use the programming data to verify the memory data in order to obtain the address of the memory cell where the memory flipped.

[0036] After the memory programming operation is completed, the programming data can be reloaded into the register, and the programmed memory cells can be verified using this data to obtain the address of the memory cell that was flipped. The data verification process is described below and will not be detailed here.

[0037] Since all data in the register is converted to "1" after the programming operation, in other embodiments, two registers can be set in the memory, both of which cache programming data. The programming data in one register is used for the programming operation of the memory, and the programming data in the other register is used for data verification of the memory.

[0038] Step S103: In response to the number of memory cells with errors that have flipped in the memory being greater than or equal to a preset target threshold, at least one erase operation is performed on the corresponding memory cell in the memory based on the address until the number of errors is less than the preset target threshold.

[0039] After verifying the data in the programmed memory cells, if the number of errors in the memory cells that have flipped is greater than or equal to a preset target threshold, then at least one erase operation can be performed on the corresponding memory cells in the memory based on the address of the flipped memory cells, until the number of errors is less than the preset target threshold.

[0040] Unlike existing technologies, the memory erasure method of this application includes: acquiring programming data and performing programming operations on the memory based on the programming data until programming is completed; acquiring programming data again and using the programming data to perform data verification on the memory to obtain the address of the memory cell where the memory flipped; in response to the number of errors of the memory cell where the memory flipped being greater than or equal to a preset target threshold, performing at least one erase operation on the corresponding memory cell based on the address until the number of errors is less than the preset target threshold. Through the above method, the memory erasure method of this application allows memory erasure to no longer be limited to memory blocks, enabling precise erasure of memory cells to meet the needs of flexible erasure and thus improve programming interference.

[0041] Optionally, a method for verifying data in the memory using programmed data is as follows: Figure 2 As shown, please refer to Figure 2 , Figure 2 yes Figure 1 A schematic flowchart of an embodiment of step S102. (See attached diagram.) Figure 2 As shown, this embodiment can be achieved through, as... Figure 2 The method shown implements step S102 above, and the implementation steps include steps S201 to S204:

[0042] Step S201: Obtain the address of the storage unit that needs to be programmed in the programming operation based on the programming data.

[0043] Before programming the memory, an erasure operation is required. After erasing, all memory cells are generally filled with data "1". Therefore, when programming the memory, you only need to program the memory cells corresponding to data "0".

[0044] Similarly, in this embodiment, after retrieving programming data from the register again, the addresses of the memory units that need to be programmed during the programming operation can be obtained based on the programming data. For example, taking the data "0" in the programming data as the data that needs to be programmed, in this embodiment, the addresses of the memory units corresponding to all data "0" in the programming data are obtained.

[0045] Step S202: Adjust the voltage of the bit line corresponding to the memory cell that needs to be programmed to the first verification voltage.

[0046] In this embodiment, after obtaining the addresses corresponding to all memory cells that need to be programmed based on the programming data, the voltage of the bit line corresponding to the memory cell to be programmed can be adjusted to the first verification voltage based on the corresponding address. In this embodiment, the first verification voltage can be set to zero voltage or a low voltage close to zero.

[0047] Step S203: Adjust the voltage of the bit line corresponding to the memory cell that does not need to be programmed to the second verification voltage, wherein the first verification voltage is less than the second verification voltage.

[0048] In this embodiment, as described above, if data "0" in the programming data represents data that needs to be programmed, then data "1" in the programming data represents data that does not need to be programmed. In this case, the addresses of the memory cells corresponding to all data "1" in the programming data can be obtained, and the voltage of the bit lines corresponding to the memory cells corresponding to all data "1" can be adjusted to the second verification voltage based on the corresponding addresses. The first verification voltage is less than the second verification voltage. In this embodiment, the second verification voltage can be set as the suppression voltage from the pre-charge operation described above.

[0049] Step S204: Perform a data verification operation on the memory to obtain the address of the memory cell whose bit line voltage is still the second verification voltage as the address of the memory cell that has flipped.

[0050] In this embodiment, after resetting the voltage of the bit line corresponding to the memory cell based on the programming data, a data verification operation can be performed on the memory cell in the memory. This allows the address of the memory cell whose bit line voltage is still the second verification voltage to be obtained as the address of the memory cell that has flipped. Specifically, in this embodiment, the steps for performing the data verification operation on the memory include: enabling the word line of the memory and performing a read data operation.

[0051] The working principle of the above data verification operation is as follows:

[0052] After resetting the voltage of the bit line corresponding to the memory cell, the voltage of the bit line corresponding to the memory cell for all data "0" in the programming data is the first verification voltage. In this embodiment, the first verification voltage can be set to zero voltage or a low voltage close to zero. The voltage of the bit line corresponding to the memory cell for all data "1" in the programming data is the second verification voltage. At this time, when the word line of the memory is turned on to perform a read data operation on the memory cell, the channel of the memory cell for data "1" is turned on. Therefore, the second verification voltage on the bit line corresponding to the memory cell for data "1" will change from the channel to zero voltage or a low voltage close to zero when it is released again. The channel of the memory cell for data "0" is not turned on, and the voltage on the bit line corresponding to the memory cell for data "0" remains at the first verification voltage. Therefore, when the data of a memory cell flips from "1" to "0" due to programming interference, the second verification voltage on the bit line corresponding to that memory cell cannot be released from the channel and will remain at the original voltage state. Therefore, after resetting the voltage of the bit line corresponding to the memory cell, and then turning on the word line of the memory cell to perform a read data operation, the voltage on the bit line can be monitored. If the memory cell corresponding to the second verification voltage is still maintained on the bit line, the address of the memory cell corresponding to the second verification voltage is used as the address of the memory cell that has flipped, and the erase operation in the following text is required.

[0053] For example, when programming the memory, the required programming data is loaded from the host to the memory's data registers 1 and 2. If a data flip error occurs in a memory cell during the programming process, an erase operation is performed. When the programming data loaded into programming data registers 1 and 2 is 10011000 ("0" represents the data to be programmed), if there is programming interference during the programming process and the data becomes 10010000 after programming, then the memory cell corresponding to the fifth bit has experienced a data flip, which is the memory cell that needs to be erased. When the programming data in data register 2 is loaded again, it is necessary to obtain the location of the memory cell corresponding to the data "0" in the programmed memory cell 10011000. Therefore, before data verification, the voltage on the bit line corresponding to the memory cell to be programmed needs to be set to zero voltage or a low voltage close to zero, while the voltage on the bit line corresponding to the memory cell not to be programmed needs to be set to a suppression voltage. So, in the absence of interference, the voltages of the above 8 memory cells should be V / 0 / 0 / V / V / 0 / 0 / 0 in sequence, and the channel for the memory cell with data "0" is not conducting, and the voltage on the bit line corresponding to the memory cell with data "0" remains unchanged. Therefore, when the data in a memory cell flips from "1" to "0" due to programming interference, the suppression voltage on the bit line corresponding to that memory cell cannot be released from the channel and will remain in the original voltage state. That is, the address of the memory cell that has a data flip error can be determined based on the above method, and the subsequent erase operation can be performed.

[0054] Optionally, a method of performing at least one erase operation on the corresponding memory cell in the memory based on the address until the number of errors is less than a preset target threshold is used, such as... Figure 3 As shown, please refer to Figure 3 , Figure 3 yes Figure 1 A flowchart illustrating an embodiment of step S103. (See attached diagram.) Figure 3 As shown, this embodiment can be achieved through, as... Figure 3 The method shown implements step S103 above, and the implementation steps include steps S301 to S303:

[0055] Step S301: Perform an erase operation on the memory cell corresponding to the address.

[0056] As mentioned earlier, after performing a data verification operation on a programmed memory, the address of the memory cell that has flipped can be obtained. At this point, the corresponding memory cell can be erased.

[0057] Step S302: Determine whether the number of errors is less than the preset target threshold.

[0058] After performing a corresponding erase operation on the memory cell corresponding to the address, it can be determined whether the number of memory cells that have been flipped (i.e. the number of errors) is less than a preset target threshold. The preset target threshold can be set based on the actual situation and is not restricted here.

[0059] If the number of errors is greater than the preset target threshold, the number of cycles for the erase operation is incremented by one, and step S301 is executed again; if the number of errors is less than or equal to the preset target threshold, the process proceeds to step S303.

[0060] Step S303: End the erasure operation.

[0061] The erasure operation can end when the number of memory cells that have been flipped is less than or equal to a preset target threshold after at least one erase operation. In this embodiment, the preset target threshold can be set to 0. In other embodiments, it can also be set to other values ​​based on actual conditions, and there are no restrictions here.

[0062] Optionally, the method for erasing the memory cell corresponding to the address is as follows: Figure 4 As shown, please refer to Figure 4 , Figure 4 yes Figure 3 A flowchart illustrating an embodiment of step S301. Figure 4 As shown, this embodiment can be achieved through, as... Figure 4 The method shown implements step S301 above, and the implementation steps include steps S401 to S402:

[0063] Step S401: Obtain the number of cycles for the erase operation.

[0064] When performing an erase operation on a memory cell that has been flipped, it is necessary to obtain the number of erase operation cycles.

[0065] Step S402: Adjust the voltage of the word line, the voltage of the bit line, and the voltage of the gate select line on the drain side based on the number of cycles to boost the channel of the memory cell corresponding to the address, thereby erasing the memory cell corresponding to the address.

[0066] After obtaining the number of erase operation cycles, the voltage of the word line, the voltage of the bit line, and the voltage of the drain-side select gate line corresponding to the memory cell that has flipped at the address can be adjusted based on the number of cycles to boost the channel of the memory cell that has flipped, thereby erasing the memory cell corresponding to the address that has flipped. The voltage adjustment is described below.

[0067] Optionally, the method for adjusting the voltage of the word line corresponding to the address based on the number of loops is as follows: Figure 5 As shown, please refer to Figure 5 , Figure 5 yes Figure 4 A flowchart illustrating step S402 of the first embodiment. (See attached diagram.) Figure 5 As shown, this embodiment can be achieved through, as... Figure 5 The method shown implements the step of adjusting the voltage of the word line corresponding to the address based on the number of loops in step S402 above. The implementation steps include steps S501 to S502:

[0068] Step S501: Obtain the first step boost voltage and the initial erase voltage of the erase operation, and calculate the first erase voltage based on the first step boost voltage, the initial erase voltage and the number of cycles.

[0069] In this embodiment, when adjusting the voltage of the word line corresponding to the memory cell address that has flipped, it is necessary to obtain the first step boost voltage and the initial erase voltage of the erase operation, and calculate the first erase voltage based on the first step boost voltage, the initial erase voltage and the number of cycles.

[0070] The initial erase voltage is the erase voltage applied to the word line during the first erase operation. If multiple erase operations are required, the initial erase voltage applied to the word line during each erase operation must be greater than the initial erase voltage applied during the previous erase operation. That is, the initial erase voltage is a voltage that increases progressively based on the number of cycles, with each increase being the first step of the voltage increment. This first step voltage increment can be set based on actual conditions. In other embodiments, the initial erase voltage can also be set to increase at intervals based on the number of cycles; this is not limited here.

[0071] Step S502: Adjust the voltage of the word lines other than the word lines corresponding to the address to the first erase voltage, and adjust the voltage of the word lines corresponding to the address to the second erase voltage, wherein the second erase voltage is less than the first erase voltage.

[0072] After obtaining the first erase voltage, when performing the erase operation on the memory cell corresponding to the address that has flipped, it is necessary to adjust the voltage of other word lines outside the word line corresponding to the address to the first erase voltage, and adjust the voltage of the word line corresponding to the address to the second erase voltage. In this embodiment, the second erase voltage can be set to zero voltage or a low voltage close to zero. In other embodiments, the second erase voltage can also be set to other values, but it needs to be set to be less than the first erase voltage, and the difference between the first erase voltage and the second erase voltage needs to be greater than the minimum voltage required to erase the edge data word line. With this setting, the first erase voltage on word lines other than the word line corresponding to the address will raise the potential of the channel corresponding to the word line corresponding to the address. Since the difference between the first erase voltage and the second erase voltage is greater than the minimum voltage required to erase the word line, the potential difference between the channel corresponding to the word line corresponding to the address and the second erase voltage on the word line corresponding to the address will also be greater than the minimum voltage required to erase the word line. At this time, the electrons of the memory cells on the word line corresponding to the address will enter the substrate through tunneling under the action of the electric field, thereby reducing their threshold voltage. This can be regarded as an erase operation on the memory cells on the word line.

[0073] Optionally, the method for adjusting the voltage of the bit line corresponding to the address based on the number of loops is as follows: Figure 6 As shown, please refer to Figure 6 , Figure 6 yes Figure 4 A flowchart illustrating step S402 of the second embodiment. (See attached diagram.) Figure 6 As shown, this embodiment can be achieved through, as... Figure 6 The method shown implements the step of adjusting the voltage of the bit line corresponding to the address based on the number of loops in step S402 above. The implementation steps include steps S601 to S604:

[0074] Step S601: Obtain the second step boost voltage, the first initial suppression voltage, and the second initial suppression voltage of the erase operation, wherein the first initial suppression voltage is greater than the second initial suppression voltage.

[0075] In this embodiment, when adjusting the voltage of the bit line corresponding to the memory cell address that has flipped, it is necessary to obtain the second step boost voltage, the first initial suppression voltage, and the second initial suppression voltage of the erase operation, wherein the first initial suppression voltage is greater than the second initial suppression voltage.

[0076] The first initial suppression voltage is the suppression voltage applied to the bit line corresponding to the address when performing the first erase operation; the second initial suppression voltage is the suppression voltage applied to the bit lines other than the bit line corresponding to the address when performing the first erase operation.

[0077] Step S602: Calculate the first suppression voltage based on the second step voltage increase, the first initial suppression voltage, and the number of cycles.

[0078] In this embodiment, the first suppression voltage applied to the bit line corresponding to the address in each erase operation can be calculated based on the second-step voltage increment, the first initial suppression voltage, and the number of cycles. Specifically, the first suppression voltage applied to the bit line corresponding to the address in each erase operation must be greater than the first suppression voltage applied to the bit line corresponding to the address in the previous erase operation. That is, the first suppression voltage is a voltage that gradually increases based on the number of cycles, and each increase is the second-step voltage increment. The second-step voltage increment can be set according to actual conditions. In other embodiments, the first suppression voltage can also be set to increase at intervals based on the number of cycles; this is not limited here.

[0079] Step S603: Calculate the second suppression voltage based on the second step voltage increase, the second initial suppression voltage, and the number of cycles.

[0080] In this embodiment, the second suppression voltage applied to the bit lines other than the address bit line in each erase operation can be calculated based on the second step voltage increment, the second initial suppression voltage, and the number of cycles. Specifically, the second suppression voltage applied to the bit lines other than the address bit line in each erase operation must be greater than the second suppression voltage applied to the bit lines other than the address bit line in the previous erase operation. That is, the second suppression voltage is a voltage that gradually increases based on the number of cycles, and each increase is the second step voltage increment. The second step voltage increment can be set according to actual conditions; in other embodiments, the second suppression voltage can also be set to increase at intervals based on the number of cycles, which is not limited here.

[0081] Step S604: Adjust the voltage of the bit line corresponding to the address to the first suppression voltage, and adjust the voltage of the other bit lines except the bit line corresponding to the address to the second suppression voltage.

[0082] In this embodiment, as described above, during each erase operation, the voltage of the bit line corresponding to the address needs to be adjusted to a first suppression voltage, and the voltages of the other bit lines besides the address bit line need to be adjusted to a second suppression voltage. Furthermore, during each erase operation, the first suppression voltage applied to the address bit line must be greater than the second suppression voltage applied to the other bit lines besides the address bit line.

[0083] Optionally, the method for adjusting the voltage of the gate line selected on the drain side based on the number of cycles is as follows: Figure 7 As shown, please refer to Figure 7 , Figure 7 yes Figure 4 A flowchart illustrating step S402 of the third embodiment. (See attached diagram.) Figure 7 As shown, this embodiment can be achieved through, as... Figure 7The method shown implements the step of adjusting the voltage of the drain-side gate line corresponding to the address based on the number of cycles in step S402 above. The implementation steps include steps S701 to S702:

[0084] Step S701: Obtain the third step voltage increase and the initial selection voltage of the erase operation, and calculate the first selection voltage based on the third step voltage increase, the initial selection voltage and the number of cycles.

[0085] In this embodiment, when adjusting the voltage of the drain-side select gate line corresponding to the memory cell address that has flipped, it is necessary to obtain the third step boost voltage and the initial select voltage of the erase operation, and calculate the first select voltage based on the third step boost voltage, the initial select voltage and the number of cycles.

[0086] The initial selection voltage is the voltage applied to the drain-side selection gate line corresponding to the address during the first erase operation. If multiple erase operations are required on the word line, the first selection voltage applied to the drain-side selection gate line corresponding to the address during each erase operation must be greater than the first selection voltage applied to the drain-side selection gate line corresponding to the address during the previous erase operation. That is, the first selection voltage is a voltage that gradually increases based on the number of cycles, and each increase is the third step voltage increment. The third step voltage increment can be set based on actual conditions. In other embodiments, the first selection voltage can also be set to increase at intervals based on the number of cycles; this is not limited here.

[0087] Step S702: Adjust the voltage of the drain-side gate line corresponding to the address to the first selection voltage, and adjust the source-side gate line corresponding to the address to the second selection voltage, wherein the second selection voltage is less than the first selection voltage.

[0088] In this embodiment, during each erase operation, the voltage of the drain-side select gate line corresponding to the address needs to be adjusted to a first select voltage; and the voltage of the source-side select gate line corresponding to the address needs to be adjusted to a second select voltage, wherein the second select voltage is less than the first select voltage. In this embodiment, the second select voltage can be set to zero voltage or a low voltage close to zero.

[0089] In one application scenario, please refer to Figure 8 , Figure 8 This is a schematic diagram of the voltage waveform during the erasure process provided in this application. For example... Figure 8 As shown, in this embodiment, when some memory cells undergo data flipping during programming, after obtaining the address of the flipped memory cell based on the above method, an erase operation is performed on that memory cell. Taking the memory cell at the intersection of word line WLn and bit line BLn as an example, the erase operation is as follows:

[0090] During the first erase operation, the voltage SGD of the drain-side select gate line of the memory cell is set to Vsgd1, the voltage SGS of the source-side select gate line is set to zero or a low voltage close to zero, the voltage of the word line WLn corresponding to the memory cell is set to zero or a low voltage close to zero, the voltage of the other word lines WL (excluding word line WLn) is set to Vers1, and the voltage of the bit line BLn corresponding to the memory cell is set to V_inhibit1, the voltage of the other bit lines BL (excluding bit line BLn) is set to V1 (0≤V1). <V_inhibit1)。

[0091] After waiting for a period of time, the first verification operation is performed. If the verification passes, the erasure of the storage unit is considered complete, and the programming is finished; otherwise, the second erasure operation is performed, and so on until the verification operation passes.

[0092] During the second erase operation, the voltage SGD of the gate select line on the drain side of the memory cell is set to Vsgd2 (Vsgd2>Vsgd1), and the voltage SGS of the gate select line on the source side is zero or a low voltage close to zero. The voltage of the word line WLn corresponding to the memory cell is set to zero or a low voltage close to zero, and the voltage of the other word lines WL (excluding word line WLn) is set to Vers2 (Vers2>Vers1). The voltage of the bit line BLn corresponding to the memory cell is set to V_inhibit2 (V_inhibit2>V_inhibit1), and the voltage of the other bit lines BL (excluding bit line BLn) is set to V2 (V1<V2>V4>V5 ... <V2<Vinhibit2)。

[0093] Optionally, such as Figure 8 As shown, the storage erasure method in this embodiment further includes the following steps: when a read operation is performed on the memory, in response to an error in the read data, an erasure operation is performed on the storage page corresponding to the read operation.

[0094] When interference is severe, causing data flipping in a large number of memory cells, an erase operation can be performed on the entire programmed memory page. Erasing the entire programmed memory page is suitable for improving read interference. For example, when reading a memory page and an error occurs, an erase operation can be performed on the memory page corresponding to the read operation. The erase operation method is similar to... Figure 8 The implementation methods are similar, except that the erase operation of a single memory page only requires setting the voltage of other bit lines BL to such a value. Figure 8 The curve corresponding to the storage page operation shown can be used to achieve a certain erasure effect on the entire storage page if it is consistent with the operation voltage on the bit line BLn. Since it is a read operation and the entire storage page is erased, no verification operation is performed in this process.

[0095] Optionally, this application further proposes a memory, see [link to relevant documentation]. Figure 9 , Figure 9 This is a schematic diagram of the structure of an embodiment of the memory provided in this application. Figure 9 As shown, the memory 100 in this embodiment includes a memory array 110 and peripheral circuitry 120. The memory array 110 includes multiple word lines WL, multiple pairs of bit lines BL and BL#, a source-side select gate line SGD, a drain-side select gate line SGS, and multiple memory cells 111. The peripheral circuitry 120 is connected to the memory array 110 and is used to execute any of the above-mentioned memory erasure methods. The source-side select gate line SGD and the drain-side select gate line SGS are respectively disposed on both sides of the multiple word lines WL and connected to the multiple pairs of bit lines BL and BL#. Each memory cell 111 is connected to one word line WL and one pair of bit lines BL and BL#.

[0096] In addition, please see Figure 10 , Figure 10 This is a schematic diagram of another embodiment of the memory in this application. Figure 10 As shown, the memory 100 in this embodiment includes a logic controller 10, a bit line control module 20, a first data register 30, a second data register 40, a voltage control module 50, a decoder 60, and a storage array 110.

[0097] The logic controller 10 is connected to the host and receives instructions and addresses sent by the host. The bit line control module 20 is connected to the logic controller 10 and the first data register 30. The first data register 30 is also connected to the host and receives programming data. The second data register 40 is connected to the first data register 30 and the memory array 110. The voltage control module 50 is connected to the logic controller 10. The decoder 60 is connected to the voltage control module 50 and the memory array 110. The voltage control module 50 is used to adjust the voltage of the word line, the voltage of the bit line, and the voltage of the drain-side selected gate line.

[0098] In other embodiments, the second data register 40 can be omitted, that is, only one data register needs to be set.

[0099] As mentioned above, in this embodiment, a high voltage is set on the word line adjacent to the target word line, and through the coupling effect, a high voltage is coupled out on the channel of the target word line, thereby realizing the erasure of the memory cell of the target bit line.

[0100] Taking the erasure of the memory cell at the intersection of word line WLn and bit line BLn as an example, a second erase voltage is set on the target word line to be erased. The second erase voltage can be set to zero voltage or a low voltage close to zero. The voltages on other word lines are a first erase voltage higher than the second erase voltage. At this time, if the channel of the target word line WLn is coupled up by the second erase voltage, and the second erase voltage on the target word line WLn is zero voltage or a low voltage close to zero, a voltage difference is formed between the channel and the target word line WLn, thereby realizing the erasure of the memory cell on the target bit line. Therefore, the key point is that the channel of the word line at the erasure position needs to be coupled with a high voltage, and the voltages on the corresponding bit lines and select transistors of the word line also need to be set as described above.

[0101] During the erase operation, the second erase voltage on the target word line WLn is zero voltage, a low voltage close to zero, or another small voltage, the same as during a normal erase operation; the voltage on other word lines is the first erase voltage. Therefore, the memory block in this embodiment does not need to add a voltage control module. Of course, different erase voltages can be set on different word lines, in which case a voltage control module needs to be added. The voltages on the drain-side select gate line SGD and the bit lines need to be set as described above so that the channel is turned off. At this time, the drain-side select gate line SGD is fully turned on, and the voltage on the bit lines can be transmitted to the channel. Therefore, in this embodiment, the voltage control module needs to add voltage level control to flexibly set the voltages on the drain-side select gate line SGD and the bit lines to meet the above requirements.

[0102] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for erasing a memory, characterized in that, include: Acquire programming data and perform programming operations on the memory based on the programming data until programming is complete; The programming data is retrieved again, and the memory is verified using the programming data to obtain the address of the memory cell where the memory flipped. If the number of errors in the memory cells that have flipped during memory operation is greater than or equal to a preset target threshold, then at least one erase operation is performed on the corresponding memory cell based on the address until the number of errors is less than the preset target threshold.

2. The erasing method according to claim 1, characterized in that, The step of verifying the memory using the programming data includes: Based on the programming data, obtain the address of the storage unit that needs to be programmed in the programming operation; The voltage of the bit line corresponding to the memory cell that needs to be programmed is adjusted to the first verification voltage; the voltage of the bit line corresponding to the memory cell that does not need to be programmed is adjusted to the second verification voltage, wherein the first verification voltage is less than the second verification voltage; A data verification operation is performed on the memory to obtain the address of the memory cell whose voltage on the bit line is still the second verification voltage, which is then used as the address of the memory cell that has flipped.

3. The erasure method according to claim 2, characterized in that, The step of performing data verification on the memory includes: Enable the word line of the memory and perform a read data operation.

4. The erasing method according to claim 1, characterized in that, The step of performing at least one erase operation on the corresponding memory cell in the memory based on the address until the number of errors is less than the preset target threshold includes: The erase operation is performed on the storage unit corresponding to the address, and after the erase operation, it is determined whether the number of errors is less than the preset target threshold. In response to the number of errors exceeding the preset target threshold, the number of cycles for the erase operation is incremented by one, and the erase operation is performed again until the number of errors is less than the preset target threshold.

5. The erasure method according to claim 4, characterized in that, The step of erasing the memory cell corresponding to the address includes: Obtain the number of cycles for the erasure operation; The voltage of the word line, the voltage of the bit line, and the voltage of the drain-side select gate line corresponding to the address are adjusted based on the number of cycles to boost the channel of the memory cell corresponding to the address, thereby erasing the memory cell corresponding to the address.

6. The erasing method according to claim 5, characterized in that, The step of adjusting the voltage of the word line corresponding to the address based on the number of cycles includes: The first step of the erase operation is obtained, along with the initial erase voltage. Based on the first step of the erase operation, the initial erase voltage, and the number of cycles, a first erase voltage is calculated. The voltage of all word lines except the word line corresponding to the address is adjusted to the first erase voltage, and the voltage of the word line corresponding to the address is adjusted to the second erase voltage, wherein the second erase voltage is less than the first erase voltage.

7. The erasure method according to claim 5, characterized in that, The step of adjusting the voltage of the bit line corresponding to the address based on the number of loops includes: The second step voltage increase, the first initial suppression voltage, and the second initial suppression voltage of the erasure operation are obtained, wherein the first initial suppression voltage is greater than the second initial suppression voltage; The first suppression voltage is calculated based on the second step voltage increase, the first initial suppression voltage, and the number of cycles. The second suppression voltage is calculated based on the second step voltage increase, the second initial suppression voltage, and the number of cycles; Adjust the voltage of the bit line corresponding to the address to the first suppression voltage, and adjust the voltage of the other bit lines besides the bit line corresponding to the address to the second suppression voltage.

8. The erasure method according to claim 5, characterized in that, The step of adjusting the voltage of the drain-side gate line corresponding to the address based on the number of cycles includes: The third step voltage increase and the initial selection voltage of the erasure operation are obtained, and the first selection voltage is calculated based on the third step voltage increase, the initial selection voltage and the number of cycles. The voltage of the drain-side gate line corresponding to the address is adjusted to the first selection voltage, and the voltage of the source-side gate line corresponding to the address is adjusted to the second selection voltage, wherein the second selection voltage is less than the first selection voltage.

9. The erasing method according to claim 1, characterized in that, The erasure method further includes: When a read operation is performed on the memory, if an error occurs in the read data, an erase operation is performed on the memory page corresponding to the read operation.

10. A memory, characterized in that, The device includes a memory array and peripheral circuitry. The memory array includes multiple word lines, multiple bit pairs, source-side select gate lines, drain-side select gate lines, and multiple memory cells. The peripheral circuitry is connected to the memory array and is used to execute the erase method of the memory according to any one of claims 1-9. The source-side gate selection line and the drain-side gate selection line are respectively disposed on both sides of the multiple word lines and connected to multiple pairs of bit lines. Each memory cell is connected to one word line and one pair of bit lines.

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