Memory device including page buffer circuit

Abstract

A memory device includes: a plurality of input / output pins; and a page buffer circuit including a plurality of page buffers configured in a first direction at M levels (M being an integer of 4 or greater), each of the plurality of page buffers being connected to one of the plurality of input / output pins, wherein the plurality of input / output pins includes a first group of input / output pins and a second group of input / output pins, and wherein the page buffers connected to the first group of input / output pins and the page buffers connected to the second group of input / output pins are respectively separated and disposed in a first page buffer region and a second page buffer region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0190473, filed with the Korean Intellectual Property Office on December 18, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a memory device including page buffer circuitry. Background Technology

[0004] NAND flash memory devices are widely used as data storage devices. NAND flash memory devices can perform the operations required to read and output data stored in memory cells by using page buffer circuitry. Summary of the Invention

[0005] In an embodiment, a memory device may include: a plurality of input / output pins; and a page buffer circuit including a plurality of page buffers configured in a first direction at multiple levels, each of the plurality of page buffers being connected to one of the plurality of input / output pins, wherein the plurality of input / output pins includes a first group of input / output pins and a second group of input / output pins, and wherein the page buffers connected to the first group of input / output pins and the page buffers connected to the second group of input / output pins are respectively divided into a first page buffer region corresponding to the first group and a second page buffer region corresponding to the second group.

[0006] In an embodiment, a memory device may include: a plurality of input / output pins; and a page buffer circuit including a plurality of page buffers configured in a first direction at multiple levels, each of the plurality of page buffers being connected to one of the plurality of input / output pins, wherein the plurality of input / output pins includes a first group of input / output pins, a second group of input / output pins, a third group of input / output pins, and a fourth group of input / output pins, and wherein the page buffers connected to the first group of input / output pins, the page buffers connected to the second group of input / output pins, the page buffers connected to the third group of input / output pins, and the page buffers connected to the fourth group of input / output pins are respectively separated and arranged as a first page buffer region, a second page buffer region, a third page buffer region, and a fourth page buffer region. Attached Figure Description

[0007] This disclosure will be more fully understood through the following detailed description and accompanying drawings, which are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0008] Figure 1 This is a block diagram of a memory device according to an embodiment of the present disclosure.

[0009] Figure 2 yes Figure 1 The equivalent circuit diagram of the storage block is shown.

[0010] Figure 3 This is a diagram illustrating the structure of a page buffer circuit according to an embodiment of the present disclosure.

[0011] Figure 4 This is a diagram illustrating the allocation of input / output paths in a page buffer circuit according to an embodiment of the present disclosure.

[0012] Figure 5 This is a diagram illustrating the arrangement of local input / output lines according to an embodiment of the present disclosure.

[0013] Figure 6 This is a block diagram of a page buffer according to an embodiment of the present disclosure.

[0014] Figure 7 This is a diagram illustrating the data output section of a page buffer according to an embodiment of the present disclosure.

[0015] Figure 8 This is a diagram illustrating a data input / output path according to an embodiment of the present disclosure.

[0016] Figure 9 This is a diagram illustrating the configuration of bit line contacts according to an embodiment of the present disclosure.

[0017] Figure 10 and Figure 11 This is a diagram illustrating the arrangement of the column decoder region and the contact opening region according to an embodiment of the present disclosure.

[0018] Figure 12 This is a diagram illustrating the configuration of a page buffer circuit according to an embodiment of the present disclosure.

[0019] Figure 13 This is a diagram illustrating the configuration of bit line contacts according to an embodiment of the present disclosure.

[0020] Figures 14 to 17 This is a diagram illustrating the arrangement of the column decoder region and the contact opening region according to an embodiment of the present disclosure.

[0021] Figure 18 This is a diagram illustrating the configuration of a page buffer circuit according to an embodiment of the present disclosure.

[0022] Figure 19 This is a diagram illustrating the arrangement of local input / output lines according to an embodiment of the present disclosure.

[0023] Figure 20 This is a diagram illustrating the configuration of bit line contacts according to an embodiment of the present disclosure.

[0024] Figure 21 This is a diagram illustrating the configuration of a page buffer circuit according to an embodiment of the present disclosure.

[0025] Figure 22 This is a diagram illustrating the arrangement of local input / output lines according to an embodiment of the present disclosure.

[0026] Figure 23 This is a diagram illustrating the configuration of bit line contacts according to an embodiment of the present disclosure.

[0027] Figure 24 This is a diagram illustrating the configuration of a page buffer circuit according to an embodiment of the present disclosure.

[0028] Figure 25 This is a diagram illustrating the arrangement of local input / output lines according to an embodiment of the present disclosure.

[0029] Figure 26 This is a diagram illustrating the configuration of bit line contacts according to an embodiment of the present disclosure.

[0030] Figure 27 This is a diagram illustrating the structure of a page buffer circuit according to an embodiment of the present disclosure.

[0031] Figure 28 This is a diagram illustrating the configuration of a page buffer circuit according to an embodiment of the present disclosure.

[0032] Figure 29 This is a diagram illustrating the arrangement of local input / output lines according to an embodiment of the present disclosure.

[0033] Figure 30 This is a diagram illustrating the configuration of a page buffer circuit according to an embodiment of the present disclosure.

[0034] Figure 31 This is a diagram illustrating the arrangement of local input / output lines according to an embodiment of the present disclosure.

[0035] Figure 32 and Figure 33 This is a diagram illustrating the configuration of a page buffer circuit according to an embodiment of the present disclosure.

[0036] Figure 34 This is a diagram illustrating the arrangement of local input / output lines according to an embodiment of the present disclosure.

[0037] Figures 35 to 37 This is a diagram showing the arrangement of the page buffer circuit and the local input / output lines according to the prior art compared to this disclosure. Detailed Implementation

[0038] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. The specific structural or functional descriptions of the embodiments are provided by way of example only to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0039] All crosshairs in the diagram represent corresponding or similar areas, rather than indicating material related to these areas.

[0040] When one element is marked "connected" or "attached" to another element, these elements can be directly connected or attached, or connected or attached through an intermediate element between the elements. When two elements are marked "directly connected" or "directly attached," one element is directly connected or directly attached to the other element without any intermediate element in between.

[0041] When one element is identified as being "above", "below", or "under" another element, these elements may be in direct contact with each other, or an intermediate element may be placed between these elements.

[0042] Terms such as “vertical,” “horizontal,” “top,” “bottom,” “above,” “below,” “down,” “under,” “below,” “above,” “upper,” “side,” “upper part,” “topmost,” “lowest,” “bottommost,” “front,” “back,” “left,” “right,” “column,” “row,” “layer,” and other terms indicating relative spatial relationships or directions are used for ease of description or reference to the accompanying drawings and are not intended to limit the scope of this disclosure. Other spatial relationships or directions not shown in the drawings or described in the specification are also possible within the scope of this disclosure.

[0043] Terms such as "first" and "second" are used to distinguish various elements and do not indicate the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be referred to as the second element, while in another example, the second element may be referred to as the first element.

[0044] In the specification, when an element included in an embodiment is described in the singular, the element can be interpreted as including multiple elements that perform the same or similar functions.

[0045] Figure 1 This is a block diagram of a memory device according to an embodiment of the present disclosure.

[0046] Reference Figure 1The memory device according to embodiments of the present disclosure may include a memory cell array 100 and peripheral circuitry 200. The peripheral circuitry 200 may include a row decoder (X-DEC) 210, a page buffer circuit 220, control logic 230, a column decoder 240, and input / output circuitry (IO circuitry) 250.

[0047] The memory cell array 100 may include a plurality of memory cells. The memory cell array 100 may be configured as a three-dimensional memory array in which the memory cells are stacked in a direction perpendicular to the substrate, but the configuration is not limited thereto.

[0048] The memory cell array 100 can be connected to the line decoder 210 via word line WL and select lines DSL and SSL. Select lines DSL and SSL may include a drain select line DSL and a source select line SSL. The memory cell array 100 can be connected to the page buffer circuit 220 via bit line BL. The memory cell array 100 can store data received through the page buffer circuit 220 during programming operations and transfer the stored data to the page buffer circuit 220 during read operations.

[0049] Memory cell array 100 may include multiple memory blocks BLK. A memory block BLK may be an erase unit. Word lines WL, select lines DSL and SSL, and bit lines BL may be connected to each memory block BLK. The word lines WL, select lines DSL and SSL may be connected to their respective memory block BLKs. The bit line BL may be connected together to multiple memory block BLKs. See below for further details. Figure 2 An example describing a storage block (BLK).

[0050] The row decoder 210 can select one of the memory blocks BLK in the memory cell array 100 in response to the row address X-ADDR received from the control logic 230. The row decoder 210 can transmit operating voltages to the word line WL and the selection lines DSL and SSL connected to the selected memory block BLK.

[0051] Page buffer circuit 220 may include multiple page buffers PB, each connected to bit line BL. Page buffers PB can exchange data with memory cell array 100 via bit line BL.

[0052] Page buffer circuit 220 can operate in response to a page buffer control signal PBCON received from control logic 230. During a write operation, page buffer PB can store data to be programmed into a memory cell. Page buffer PB can apply voltages to multiple bit lines BL based on the stored data. During a read operation or a verified read operation, page buffer PB can sense the voltage on the bit lines BL and store the sensing result.

[0053] Control logic 230 can generate the page buffer control signal PBCON in response to the command CMD input via input / output circuit 250. Control logic 230 can also generate the row address X-ADDR and column address Y-ADDR in response to the address ADDR input via input / output circuit 250.

[0054] The column decoder 240 exchanges data with the page buffer PB in response to the column address Y-ADDR from the control logic 230.

[0055] Input / output circuitry 250 can exchange data with column decoder 240. Input / output circuitry 250 can exchange data DATA with external devices, such as memory controllers, via input / output paths, and can transmit commands CMD and addresses ADDR received from external devices via input / output paths to control logic 230. Input / output paths may include 2... N (Where N is a natural number equal to or greater than 2) the number of input / output pins. In the example, N=3, meaning the input / output path can include eight input / output pins (IO pins). <0> To IO <7> ).

[0056] All or part of the peripheral circuitry 200 may be disposed on a different plane from the memory cell array 100. For example, the memory cell array 100 may be disposed in a first semiconductor layer, and the peripheral circuitry 200 may be disposed in a second semiconductor layer that vertically overlaps with the first semiconductor layer. Part or all of the peripheral circuitry 200 disposed in the second semiconductor layer may vertically overlap with the memory cell array 100.

[0057] Figure 2 yes Figure 1 The equivalent circuit diagram of the memory block shown is shown.

[0058] Reference Figure 2 Each memory block BLK may include multiple cell strings CSTR, which are connected between multiple bit lines BL and common source line CSL.

[0059] Each cell string (CSTR) can be connected between the corresponding bit line (BL) and the common source line (CSL). Each cell string (CSTR) may include a source select transistor (SST) connected to the common source line (CSL), a drain select transistor (DST) connected to the bit line (BL), and multiple memory cells (MCs) connected between the source select transistor (SST) and the drain select transistor (DST). The gate of the source select transistor (SST) can be connected to the source select line (SSL). The gate of each memory cell (MC) can be connected to its corresponding word line (WL). The gate of the drain select transistor (DST) can be connected to the drain select line (DSL).

[0060] The source select line (SSL), word line (WL), and drain select line (DSL) can extend in a direction perpendicular to the bit line (BL). The source select line (SSL), word line (WL), and drain select line (DSL) can be stacked in a direction perpendicular to the surface of the substrate to form a three-dimensional structure.

[0061] The memory cells (MCs) included in a memory block (BLK) can be divided into physical page units or logical page units. For example, memory cells that share a word line (WL) and are connected to different cell strings (CSTRs) can form a physical page (PG). A page (PG) can be the basic unit for read operations.

[0062] For example, Figure 2 The diagram shows one drain-select transistor (DST) and one source-select transistor (SST) in each cell string (CSTR). However, two or more drain-select transistors or two or more source-select transistors can be configured in each cell string (CSTR).

[0063] Figure 3 This is a diagram illustrating the structure of a page buffer circuit according to an embodiment of the present disclosure.

[0064] Reference Figure 3 The input / output pins can be divided into two groups. The input / output pins can include the first group of input / output pins IO<0:3> and the second group of input / output pins IO<4:7>. Figure 3 Eight input / output pins are shown, so the number of input / output pins IO<0:3> in the first group and the number of input / output pins IO<4:7> in the second group are each four. However, in other embodiments, the number of input / output pins may exceed eight. As the total number of input / output pins changes, the number of input / output pins included in each group also changes.

[0065] Page buffer circuit 220 includes a first page buffer group PB Group1 221 connected to the first group of input / output pins IO<0:3> and a second page buffer group PB Group2 222 connected to the second group of input / output pins IO<4:7>.

[0066] The first page buffer group 221 is connected to the input / output pins IO<0:3> of the first group via the column decoder 240 and the input / output circuit 250, and the second page buffer group 222 is connected to the input / output pins IO<4:7> of the second group via the column decoder 240 and the input / output circuit 250.

[0067] The first page buffer group 221 and the second page buffer group 222 are separate from each other and are respectively disposed in the first page buffer area R1 and the second page buffer area R2. The first page buffer area R1 and the second page buffer area R2 can be arranged in a second direction HD2 perpendicular to the first direction HD1.

[0068] The first direction HD1 is the extension direction of the bit line, and the second direction HD2 is the arrangement direction of the bit line. In this specification, the first direction HD1 can also be defined as the column direction, and the second direction HD2 can also be defined as the row direction.

[0069] Figure 4 This is a diagram illustrating the allocation of input / output paths in a page buffer circuit according to an embodiment of the present disclosure.

[0070] Reference Figure 4 The page buffer circuit 220 can be constructed as a six-stage circuit. Figure 4 In the middle, the page buffer PB of the page buffer circuit 220, which consists of six 6-stages, is set to six rows in the first direction HD1.

[0071] The number # of page buffer PB# indicates which input / output pin page buffer PB# is connected to. For example, page buffer PB0 is connected to input / output pin IO. <0> Page buffer PB2 is connected to the input / output pin IO. <2> Each page buffer PB in the first page buffer area R1 is connected to the first group of input / output pins (IO). <0> To IO <3> One of them, each page buffer PB in the second page buffer region R2 is connected to the second group of input / output pins IO. <4> To IO <7> one of the.

[0072] The page buffer PB is configured with six levels in the first page buffer area R1 along the first direction HD1, and the first group of input / output pins IO<0:3> can be sequentially assigned on the first direction HD1. The page buffer PB is configured with six levels in the second page buffer area R2 along the first direction HD1, and the second group of input / output pins IO<4:7> can be sequentially assigned on the first direction HD1.

[0073] Four page buffers PB belonging to the first page buffer region R1 and four page buffers PB belonging to the second page buffer region R2 can be simultaneously assigned to eight input / output pins IO<0:7> to form a single page buffer input / output unit. For example, in Figure 4In the first page buffer region R1, the four page buffers PB0, PB1, PB2 and PB3 included in the dashed box 221a and the four page buffers PB4, PB5, PB6 and PB7 included in the dashed box 222a of the second page buffer R2 can constitute a single page buffer input / output unit.

[0074] Within the page buffers PB in the first page buffer region R1, four page buffers PB belonging to a single page buffer input / output unit can constitute a first page buffer input / output subunit. For example, the four page buffers PB0, PB1, PB2, and PB3 included in dashed box 221a can constitute a first page buffer input / output subunit. Similarly, within the page buffers PB in the second page buffer region R2, four page buffers PB belonging to a single page buffer input / output unit can constitute a second page buffer input / output subunit. For example, the four page buffers PB4, PB5, PB6, and PB7 included in dashed box 222a can constitute a second page buffer input / output subunit.

[0075] Multiple first page buffer input / output sub-units are set in the first page buffer area R1, and multiple second page buffer input / output sub-units are set in the second page buffer area R2. One of the multiple first page buffer input / output sub-units and one of the multiple second page buffer input / output sub-units constitute a page buffer input / output unit.

[0076] Figure 5 This is a diagram illustrating the arrangement of partial input / output lines according to an embodiment of the present disclosure. For example, Figure 5 Showing settings Figure 4 Local input / output lines in the first page buffer area R1 and the second page buffer area R2.

[0077] For ease of explanation, this specification only shows and describes local input / output lines, but may further include inverting local input / output lines corresponding to the local input / output lines. The description of local input / output lines also applies to inverting local input / output lines.

[0078] Reference Figure 5 Multiple local input / output lines (LIOs) are provided in each of the first page buffer region R1 and the second page buffer region R2. The local input / output lines (LIOs) can extend in the second horizontal direction HD2 and can be arranged parallel to each other.

[0079] Within a single-level page buffer PB, page buffers PB connected to the same input / output pins are collectively connected to a local input / output line LIO.

[0080] Since the page buffer PB belonging to each stage in each of the first page buffer region R1 and the second page buffer region R2 is connected to two input / output pins, each stage is configured with two local input / output lines LIO. Specifically, in the first page buffer region R1, since page buffer "PB0" connected to input / output pin IO0 and page buffer "PB3" connected to input / output pin IO3 are configured in Stage... <0> Stage <3> and Stage <4> In each of the levels, therefore in Stage <0> Stage <3> and Stage <4> Each level is configured with local input / output lines (LIOs) corresponding to "0" and "3". <0> and LIO <3> In the first page buffer region R1, page buffer "PB1" connected to input / output pin IO1 and page buffer "PB2" connected to input / output pin IO2 are set in Stage. <1> Stage <2> and Stage <5> In each of the levels, therefore in Stage <1> Stage <2> and Stage <5> Each level has a local input / output line (LIO) corresponding to "1" and "2". <1> and LIO <2> .

[0081] In the second page buffer region R2, page buffer "PB4" connected to input / output pin IO4 and page buffer "PB7" connected to input / output pin IO7 are set at Stage <0> Stage <3> and Stage <4> In each of the levels, therefore in Stage <0> Stage <3> and Stage <4> Each level has a local input / output line (LIO) corresponding to "4" and "7". <4> and LIO <7> In the second page buffer region R2, page buffer "PB5" connected to input / output pin IO5 and page buffer "PB6" connected to input / output pin IO6 are set in Stage <1> Stage <2> and Stage <5> In each of the levels, therefore in Stage <1> Stage <2> and Stage <5> Each level has a local input / output line (LIO) corresponding to "5" and "6". <5> and LIO <6> .

[0082] Figure 6 This is a block diagram of a page buffer according to an embodiment of the present disclosure.

[0083] Reference Figure 6 The page buffer PB includes a bit line selection unit 10, a sensing unit 20, a precharge unit 30, a latch unit 40, and a data output unit 50.

[0084] Bit line selection unit 10 is connected between bit line BL and sensing unit 20, and electrically connects bit line BL and sensing unit 20 during read operations. Sensing unit 20 is connected between bit line selection unit 10 and sensing node SO. During read operations, sensing unit 20 connects to sensing node SO via bit line BL connected through bit line selection unit 10, and evaluates sensing node SO based on the current in bit line BL. For example, sensing unit 20 reduces the potential of sensing node SO from a pre-charge first level to a second level based on the current in bit line BL. The larger the current in bit line BL, the shorter the time it takes for the potential of sensing node SO to decrease to the second level. That is, during read operations, the potential of sensing node SO decreases from the first level to the second level based on the cell current of the selected memory cell connected to bit line BL. When the cell current of the selected memory cell is large, the time it takes for sensing node SO to decrease from the first level to the second level is short; when the cell current of the selected memory cell is small, the time it takes for sensing node SO to decrease from the first level to the second level is long.

[0085] The pre-charge unit 30 is connected to the sensing node SO. During the read operation, the bit line BL is pre-charged to a set level by the sensing unit 20 and the bit line selection unit 10, and the sensing node SO is pre-charged to a first level. The latch unit 40 is connected to the sensing node SO and latches data by periodically sensing the potential level of the sensing node SO. The data output unit 50 is connected between the output terminal of the latch unit 40 and the local input / output line LIO, receives the data latched by the latch unit 40, and outputs the data to the local input / output line LIO.

[0086] Figure 7 This is a diagram illustrating the data output section of a page buffer according to an embodiment of the present disclosure. For example, Figure 7 Stage R1 of the first page buffer area is shown. <0> The data output sections of page buffers PB0 and PB3 are included in the stage.

[0087] Reference Figure 7 A page buffer (PB) may include data output transistors. The number of data output transistors is the same as the number of local input / output lines set in the level of the page buffer region to which the page buffer PB belongs.

[0088] For example, when in Stage R1 of the first page buffer area <0> Two local input / output lines LIO_T1 are set in the stage. <0> and LIO_T1 <3> At this time, each of the data output sections 50a and 50b of page buffer PB0 and page buffer PB3 may include two data output transistors. Specifically, the data output section 50a of page buffer PB0 includes a first data output transistor TR1 and a second data output transistor TR2, and the data output section 50b of page buffer PB3 includes a third data output transistor TR3 and a fourth data output transistor TR4. The first data output transistor TR1 is connected to the local input / output line LIO_T1. <0> The fourth data output transistor TR4 is connected to the local input / output line LIO_T1. <3> .

[0089] Since the number of data output transistors included in the page buffer PB is the same as the number of local input / output lines set in the stage of the page buffer region to which the page buffer PB belongs, the size of the page buffer PB may need to be increased when the number of local input / output lines set in the stage to which the page buffer PB belongs increases.

[0090] Embodiments of this disclosure can divide input / output pins into a first group and a second group, and can separate and set up page buffers connected to the input / output pins of the first group and page buffers connected to the input / output pins of the second group in different regions. Therefore, the number of local input / output lines set up at each stage in each page buffer region can be reduced, thereby reducing the number of data output transistors included in the page buffer and reducing the size of the page buffer.

[0091] For ease of explanation, Figure 7 Only local input / output lines and data output transistors are shown, but may further include inverting local input / output lines corresponding to the local input / output lines and inverting data output transistors corresponding to the data output transistors.

[0092] Figure 8 This is a diagram illustrating a data input / output path according to an embodiment of the present disclosure.

[0093] Reference Figure 8 Each local input / output line (LIO) is connected to a corresponding switching circuit (SW), and then connected to a corresponding global input / output line (GIO) via the switching circuit (SW). A multiplexer (MUX) may include two switching circuits (SW), and the multiplexer (MUX) may include... Figure 1 In column decoder 240.

[0094] Each of the global input / output lines (GIOs) is connected to the corresponding input / output sense amplifier (IOSA). Global input / output lines (GIOs) that are connected to a single input / output pin (IO) are connected to each other before being connected to the input / output sense amplifier (IOSA), and can be connected to the input / output sense amplifier (IOSA) while still connected to each other.

[0095] Input / output circuit 250 (see) Figure 1 It may include multiple input / output sense amplifiers (IOSAs), and each input / output sense amplifier (IOSA) is connected to an input / output pin (IO).

[0096] In data output operations, in response to column address Y-ADDR (see...) Figure 1 Choose one of the following multiplexers: MUX1 connected to local input / output line LIO_T1<0,3>, MUX4 connected to local input / output line LIO_T4<0,3>, and MUX5 connected to local input / output line LIO_T5<0,3>; and choose one of the following multiplexers: MUX2 connected to local input / output line LIO_T2<1,2>, MUX3 connected to local input / output line LIO_T3<1,2>, and MUX6 connected to local input / output line LIO_T6<1,2>. One multiplexer is selected from multiplexers MUX7 (connected to local input / output lines LIO_T1<4,7>), MUX10 (connected to local input / output lines LIO_T4<4,7>), and MUX11 (connected to local input / output lines LIO_T5<4,7>); and one multiplexer is selected from multiplexers MUX8 (connected to local input / output lines LIO_T2<5,6>), MUX9 (connected to local input / output lines LIO_T3<5,6>), and MUX12 (connected to local input / output lines LIO_T6<5,6>). During the selection period, the switching circuits SW included in the four selected multiplexers MUX are turned on, and the local input / output lines LIO and global input / output lines GIO connected to the turned-on switching circuits SW are electrically connected to each other. The switch circuit SW included in the unselected multiplexer MUX is turned off, and the local input / output lines connected to the turned-off switch circuit SW are electrically isolated from the global input / output lines.

[0097] Figure 9 This is a diagram illustrating the arrangement of bit line contacts according to an embodiment of the present disclosure. By way of example, Figure 9 Show Figure 4The setting of bit line contacts in the page buffer circuit.

[0098] Reference Figure 9 The page buffer PB can be configured as a 6-stage, and the six bit lines 6-BL can be set in each column of the first page buffer area R1 and the second page buffer area R2. Each page buffer PB is connected to the corresponding bit line BL via bit line contacts CNT.

[0099] Bit line contacts (CNTs) can be arranged diagonally in a column. For example, in the first column, as the page buffer PB is positioned lower in the direction opposite to the first direction HD1, the bit line contacts (CNTs) can be arranged at positions that move further away in the second direction HD2. Similarly, in the second column, as the page buffer PB is positioned higher in the first direction HD1, the bit line contacts (CNTs) can be arranged at positions that move further away in the second direction HD2. When the bit line contacts are arranged as described above in two adjacent columns of page buffers, the repeated bit line contacts in the first and second columns form a V-shape.

[0100] In each of the first page buffer region R1 and the second page buffer region R2, the bit lines BL connected to the page buffers PB belonging to the individual page buffer input / output subunits (indicated by bold boxes) are arranged adjacent to each other.

[0101] When the bit line contact CNT is set to V-shape, the four bit lines (hereinafter referred to as "bit line input / output sub-units") connected to the bit line contact CNT in each of the first page buffer region R1 and the second page buffer region R2 can be set continuously.

[0102] Unlike this disclosure, when the four bit lines belonging to a single bit line input / output subunit are not discontinuous, defect particles appearing at the boundary between two adjacent bit line input / output subunits may cause defects in both bit line input / output subunits. In other words, when the bit lines belonging to the same bit line input / output subunit are not discontinuous, the probability of defects appearing in two adjacent bit line input / output subunits may increase when defect particles appear at or near the boundary between bit line input / output subunits.

[0103] According to embodiments of this disclosure, since the four bit lines belonging to a single bit line input / output subunit are arranged consecutively, the probability of defects in the bit line input / output unit due to defect particles can be reduced.

[0104] Figure 10 and Figure 11This is a diagram illustrating the arrangement of the column decoder region and the contact opening region according to an embodiment of the present disclosure. By way of example, Figure 10 and Figure 11 Showing with Figure 4 The settings of the column decoder area and contact opening area related to the page buffer circuit.

[0105] Reference Figure 10 Multiple column decoder regions (CSRs) are arranged on the first direction HD1. Multiple column decoder codecs (CSDECs) are disposed within the column decoder regions (CSRs). The multiple column decoder codecs constitute the column decoder circuit 240 (see [reference]). Figure 1 ).

[0106] One of the odd-numbered stages and one of the even-numbered stages of the page buffer circuit (e.g., PB0 and PB1) are set in the column decoder region CSRs adjacent to each other on the first direction HD1 (e.g., with Stage). <0> and Stage <1> Between adjacent CSRs.

[0107] The column decoder CSDEC is connected to the adjacent page buffer PB on the first direction HD1 via a page line PL. The page line PL can extend on the first direction HD1. The column decoder CSDEC on the second direction HD2 is larger than the page buffer PB on the second direction HD2. For example, the column decoder CSDEC on the second direction HD2 can be twice the size of the page buffer PB on the second direction HD2.

[0108] The contact opening region OFC is positioned on the first direction HD1 between the odd and even stages of the page buffer circuit, which in turn are located between the two column decoder regions CSR.

[0109] Bit line contacts (not shown) connecting the page buffer PB and the bit lines can be located in the contact opening region OFC. Bit line contacts connecting the page buffer PB of odd-numbered and even-numbered stages located on both sides of a contact opening region OFC can be located in that contact opening region OFC. For example, two adjacent stages (e.g., Stage...) <0> and Stage <1> The OFC is a contact opening area located directly between two adjacent stages.

[0110] exist Figure 10 In this design, there are three OFC (Oriented Contact Opening Regions) and four CSR (Column Renderer Regions). Since the number of OFCs not used for circuit setup is less than the number of CSRs, more substrate area is used for circuit setup.

[0111] Reference Figure 11Multiple contact opening areas OFC are arranged in the first direction HD1.

[0112] One of the odd-numbered stages and one of the even-numbered stages of the page buffer circuit are positioned between two adjacent contact opening regions OFC on the first direction HD1.

[0113] Two adjacent OFC stages, separated by a contact opening region, share a single OFC. However, the top-level stage... <0> and the lowest level Stage <5> Each of them does not share the OFC (Opportunity Opening Area) with other levels.

[0114] A column decoder region (CSR) is set between the odd and even stages of the page buffer circuit, and these two stages and the column decoder region (CSR) can be set between two contact opening regions (OFC).

[0115] Each of the column decoders CSDEC, located in the column decoder region CSR, is connected to the adjacent page buffer PB on the first direction HD1 via the page line PL.

[0116] One of the page buffers PB in odd-numbered levels and one of the page buffers PB in even-numbered levels are connected to a column decoder CSDEC to share that column decoder CSDEC. In this embodiment, in all levels, the page buffer PB shares the column decoder CSDEC with another page buffer PB.

[0117] Since all page buffers PB share the column decoder CSDEC with other page buffers PB, the number of column decoder CSDECs can be reduced compared to the case where there are page buffers PB that do not share the column decoder CSDEC with other page buffers PB, and the column decoder circuitry 240 can be reduced (see [link]). Figure 1 The size of the column decoder circuit 240 (see...) Figure 1 It can be configured to a smaller size, thus allowing for the addition of additional circuitry for setting up the divider decoder circuit 240 (see [link]). Figure 1 The available area of ​​other circuits besides ).

[0118] Figure 12 This is a diagram illustrating the configuration of a page buffer circuit according to an embodiment of the present disclosure.

[0119] Reference Figure 12 Page buffers PB are set in the first page buffer area R1 and arranged in six levels on the first direction HD1. The four page buffers PB included in a first page buffer input / output subunit 221a-1 are set in a 2×2 matrix form on the first direction HD1 and the second direction HD2.

[0120] Page buffers PB are located in the second page buffer region R2 and arranged in six stages on the first direction HD1. The four page buffers PB included in a second page buffer input / output subunit 222a-1 are arranged in a 2×2 matrix on the first direction HD1 and the second direction HD2. Due to the arrangement of local input / output lines and... Figure 5 Since they are the same, repeated descriptions are omitted here.

[0121] Figure 13 This is a diagram illustrating the arrangement of bit line contacts according to an embodiment of the present disclosure. By way of example, Figure 13 Show Figure 12 The setting of bit line contacts in the page buffer circuit.

[0122] Reference Figure 13 The bit line contacts (CNTs) can be configured as a diagonal shape extending in the same direction across all columns. This configuration of the bit line contacts (CNTs) can be defined as a unidirectional diagonal shape. Two bit lines (BLs) connected to two page buffers (PBs) adjacent to each other in the first direction (HD1) are configured to be directly adjacent to each other.

[0123] Because the bit line contacts (CNTs) are arranged diagonally in the six bit lines (6-BL), bit line contacts (CNTs) in the same row (i.e., the same level) can be configured to not be adjacent to each other. As the integration density of memory devices increases, the spacing between bit lines (BL) becomes narrower. In this case, when two bit line contacts (CNTs) in the same row are adjacent to each other, there is a high probability of a short circuit between the two bit line contacts (CNTs). Figure 13 As shown, arranging the bit line contacts CNTs in a unidirectional diagonal shape in the six bit line 6-BL columns can reduce the defect of short circuits between the bit line contacts CNTs.

[0124] Figures 14 to 17 This is a diagram illustrating the arrangement of the column decoder region and the contact opening region according to an embodiment of the present disclosure. By way of example, Figures 14 to 17 Showing with Figure 12 The settings of the column decoder area and contact opening area related to the page buffer circuit.

[0125] Reference Figure 14 The rows of the column decoder region CSR are arranged on the first direction HD1.

[0126] Two levels are set between two adjacent column decoder regions (CSRs) on the first direction HD1. This belongs to a single page buffer input / output subunit 221a-1 or 222a-1 (see...). Figure 12 The four page buffers (PB) are arranged in a 2×2 matrix between two adjacent column decoder regions (CSR).

[0127] Because it belongs to a single-page buffer input / output subunit 221a-1 or 222a-1 (see...) Figure 12 The four page buffers PB are set between two adjacent column decoder regions CSR, so the column decoder CSDEC and page buffers PB connected to each other via page lines PL can be set to be adjacent to each other in the first direction HD1.

[0128] The page line PL extends in the first direction HD1 and connects the column decoder CSDEC and page buffer PB, which are adjacent to each other, and the length of these connections can be relatively short.

[0129] A contact opening region (OFC) is positioned between two stages, which in turn are positioned between two adjacent column decoder regions (CSRs). Bit line contacts of the page buffers (PBs) of the two stages located on either side of the contact opening region (OFC) can be positioned within the contact opening region (OFC). Therefore, the page buffers (PBs) of the two stages positioned on either side of the contact opening region (OFC) can share the same contact opening region (OFC).

[0130] Reference Figure 15 Two page buffers PB are adjacent to the same column decoder CSDEC in the first direction HD1. The first page buffer PB can be connected to the column decoder CSDEC via the page line PL. The second page buffer PB can be connected to the column decoder CSDEC via the page connection line PCL connected to the page line PL in the first page buffer PB. The page connection line PCL is not directly connected to the column decoder CSDEC.

[0131] Page connection lines (PCLs) can be set in a different routing layer than the routing layer where page lines (PLs) are set. Because the page lines (PLs) and page connection lines (PCLs) connecting the page buffer (PB) and the column decoder (CSDEC) are set in different routing layers, the number of traces in a single routing layer can be reduced, and the spacing between adjacent traces within the same layer can be increased to reduce interference between traces.

[0132] Reference Figure 16 Multiple contact opening regions OFC extending in the second direction HD2 are arranged in the first direction HD1.

[0133] One of the odd-numbered stages and one of the even-numbered stages are set between two adjacent contact opening regions OFC on the first direction HD1. This belongs to a single page buffer input / output subunit 221a-1 or 222a-1 (see...). Figure 12 The four page buffers PB are arranged in a 2×2 matrix between two adjacent contact opening regions OFC.

[0134] A column decoder region (CSR) is positioned between two stages, which in turn are positioned between two adjacent contact opening regions (OFC). A single page buffer input / output subunit 221a-1 or 222a-1 (see...) Figure 12 The four page buffers PB included in the code are divided such that two page buffers PB are respectively set on each side of a column decoder CSDEC in the first direction HD1.

[0135] The page buffer PB is connected to the column decoder CSDEC via a page line PL extending in the first direction HD1. The page line PL can extend from the center of the column decoder CSDEC in the first direction HD1 to both sides of the column decoder CSDEC, thereby connecting the column decoder CSDEC and the page buffer PB located on each side of the column decoder CSDEC.

[0136] Reference Figure 17 Multiple contact opening areas OFC, page buffer PB, column decoder CSDEC, and level are set to be consistent with Figure 16 The configurations shown are basically the same, so they will not be repeated here. Figure 17 In this configuration, two of the four page buffers PB, located adjacent to a column decoder CSDEC on the first direction HD1, can be connected to the column decoder CSDEC via page lines PL. The other two can be connected to page lines PL via page connection lines PCL. Page connection lines PCL are not directly connected to the column decoder CSDEC. Page connection lines PCL can be located on a different routing layer than the routing layer on which page lines PL are located.

[0137] Figure 18 This is a diagram illustrating the configuration of a page buffer circuit according to an embodiment of the present disclosure.

[0138] Reference Figure 18 The page buffer circuit 220 can be composed of five 5-stages. The page buffer PB of the page buffer circuit 220 composed of five 5-stages is arranged in five rows on the first direction HD1.

[0139] The page buffer PB is configured with five levels in the first page buffer area R1 in the first direction HD1, and the first group of input / output pins IO<0:3> can be sequentially assigned on the first direction HD1. Similarly, the page buffer PB is configured with five levels in the second page buffer area R2 in the first direction HD1, and the second group of input / output pins IO<4:7> can be sequentially assigned on the first direction HD1.

[0140] Four page buffers PB in the first page buffer region R1 and four page buffers PB in the second page buffer region R2 can be simultaneously assigned to eight input / output pins IO<0:7> to form a page buffer input / output unit.

[0141] Within the page buffers PB in the first page buffer region R1, there are four page buffers PB belonging to a single page buffer input / output unit, namely the four page buffers PB0, PB1, PB2, and PB3 ( Figure 18 (highlighted in bold) can constitute the first page buffer input / output subunit. Within the page buffers PB in the second page buffer region R2, the four page buffers PB belonging to a single page buffer input / output unit are PB4, PB5, PB6, and PB7 (…). Figure 18 (highlighted in bold) can form the second page buffer input / output subunit.

[0142] Figure 19 This is a diagram illustrating the arrangement of partial input / output lines according to an embodiment of the present disclosure. For example, Figure 19 Showing settings Figure 18 Local input / output lines in the first page buffer area R1 and the second page buffer area R2.

[0143] Reference Figure 19 Since the page buffer PB set in each stage of the first page buffer region R1 and the second page buffer region R2 is connected to four input / output pins, four local input / output lines LIO are set in each stage.

[0144] For example, since page buffers "PB0", "PB1", "PB2" and "PB3" are set in each level of the first page buffer area R1, local input / output lines LIO corresponding to "0", "1", "2" and "3" are set in each level of the first page buffer area R1, respectively. <0> LIO <1> LIO <2> and LIO <3> Since page buffers "PB4", "PB5", "PB6" and "PB7" are set in each level of the second page buffer area R2, local input / output lines LIO corresponding to "4", "5", "6" and "7" are set in each level of the second page buffer area R2, respectively. <4> LIO <5> LIO <6> and LIO <7> .

[0145] Figure 20 This is a diagram illustrating the arrangement of bit line contacts according to an embodiment of the present disclosure. By way of example, Figure 20 Show Figure 18The setting of bit line contacts in the page buffer circuit.

[0146] Reference Figure 20 The page buffer PB can be set to five stages (5-Stage), and five bit lines (5-BL) can be set in each column of the first page buffer area R1 and the second page buffer area R2.

[0147] Each page buffer PB is connected to the bit line BL via bit line contacts CNTs. The bit line contacts CNTs can be arranged diagonally within the columns of the five bit lines 5-BL. For example, in the first column, as the page buffer PB is positioned lower in the direction opposite to the first direction HD1, the bit line contacts CNTs can be positioned progressively further away in the second direction HD2. Similarly, in the second column, as the page buffer PB is positioned higher in the first direction HD1, the bit line contacts CNTs can be positioned progressively further away in the second direction HD2. Therefore, the bit line contacts CNTs in the five adjacent columns of bit lines 5-BL can be arranged in a V-shape.

[0148] In each of the first page buffer region R1 and the second page buffer region R2, the bit lines BL connected to the page buffers PB that belong to a single page buffer input / output subunit and are adjacent to each other are set to be adjacent to each other.

[0149] Figure 21 This is a diagram illustrating the configuration of a page buffer circuit according to an embodiment of the present disclosure.

[0150] Reference Figure 21 The page buffer PB is located in the first page buffer area R1 and arranged in five levels on the first direction HD1. The first group of input / output pins IO<0:3> can be sequentially allocated on the second direction HD2. The page buffer PB is located in the second page buffer area R2 and arranged in five levels on the first direction HD1. The second group of input / output pins IO<4:7> can be sequentially allocated on the second direction HD2.

[0151] The page buffer PB belonging to the first page buffer input / output subunit 221a-2 (i.e., the page buffer PB surrounded by a thick line in the first page buffer region R1) is set as a line in the second direction HD2, and the page buffer PB belonging to the second page buffer input / output subunit 222a-2 (i.e., the page buffer PB surrounded by a thick line in the second page buffer region R2) is set as a line in the second direction HD2.

[0152] Figure 22 This is a diagram illustrating the arrangement of partial input / output lines according to an embodiment of the present disclosure. For example, Figure 22Showing settings Figure 21 Local input / output lines in the first page buffer area R1 and the second page buffer area R2.

[0153] Reference Figure 22 Since the page buffer PB set in each stage of the first page buffer region R1 and the second page buffer region R2 is connected to four input / output pins respectively, four local input / output lines LIO are set in each stage.

[0154] Specifically, since each level in the first page buffer region R1 is configured with page buffers "PB0", "PB1", "PB2" and "PB3", each level in the first page buffer region R1 is configured with a local input / output line LIO. <0> LIO <1> LIO <2> and LIO <3> Since each stage in the second page buffer region R2 is configured with page buffers "PB4", "PB5", "PB6" and "PB7", each stage of the second page buffer region R2 is configured with a local input / output line LIO. <4> LIO <5> LIO <6> and LIO <7> .

[0155] Figure 23 This is a diagram illustrating the configuration of bit line contacts according to an embodiment of the present disclosure.

[0156] Reference Figure 23 The page buffers PB belonging to each of the first and second page buffer input / output subunits are arranged as a line in the second direction HD2, and the bit line contacts CNT can be arranged in a unidirectional diagonal shape in each column. In each column, the two bit lines BL connected to two adjacent page buffers PB in the first direction HD1 are set to be directly adjacent to each other, and the bit line contacts CNT in the same row (i.e., the same level) can be arranged such that the bit line contacts are spaced apart and not directly adjacent.

[0157] Figure 24 This is a diagram illustrating the configuration of a page buffer circuit according to an embodiment of the present disclosure.

[0158] Reference Figure 24 The page buffer circuit 220 can be configured as a four-stage circuit. The page buffer PB of the four-stage page buffer circuit 220 is configured as four rows arranged on the first direction HD1.

[0159] Page buffers PB are located in the first page buffer region R1 and arranged in four levels along the first direction HD1. The four page buffers PB included in a first page buffer input / output subunit 221a-3 are arranged in a 2×2 matrix form along the first direction HD1 and the second direction HD2. Page buffers PB are located in the second page buffer region R2 and arranged in four levels along the first direction HD1. The four page buffers PB included in a second page buffer input / output subunit 222a-3 are arranged in a 2×2 matrix form along the first direction HD1 and the second direction HD2.

[0160] Figure 25 This is a diagram illustrating the arrangement of partial input / output lines according to an embodiment of the present disclosure. For example, Figure 25 Show Figure 24 The settings for local input / output lines in the first page buffer area R1 and the second page buffer area R2.

[0161] Reference Figure 25 Since the page buffer PB set in each stage of the first page buffer region R1 and the second page buffer region R2 is connected to two input / output pins, each stage is equipped with two local input / output lines LIO.

[0162] Specifically, in the first page buffer area R1, due to Stage <0> and Stage <3> Page buffers "PB0" and "PB2" are set in each stage, therefore in Stage <0> and Stage <3> Each stage in the series is equipped with a local input / output line (LIO). <0> and LIO <2> In the first page buffer area R1, due to Stage <1> and Stage <2> Page buffers "PB1" and "PB3" are set in each stage, therefore in Stage <1> and Stage <2> Each stage in the series is equipped with a local input / output line (LIO). <1> and LIO <3> In the second page buffer area R2, due to Stage <0> and Stage <3> Page buffers "PB4" and "PB6" are set in each stage, therefore in Stage <0> and Stage <3> Each stage in the series is equipped with a local input / output line (LIO). <4> and LIO <6> In the second page buffer area R2, due to Stage <1> and Stage <2> Page buffers "PB5" and "PB7" are set in each stage, therefore in Stage <1> and Stage <2> Each stage in the series is equipped with a local input / output line (LIO). <5> and LIO <7> .

[0163] Figure 26This is a diagram illustrating the arrangement of bit line contacts according to an embodiment of the present disclosure. By way of example, Figure 26 Show Figure 24 The setting of bit line contacts in the page buffer circuit.

[0164] Reference Figure 26 The page buffer PB can be set to four stages, and four bit lines 4-BL can be set in each column of the first page buffer area R1 and the second page buffer area R2.

[0165] Each page buffer PB is connected to a bit line BL via a bit line contact CNT. The bit line contact CNT can be set in a unidirectional diagonal shape in all columns. In each column, the two bit lines BL of two page buffers PB that are respectively connected to each other on the first direction HD1 are set to be directly adjacent to each other, and the bit line contacts CNT in a single row (i.e., the same level) can be set to not be directly adjacent to each other.

[0166] In the above reference Figures 3 to 26 In the described embodiment, the page buffer connected to the input / output pins of the first group is disposed in a first page buffer region, and the page buffer connected to the input / output pins of the second group is disposed in a second page buffer region, but this disclosure is not limited thereto. The page buffer connected to the input / output pins of the first group may be disposed in multiple first page buffer regions, and the page buffer connected to the input / output pins of the second group may be disposed in multiple second page buffer regions. For example, the first page buffer region and the second page buffer region may be alternately disposed on the second direction HD2.

[0167] In the above reference Figures 3 to 26 In the described embodiment, the input / output pins are divided into two groups, but this disclosure is not limited thereto. In other embodiments, the input / output pins may be divided into four groups or other numbers of groups.

[0168] Figure 27 This is a diagram illustrating the structure of a page buffer circuit according to an embodiment of the present disclosure.

[0169] Reference Figure 27 The input / output pins can be divided into four groups. The input / output pins can include the first group of input / output pins IO<0:1>, the second group of input / output pins IO<2:3>, the third group of input / output pins IO<4:5>, and the fourth group of input / output pins IO<6:7>. Figure 27 Eight input / output pins are shown, and two input / output pins belong to each group. However, when the total number of input / output pins changes, the number of input / output pins belonging to each group also changes to reflect the total number.

[0170] Page buffer circuit 220 includes: a first page buffer group PB Group1 221', connected to the input / output pins IO<0:1> of the first group; a second page buffer group PB Group2 222', connected to the input / output pins IO<2:3> of the second group; a third page buffer group PB Group3 223', connected to the input / output pins IO<4:5> of the third group; and a fourth page buffer group PB Group4 224', connected to the input / output pins IO<6:7> of the fourth group.

[0171] The first page buffer group 221', the second page buffer group 222', the third page buffer group 223', and the fourth page buffer group 224' can be separated from each other and respectively disposed in the first page buffer area R1', the second page buffer area R2', the third page buffer area R3', and the fourth page buffer area R4'. The first page buffer area R1', the second page buffer area R2', the third page buffer area R3', and the fourth page buffer area R4' can be arranged on the second direction HD2.

[0172] Figure 28 This is a diagram illustrating the configuration of a page buffer circuit according to an embodiment of the present disclosure.

[0173] Reference Figure 28 The page buffer circuit 220 can be composed of six 6-stages.

[0174] Page buffer PB is located in the first page buffer area R1' and arranged in six levels on the first direction HD1. The first group of input / output pins IO<0:1> can be sequentially assigned on the first direction HD1. Page buffer PB is located in the second page buffer area R2' and arranged in six levels on the first direction HD1. The second group of input / output pins IO<2:3> can be sequentially assigned on the first direction HD1. Page buffer PB is located in the third page buffer area R3' and arranged in six levels on the first direction HD1. The third group of input / output pins IO<4:5> can be sequentially assigned on the first direction HD1. Page buffer PB is located in the fourth page buffer area R4' and arranged in six levels on the first direction HD1. The fourth group of input / output pins IO<6:7> can be sequentially assigned on the first direction HD1.

[0175] Two page buffers PB belonging to the first page buffer region R1', two page buffers PB belonging to the second page buffer region R2', two page buffers PB belonging to the third page buffer region R3', and two page buffers PB belonging to the fourth page buffer region R4' can be simultaneously assigned to eight input / output pins IO<0:7> to form a page buffer input / output unit. For example, in Figure 28 In the first page buffer region R1', the two page buffers PB0 and PB1 included in the dashed box 221a-4, the two page buffers PB2 and PB3 included in the dashed box 222a-4, the two page buffers PB4 and PB5 included in the dashed box 223a-4, the third page buffer region R3', and the two page buffers PB6 and PB7 included in the dashed box 224a-4, can constitute a page buffer input / output unit.

[0176] Two page buffers PB belonging to a single page buffer input / output unit in the first page buffer region R1' can form a first page buffer input / output subunit. Two page buffers PB belonging to a single page buffer input / output unit in the second page buffer region R2' can form a second page buffer input / output subunit. Two page buffers PB belonging to a single page buffer input / output unit in the third page buffer region R3' can form a third page buffer input / output subunit. Two page buffers PB belonging to a single page buffer input / output unit in the fourth page buffer region R4' can form a fourth page buffer input / output subunit.

[0177] Figure 29 This is a diagram illustrating the arrangement of partial input / output lines according to an embodiment of the present disclosure. For example, Figure 29 Show Figure 28 Local input / output lines set in the first page buffer area R1', the second page buffer area R2', the third page buffer area R3', and the fourth page buffer area R4'.

[0178] Reference Figure 29 Since the page buffer PB set in each of the first page buffer region R1', the second page buffer region R2', the third page buffer region R3' and the fourth page buffer region R4' is connected to an input / output pin, each stage is set with a local input / output line LIO.

[0179] Specifically, due to the Stage in the first page buffer area R1' <0> Stage <2> and Stage <4> Each stage in the stage sets the page buffer "PB0", therefore in Stage <0> Stage <2> and Stage <4> Each stage in the series is configured with local input / output lines (LIO). <0> Due to the Stage of the first page buffer area R1' <1> Stage <3> and Stage <5> Each stage in the stage sets up a page buffer "PB1", therefore in Stage <1> Stage <3> and Stage <5> Each stage in the series is configured with local input / output lines (LIO). <1> .

[0180] Local input / output lines are also set in the second page buffer area R2', the third page buffer area R3', and the fourth page buffer area R4' in a similar manner to the first page buffer area R1'.

[0181] Figure 30 This is a diagram illustrating the configuration of a page buffer circuit according to an embodiment of the present disclosure.

[0182] Reference Figure 30 The page buffer circuit 220 can be composed of five 5-stage stages.

[0183] In the first page buffer area R1', the page buffer PB is configured with five levels arranged in the first direction HD1, and the first group of input / output pins IO<0:1> can be sequentially assigned in the second direction HD1. In the second page buffer area R2', the page buffer PB is configured with five levels in the first direction HD1, and the second group of input / output pins IO<2:3> can be sequentially assigned in the second direction HD2. In the third page buffer area R3', the page buffer PB is configured with five levels in the first direction HD1, and the third group of input / output pins IO<4:5> can be sequentially assigned in the second direction HD2. In the fourth page buffer area R4', the page buffer PB is configured with five levels in the first direction HD1, and the fourth group of input / output pins IO<6:7> can be sequentially assigned in the second direction HD2.

[0184] Figure 31 This is a diagram illustrating the arrangement of partial input / output lines according to an embodiment of the present disclosure. For example, Figure 31 Show Figure 30 Local input / output lines set in the first page buffer area R1', the second page buffer area R2', the third page buffer area R3', and the fourth page buffer area R4'.

[0185] Reference Figure 31Since the page buffer PB set in each of the first page buffer region R1', the second page buffer region R2', the third page buffer region R3' and the fourth page buffer region R4' is connected to two input / output pins, two local input / output lines LIO are set in each stage.

[0186] Specifically, since page buffers "PB0" and "PB1" are set in each level of the first page buffer region R1', a local input / output line LIO is set in each level. <0> and LIO <1> Local input / output lines are also set in the second page buffer area R2', the third page buffer area R3', and the fourth page buffer area R4' in a similar manner to the first page buffer area R1'.

[0187] Figure 32 This is a diagram illustrating the configuration of a page buffer circuit according to an embodiment of the present disclosure.

[0188] Reference Figure 32 The page buffer circuit 220 can be composed of five 5-stage stages.

[0189] Page buffer PB is located in the first page buffer area R1' and arranged in five levels on the first direction HD1. The first group of input / output pins IO<0:1> can be sequentially assigned on the first direction HD1. Page buffer PB is located in the second page buffer area R2' and arranged in five levels on the first direction HD1. The second group of input / output pins IO<2:3> can be sequentially assigned on the first direction HD1. Page buffer PB is located in the third page buffer area R3' and arranged in five levels on the first direction HD1. The third group of input / output pins IO<4:5> can be sequentially assigned on the first direction HD1. Page buffer PB is located in the fourth page buffer area R4' and arranged in five levels on the first direction HD1. The fourth group of input / output pins IO<6:7> can be sequentially assigned on the first direction HD1. Due to the arrangement of local input / output lines and... Figure 31 Since they are the same, repeated descriptions are omitted here.

[0190] Figure 33 This is a diagram illustrating the configuration of a page buffer circuit according to an embodiment of the present disclosure.

[0191] Reference Figure 33 The page buffer circuit 220 can be composed of four 4-stage stages.

[0192] Page buffer PB is located in the first page buffer area R1' and arranged in four levels on the first direction HD1. The input / output pins IO<0:1> of the first group can be sequentially assigned on the first direction HD1. Page buffer PB is located in the second page buffer area R2' and arranged in four levels on the first direction HD1. The input / output pins IO<2:3> of the second group can be sequentially assigned on the first direction HD1. Page buffer PB is located in the third page buffer area R3' and arranged in four levels on the first direction HD1. The input / output pins IO<4:5> of the third group can be sequentially assigned on the first direction HD1. Page buffer PB is located in the fourth page buffer area R4' and arranged in four levels on the first direction HD1. The input / output pins IO<6:7> of the fourth group can be sequentially assigned on the first direction HD1.

[0193] Figure 34 This is a diagram illustrating the arrangement of partial input / output lines according to an embodiment of the present disclosure. For example, Figure 34 Show Figure 33 Local input / output lines set in the first page buffer area R1', the second page buffer area R2', the third page buffer area R3', and the fourth page buffer area R4'.

[0194] Reference Figure 34 Since the page buffer PB set in each of the first page buffer region R1', the second page buffer region R2', the third page buffer region R3' and the fourth page buffer region R4' is connected to an input / output pin, each stage is provided with a local input / output line LIO.

[0195] Specifically, due to the Stage in the first page buffer area R1' <0> and Stage <2> Each stage sets the page buffer "PB0", therefore in Stage <0> and Stage <2> Each setting in the level is a local input / output line (LIO). <0> Due to the Stage in the first page buffer area R1' <1> and Stage <3> Each of the stages sets the page buffer "PB1", therefore in Stage <1> and Stage <3> Each setting in the level is a local input / output line (LIO). <1> .

[0196] Local input / output lines are also set in the second page buffer area R2', the third page buffer area R3', and the fourth page buffer area R4' in a similar manner to the first page buffer area R1'.

[0197] Figures 35 to 37This is a diagram showing the arrangement of the page buffer circuit and the local input / output lines according to the prior art compared to this disclosure.

[0198] Reference Figure 35 The page buffer circuit's page buffers PB are configured as six stages arranged on the first direction HD1, and the input / output pins IO<0:7> are sequentially assigned to the page buffers PB on the first direction HD1. The number of input / output pins connected to the page buffers included in each stage is four, and each stage has four local input / output lines.

[0199] Refer again Figure 5 According to embodiments of this disclosure, each of the six stages comprising a page buffer PB connected to each of the first page buffer region R1 and the second page buffer region R2 includes two input / output pins, and each stage is provided with two local input / output lines. The number of local input / output lines provided in each stage is two, which is less than the number provided according to... Figure 35 The number of local input / output lines disclosed in the prior art.

[0200] Refer again Figure 29 According to embodiments of this disclosure, each of the six levels of the first page buffer region R1', the second page buffer region R2', the third page buffer region R3', and the fourth page buffer region R4' includes one input / output pin for the page buffer, and each level is provided with one local input / output line. The number of local input / output lines provided in each level is one, which is less than the number of pins provided in the first page buffer region R1', the second page buffer region R2', the third page buffer region R3', and the fourth page buffer region R4'. Figure 35 The number of existing technologies disclosed in the literature.

[0201] Reference Figure 36 The page buffer circuit's page buffer PB is configured in five stages on the first direction HD1, with input / output pins IO<0:7> sequentially assigned to the page buffer PB on the first direction HD1. The number of input / output pins connected to the page buffers included in each stage is eight, and each stage has eight local input / output lines.

[0202] Refer again Figure 19 and Figure 22 According to embodiments of this disclosure, each of the five stages connected to each of the first page buffer region R1 and the second page buffer region R2 includes four input / output pins for the page buffer, and four local input / output lines are provided in each stage. The number of local input / output lines provided in each stage is four, which is less than the number of local input / output lines provided in the first page buffer region R1 and the second page buffer region R2. Figure 36 The number of local input / output lines disclosed in the prior art.

[0203] Refer again Figure 31 According to embodiments of this disclosure, each of the five stages connected to each of the first page buffer region R1', the second page buffer region R2', the third page buffer region R3', and the fourth page buffer region R4' includes a page buffer with two input / output pins, and each stage has two local input / output lines. The number of local input / output lines in each stage is two, which is less than the number of local input / output lines provided according to the present disclosure. Figure 36 The number of local input / output lines disclosed in the prior art.

[0204] Reference Figure 37 The page buffer circuit's page buffer PB is configured as four stages on the first direction HD1, and the input / output pins IO<0:7> are sequentially assigned to the page buffer PB on the first direction HD1. In this case, the number of input / output pins connected to the page buffer included in each stage is two, and two local input / output lines are provided in each stage.

[0205] Refer again Figure 34 According to embodiments of this disclosure, the number of input / output pins for the page buffers included in each of the four stages connected to each of the first page buffer region R1', the second page buffer region R2', the third page buffer region R3', and the fourth page buffer region R4' is one, and each stage is provided with one local input / output line. The number of local input / output lines provided in each stage is one, which is less than the number of local input / output lines provided in the embodiments of this disclosure. Figure 37 The number of existing technologies disclosed in the literature.

[0206] According to embodiments of this disclosure, since the number of local input / output lines arranged in parallel with each other in each stage is less than the number of local input / output lines according to the prior art, the spacing between adjacent local input / output lines can be increased and the coupling between adjacent local input / output lines can be reduced.

[0207] Furthermore, since the number of local input / output lines arranged in parallel with each other in each stage is less than the number of local input / output lines according to the prior art, the number of data output transistors in the page buffer can be reduced, and the area of ​​the page buffer can be reduced.

[0208] Although specific embodiments of the present disclosure have been disclosed, those skilled in the art will understand that various modifications, additions, and substitutions can be made to these embodiments without departing from the scope and concept of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the foregoing embodiments. All changes within the equivalent meaning and scope of the claims are included within its scope.

Claims

1. A memory device, comprising: Multiple input / output pins; as well as A page buffer circuit includes multiple page buffers configured in a first direction at multiple levels, each of the multiple page buffers being connected to one of the multiple input / output pins. The plurality of input / output pins includes a first group of input / output pins and a second group of input / output pins, and The page buffers connected to the input / output pins of the first group and the page buffers connected to the input / output pins of the second group are respectively divided into a first page buffer region corresponding to the first group and a second page buffer region corresponding to the second group.

2. The memory device according to claim 1, wherein, The first page buffer region and the second page buffer region are arranged in a second direction perpendicular to the first direction.

3. The memory device according to claim 1, further comprising: Column decoder circuitry, including multiple column decoders; as well as Local input / output lines connect the page buffer circuit and the multiple column decoders. The local input / output lines include: The first set of local input / output lines is connected to the page buffer of the first page buffer area; and The second set of local input / output lines is connected to the page buffer of the second page buffer area.

4. The memory device according to claim 3, wherein, The local input / output lines of the first group are set in the first page buffer area, and The local input / output lines of the second group are set in the second page buffer area.

5. The memory device according to claim 3, wherein, The number of the multiple input / output pins is eight. The number of the multiple levels is six, and Two local input / output lines are provided in each level of each of the first page buffer region and the second page buffer region.

6. The memory device according to claim 3, wherein, The number of the multiple input / output pins is eight. The number of the multiple levels is five, and Four local input / output lines are provided in each level of each of the first page buffer region and the second page buffer region.

7. The memory device according to claim 3, wherein, The number of the multiple input / output pins is eight. The number of the multiple levels is four, and Two local input / output lines are provided in each level of each of the first page buffer region and the second page buffer region.

8. The memory device according to claim 3, wherein, Each of the plurality of page buffers includes a data output transistor. Each of the plurality of stages is provided with N local input / output lines, where N is an integer, and Each of the plurality of page buffers includes N data output transistors.

9. The memory device according to claim 1, further comprising: Multiple column decoder regions; as well as Multiple contact opening areas, Among the plurality of levels, one of the odd-numbered levels and one of the even-numbered levels are positioned between two adjacent column decoder regions within the plurality of column decoder regions, and One of the plurality of contact opening regions is located between the odd-numbered and even-numbered levels among the plurality of levels.

10. The memory device of claim 1, further comprising: Multiple column decoder regions; as well as Multiple contact opening areas, Among these, one of the multiple odd-numbered levels and one of the multiple even-numbered levels are positioned between two adjacent contact opening regions within the multiple contact opening regions, and One of the plurality of column decoder regions is located between the odd-numbered levels and the even-numbered levels.

11. The memory device according to claim 1, wherein, The multiple page buffers are respectively connected to multiple bit lines via bit line contacts, and Bit lines belonging to a bit line input / output unit are set to be consecutively adjacent to each other.

12. The memory device according to claim 1, wherein, The multiple page buffers are respectively connected to multiple bit lines via bit line contacts, and The bit line contacts in a single stage of the page buffer circuit are configured not to be directly adjacent to each other.

13. A memory device, comprising: Multiple input / output pins; as well as A page buffer circuit includes multiple page buffers configured in a first direction at multiple levels, each of the multiple page buffers being connected to one of the multiple input / output pins. The plurality of input / output pins includes a first group of input / output pins, a second group of input / output pins, a third group of input / output pins, and a fourth group of input / output pins. The page buffers connected to the input / output pins of the first group, the page buffers connected to the input / output pins of the second group, the page buffers connected to the input / output pins of the third group, and the page buffers connected to the input / output pins of the fourth group are respectively separated and arranged as a first page buffer region, a second page buffer region, a third page buffer region, and a fourth page buffer region.

14. The memory device according to claim 13, wherein, The first page buffer region, the second page buffer region, the third page buffer region, and the fourth page buffer region are arranged in a second direction perpendicular to the first direction.

15. The memory device of claim 13, further comprising: Column decoder circuitry, including multiple column decoders; as well as Local input / output lines connect the page buffer circuit and the multiple column decoders. The local input / output lines include: The local input / output lines of the first group are connected to the page buffer of the first page buffer area; The second set of local input / output lines is connected to the page buffer of the second page buffer area; The third set of local input / output lines is connected to the page buffer of the third page buffer region; and The fourth group of local input / output lines is connected to the page buffer of the fourth page buffer area.

16. The memory device according to claim 15, wherein, The local input / output lines of the first group are set in the first page buffer area. The second group of local input / output lines is set in the second page buffer area. The local input / output lines of the third group are located in the third page buffer area, and The local input / output lines of the fourth group are located in the fourth page buffer area.

17. The memory device according to claim 15, wherein, The number of the multiple input / output pins is eight. The number of the multiple levels is six, and A local input / output line is provided in each level of each of the first page buffer region, the second page buffer region, the third page buffer region, and the fourth page buffer region.

18. The memory device according to claim 15, wherein, The number of the multiple input / output pins is eight. The number of the multiple levels is five, and Two local input / output lines are provided in each level of each of the first page buffer region, the second page buffer region, the third page buffer region, and the fourth page buffer region.

19. The memory device according to claim 15, wherein, The number of the multiple input / output pins is eight. The number of the multiple levels is four, and A local input / output line is provided in each level of each of the first page buffer region, the second page buffer region, the third page buffer region, and the fourth page buffer region.

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