Memory devices and memory systems

Abstract

The present invention provides a memory device and a memory system. The memory device includes a plurality of memory blocks for storing first stored data and for comparing the first stored data with first input data to generate a first current signal. The memory blocks include a plurality of memory word strings coupled to each other for generating a plurality of word string current signals. The memory blocks are used to add the word string current signals to generate the first current signal, and the current level of the first current signal is proportional to a difference between an input value of the first input data and a stored value of the first stored data.

Description

Technical Field

[0001] This invention relates to a memory technology, and more particularly to a memory device and memory system. Background Technology

[0002] Manhattan distance is a scale used to determine the distance between two data points in a lattice-like path, and it can be used to measure the sum of the differences between multiple coordinates between two data points. In artificial intelligence applications, Manhattan distance can provide good accuracy. However, memory devices used to calculate Manhattan distance can be unstable and complex to operate. Therefore, designing a stable and easy-to-operate memory device for calculating Manhattan distance is an important issue in this field. Summary of the Invention

[0003] This invention includes a memory device. The memory device includes a plurality of memory blocks for storing first stored data and for comparing the first stored data with first input data to generate a first current signal. Each memory block includes a plurality of memory strings coupled to each other for generating a plurality of string current signals. The memory blocks are used to add the string current signals to generate the first current signal, and the current level of the first current signal is proportional to a difference between an input value of the first input data and a stored value of the first stored data.

[0004] In some embodiments, the memory string is used to receive a plurality of string select line signals, the string select line signals including a first string select line signal and a second string select line signal. When the first input data has a first input value, each of the first string select line signal and the second string select line signal has a first voltage level. When the first input data has a second input value, the first string select line signal and the second string select line signal have a first voltage level and a second voltage level, respectively. And when the first input data has a third input value, each of the first string select line signal and the second string select line signal has a second voltage level.

[0005] In some embodiments, the second voltage level is lower than the first voltage level, and the second input value is lower than the first input value and greater than the third input value.

[0006] In some embodiments, the first stored data includes at least a first stored data bit and a second stored data bit, and the memory string includes a first switching element for storing the first stored data bit and a second switching element for storing the second stored data bit. When the first stored data has a first stored value, each of the first switching element and the second switching element has a first threshold voltage level. When the first stored data has a second stored value, the first switching element and the second switching element have a first threshold voltage level and a second threshold voltage level, respectively. And when the first stored data has a third stored value, each of the first switching element and the second switching element has a second threshold voltage level.

[0007] In some embodiments, the second threshold voltage level is less than the first threshold voltage level, and the second stored value is less than the first stored value and greater than the third stored value.

[0008] In some embodiments, when there is a first difference between the input value of the first input data and the stored value of the first stored data, each string current signal in a first portion of the string current signal has a first current level, and the number of string current signals in the first portion is equal to the first difference.

[0009] In some embodiments, when there is a second difference between the input value of the first input data and the stored value of the first stored data, each string current signal in a second portion of the string current signal has a first current level, the number of string current signals in the second portion is equal to the second difference, and the second difference is greater than the first difference.

[0010] In some embodiments, the memory string is used to receive a plurality of string select line signals, the string select line signals including a first string select line signal and a second string select line signal. When the first input data has a first input value, the first string select line signal and the second string select line signal respectively have a first voltage level and a second voltage level. When the first input data has a second input value, the first string select line signal and the second string select line signal respectively have a second voltage level and a first voltage level.

[0011] In some embodiments, the second voltage level is greater than the first voltage level, and the second input value is greater than the first input value.

[0012] In some embodiments, the memory string includes: a first switching element for receiving a first string select line signal; a second switching element for receiving a second string select line signal; a third switching element connected in series with the first switching element; and a fourth switching element connected in series with the second switching element, wherein when the first stored data has a first stored value, the third switching element is turned off and the fourth switching element is turned on, and when the first stored data has a second stored value, the third switching element is turned on and the fourth switching element is turned off.

[0013] In some embodiments, the memory string further includes: a fifth switching element for receiving a third string selection line signal from the string selection line signals; and a sixth switching element for receiving a fourth string selection line signal from the string selection line signals, wherein when the first input data has a first input value, the third string selection line signal and the fourth string selection line signal have a second voltage level and a first voltage level, respectively.

[0014] In some embodiments, the memory string further includes: a seventh switching element coupled in series with a fifth switching element; and an eighth switching element coupled in series with a sixth switching element, wherein when the first stored data has a third stored value, the seventh switching element is turned off and the eighth switching element is turned on, and when the first stored data has a second stored value, the seventh switching element is turned on and the eighth switching element is turned off.

[0015] This invention includes a memory device. The memory device includes a plurality of memory word strings coupled to each other. The memory word strings are used to generate a plurality of word string current signals and to add the word string current signals together to generate a first current signal. The memory word strings include a first switching element group and a second switching element group. The first switching element group is used to receive a plurality of word string select line signals, which carry first input data. The second switching element group is used to store the first stored data. The current level of the first current signal is proportional to a difference between an input value of the first input data and a stored value of the first stored data.

[0016] In some embodiments, the first switching element group includes a first switching element and a second switching element, the second switching element group includes a third switching element and a fourth switching element, the first switching element and the second switching element are respectively connected in series with the third switching element and the fourth switching element, and each of the third switching element and the fourth switching element is turned off when the first switching element and the second switching element are turned on, in response to the input value being equal to the stored value.

[0017] In some embodiments, when each of the first and second switching elements is turned on, a third switching element is turned on in response to an input value greater than a stored value, and when each of the first and second switching elements is turned on, a fourth switching element is turned on in response to an input value less than a stored value.

[0018] This invention includes a memory system. The memory system includes multiple first memory block groups and multiple second memory block groups. The first memory block groups are used to generate multiple first current signals and sum the first current signals to generate a first bit line signal. The second memory block groups are used to generate multiple second current signals and sum the second current signals to generate a second bit line signal. The first memory block groups include a third memory block group for storing first stored data and generating a third current signal from the first current signals. The second memory block groups include a fourth memory block group for storing second stored data and generating a fourth current signal from the second current signals. The current level of the third current signal is proportional to a first difference between a stored value of the first stored data and an input value of the first input data, and the current level of the fourth current signal is proportional to a second difference between a stored value of the second stored data and the input value of the first input data.

[0019] In some embodiments, in response to the first difference being less than the second difference, the current level of the third current signal is less than the current level of the fourth current signal.

[0020] In some embodiments, the first memory block group further includes a fifth memory block group for storing third stored data and generating a fifth current signal in the first current signal, the current level of the fifth current signal being proportional to a third difference between a stored value of the third stored data and an input value of a second input data, and in response to the third difference being equal to the first difference, the current level of the fifth current signal being equal to the current level of the third current signal.

[0021] In some embodiments, the first memory block group further includes a sixth memory block group for storing fourth stored data and generating a sixth current signal in the first current signal, the current level of the sixth current signal being proportional to a fourth difference between a stored value of the fourth stored data and an input value of the second input data, and the current level of the sixth current signal being greater than the current level of the fourth current signal in response to the fourth difference being greater than the second difference.

[0022] In some embodiments, in response to the fourth difference being less than the third difference, the current level of the sixth current signal is less than the current level of the fifth current signal. Attached Figure Description

[0023] Figure 1AThis is a schematic diagram illustrating a portion of a memory device according to some embodiments of the present invention.

[0024] Figures 1B to 1H The diagram illustrates other scenarios of a memory device according to some embodiments of the present invention.

[0025] Figure 1I This is a schematic diagram illustrating the distribution of threshold voltage levels of a switching element according to some embodiments of the present invention.

[0026] Figure 2A This is a schematic diagram of a memory device according to some embodiments of the present invention.

[0027] Figure 2B A schematic diagram illustrating further details of a memory device according to some embodiments of the present invention.

[0028] Figure 2C This is a schematic diagram illustrating the encoding method of stored data and input data in a memory device according to some embodiments of the present invention.

[0029] Figure 2D This is a schematic diagram illustrating input data with various input values ​​according to some embodiments of the present invention.

[0030] Figure 2E This is a schematic diagram illustrating various stored values ​​of stored data according to some embodiments of the present invention.

[0031] Figure 2F This is a schematic diagram illustrating the storage and input of data in a memory device according to some embodiments of the present invention.

[0032] Figure 3A and Figure 3B This is a schematic diagram of a memory device according to some embodiments of the present invention.

[0033] Figure 4A This is a schematic diagram illustrating a memory system according to some embodiments of the present invention.

[0034] Figure 4B Illustrations based on some embodiments of the present invention Figure 4A A schematic diagram showing further details of the memory system.

[0035] Figures 4C to 4F This is a schematic diagram of a group of memory blocks in a memory system according to some embodiments of the present invention.

[0036] Figures 5A to 5D Illustrations based on some embodiments of the present invention Figure 2AThe diagram shows the storage and input data of the memory device.

[0037] Figures 6A to 6D Illustrations based on some embodiments of the present invention Figures 4C to 4F The diagram shows a search operation performed on a group of memory blocks.

[0038] Figure 6E Illustrations based on some embodiments of the present invention Figure 4A A schematic diagram showing further details of the memory system.

[0039] Explanation of reference numerals in the attached figures:

[0040] 100, 200A, 300A, 300B: Memory devices

[0041] MS1, MS1_1~MS32_8: Memory strings

[0042] IS1, IS1_1~IS4_8: String current signals

[0043] TS, T0~T95, T1_1_0~T4_8_191, TS1_1~TS4_8: Switching elements

[0044] WL0~WL191: Word line signals

[0045] SSL, SSL1_1~SSL32_8: String select line signals

[0046] HVT, LVT: Threshold voltage level

[0047] HVSSL, LVSSL: Voltage Level

[0048] VREAD: Read voltage level

[0049] VPASS: Through voltage level

[0050] RSTR1: String resistor

[0051] r, R: Resistance values

[0052] 100I: Schematic diagram

[0053] BK1~BK32: Memory blocks

[0054] SBK1_1~SBK32_8: Sub-blocks

[0055] MBL: Home Line

[0056] BL1~BL128K: Bit line signals

[0057] IT1: Current signal

[0058] SDT0~ SDT191: Storing data

[0059] IDT: Input Data

[0060] ISL1: Current Level

[0061] SDB1_1_0~ SDB4_8_191: Storage data bits

[0062] 400: Memory System

[0063] 410: Memory device

[0064] 420: Sensing device

[0065] 430: Buffer encoding device

[0066] 440: Output device

[0067] BKG1_1~BKG128K_128: Memory block group

[0068] SDT1_1~SDT128K_128: Data storage

[0069] IDT1~IDT128: Input Data

[0070] IT1_1~IT128K_128: Current signals

[0071] MS1_1_1_1~MS128K_128_4_8: Memory string

[0072] IS1_1_1_1~ IS128K_128_4_8: String current signal

[0073] T1_1_1_1~ T128K_128_4_8, TS1_1_1_1~ TS128K_128_4_8: Switching elements

[0074] SSL1_1~SSL512_8: String select line signals Detailed Implementation

[0075] In this document, when an element is referred to as a "connection" or "coupled," it may mean an "electrical connection" or "electrical coupling." "Connection" or "coupled" can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as "first," "second," etc., are used herein to describe different elements, these terms are merely used to distinguish elements or operations described using the same technical terms. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply any order or sequence, nor are they intended to limit the invention.

[0076] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and this invention, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0077] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include multiple forms, including "at least one." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms "comprising" and / or "including" specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0078] The following describes several embodiments of the present invention with reference to the accompanying drawings. For clarity, many practical details will be described in conjunction with the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential. Furthermore, for the sake of simplicity, some known and conventional structures and elements will be shown in the drawings in a simple schematic manner.

[0079] Figure 1A This is a schematic diagram illustrating a portion of a memory device 100 according to some embodiments of the present invention. In some embodiments, the memory device 100 may include a plurality of memory strings, such as memory string MS1. Memory string MS1 is used to generate a string current signal IS1.

[0080] like Figure 1A As shown, the memory string MS1 can contain multiple switching elements, such as switching elements TS and T0~T95. However, the embodiments of the present invention are not limited thereto. In various embodiments, the memory string MS1 can contain various numbers of switching elements, that is, 95 can be replaced with other positive integers.

[0081] In some embodiments, switching elements T0~T95 and TS are connected in series and arranged sequentially. The control terminals of switching elements T0~T95 and TS are used to receive word line signals WL0~WL95 and word string select line signal SSL, respectively.

[0082] In some embodiments, switching elements T0~T95 can store corresponding stored data bits and have corresponding threshold voltage levels HVT or LVT. The threshold voltage level HVT is greater than the threshold voltage level LVT. For example, the threshold voltage level HVT can be between 3 volts and 4 volts, and the threshold voltage level LVT can be between 0 volts and 1 volt.

[0083] In some embodiments, the string select line signal SSL can carry the corresponding input bits and have a corresponding voltage level HVSSL or LVSSL. When the string select line signal SSL has a voltage level of HVSSL, the switching element TS is turned on. When the string select line signal SSL has a voltage level of LVSSL, the switching element TS is turned off. In some embodiments, the voltage level HVSSL is greater than the voltage level LVSSL. For example, the voltage level HVSSL is approximately equal to 3 volts, and the voltage level LVSSL is approximately equal to 0 volts.

[0084] In various embodiments, one of the word line signals WL0~WL95 has a read voltage level VREAD to read the corresponding stored data bit. For example, in Figure 1A In the illustrated embodiment, the word line signal WL95 has a read voltage level VREAD to read the stored data bit corresponding to the switching element T95. In some embodiments, the read voltage level VREAD is greater than the threshold voltage level LVT and less than the threshold voltage level HVT. For example, the read voltage level VREAD may be 2 volts.

[0085] Correspondingly, when the switching element has a threshold voltage level LVT and the control terminal of the switching element has a read voltage level VREAD, the switching element is turned on. When the switching element has a threshold voltage level HVT and the control terminal of the switching element has a read voltage level VREAD, the switching element is turned off.

[0086] On the other hand, Figure 1A In the illustrated embodiment, each of the word line signals WL0~WL94 has a pass voltage level VPASS, causing each of the switching elements T0~T94 to be turned on. The word string select line signal SSL has a voltage level HVSSL, causing the switching element TS to be turned on. At this time, the resistance value of the word string resistor RSTR1 of the memory word string MS1 depends on the threshold voltage level of the switching element T95. In some embodiments, the pass voltage level VPASS is greater than the threshold voltage level HVT. For example, the pass voltage level VPASS can be between 6 volts and 7 volts.

[0087] exist Figure 1AIn the illustrated embodiment, the switching element T95 has a threshold voltage level LVT, such that the word string resistor RSTR1 has a resistance value r. Correspondingly, the word string current signal IS1 has a current level ISL1.

[0088] Figure 1B This is a schematic diagram illustrating another scenario of the memory device 100 according to some embodiments of the present invention. Figure 1B In the illustrated embodiment, each of the word line signals WL0 to WL94 has a voltage level VPASS that turns on each of the switching elements T0 to T94. The word string select line signal SSL has a voltage level HVSSL that turns on the switching element TS.

[0089] At this time, in response to the switching element T95 having a threshold voltage level HVT and the word line signal WL95 having a read voltage level VREAD, the switching element T95 is turned off, causing the word string resistor RSTR1 to have a resistance value R. The resistance value R corresponds to the memory word string with the switching element turned off. Correspondingly, the word string current signal IS1 has a current level ISL2. Please refer to... Figure 1A and Figure 1B The resistance value R is greater than the resistance value r. Correspondingly, the current level ISL2 is less than the current level ISL1 and can be considered as zero current level.

[0090] Figure 1C This is a schematic diagram illustrating another scenario of the memory device 100 according to some embodiments of the present invention. Figure 1C In the illustrated embodiment, each of the word line signals WL0 to WL94 has a pass voltage level VPASS, causing each of the switching elements T0 to T94 to be turned on. Switching element T95 is turned on in response to a threshold voltage level LVT and a read voltage level VREAD for the word line signal WL95. At this time, the word string select line signal SSL has a voltage level LVSSL, causing the switching element TS to be turned off. Correspondingly, the word string resistor RSTR1 has a resistance value R. The word string current signal IS1 has a current level ISL2.

[0091] Figure 1D This is a schematic diagram illustrating another scenario of the memory device 100 according to some embodiments of the present invention. Figure 1DIn the illustrated embodiment, each of the word line signals WL0 to WL94 has a pass voltage level VPASS, causing each of the switching elements T0 to T94 to be turned on. In response to switching element T95 having a threshold voltage level HVT and word line signal WL95 having a read voltage level VREAD, switching element T95 is turned off. At this time, the word string select line signal SSL has a voltage level HVSSL, causing switching element TS to be turned on. Correspondingly, the word string resistor RSTR1 has a resistance value R. The word string current signal IS1 has a current level ISL2.

[0092] Figure 1E This is a schematic diagram illustrating another scenario of the memory device 100 according to some embodiments of the present invention. Figure 1E In the illustrated embodiment, the memory device 100 is used to read the stored data bits of the corresponding switching element T93. Correspondingly, the word line signal WL93 has a read voltage level VREAD. Each of the word line signals WL0~WL92 and WL94~WL95 has a pass voltage level VPASS, causing each of the switching elements T0~T92 and T94~T95 to be turned on. In response to the switching element T93 having a threshold voltage level LVT and the word line signal WL93 having a read voltage level VREAD, the switching element T93 is turned on. At this time, the word string select line signal SSL has a voltage level HVSSL, causing the switching element TS to be turned on. Correspondingly, the word string resistor RSTR1 has a resistance value r. The word string current signal IS1 has a current level ISL1.

[0093] Figure 1F This is a schematic diagram illustrating another scenario of the memory device 100 according to some embodiments of the present invention. Figure 1F In the illustrated embodiment, each of the word line signals WL0~WL92 and WL94~WL95 has a pass voltage level VPASS, causing each of the switching elements T0~T92 and T94~T95 to be turned on. In response to switching element T93 having a threshold voltage level HVT and word line signal WL93 having a read voltage level VREAD, switching element T93 is turned off. At this time, the word string select line signal SSL has a voltage level HVSSL, causing switching element TS to be turned on. Correspondingly, the word string resistor RSTR1 has a resistance value R. The word string current signal IS1 has a current level ISL2.

[0094] Figure 1G This is a schematic diagram illustrating another scenario of the memory device 100 according to some embodiments of the present invention. Figure 1GIn the illustrated embodiment, each of the word line signals WL0~WL92 and WL94~WL95 has a pass voltage level VPASS, causing each of the switching elements T0~T92 and T94~T95 to be turned on. Switching element T93 is turned on in response to a threshold voltage level LVT and a read voltage level VREAD for the word line signal WL93. At this time, the word string select line signal SSL has a voltage level LVSSL, causing the switching element TS to be turned off. Correspondingly, the word string resistor RSTR1 has a resistance value R. The word string current signal IS1 has a current level ISL2.

[0095] Figure 1H This is a schematic diagram illustrating another scenario of the memory device 100 according to some embodiments of the present invention. Figure 1H In the illustrated embodiment, each of the word line signals WL0~WL92 and WL94~WL95 has a pass voltage level VPASS, causing each of the switching elements T0~T92 and T94~T95 to be turned on. In response to switching element T93 having a threshold voltage level HVT and word line signal WL93 having a read voltage level VREAD, switching element T93 is turned off. At this time, the word string select line signal SSL has a voltage level LVSSL, causing switching element TS to be turned off. Correspondingly, the word string resistor RSTR1 has a resistance value R. The word string current signal IS1 has a current level ISL2.

[0096] Figure 1I A schematic diagram 100I illustrating the distribution of threshold voltage levels of a switching element according to some embodiments of the present invention. Figure 1I The horizontal axis in the graph corresponds to voltage, and Figure 1I The vertical axis corresponds to the number of switching elements. In some embodiments, the switching elements may have different threshold voltage levels to store different logic values. For example... Figure 1I As shown, when the switching element has a threshold voltage level HVT, the switching element stores a logic value of 0. When the switching element has a threshold voltage level LVT, the switching element stores a logic value of 1. The read voltage level VREAD is between the threshold voltage levels HVT and LVT.

[0097] Figure 2A This is a schematic diagram illustrating a memory device 200A according to some embodiments of the present invention. Figure 2AAs shown, memory device 200A includes memory blocks BK1 to BK4. Memory block BK1 includes sub-blocks SBK1_1 to SBK1_8. Memory block BK2 includes sub-blocks SBK2_1 to SBK2_8. Memory block BK3 includes sub-blocks SBK3_1 to SBK3_8. Memory block BK4 includes sub-blocks SBK4_1 to SBK4_8. However, embodiments of the present invention are not limited thereto. In various embodiments, memory device 200A may include various numbers of memory blocks and sub-blocks. In other words, the 4 and 8 mentioned above may be replaced with other positive integers.

[0098] In some embodiments, the 32 sub-blocks SBK1_1 to SBK4_8 each contain 32 memory strings MS1_1 to MS4_8. The memory strings MS1_1 to MS4_8 are coupled to each other on the main bit line MBL and are used to generate the bit line signal BL1.

[0099] like Figure 2A As shown, each of the memory word strings MS1_1 to MS4_8 is used to receive word line signals WL0 to WL191. The memory word strings MS1_1 to MS4_8 are respectively used to receive word string selection line signals SSL1_1 to SSL4_8.

[0100] exist Figure 2A In the illustrated embodiment, the memory device 200A performs a read operation on the switching element corresponding to the word line signal WL191. Correspondingly, the word line signal WL191 has a read voltage level VREAD, and each of the word line signals WL0 to WL190 has a pass voltage level VPASS.

[0101] Please refer to Figures 1A to 2A The configuration of each memory string MS1_1 to MS4_8 is similar to that of memory string MS1. Therefore, for the sake of brevity, some descriptions will not be repeated. Details of memory strings MS1_1 to MS4_8 are described below. Figure 2B The embodiments are further illustrated below.

[0102] Figure 2B A schematic diagram illustrating further details of a memory device 200A according to some embodiments of the present invention. Figure 2BAs shown, memory strings MS1_1 to MS4_8 are arranged sequentially in the horizontal direction. Memory string MS1_1 contains switching elements T1_1_0 to T1_1_191 and TS1_1, which are connected in series and arranged sequentially. Memory string MS1_2 contains switching elements T1_2_0 to T1_2_191 and TS1_2, which are connected in series and arranged sequentially, and so on. Memory string MS1_8 contains switching elements T1_8_0 to T1_8_191 and TS1_8, which are connected in series and arranged sequentially.

[0103] Similarly, memory string MS2_1 contains switching elements T2_1_0 to T2_1_191 and TS2_1 that are connected in series and arranged sequentially. Memory string MS2_2 contains switching elements T2_2_0 to T2_2_191 and TS2_2 that are connected in series and arranged sequentially, and so on. Memory string MS2_8 contains switching elements T2_8_0 to T2_8_191 and TS2_8 that are connected in series and arranged sequentially.

[0104] Similarly, memory string MS3_1 contains switching elements T3_1_0 to T3_1_191 and TS3_1 that are connected in series and arranged sequentially. Memory string MS3_2 contains switching elements T3_2_0 to T3_2_191 and TS3_2 that are connected in series and arranged sequentially, and so on. Memory string MS3_8 contains switching elements T3_8_0 to T3_8_191 and TS3_8 that are connected in series and arranged sequentially.

[0105] Similarly, memory string MS4_1 contains switching elements T4_1_0 to T4_1_191 and TS4_1 that are connected in series and arranged sequentially. Memory string MS4_2 contains switching elements T4_2_0 to T4_2_191 and TS4_2 that are connected in series and arranged sequentially, and so on. Memory string MS4_8 contains switching elements T4_8_0 to T4_8_191 and TS4_8 that are connected in series and arranged sequentially.

[0106] In summary, each memory string contains 193 switching elements, such that the 32 memory strings MS1_1~MS4_8 contain 193×32 switching elements T1_1_0~T4_8_191 and TS1_1~TS4_8. However, the embodiments of the present invention are not limited thereto. In various embodiments, the above 193 and 32 can be replaced with various positive integers. For example, in Figures 1A to 1H In the embodiment, 193 is replaced with 97.

[0107] In some embodiments, the control terminals of switching elements TS1_1 to TS4_8 are respectively used to receive string selection line signals SSL1_1 to SSL4_8. Each of the control terminals of switching elements T1_1_0 to T4_8_0 is used to receive word line signal WL0. Each of the control terminals of switching elements T1_1_1 to T4_8_1 is used to receive word line signal WL1, and so on. Each of the control terminals of switching elements T1_1_190 to T4_8_190 is used to receive word line signal WL190. Each of the control terminals of switching elements T1_1_191 to T4_8_191 is used to receive word line signal WL191.

[0108] like Figure 2B As shown, memory word strings MS1_1 to MS4_8 are used to generate word string current signals IS1_1 to IS1_8, respectively. Memory device 200A further uses the sum of word string current signals IS1_1 to IS1_8 to generate current signal IT1. In other words, the current level of current signal IT1 is equal to the sum of the current levels of word string current signals IS1_1 to IS1_8.

[0109] In some embodiments, switching elements T1_1_0 to T4_8_0 are used to store stored data SDT0. Switching elements T1_1_1 to T4_8_1 are used to store stored data SDT1, and so on. Switching elements T1_1_190 to T4_8_190 are used to store stored data SDT190. Switching elements T1_1_191 to T4_8_191 are used to store stored data SDT191. In summary, switching elements T1_1_0 to T4_8_191 can store stored data SDT0 to SDT191.

[0110] In some embodiments, each of the stored data SDT0 to SDT191 comprises 32 stored data bits. Specifically, stored data SDT0 comprises stored data bits SDB1_1_0 to SDB4_8_0. Stored data SDT1 comprises stored data bits SDB1_1_1 to SDB4_8_1, and so on. Stored data SDT191 comprises stored data bits SDB1_1_191 to SDB4_8_191. Correspondingly, switching elements T1_1_0 to T4_8_191 are used to store stored data bits SDB1_1_0 to SDB4_8_191, respectively.

[0111] When the stored data bit has a logic value of 0, the corresponding switching element has a threshold voltage level HVT. When the stored data bit has a logic value of 1, the corresponding switching element has a threshold voltage level LVT. For example, when the stored data bit SDB1_1_0 has a logic value of 0, the switching element T1_1_0 has a threshold voltage level HVT. When the stored data bit SDB1_1_0 has a logic value of 1, the switching element T1_1_0 has a threshold voltage level LVT.

[0112] exist Figure 2B In the illustrated embodiment, each of the stored data bits SDB1_1_191 to SDB1_3_191 has a logic value of 1, and each of the switching elements T1_1_191 to T1_3_191 has a threshold voltage level LVT. Each of the stored data bits SDB1_4_191 to SDB4_8_191 has a logic value of 0, and each of the switching elements T1_4_191 to T4_8_191 has a threshold voltage level HVT.

[0113] In some embodiments, the stored data SDT0~SDT191 each have a corresponding stored value. Figure 2B In the illustrated embodiment, the stored value is equal to the number of stored data bits with logic value 0 in the corresponding stored data. For example, in response to stored data SDT0 containing 29 stored data bits SDB1_4_191~SDB4_8_191 with logic value 0, stored data SDT0 has a stored value of 29.

[0114] On the other hand, the string select lines SSL1_1 to SSL4_8 are used to carry the input data IDT. In response to the input value of the input data IDT, the string select lines SSL1_1 to SSL4_8 have voltage levels HVSSL or LVSSL.

[0115] exist Figure 2B In the illustrated embodiment, the input value of the input data IDT is equal to the number of string select line signals with voltage level HVSSL. For example, in response to each of the string select line signals SSL1_1 to SSL4_8 having voltage level HVSSL, the input data IDT has an input value of 32. As another example, in response to each of the string select line signals SSL1_3 to SSL4_8 having voltage level HVSSL and each of the string select line signals SSL1_1 to SSL1_2 having voltage level LVSSL, the input data IDT has an input value of 30.

[0116] Figure 2CThis is a schematic diagram illustrating the encoding method of stored data and input data in a memory device 200A according to some embodiments of the present invention. In some embodiments, the encoding method of input data and stored data is referred to as thermometer encoding.

[0117] exist Figure 2C In the illustrated embodiment, voltage levels HVSSL and LVSSL are equal to 3 volts (3V) and 0 volts (0V), respectively. Input data IDT has an input value of 30. Stored data SDT0, SDT190, and SDT191 have stored values ​​of 24, 31, and 29, respectively.

[0118] In response to stored data SDT0 having a stored value of 24, each of the stored data bits SDB1_1_0 to SDB1_8_0 has a logical value of 1, and each of the stored data bits SDB2_1_0 to SDB4_8_0 has a logical value of 0. In response to stored data SDT190 having a stored value of 31, each of the stored data bits SDB1_1_190 has a logical value of 1, and each of the stored data bits SDB1_2_190 to SDB4_8_190 has a logical value of 0. In response to stored data SDT191 having a stored value of 29, each of the stored data bits SDB1_1_191 to SDB1_3_191 has a logical value of 1, and each of the stored data bits SDB1_4_191 to SDB4_8_191 has a logical value of 0.

[0119] exist Figure 2C In the illustrated embodiment, the memory device 200A compares input data IDT and stored data SDT191. Correspondingly, each of the word line signals WL0 to WL190 has a pass voltage level VPASS, causing the corresponding switching element to be turned on. The word line signal WL191 has a voltage level VREAD. Correspondingly, each of the switching elements T1_1_191 to T1_3_191 is turned on, and each of the switching elements T1_4_191 to T4_8_191 is turned off. In response to the turning off of the switching elements T1_4_191 to T4_8_191, each of the word string current signals IS1_4 to IS4_8 has a current level ISL2.

[0120] On the other hand, each of the string selection line signals SSL1_3~SSL4_8 has a voltage level HVSSL and each of the string selection line signals SSL1_1~SSL1_2 has a voltage level LVSSL, causing each of the switching elements TS1_1~TS1_2 to be turned off and each of the switching elements TS1_3~TS4_8 to be turned on. In response to the turning off of the switching elements TS1_1~TS1_2, each of the string current signals IS1_1~IS1_2 has a current level ISL2.

[0121] At this time, in response to each turn-on of switching elements TS1_3 and T1_3_0 to T1_3_191, the string current signal IS1_3 has a current level ISL1, such that the current level of the current signal IT1 is equal to the current level ISL1 multiplied by 1.

[0122] The greater the difference between the input value of input data IDT and the stored value of stored data SDT191, the greater the number of memory word strings with a logic value of 1 corresponding to the word string select line signal with voltage level HVSSL. In other words, the number of word string current signals with current level ISL1 is proportional to the difference between input data IDT and stored data SDT191, such that the current level of current signal IT1 is proportional to the difference between the input value of input data IDT and the stored value of stored data SDT191.

[0123] In some embodiments, the difference between the input value of input data IDT and the stored value of stored data SDT191 can be referred to as the Manhattan distance between input data IDT and stored data SDT191.

[0124] In some approaches, memory devices use word line signals to carry input data to calculate the Manhattan distance. However, the encoding of word line signals is more complex, resulting in lower reliability and robustness.

[0125] Compared to the above approach, in this embodiment of the invention, the memory device 200A uses string select lines SSL1_1~SSL4_8 to carry the input data IDT and operates through thermometer encoding to calculate the Manhattan distance. This improves reliability and robustness.

[0126] exist Figure 2C In the illustrated embodiment, when the stored value of the stored data is greater than the input value of the input data, the current signal IT1 has a zero current level. For example, when comparing the input value 30 of the input data IDT and the stored value 31 of the stored data SDT190, each of the word line signals WL0~WL189 and WL191 has a pass voltage level VPASS, causing the corresponding switching element to be turned on. The word line signal WL190 has a voltage level VREAD. Correspondingly, each of the switching elements T1_2_190~T4_8_190 is turned off, causing each of the word string current signals IS1_2~IS4_8 to have a current level ISL2. On the other hand, the word string select line signal SSL1_1 has a voltage level LVSSL, causing the word string current signal IS1_1 to have a current level ISL2. In response to the current level ISL2 being considered a zero current level, the current level of the current signal IT1 is equal to the zero current level.

[0127] Figure 2D This is a schematic diagram illustrating input data having various input values ​​according to some embodiments of the present invention. In various embodiments, the input data IDT can have one of the input values ​​0 to 32. In some embodiments, the input value of the input data IDT is equal to the number of string select line signals having a voltage level HVSSL. Figure 2D In the embodiment shown, the voltage levels HVSSL and LVSSL are equal to 3 volts and 0 volts, respectively.

[0128] like Figure 2D As shown, when the input data IDT has an input value of 30, each of the string selection line signals SSL1_1 and SSL1_2 has a voltage level of LVSSL, and each of SSL1_3 to SSL4_8 has a voltage level of HVSSL. When the input data IDT has an input value of 24, each of the string selection line signals SSL1_1 to SSL1_8 has a voltage level of LVSSL, and each of SSL2_1 to SSL4_8 has a voltage level of HVSSL. When the input data IDT has an input value of 10, each of the string selection line signals SSL1_1 to SSL3_6 has a voltage level of LVSSL, and each of SSL3_7 to SSL4_8 has a voltage level of HVSSL.

[0129] Figure 2E This is a schematic diagram illustrating various stored values ​​of stored data according to some embodiments of the present invention. Figure 2E The illustrated embodiment uses stored data SDT191 as an example. However, the embodiments of the present invention are not limited thereto. The following description can also be applied to each of stored data SDT0 to SDT190.

[0130] In various embodiments, the stored data SDT191 may have a stored value from 0 to 32. In some embodiments, the stored value of the stored data SDT191 is equal to the number of stored data bits with a logic value of 0. In other words, the stored value of the stored data SDT191 is equal to the number of switching elements with a threshold voltage level HVT.

[0131] like Figure 2EAs shown, when the stored data SDT191 has a stored value of 29, each of the stored data bits SDB1_1_191 to SDB1_3_191 has a logical value of 1, and each of the stored data bits SDB1_4_191 to SDB4_8_191 has a logical value of 0. When the stored data SDT191 has a stored value of 23, each of the stored data bits SDB1_1_191 to SDB2_1_191 has a logical value of 1, and each of the stored data bits SDB2_2_191 to SDB4_8_191 has a logical value of 0. When the stored data SDT191 has a stored value of 5, each of the stored data bits SDB1_1_191 to SDB4_3_191 has a logical value of 1, and each of the stored data bits SDB4_4_191 to SDB4_8_191 has a logical value of 0.

[0132] Figure 2F This is a schematic diagram illustrating the storage and input of data in a memory device 200A according to some embodiments of the present invention. Figure 2F In the illustrated embodiment, voltage levels HVSSL and LVSSL are equal to 3 volts and 0 volts, respectively. Input data IDT has an input value of 24. Stored data SDT0, SDT190, and SDT191 have stored values ​​of 24, 24, and 22, respectively.

[0133] In response to stored data SDT0 having a stored value of 24, each of the stored data bits SDB1_1_0 to SDB1_8_0 has a logical value of 1, and each of the stored data bits SDB2_1_0 to SDB4_8_0 has a logical value of 0. In response to stored data SDT190 having a stored value of 24, each of the stored data bits SDB1_1_190 to SDB1_8_190 has a logical value of 1, and each of the stored data bits SDB2_1_190 to SDB4_8_190 has a logical value of 0. In response to stored data SDT191 having a stored value of 22, each of the stored data bits SDB1_1_191 to SDB2_2_191 has a logical value of 1, and each of the stored data bits SDB2_3_191 to SDB4_8_191 has a logical value of 0.

[0134] exist Figure 2FIn the illustrated embodiment, the memory device 200A compares the input data IDT and the stored data SDT191. Correspondingly, each of the word line signals WL0 to WL190 has a pass voltage level VPASS, and the word line signal WL191 has a voltage level VREAD. Correspondingly, each of the switching elements T1_1_191 to T2_2_191 is turned on, and each of the switching elements T2_3_191 to T4_8_191 is turned off, such that the word string current signals IS2_3 to IS4_8 are blocked by the switching elements T2_3_191 to T4_8_191, respectively. In other words, each of the word string current signals IS2_3 to IS4_8 has a current level ISL2.

[0135] On the other hand, in response to the input data IDT having an input value of 24, each of the string selection line signals SSL2_1 to SSL4_8 has a voltage level HVSSL and each of the string selection line signals SSL1_1 to SSL1_8 has a voltage level LVSSL, causing each of the switching elements TS1_1 to TS1_8 to be turned off and each of the switching elements TS2_1 to TS4_8 to be turned on. At this time, the switching elements TS1_1 to TS1_8 respectively block the string current signals IS1_1 to IS1_8, causing each of the string current signals IS1_1 to IS1_8 to have a current level ISL2.

[0136] At this time, in response to the string select line signal SSL2_1 having a voltage level HVSSL and the stored data bit SDB2_1_191 having a logic value of 1, the string current signal IS2_1 has a current level ISL1. Similarly, in response to the string select line signal SSL2_2 having a voltage level HVSSL and the stored data bit SDB2_2_191 having a logic value of 1, the string current signal IS2_2 has a current level ISL1. Correspondingly, the current level of the current signal IT1 is equal to the current level ISL1 multiplied by 2, where 2 represents the difference of 2 between the input value 24 of the input data IDT and the stored value 22 of the stored data SDT191.

[0137] In summary, when the string select line signal has a voltage level HVSSL and the corresponding stored data bit has a logic value of 1, the corresponding string current signal has a current level ISL1. When the difference between the input value of the input data IDT and the stored value of the stored data SDT191 increases, the number of string current signals with current level ISL1 increases, causing the current level of the current signal IT1 to increase. Conversely, when the difference between the input value of the input data IDT and the stored value of the stored data SDT191 decreases, the number of string current signals with current level ISL1 decreases, causing the current level of the current signal IT1 to decrease.

[0138] In some embodiments, the number of string current signals with current level ISL1 is equal to the difference between the input value of input data IDT and the stored value of stored data SDT191. For example, in Figure 2C In the illustrated embodiment, the number of string current signals IS1_3 with current level ISL1 is equal to the difference of 1 between the input value 30 and the stored value 29. Figure 2F In the embodiment shown, the number of string current signals IS2_1 and IS2_2 with current level ISL1 is equal to the difference 2 between input value 24 and stored value 22.

[0139] Figure 3A This is a schematic diagram illustrating a memory device 300A according to some embodiments of the present invention. Please refer to... Figure 2A , Figure 2B and Figure 3A The memory device 300A is a variation of the memory device 200A. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0140] like Figure 3A As shown, memory device 300A includes memory blocks BK1 and BK2. Memory block BK1 includes sub-blocks SBK1_1 to SBK1_8. Memory block BK2 includes sub-blocks SBK2_1 to SBK2_8. Sub-blocks SBK1_1 to SBK2_8 each include memory strings MS1_1 to MS2_8. Memory strings MS1_1 to MS2_8 are used to receive string select line signals SSL1_1 to SSL2_8. Each of memory strings MS1_1 to MS2_8 is used to receive word line signals WL0 to WL191.

[0141] exist Figure 3A In the illustrated embodiment, the memory device 300A performs a read operation on the switching element corresponding to the word line signal WL191. Correspondingly, the word line signal WL191 has a read voltage level VREAD, and each of the word line signals WL0 to WL190 has a pass voltage level VPASS. The stored value of the stored data in memory blocks BK1 and BK2 can be equal to one of the stored values ​​0 to 16.

[0142] Figure 3B This is a schematic diagram illustrating a memory device 300B according to some embodiments of the present invention. Please refer to... Figure 2A , Figure 2B and Figure 3B The memory device 300B is a variation of the memory device 200A. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0143] like Figure 3BAs shown, memory device 300B includes memory blocks BK1 to BK32. Memory block BK1 includes sub-blocks SBK1_1 to SBK1_8. Memory block BK2 includes sub-blocks SBK2_1 to SBK2_8, and so on. Memory block BK10 includes sub-blocks SBK10_1 to SBK10_8. Memory block BK32 includes sub-blocks SBK32_1 to SBK32_8. Sub-blocks SBK1_1 to SBK32_8 each include memory strings MS1_1 to MS32_8. Memory strings MS1_1 to MS32_8 are used to receive string selection line signals SSL1_1 to SSL32_8. Each of memory strings MS1_1 to MS32_8 is used to receive word line signals WL0 to WL191.

[0144] exist Figure 3B In the illustrated embodiment, the memory device 300B performs a read operation on the switching element corresponding to the word line signal WL191. Correspondingly, the word line signal WL191 has a read voltage level VREAD, and each of the word line signals WL0 to WL190 has a pass voltage level VPASS. The stored value of the stored data in memory blocks BK1 to BK32 can be equal to one of the stored values ​​0 to 256.

[0145] In conclusion, Figure 3A In the illustrated embodiment, memory blocks BK1~BK2 can have stored values ​​0~16. Figure 2A In the illustrated embodiment, memory blocks BK1~BK4 can have stored values ​​from 0 to 32. Figure 3B In the illustrated embodiment, memory blocks BK1 to BK32 can store values ​​from 0 to 256. In other words, by configuring different numbers of memory blocks, the memory device can store various values.

[0146] Figure 4A This is a schematic diagram illustrating a memory system 400 according to some embodiments of the present invention. Figure 4A As shown, the memory system 400 includes a memory device 410, a sensing device 420, a cache encoding device 430, and an output device 440.

[0147] In some embodiments, the memory device 410 is used to generate bit line signals BL1~BL128K, where K represents one thousand. However, the invention is not limited thereto. In various embodiments, the memory device 410 can generate various numbers of bit line signals. In other words, 128K can be replaced with other positive integers. The sensing device 420 may include a page buffer and a sensing amplifier, and is used to sense the search results corresponding to the bit line signals BL1~BL128K. The cache encoding device 430 may include a cache cache and a priority encoder. The output device 440 is used to output the pairing results of the memory device 410.

[0148] In some embodiments, the processing of the bit line signals by the buffer encoding device 430 includes AND logic, OR logic, and counting logic processing, and may also include a combination of the above three logics. Please refer to Figures 1A to 4A The cache encoding device 430 can receive sensing results from the memory device 100 and / or 410, and control the sorting (which can be serial or parallel) and combine the sensing results to generate an overall search result as the pairing result output by the output device 440.

[0149] In some embodiments, the cache encoding device 430 is further used to perform priority encoding on the search results corresponding to the bit line signals BL1~BL128K. For example, the cache encoding device 430 integrates the search results corresponding to the bit line signals BL1~BL128K and preferentially selects the address of the bit line signal corresponding to the best search result (that is, the input value of the input data and the stored value of the stored data are closest to each other).

[0150] Figure 4B Illustrations based on some embodiments of the present invention Figure 4A A schematic diagram showing further details of the memory system 400. (See attached diagram.) Figure 4B As shown, memory device 410 includes memory block groups BKG1_1 to BKG128K_128. However, embodiments of the present invention are not limited thereto. In various embodiments, memory device 410 may include various numbers of memory block groups. In other words, 128 may be replaced with other positive integers.

[0151] In some embodiments, each of the memory block groups BKG1_1 to BKG128K_128 contains multiple blocks. Each block contains multiple sub-blocks. Details regarding the memory block groups BKG1_1 to BKG128K_128 are provided below. Figures 4C to 4F The embodiments are further illustrated below.

[0152] In some embodiments, memory block groups BKG1_1 to BKG128K_128 are used to store stored data SDT1_1 to SDT128K_128, respectively. Memory block group BKG1_1 is used to compare stored data SDT1_1 with input data IDT1 to generate a current signal IT1_1. Memory block group BKG2_1 is used to compare stored data SDT2_1 with input data IDT1 to generate a current signal IT2_1, and so on. Memory block group BKG128K_1 is used to compare stored data SDT128K_1 with input data IDT1 to generate a current signal IT128K_1.

[0153] Similarly, memory block group BKG1_128 is used to compare stored data SDT1_128 and input data IDT128 to generate current signal IT1_128. Memory block group BKG2_128 is used to compare stored data SDT2_128 and input data IDT128 to generate current signal IT2_128, and so on. Memory block group BKG128K_128 is used to compare stored data SDT128K_128 and input data IDT128 to generate current signal IT128K_128.

[0154] In some embodiments, the current level of current signal IT1_1 is proportional to the difference between stored data SDT1_1 and input data IDT1. The current level of current signal IT2_1 is proportional to the difference between stored data SDT2_1 and input data IDT1, and so on. The current level of current signal IT128K_1 is proportional to the difference between stored data SDT128K_1 and input data IDT1.

[0155] Similarly, the current level of current signal IT1_128 is proportional to the difference between stored data SDT1_128 and input data IDT128. The current level of current signal IT2_128 is proportional to the difference between stored data SDT2_128 and input data IDT128, and so on. The current level of current signal IT128K_128 is proportional to the difference between stored data SDT128K_128 and input data IDT128.

[0156] Please refer to Figure 2A , Figure 2B and Figure 4B The configuration of each memory block group BKG1_1 to BKG128K_128 is similar to the configuration of memory blocks BK1 to BK4. The configuration of each current signal IT1_1 to IT128K_128 is similar to the current signal IT1. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0157] In some embodiments, memory block groups BKG1_1 to BKG1_128 are used to sum current signals IT1_1 to IT1_128 to generate bit line signal BL1. In other words, the current level of bit line signal BL1 is equal to the sum of the current levels of current signals IT1_1 to IT1_128. Correspondingly, the current level of bit line signal BL1 is proportional to the sum of the differences between stored data SDT1_1 to SDT1_128 and input data IDT1 to IDT128.

[0158] Similarly, memory block groups BKG128K_1 to BKG128K_128 are used to sum the current signals IT128K_1 to IT128K_128 to generate the bit line signal BL128K. In other words, the current level of the bit line signal BL128K is equal to the sum of the current levels of the current signals IT128K_1 to IT128K_128. Correspondingly, the current level of the bit line signal BL1 is proportional to the sum of the differences between the stored data SDT128K_1 to SDT128K_128 and the input data IDT1 to IDT128.

[0159] Figure 4C This is a schematic diagram illustrating a memory block group BKG1_1 in a memory system 400 according to some embodiments of the present invention. Figure 4C As shown, memory block group BKG1_1 contains 32 memory strings MS1_1_1_1 to MS1_1_4_8. Memory strings MS1_1_1_1 to MS1_1_4_8 are used to generate string current signals IS1_1_1_1 to IS1_1_4_8. Memory block group BKG1_1 uses the string current signals IS1_1_1_1 to IS1_1_4_8 to sum them to generate a current signal IT1_1. Each memory string MS1_1_1_1 to MS1_1_4_8 contains 192 switching elements for storing data bits and one switching element for receiving string select line signals.

[0160] Please refer to Figure 4C and Figure 2B The configuration of memory strings MS1_1_1_1 to MS1_1_4_8 is similar to that of memory strings MS1_1 to MS4_8. The configuration of string current signals IS1_1_1_1 to IS1_1_4_8 is similar to that of string current signals IS1_1 to IS4_8. The configuration of current signal IT1_1 is similar to that of current signal IT1. Therefore, for the sake of brevity, some descriptions will not be repeated. For example, the switching elements receiving word line signals WL0 to WL190 are labeled as follows: Figure 4C Not shown in the image.

[0161] like Figure 4C As shown, memory word string MS1_1_1_1 contains switching elements TS1_1_1_1, T1_1_1_1, and 191 other switching elements used to receive word line signals WL0 to WL190. Memory word string MS1_1_1_2 contains switching elements TS1_1_1_2, T1_1_1_2, and 191 other switching elements used to receive word line signals WL0 to WL190, and so on. Memory word string MS1_1_1_8 contains switching elements TS1_1_1_8, T1_1_1_8, and 191 other switching elements used to receive word line signals WL0 to WL190.

[0162] Similarly, memory word string MS1_1_4_1 includes switching elements TS1_1_4_1, T1_1_4_1, and 191 other switching elements for receiving word line signals WL0 to WL190. Memory word string MS1_1_4_2 includes switching elements TS1_1_4_2, T1_1_4_2, and 191 other switching elements for receiving word line signals WL0 to WL190, and so on. Memory word string MS1_1_4_8 includes switching elements TS1_1_4_8, T1_1_4_8, and 191 other switching elements for receiving word line signals WL0 to WL190.

[0163] The control terminals of switching elements TS1_1_1_1 to TS1_1_4_8 are used to receive the string selection line signals SSL1_1 to SSL4_8, respectively. Each of the control terminals of switching elements T1_1_1_1 to T1_1_4_8 is used to receive the word line signal WL191.

[0164] exist Figure 4C In the illustrated embodiment, switching elements T1_1_1_1 to T1_1_4_8 are used to store stored data SDT1_1 with a stored value of 30. String select lines SSL1_1 to SSL4_8 are used to carry input data IDT1 with an input value of 30. Word line signal WL191 has a read voltage level VREAD, and each of word line signals WL0 to WL190 has a pass voltage level VPASS.

[0165] In response to the stored data SDT1_1 having a stored value 30, each of the switching elements T1_1_1_1 to T1_1_1_2 has a threshold voltage level LVT corresponding to a logic value of 1, and each of the switching elements T1_1_1_3 to T1_1_4_8 has a threshold voltage level HVT corresponding to a logic value of 0. Correspondingly, when each of the switching elements T1_1_1_3 to T1_1_4_8 is turned off, each of the word string current signals IS1_1_1_3 to IS1_1_4_8 has a current level ISL2.

[0166] In response to input data IDT1 having an input value of 30, each of the string selection line signals SSL1_1 to SSL1_2 has a voltage level LVSSL, and each of the string selection line signals SSL1_3 to SSL4_8 has a voltage level HVSSL. Correspondingly, the turn-off of each of the switching elements TS1_1_1_1 to TS1_1_1_2 causes each of the string current signals IS1_1_1_1 to IS1_1_1_2 to have a current level ISL2. The voltage levels HVSSL and LVSSL can be 3 volts (3V) and 0 volts (0V), respectively.

[0167] In response to each of the string current signals IS1_1_1_1 to IS1_1_4_8 having a current level ISL2, the current level of the current signal IT1_1 is equal to the current level ISL1 multiplied by 0, where 0 represents the difference between the input value 30 of the input data IDT1 and the stored value 30 of the stored data SDT1_1.

[0168] Figure 4D This is a schematic diagram illustrating a memory block group BKG1_128 in a memory system 400 according to some embodiments of the present invention. Figure 4D As shown, memory block group BKG1_128 contains 32 memory word strings MS1_128_1_1 to MS1_128_4_8. Memory word strings MS1_128_1_1 to MS1_128_4_8 are used to generate word string current signals IS1_128_1_1 to IS1_128_4_8, respectively. Memory block group BKG1_128 is used to sum the word string current signals IS1_128_1_1 to IS1_128_4_8 to generate the current signal IT1_128.

[0169] Please refer to Figure 4D and Figure 4C The configuration of memory strings MS1_128_1_1 to MS1_128_4_8 is similar to that of memory strings MS1_1_1_1 to MS1_1_4_8. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0170] like Figure 4D As shown, the memory string MS1_128_1_1 contains at least switching elements TS1_128_1_1 and T1_128_1_1. The memory string MS1_128_1_2 contains at least switching elements TS1_128_1_2 and T1_128_1_2, and so on. The memory string MS1_128_1_8 contains at least switching elements TS1_128_1_8 and T1_128_1_8.

[0171] Similarly, memory string MS1_128_4_1 contains at least switching elements TS1_128_4_1 and T1_128_4_1. Memory string MS1_128_4_2 contains at least switching elements TS1_128_4_2 and T1_128_4_2, and so on. Memory string MS1_128_4_8 contains at least switching elements TS1_128_4_8 and T1_128_4_8.

[0172] The control terminals of switching elements TS1_128_1_1 to TS1_128_4_8 are used to receive the string selection line signals SSL509_1 to SSL512_8, respectively. Each of the control terminals of switching elements T1_128_1_1 to T1_128_4_8 is used to receive the word line signal WL191.

[0173] exist Figure 4D In the illustrated embodiment, switching elements T1_128_1_1 to T1_128_4_8 are used to store stored data SDT1_128 with a stored value of 10. String select lines SSL509_1 to SSL512_8 are used to carry input data IDT128 with an input value of 10. Word line signal WL191 has a read voltage level VREAD, and each of word line signals WL0 to WL190 has a pass voltage level VPASS.

[0174] In response to the stored data SDT1_128 having a stored value of 10, each of the switching elements T1_128_1_1 to T1_128_3_6 has a threshold voltage level LVT corresponding to a logic value of 1, and each of the switching elements T1_128_3_7 to T1_128_4_8 has a threshold voltage level HVT corresponding to a logic value of 0. Correspondingly, the turn-off of each of the switching elements T1_128_3_7 to T1_128_4_8 causes each of the word string current signals IS1_128_3_7 to IS1_128_4_8 to have a current level ISL2.

[0175] In response to input data IDT128 having an input value of 10, each of the string select line signals SSL509_1 to SSL511_6 has a voltage level LVSSL, and each of the string select line signals SSL511_7 to SSL512_8 has a voltage level HVSSL. Correspondingly, each of the switching elements TS1_128_1_1 to TS1_128_3_6 is turned off, causing each of the string current signals IS1_128_1_1 to IS1_128_3_6 to have a current level ISL2.

[0176] Each of the string current signals IS1_128_1_1 to IS1_128_4_8 has a current level ISL2. The current level of the current signal IT1_128 is equal to the current level ISL1 multiplied by 0, where 0 represents the difference between the input value 10 of the input data IDT128 and the stored value 10 of the stored data SDT1_128.

[0177] Figure 4E This is a schematic diagram illustrating a memory block group BKG128K_1 in a memory system 400 according to some embodiments of the present invention. Figure 4E As shown, memory block group BKG128K_1 contains 32 memory word strings MS128K_1_1_1 to MS128K_1_4_8. Memory word strings MS128K_1_1_1 to MS128K_1_4_8 are used to generate word string current signals IS128K_1_1_1 to IS128K_1_4_8, respectively. Memory block group BKG128K_1 is used to sum the word string current signals IS128K_1_1_1 to IS128K_1_4_8 to generate the current signal IT128K_1.

[0178] Please refer to Figure 4E and Figure 4C The configuration of memory strings MS128K_1_1_1 to MS128K_1_4_8 is similar to that of memory strings MS1_1_1_1 to MS1_1_4_8. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0179] like Figure 4E As shown, the memory string MS128K_1_1_1 contains at least switching elements TS128K_1_1_1 and T128K_1_1_1. The memory string MS128K_1_1_2 contains at least switching elements TS128K_1_1_2 and T128K_1_1_2, and so on. The memory string MS128K_1_1_8 contains at least switching elements TS128K_1_1_8 and T128K_1_1_8.

[0180] Similarly, memory string MS128K_1_4_1 contains at least switching elements TS128K_1_4_1 and T128K_1_4_1. Memory string MS128K_1_4_2 contains at least switching elements TS128K_1_4_2 and T128K_1_4_2, and so on. Memory string MS128K_1_4_8 contains at least switching elements TS128K_1_4_8 and T128K_1_4_8.

[0181] The control terminals of switching elements TS128K_1_1_1 to TS128K_1_4_8 are used to receive the word string selection line signals SSL1_1 to SSL4_8, respectively. Each of the control terminals of switching elements T128K_1_1_1 to T128K_1_4_8 is used to receive the word line signal WL191.

[0182] exist Figure 4E In the illustrated embodiment, switching elements T128K_1_1_1 to T128K_1_4_8 are used to store stored data SDT128K_1 with a stored value of 5. String select lines SSL1_1 to SSL4_8 are used to carry input data IDT1 with an input value of 30. Word line signal WL191 has a read voltage level VREAD, and each of word line signals WL0 to WL190 has a pass voltage level VPASS.

[0183] In response to the stored data SDT128K_1 having a stored value of 5, each of the switching elements T128K_1_1_1 to T128K_1_4_3 has a threshold voltage level LVT corresponding to a logic value of 1, and each of the switching elements T128K_1_4_4 to T128K_1_4_8 has a threshold voltage level HVT corresponding to a logic value of 0. Correspondingly, the turn-off of each of the switching elements T128K_1_4_4 to T128K_1_4_8 causes each of the word string current signals IS128K_1_4_4 to IS128K_1_4_8 to have a current level ISL2.

[0184] In response to input data IDT1 having an input value of 30, each of the string select line signals SSL1_1 to SSL1_2 has a voltage level LVSSL, and each of the string select line signals SSL1_3 to SSL4_8 has a voltage level HVSSL. Correspondingly, each of the switching elements TS128K_1_1_1 to TS128K_1_1_2 is turned off, causing each of the string current signals IS128K_1_1_1 to IS128K_1_1_2 to have a current level ISL2.

[0185] At this time, in response to the conduction of each of the switching elements T128K_1_1_3~T128K_1_4_3 and TS128K_1_1_3~TS128K_1_4_3, each of the word string current signals IS128K_1_1_3~IS128K_1_4_3 has a current level ISL1. In other words, the memory block group BKG128K_1 generates 25 word string current signals with a current level ISL1. Correspondingly, the current level of the current signal IT128K_1 is equal to the current level ISL1 multiplied by 25, where 25 represents the difference between the input value 30 of the input data IDT1 and the stored value 5 of the stored data SDT128K_1.

[0186] Figure 4F This is a schematic diagram illustrating a memory block group BKG128K_128 in a memory system 400 according to some embodiments of the present invention. Figure 4F As shown, memory block group BKG128K_128 contains 32 memory word strings MS128K_128_1_1 to MS128K_128_4_8. Memory word strings MS128K_128_1_1 to MS128K_128_4_8 are used to generate word string current signals IS128K_128_1_1 to IS128K_128_4_8, respectively. Memory block group BKG128K_128 is used to sum the word string current signals IS128K_128_1_1 to IS128K_128_4_8 to generate the current signal IT128K_128.

[0187] Please refer to Figure 4F and Figure 4C The configuration of memory strings MS128K_128_1_1 to MS128K_128_4_8 is similar to that of memory strings MS1_1_1_1 to MS1_1_4_8. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0188] like Figure 4F As shown, the memory string MS128K_128_1_1 contains at least switching elements TS128K_128_1_1 and T128K_128_1_1. The memory string MS128K_128_1_2 contains at least switching elements TS128K_128_1_2 and T128K_128_1_2, and so on. The memory string MS128K_128_1_8 contains at least switching elements TS128K_128_1_8 and T128K_128_1_8.

[0189] Similarly, the memory string MS128K_128_4_1 contains at least switching elements TS128K_128_4_1 and T128K_128_4_1. The memory string MS128K_128_4_2 contains at least switching elements TS128K_128_4_2 and T128K_128_4_2, and so on. The memory string MS128K_128_4_8 contains at least switching elements TS128K_128_4_8 and T128K_128_4_8.

[0190] The control terminals of switching elements TS128K_128_1_1 to TS128K_128_4_8 are used to receive string select line signals SSL509_1 to SSL512_8, respectively. Each control terminal of switching elements T128K_128_1_1 to T128K_128_4_8 is used to receive word line signal WL191.

[0191] exist Figure 4F In the illustrated embodiment, switching elements T128K_128_1_1 to T128K_128_4_8 are used to store stored data SDT128K_128 with a stored value of 23. String select lines SSL509_1 to SSL512_8 are used to carry input data IDT128 with an input value of 10. Word line signal WL191 has a read voltage level VREAD, and each of word line signals WL0 to WL190 has a pass voltage level VPASS.

[0192] In response to the stored data SDT128K_128 having a stored value 23, each of the switching elements T128K_128_1_1 to T128K_128_2_1 has a threshold voltage level LVT corresponding to a logic value of 1, and each of the switching elements T128K_128_2_2 to T128K_128_4_8 has a threshold voltage level HVT corresponding to a logic value of 0. Correspondingly, when each of the switching elements T128K_128_2_2 to T128K_128_4_8 is turned off, each of the word string current signals IS128K_128_2_2 to IS128K_128_4_8 has a current level ISL2.

[0193] In response to input data IDT128 having an input value of 10, each of the string select line signals SSL509_1 to SSL511_6 has a voltage level LVSSL, and each of the string select line signals SSL511_7 to SSL512_8 has a voltage level HVSSL. Correspondingly, each of the switching elements TS128K_128_1_1 to TS128K_128_3_6 is turned off, causing each of the string current signals IS128K_128_1_1 to IS128K_128_3_6 to have a current level ISL2.

[0194] In response to each of the string current signals IS128K_128_1_1 to IS128K_128_4_8 having a current level ISL2, the current level of the current signal IT128K_128 is equal to the current level ISL1 multiplied by 0. In other words, since the stored value 23 of the stored data SDT128K_128 is greater than the input value 10 of the input data IDT128, the current signal IT128K_128 has a zero current level.

[0195] In some embodiments, the higher the similarity between the input data IDT1~IDT128 and the stored data, the lower the current level of the corresponding bit line signal. For example, in response to the fact that the similarity between the input data IDT1~IDT128 and the stored data SDT1_1~SDT1_128 is higher than the similarity between the input data IDT1~IDT128 and the stored data SDT128K_1~SDT128K_128, the current level of the bit line signal BL1 is lower than the current level of the bit line signal BL128K.

[0196] In summary, the memory system 400 can simultaneously compare input data IDT1~IDT128 and 128K corresponding stored data to generate 128K bit line signals BL1~BL128K. In this way, the memory system 400 can determine the similarity between the input data and the stored data based on the bit line signals BL1~BL128K.

[0197] Figure 5A Illustrations based on some embodiments of the present invention Figure 2A This diagram illustrates the storage and input of data in the memory device 200A. Please refer to... Figure 2C and Figure 5A , Figure 5A The encoding method shown is Figure 2C This is an example of a variation of the encoding method shown.

[0198] exist Figure 5AIn the illustrated embodiment, the memory device 200A encodes stored data and input data using pairs of switching elements and pairs of string select line signals. Specifically, the stored value of the stored data is proportional to the number of pairs of stored data bits having logic values ​​of 0 and 1. The input value of the input data is proportional to the number of pairs of string select line signals having voltage levels HVSSL and LVSSL. The voltage levels HVSSL and LVSSL can be equal to 3V and 0V, respectively.

[0199] For example, please refer to Figure 2B and Figure 5A In response to the input data IDT having an input value of 12, the string selection line signals SSL2_1~SSL4_8 have voltage levels of 3V, 0V, 3V, 0V, ..., 3V and 0V respectively, and the string selection line signals SSL1_1~SSL1_8 have voltage levels of 0V, 3V, 0V, 3V, ..., 0V and 3V respectively. Specifically, the string selection line signals SSL2_1~SSL4_8 correspond to 12 pairs of string selection line signals with voltage levels of 3V and 0V, and the string selection line signals SSL1_1~SSL1_8 correspond to 4 pairs of string selection line signals with voltage levels of 0V and 3V.

[0200] On the other hand, in response to the stored data SDT191 having a stored value of 10, the stored data bits SDB2_5_191 to SDB4_8_191 have logical values ​​0, 1, 0, 1, ..., 0 and 1 respectively, and the stored data bits SDB1_1_191 to SDB2_4_191 have logical values ​​1, 0, 1, 0, ..., 1 and 0 respectively. Specifically, the stored data bits SDB2_5_191 to SDB4_8_191 correspond to 10 pairs of stored data bits with logical values ​​0 and 1, and the stored data bits SDB1_1_191 to SDB2_4_191 correspond to 6 pairs of stored data bits with logical values ​​1 and 0.

[0201] Similarly, in response to the stored data SDT190 having a stored value of 14, the stored data bits SDB1_5_190 to SDB4_8_190 have logical values ​​0, 1, 0, 1, ..., 0 and 1 respectively, and the stored data bits SDB1_1_190 to SDB1_4_190 have logical values ​​1, 0, 1 and 0 respectively. Specifically, the stored data bits SDB1_5_190 to SDB4_8_190 correspond to 14 pairs of stored data bits with logical values ​​0 and 1, and the stored data bits SDB1_1_190 to SDB1_4_190 correspond to 2 pairs of stored data bits with logical values ​​1 and 0.

[0202] Similarly, in response to the stored data SDT0 having a stored value of 0, the stored data bits SDB1_1_0 to SDB4_8_0 have logical values ​​of 1, 0, 1, 0, ..., 1 and 0, respectively. Among them, the stored data bits SDB1_1_0 to SDB4_8_0 correspond to 16 pairs of stored data bits with logical values ​​of 1 and 0.

[0203] exist Figure 5A In the illustrated embodiment, the memory device 200A compares stored data SDT191 and input data IDT. Correspondingly, word line signal WL191 has a read voltage level VREAD, and each of word line signals WL0 to WL190 has a pass voltage level VPASS.

[0204] At this time, in response to each of the string select line signals SSL1_1, SSL1_3, SSL1_5, and SSL1_7 having a voltage level of 0V, each of the switching elements TS1_1, TS1_3, TS1_5, and TS1_7 is turned off. Correspondingly, each of the string current signals IS1_1, IS1_3, IS1_5, and IS1_7 has a current level of ISL2.

[0205] In response to each of the string select line signals SSL2_2, SSL2_4, SSL2_6, ..., SSL4_6 and SSL4_8 having a voltage level of 0V, each of the switching elements TS2_2, TS2_4, TS2_6, ..., TS4_6 and TS4_8 is turned off. Correspondingly, each of the string current signals IS2_2, IS2_4, IS2_6, ..., IS4_6 and IS4_8 has a current level of ISL2.

[0206] On the other hand, in response to each of the stored data bits SDB1_2_191, SDB1_4_191, ..., SDB2_2_191 and SDB2_4_191 having a logic value of 0, each of the switching elements T1_2_191, T1_4_191, ..., T2_2_191 and T2_4_191 is turned off. Correspondingly, each of the string current signals IS1_2, IS1_4, ..., IS2_2 and IS2_4 has a current level ISL2.

[0207] In response to each of the stored data bits SDB2_5_191, SDB2_7_191, ..., SDB4_5_191 and SDB4_7_191 having a logic value of 0, each of the switching elements T2_5_191, T2_7_191, ..., T4_5_191 and T4_7_191 is turned off. Correspondingly, each of the string current signals IS2_5, IS2_7, ..., IS4_5 and IS4_7 has a current level ISL2.

[0208] At this time, in response to the string select line signal SSL2_1 having a voltage level of 3V and the stored data bit SDB2_1_191 having a logic value of 1, the string current signal IS2_1 has a current level ISL1. Similarly, in response to the string select line signal SSL2_3 having a voltage level of 3V and the stored data bit SDB2_3_191 having a logic value of 1, the string current signal IS2_3 has a current level ISL1. Correspondingly, the current level of the current signal IT1 is equal to the current level ISL1 multiplied by 2, where 2 represents the difference of 2 between the stored value 10 of the stored data SDT191 and the input value 12 of the input data IDT.

[0209] As another example, the memory device 200A can also compare stored data SDT190 and input data IDT. Correspondingly, word line signal WL190 has a read voltage level VREAD, and each of word line signals WL0~WL189 and WL191 has a pass voltage level VPASS.

[0210] At this time, in response to a stored data bit with a logic value of 0 or a word string select line signal with a voltage level of 0V, each of the word string current signals IS1_1~IS1_5, IS1_7 and IS2_1~IS4_8 has a current level ISL2.

[0211] On the other hand, in response to each of the string select line signals SSL1_6 and SSL1_8 having a voltage level of 3V and each of the stored data bits SDB1_6_191 and SDB1_8_191 having a logic value of 1, each of the string current signals IS1_6 and IS1_8 has a current level ISL1. Correspondingly, the current level of the current signal IT1 is equal to the current level ISL1 multiplied by 2, where 2 represents the difference of 2 between the stored value 14 of the stored data SDT190 and the input value 12 of the input data IDT.

[0212] In some embodiments, the difference is an absolute value. In other words, the difference between stored value 14 and input value 12 is equal to 2, and the difference between stored value 10 and input value 12 is also equal to 2.

[0213] In summary, using the above encoding method, regardless of whether the stored data is greater than the input data or the stored data is less than the input data, the current level of the current signal IT1 can correspond to the difference between the stored data and the input data.

[0214] Please refer to Figure 5A , Figure 3A and Figure 3B In various configurations, the stored values ​​for the data have different ranges. Figure 3A In the illustrated embodiment, the stored data can have stored values ​​from 0 to 8. Figure 5A In the illustrated embodiment, the stored data can have stored values ​​from 0 to 16. Figure 3B In the illustrated embodiment, the stored data may have a stored value from 0 to 128.

[0215] Figure 5B Illustrations based on some embodiments of the present invention Figure 2A This is a schematic diagram showing the storage and input of data in the memory device 200A. Figure 5B In the illustrated embodiment, voltage levels HVSSL and LVSSL are equal to 3V and 0V, respectively. Input data IDT has an input value of 10. Stored data SDT191 has a stored value of 10. Word line signal WL191 has a read voltage level VREAD to compare the input data IDT and the stored data SDT191.

[0216] In response to the input data IDT having an input value of 10, the string selection line signals SSL1_1~SSL2_4 have voltage levels of 0V, 3V, 0V, 3V, ..., 0V and 3V respectively, and the string selection line signals SSL2_5~SSL4_8 have voltage levels of 3V, 0V, 3V, 0V, ..., 3V and 0V respectively, causing each of the switching elements TS1_1, TS1_3, ..., TS2_1, TS2_3 and TS2_6, TS2_8, ..., TS4_6, TS4_8 to be turned off. Correspondingly, each of the string current signals IS1_1, IS1_3, ..., IS2_1, IS2_1 and IS2_6, IS2_8, ..., IS4_6, IS4_8 has a current level ISL2.

[0217] In response to the stored data SDT191 having a stored value of 10, the stored data bits SDB1_1_191 to SDB2_4_191 have logic values ​​1, 0, 1, 0, ..., 1 and 0 respectively, and the stored data bits SDB2_5_191 to SDB4_8_191 have logic values ​​0, 1, 0, 1, ..., 0 and 1 respectively, causing each of the switching elements T1_2_191, T1_4_191, ..., T2_4_191 and T2_5_191, T2_7_191, ..., T4_7_191 to be turned off. Correspondingly, each of the string current signals IS1_2, IS1_4, ..., IS2_4 and IS2_5, IS2_7, ..., IS4_7 has a current level ISL2.

[0218] In summary, in response to the difference between the input value 10 of the input data IDT and the stored value 10 of the stored data SDT191 being 0, each of the string current signals IS1_1 to IS4_8 has a current level ISL2, such that the current level of the current signal IT1 is equal to the current level ISL1 multiplied by 0.

[0219] Figure 5C Illustrations based on some embodiments of the present invention Figure 2A This diagram illustrates the storage and input of data in the memory device 200A. Please refer to... Figure 5B and Figure 5C , Figure 5C The situation is Figure 5B This is a variation of the situation. Therefore, for the sake of brevity, some parts of the description will not be repeated. Figure 5B In the illustrated embodiment, the input data IDT has an input value of 10. The stored data SDT191 has a stored value of 8.

[0220] In response to the stored data SDT191 having a stored value of 8, the stored data bits SDB1_1_191 to SDB2_8_191 have logic values ​​1, 0, 1, 0, ..., 1 and 0 respectively, and the stored data bits SDB3_1_191 to SDB4_8_191 have logic values ​​0, 1, 0, 1, ..., 0 and 1 respectively, causing each of the switching elements T1_2_191, T1_4_191, ..., T2_8_191 and T3_1_191, T3_3_191, ..., T4_7_191 to be turned off. Correspondingly, each of the word string current signals IS1_2, IS1_4, ..., IS2_8 and IS3_1, IS3_3, ..., IS4_7 has a current level ISL2.

[0221] At this time, in response to the string select line signal SSL2_5 having a voltage level of 3V and the switching element T2_5_191 being turned on, the string current signal IS2_5 has a current level of ISL1. Similarly, in response to the string select line signal SSL2_7 having a voltage level of 3V and the switching element T2_7_191 being turned on, the string current signal IS2_7 has a current level of ISL1.

[0222] In summary, in response to the difference of 2 between the input value 10 of the input data IDT and the stored value 8 of the stored data SDT191, each of the string current signals IS1_1~IS2_4, IS2_6 and IS2_8~IS4_8 has a current level ISL2, and each of the string current signals IS2_5 and IS2_7 has a current level ISL1, such that the current level of the current signal IT1 is equal to the current level ISL1 multiplied by 2.

[0223] Figure 5D Illustrations based on some embodiments of the present invention Figure 2A This diagram illustrates the storage and input of data in the memory device 200A. Please refer to... Figure 5B and Figure 5D , Figure 5D The situation is Figure 5B This is a variation of the situation. Therefore, for the sake of brevity, some parts of the description will not be repeated. Figure 5B In the illustrated embodiment, the input data IDT has an input value of 10. The stored data SDT191 has a stored value of 12.

[0224] In response to the stored data SDT191 having a stored value of 12, the stored data bits SDB1_1_191 to SDB1_8_191 have logic values ​​1, 0, 1, 0, ..., 1 and 0 respectively, and the stored data bits SDB2_1_191 to SDB4_8_191 have logic values ​​0, 1, 0, 1, ..., 0 and 1 respectively, causing each of the switching elements T1_2_191, T1_4_191, ..., T1_8_191 and T2_1_191, T3_3_191, ..., T4_7_191 to be turned off. Correspondingly, each of the word string current signals IS1_2, IS1_4, ..., IS1_8 and IS2_1, IS2_3, ..., IS4_7 has a current level ISL2.

[0225] At this time, in response to the string select line signal SSL2_2 having a voltage level of 3V and the switching element T2_2_191 being turned on, the string current signal IS2_2 has a current level of ISL1. Similarly, in response to the string select line signal SSL2_4 having a voltage level of 3V and the switching element T2_4_191 being turned on, the string current signal IS2_4 has a current level of ISL1.

[0226] In summary, in response to the difference of 2 between the input value 10 of the input data IDT and the stored value 12 of the stored data SDT191, each of the string current signals IS1_1~IS2_1, IS2_3 and IS2_5~IS4_8 has a current level ISL2, and each of the string current signals IS2_2 and IS2_4 has a current level ISL1, such that the current level of the current signal IT1 is equal to the current level ISL1 multiplied by 2.

[0227] Please refer to Figure 2B and Figures 5B to 5D , Figure 5B , Figure 5C and Figure 5D The scenarios shown correspond to the stored values ​​being equal to, less than, and greater than the input values, respectively. Figure 5B In the illustrated embodiment, the turn-off of each of the switching elements T2_4_191 and T2_5_191 causes each of the string current signals IS2_4 and IS2_5 to have a current level ISL2 (i.e., a zero current level). Figure 5C In the illustrated embodiment, the switching element T2_5_191 is turned on, causing the string current signal IS2_5 to have a current level ISL1. Figure 5D In the embodiment shown, the switching element T2_4_191 is turned on, so that the word string current signal IS2_4 has a current level ISL1.

[0228] In this way, in the case where the stored value is not equal to the input value, the memory device 200A generates at least one word string current signal with a current level ISL1, such that the current level of the current signal IT1 is greater than the zero current level.

[0229] Please refer to Figure 4B and Figures 5A to 5D The memory system 400 can also be based on Figures 5A to 5D The encoding method shown generates bit line signals BL1~BL128K. Details are as follows. Figures 6A to 6D The examples shown are further illustrated.

[0230] Figure 6A Illustrations based on some embodiments of the present invention Figure 4C The diagram shows a search operation performed on memory block group BKG1_1. Figure 6A The scenario shown is Figure 4C This is a variation of the scenario shown. Therefore, for the sake of brevity, some parts of the description will not be repeated. Figure 6A In the illustrated embodiment, input data IDT1 has an input value of 12, and stored data SDT1_1 has a stored value of 12. Word line signal WL191 has a read voltage level VREAD.

[0231] In response to the input data IDT1 having an input value of 12, the string selection line signals SSL1_1~SSL1_8 have voltage levels of 0V, 3V, 0V, 3V, ..., 0V and 3V respectively, and the string selection line signals SSL2_1~SSL4_8 have voltage levels of 3V, 0V, 3V, 0V, ..., 3V and 0V respectively. Correspondingly, the turn-off of each of the switching elements TS1_1_1_1, TS1_1_1_3, TS1_1_1_5, TS1_1_1_7 and TS1_1_2_2, TS1_1_2_4, ..., TS1_1_4_6, TS1_1_4_8 causes each of the string current signals IS1_1_1_1, IS1_1_1_3, IS1_1_1_5, IS1_1_1_7 and IS1_1_2_2, IS1_1_2_4, ..., IS1_1_4_6, IS1_1_4_8 to have a current level ISL2.

[0232] On the other hand, in response to the stored data SDT1_1 having a stored value 12, the switching elements T1_1_1_1 to T1_1_1_8 respectively store logic values ​​1, 0, 1, 0, ..., 1 and 0, and the switching elements T1_1_2_1 to T1_1_4_8 respectively store logic values ​​0, 1, 0, 1, ..., 0 and 1. In other words, the turn-off of each of the switching elements T1_1_1_2, T1_1_1_4, T1_1_1_6, T1_1_1_8 and T1_1_2_1, T1_1_2_3, ..., T1_1_4_5, T1_1_4_7 causes each of the current signals IS1_1_1_2, IS1_1_1_4, IS1_1_1_6, IS1_1_1_8 and IS1_1_2_1, IS1_1_2_3, ..., IS1_1_4_5, IS1_1_4_7 to have a current level ISL2.

[0233] In summary, in response to the difference between the input value 12 of input data IDT1 and the stored value 12 of stored data SDT1_1 being 0, each of the string current signals IS1_1_1_1 to IS1_1_4_8 has a current level ISL2, such that the current level of current signal IT1_1 is equal to the current level ISL1 multiplied by 0.

[0234] Figure 6B Illustrations based on some embodiments of the present invention Figure 4D The diagram shows a search operation performed on memory block group BKG1_128. Figure 6B The scenario shown is Figure 4D This is a variation of the scenario shown. Therefore, for the sake of brevity, some parts of the description will not be repeated. Figure 6B In the illustrated embodiment, input data IDT128 has an input value of 10, and stored data SDT1_128 has a stored value of 10. Word line signal WL191 has a read voltage level VREAD.

[0235] In response to the input data IDT128 having an input value of 10, the string selection line signals SSL509_1~SSL510_4 have voltage levels of 0V, 3V, 0V, 3V, ..., 0V and 3V respectively, and the string selection line signals SSL510_5~SSL512_8 have voltage levels of 3V, 0V, 3V, 0V, ..., 3V and 0V respectively. Correspondingly, the turn-off of each of the switching elements TS1_128_1_1, TS1_128_1_3, ..., TS1_128_2_1, TS1_128_2_3 and TS1_128_2_6, TS1_128_2_8, ..., TS1_128_4_6, TS1_128_4_8 causes each of the current signals IS1_128_1_1, IS1_128_1_3, ..., IS1_128_2_1, IS1_128_2_3 and IS1_128_2_6, IS1_128_2_8, ..., IS1_128_4_6, IS1_128_4_8 to have a current level ISL2.

[0236] On the other hand, in response to the stored data SDT1_128 having a stored value of 10, the switching elements T1_128_1_1 to T1_128_2_4 respectively store logic values ​​1, 0, 1, 0, ..., 1 and 0, and the switching elements T1_128_2_5 to T1_128_4_8 respectively store logic values ​​0, 1, 0, 1, ..., 0 and 1. In other words, the turn-off of each of the switching elements T1_128_1_2, T1_128_1_4, ..., T1_128_2_2, T1_128_2_4 and T1_128_2_5, T1_128_2_7, ..., T1_128_4_5, T1_128_4_7 causes each of the current signals IS1_128_1_2, IS1_128_1_4, ..., IS1_128_2_2, IS1_128_2_4 and IS1_128_2_5, IS1_128_2_7, ..., IS1_128_4_5, IS1_128_4_7 to have a current level ISL2.

[0237] In summary, in response to the difference between the input value 10 of the input data IDT128 and the stored value 10 of the stored data SDT1_128, each of the string current signals IS1_128_1_1 to IS1_128_4_8 has a current level ISL2, such that the current level of the current signal IT1_128 is equal to the current level ISL1 multiplied by 0.

[0238] Figure 6C Illustrations based on some embodiments of the present invention Figure 4E The diagram shows a search operation performed on memory block group BKG128K_1. Figure 6CThe scenario shown is Figure 4E This is a variation of the scenario shown. Therefore, for the sake of brevity, some parts of the description will not be repeated. Figure 6C In the illustrated embodiment, input data IDT1 has an input value of 12, and stored data SDT128K_1 has a stored value of 0. The word line signal WL191 has a read voltage level VREAD.

[0239] Please refer to Figure 6A and Figure 6C The scenario where input data IDT1 has an input value of 12 is described above regarding... Figure 6A The embodiments have already been described. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0240] On the other hand, in response to the stored data SDT128K_1 having a stored value of 0, the switching elements T128K_1_1_1 to T128K_1_4_8 respectively store logic values ​​1, 0, 1, 0, ..., 1 and 0. In other words, the turn-off of each of the switching elements T128K_1_1_2, T128K_1_1_4, ..., T128K_1_4_6 and T128K_1_4_8 causes each of the current signals IS128K_1_1_2, IS128K_1_1_4, ..., IS128K_1_4_6 and IS128K_1_4_8 to have a current level ISL2.

[0241] At this time, in response to each of the 12 string select line signals SSL2_1, SSL2_3, ..., SSL4_5 and SSL4_7 having a voltage level of 3V and each of the 12 switching elements T128K_1_2_1, T128K_1_2_3, ..., T128K_1_4_5 and T128K_1_4_7 being turned on, each of the 12 string current signals IS128K_1_2_1, IS128K_1_2_3, ..., IS128K_1_4_5 and IS128K_1_4_7 having a current level of ISL1.

[0242] In summary, the difference between the input value 12 of the input data IDT1 and the stored value 0 of the stored data SDT128K_1 is 12. Each of the 12 string current signals IS128K_1_2_1, IS128K_1_2_3, ..., IS128K_1_4_5, IS128K_1_4_7 has a current level ISL1, such that the current level of the current signal IT128K_1 is equal to the current level ISL1 multiplied by 12.

[0243] Figure 6D Illustrations based on some embodiments of the present invention Figure 4FThe diagram shows a search operation performed on memory block group BKG128K_128. Figure 6D The scenario shown is Figure 4F This is a variation of the scenario shown. Therefore, for the sake of brevity, some parts of the description will not be repeated. Figure 6D In the illustrated embodiment, the input data IDT128 has an input value of 10, and the stored data SDT128K_128 has a stored value of 0. The word line signal WL191 has a read voltage level VREAD.

[0244] Please refer to Figure 6B and Figure 6D The scenario where the input data IDT128 has an input value of 10 is described above. Figure 6B The embodiments have already been described. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0245] On the other hand, in response to the stored data SDT128K_128 having a stored value of 0, the switching elements T128K_128_1_1 to T128K_128_4_8 respectively store logic values ​​1, 0, 1, 0, ..., 1 and 0. In other words, the turn-off of each of the switching elements T128K_128_1_2, T128K_128_1_4, ..., T128K_128_4_6 and T128K_128_4_8 causes each of the current signals IS128K_128_1_2, IS128K_128_1_4, ..., IS128K_128_4_6 and IS128K_128_4_8 to have a current level ISL2.

[0246] At this time, in response to each of the 10 string select line signals SSL510_5, SSL510_7, ..., SSL512_5 and SSL512_7 having a voltage level of 3V and each of the 10 switching elements T128K_128_2_5, T128K_128_2_7, ..., T128K_128_4_5 and T128K_128_4_7 being turned on, each of the 10 string current signals IS128K_128_2_5, IS128K_128_2_7, ..., IS128K_128_4_5 and IS128K_128_4_7 having a current level of ISL1.

[0247] In summary, in response to the difference between the input value 10 of the input data IDT128 and the stored value 0 of the stored data SDT128K_128, which is 10, the 10 string current signals IS128K_128_2_5, IS128K_128_2_7, ..., IS128K_128_4_5, IS128K_128_4_7 have a current level ISL1, such that the current level of the current signal IT128K_128 is equal to the current level ISL1 multiplied by 10.

[0248] Figure 6E Illustrations based on some embodiments of the present invention Figure 4A A schematic diagram showing further details of the memory system 400. Figure 6E The scenario shown is Figure 4B This is a variation of the scenario shown. Therefore, for the sake of brevity, some parts of the description will not be repeated.

[0249] Compared to Figure 4B The scenario shown is in Figure 6E In the scenario shown, the memory device 410 encodes stored data and input data using pairs of switching elements and pairs of word string select line signals. Specific details regarding paired data input and storage are as described above. Figures 5A to 5D As shown in the embodiments.

[0250] exist Figure 6E In the illustrated embodiment, input data IDT1 and IDT128 have input values ​​12 and 10, respectively. Stored data SDT1_1 and SDT1_128 have stored values ​​12 and 10, respectively. Each of SDT128K_1 and SDT128K_128 has a stored value of 0. The specific configuration of the input and stored data is as described above. Figures 6A to 6D As shown in the embodiments.

[0251] Please refer to Figure 6E and Figure 4B ,exist Figure 6E In the illustrated embodiment, the memory device 410 stores a stored data bit via a pair of switching elements and carries an input data bit via a pair of word string select line signals. Conversely, in Figure 4B In the illustrated embodiment, the memory device 410 stores a stored data bit via a switching element and carries an input data bit via a string select line signal. This results in different data resolutions.

[0252] For example, in Figure 6E In the illustrated embodiment, the 32 string select lines can carry 16 input data bits. Here, 16 equals 2 to the power of 4. Correspondingly, Figure 6EThe data resolution shown in the configuration can be referred to as int 4. In contrast, in Figure 4B In the illustrated embodiment, the 32 string select lines can carry 32 input data bits. Here, 32 equals 2 to the power of 5. Correspondingly, Figure 4B The data resolution of the configuration shown can be referred to as int 5.

[0253] In some embodiments, the memory cell in this invention is referred to as an in-memorysearching (IMS) cell. In various embodiments, the IMS cell can be implemented using floating gate memory, split-gate memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, floating dot memory, dynamic random-access memory (DRAM), and / or ferroelectric field-effect transistor (FeFET).

[0254] In various embodiments, the memory device of the present invention can be implemented by various structures, such as a two-dimensional (2D) cache structure or a three-dimensional (3D) cache structure.

[0255] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A memory device comprising a plurality of memory blocks for storing first stored data and for comparing the first stored data with first input data to generate a first current signal, the memory blocks comprising: Multiple memory word strings coupled to each other are used to generate multiple word string current signals. These memory blocks are used to sum the string current signals to generate the first current signal, and The current level of the first current signal is proportional to the difference between an input value of the first input data and a stored value of the first stored data.

2. The memory device of claim 1, wherein the memory strings are configured to receive a plurality of string select line signals. These string select line signals include a first string select line signal and a second string select line signal. When the first input data has a first input value, each of the first string select line signal and the second string select line signal has a first voltage level. When the first input data has a second input value, the first string select line signal and the second string select line signal respectively have the first voltage level and a second voltage level, and When the first input data has a third input value, each of the first string select line signal and the second string select line signal has the second voltage level.

3. The memory device of claim 2, wherein the second voltage level is lower than the first voltage level, and The second input value is less than the first input value and greater than the third input value.

4. The memory device of claim 1, wherein the first stored data comprises at least a first stored data bit and a second stored data bit. These memory strings include a first switching element for storing the first stored data bit and a second switching element for storing the second stored data bit. When the first stored data has a first stored value, each of the first switching element and the second switching element has a first threshold voltage level. When the first stored data has a second stored value, the first switching element and the second switching element respectively have the first threshold voltage level and a second threshold voltage level, and When the first stored data has a third stored value, each of the first switching element and the second switching element has the second threshold voltage level.

5. The memory device of claim 4, wherein the second threshold voltage level is less than the first threshold voltage level, and The second stored value is less than the first stored value and greater than the third stored value.

6. The memory device of claim 1, wherein when there is a first difference between the input value of the first input data and the stored value of the first stored data, each string current signal in a first portion of the string current signals has a first current level, and The number of string current signals in the first part is equal to the first difference.

7. The memory device of claim 6, wherein when there is a second difference between the input value of the first input data and the stored value of the first stored data, each string current signal in a second portion of the string current signals has the first current level. The number of string current signals in the second part is equal to the second difference, and The second difference is greater than the first difference.

8. The memory device of claim 1, wherein the memory strings are configured to receive a plurality of string select line signals. These string select line signals include a first string select line signal and a second string select line signal. When the first input data has a first input value, the first string selection line signal and the second string selection line signal respectively have a first voltage level and a second voltage level. When the first input data has a second input value, the first string selection line signal and the second string selection line signal have the second voltage level and the first voltage level, respectively.

9. The memory device of claim 8, wherein the second voltage level is greater than the first voltage level, and The second input value is greater than the first input value.

10. The memory device of claim 8, wherein the memory strings comprise: A first switching element is used to receive the first character string selection line signal; A second switching element is used to receive the second string selection line signal; A third switching element, coupled in series with the first switching element; and A fourth switching element is connected in series with the second switching element. When the first stored data has a first stored value, the third switching element is turned off and the fourth switching element is turned on, and When the first stored data has a second stored value, the third switching element is turned on and the fourth switching element is turned off.

11. The memory device of claim 10, wherein the memory strings further comprise: A fifth switching element for receiving a third string select line signal from these string select line signals; and A sixth switching element is used to receive a fourth string select line signal from these string select line signals. When the first input data has the first input value, the third string selection line signal and the fourth string selection line signal have the second voltage level and the first voltage level, respectively.

12. The memory device of claim 11, wherein the memory strings further comprise: A seventh switching element, coupled in series with the fifth switching element; and An eighth switching element is connected in series with the sixth switching element. When the first stored data has a third stored value, the seventh switching element is turned off and the eighth switching element is turned on, and When the first stored data has the second stored value, the seventh switching element is turned on and the eighth switching element is turned off.

13. A memory device comprising: Multiple memory word strings coupled to each other are used to generate multiple word string current signals, and these word string current signals are summed to generate a first current signal. These memory strings include a first set of switching elements and a second set of switching elements. The first set of switching elements is used to receive multiple string select line signals. These string select lines are used to carry the first input data. The second set of switching elements is used to store the first stored data, and The current level of the first current signal is proportional to the difference between an input value of the first input data and a stored value of the first stored data.

14. The memory device of claim 13, wherein the first switching element group comprises a first switching element and a second switching element. The second switching element group includes a third switching element and a fourth switching element. The first switching element and the second switching element are respectively connected in series with the third switching element and the fourth switching element, and When each of the first and second switching elements is turned on, each of the third and fourth switching elements is turned off in response to the input value being equal to the stored value.

15. The memory device of claim 14, wherein When each of the first and second switching elements is turned on, in response to the input value being greater than the stored value, the third switching element is turned on, and When each of the first and second switching elements is turned on, the fourth switching element is turned on in response to the input value being less than the stored value.

16. A memory system comprising: Multiple first memory block groups are used to generate multiple first current signals, and these first current signals are summed to generate a first bit line signal; and Multiple second memory block groups are used to generate multiple second current signals, and these second current signals are summed to generate a second bit line signal. These first memory block groups include a third memory block group for storing first stored data and generating a third current signal among these first current signals. These second memory block groups include a fourth memory block group for storing second stored data and generating a fourth current signal among these second current signals. The current level of the third current signal is proportional to a first difference between a stored value of the first stored data and an input value of the first input data, and The current level of the fourth current signal is proportional to a second difference between a stored value of the second stored data and an input value of the first input data.

17. The memory system of claim 16, wherein in response to the first difference being less than the second difference, the current level of the third current signal is less than the current level of the fourth current signal.

18. The memory system of claim 16, wherein the first memory block groups further comprise a fifth memory block group for storing third stored data and generating a fifth current signal among the first current signals. The current level of the fifth current signal is proportional to a third difference between a stored value of the third stored data and an input value of the second input data, and In response to the third difference being equal to the first difference, the current level of the fifth current signal is equal to the current level of the third current signal.

19. The memory system of claim 18, wherein the first memory block groups further comprise a sixth memory block group for storing fourth stored data and generating a sixth current signal among the first current signals. The current level of the sixth current signal is proportional to a fourth difference between a stored value of the fourth stored data and an input value of the second input data, and In response to the fourth difference being greater than the second difference, the current level of the sixth current signal is greater than the current level of the fourth current signal.

20. The memory system of claim 19, wherein in response to the fourth difference being less than the third difference, the current level of the sixth current signal is less than the current level of the fifth current signal.

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