A nor memory port exception protection circuit

Abstract

This invention discloses a NOR memory port anomaly protection circuit, relating to the field of NOR memory technology. It includes a power supply module that supplies power to the memory module for data storage. When the memory module needs to detect the status of a port of the memory under test, it controls the power supply module to stop voltage regulation. A timing control switching module periodically provides trigger signals, allowing a detection control module to periodically provide detection voltages to different ports of the memory module. A status detection module then detects whether the voltage at different ports of the memory module is abnormal based on a first and second voltage threshold, determining whether the internal resistance of the memory under test has changed. Upon an anomaly, the power supply module self-locks and stops voltage regulation, and the abnormal port is displayed. This NOR memory port anomaly protection circuit improves circuit safety and detection efficiency.

Description

Technical Field

[0001] This invention relates to the field of NOR memory technology, specifically a NOR memory port fault protection circuit. Background Technology

[0002] NOR memory, a type of non-volatile memory, currently requires manual inspection. To prevent port malfunctions, operators use a multimeter to check the port status of the NOR memory when it is powered off, and then manually determine whether data storage can be performed normally. This requires considerable manpower, and because NOR memory has many data ports, the inspection method is complex and needs improvement. Summary of the Invention

[0003] This invention provides a NOR memory port fault protection circuit to solve the problems mentioned in the background art.

[0004] According to an embodiment of the present invention, a NOR memory port abnormality protection circuit is provided, comprising: a power supply module, a memory module, a timing switching module, a detection control module, and a status detection module; The power module is used to transmit the incoming DC power, regulate and standardize the DC power, and output the first power. The memory module is connected to the power supply module, the timing switching module and the status detection module. It is used to receive the first electrical energy and perform data storage and data interaction. When it is necessary to detect the status of the port of the memory under test, it outputs the first control signal and controls the power supply module to stop the voltage regulation work. It cyclically outputs the second control signal and controls the timing switching module to work. It receives the first abnormal signal, the second abnormal signal and the third abnormal signal output by the status detection module. The timing switching module is connected to the power supply module and the detection and control module. The memory module is used to receive DC power and the second control signal and, according to the number of times the second control signal is received, sequentially outputs the first trigger signal, the second trigger signal and the third trigger signal and controls the detection and control module to switch the signal transmission path. When the second control signal is received for the fourth time, the count is reset. The detection control module, connected to the memory module, is used to switch the signal transmission path and sequentially transmit the provided first detection voltage, second detection voltage and third detection voltage to different ports of the memory under test of the memory module when a first contact signal, a second contact signal or a third contact signal is received. The status detection module, connected to the power supply module and the detection control module, is used to compare the first detection voltage, second detection voltage, or third detection voltage of different ports of the memory under test transmitted to the memory module with the set first voltage threshold and second voltage threshold. When the first detection signal is greater than the first voltage threshold or less than the second voltage threshold, the module outputs a first abnormal signal and controls the power supply module to stop voltage regulation and perform self-locking illumination. When the second detection signal is greater than the first voltage threshold or less than the second voltage threshold, the module outputs a second abnormal signal and controls the power supply module to stop voltage regulation and perform self-locking illumination. When the third detection signal is greater than the first voltage threshold or less than the second voltage threshold, the module outputs a third abnormal signal and controls the power supply module to stop voltage regulation and perform self-locking illumination.

[0005] As a further embodiment of the present invention: the power module includes a power interface, a first power transistor, a third resistor, and a voltage regulator; the memory module includes a first capacitor, a memory under test, a fifth resistor, an eighth diode, a ninth diode, a tenth diode, and a first controller; Preferably, the first end of the power interface is connected to the source of the first power transistor, the drain of the first power transistor is connected to the input of the voltage regulator, the output of the voltage regulator is connected to the power supply of the memory under test and one end of the first capacitor, and is connected to the first data terminal of the memory under test and the IO1 terminal of the first controller through the fifth resistor, the second data terminal of the memory under test is connected to the cathode of the eighth diode and the IO2 terminal of the first controller, the third data terminal of the memory under test is connected to the cathode of the ninth diode and the IO3 terminal of the first controller, the fourth data terminal of the memory under test is connected to the IO4 terminal of the first controller and the cathode of the tenth diode, the ground terminal of the memory under test is connected to the other end of the first capacitor, the ground terminal of the voltage regulator, one end of the third resistor, the second end of the power interface and the ground terminal, and the IO6 terminal of the first controller is connected to the gate of the first power transistor and the other end of the third resistor.

[0006] As a further embodiment of the present invention: the timing switching module includes a second resistor, a first switching transistor, a first counter, a second switching transistor, and a fourth resistor; Preferably, one end of the second resistor is connected to one end of the fourth resistor, the second end of the power interface, and the eighth and thirteenth ends of the first counter; the other end of the second resistor is connected to the fourteenth end of the first counter and the emitter of the first switching transistor; the collector of the first switching transistor is connected to the collector of the second switching transistor and the sixteenth end of the first counter, and is connected to the first end of the power interface through the first resistor; the base of the second switching transistor is connected to the seventh end of the first counter; the emitter of the second switching transistor is connected to the fifteenth end of the first counter and the other end of the fourth resistor; and the base of the first switching transistor is connected to the IO5 end of the first controller.

[0007] As a further embodiment of the present invention: the detection control module includes a sixth resistor, a first voltage regulator, and a first analog switch; Preferably, the fifth, eighth, and first terminals of the first analog switch are all connected to the first voltage regulator through the sixth resistor; the third, sixth, and thirteenth terminals of the first analog switch are respectively connected to the third, second, and fourth terminals of the first counter; and the fourth, ninth, and second terminals of the first counter are respectively connected to the anodes of the eighth, ninth, and tenth diodes.

[0008] As a further embodiment of the present invention: the state detection module includes a first diode, a second diode, a third diode, a first comparator, a second comparator, a fourth diode, a fifth diode, a first reference power supply, and a second reference power supply; Preferably, the anodes of the first diode, the second diode, and the third diode are connected to the anodes of the eighth diode, the ninth diode, and the tenth diode, respectively. The cathode of the first diode is connected to the cathodes of the second and third diodes, the non-inverting input of the first comparator, and the inverting input of the second comparator. The inverting input of the first comparator and the non-inverting input of the second comparator are connected to the first reference power supply and the second reference power supply, respectively. The outputs of the first and second comparators are connected to the anodes of the fourth and fifth diodes, respectively. The cathode of the fourth diode is connected to the cathode of the fifth diode and the IO7 terminal of the first controller.

[0009] As a further embodiment of the present invention: the state detection module also includes a self-locking device, a sixth diode, a seventh diode, a first logic device, and a first indicator light; Preferably, the input terminal of the self-locking device is connected to the cathode of the fourth diode, the output terminal of the self-locking device is connected to the B terminal of the first logic device and the gate of the first power transistor, the A terminal of the first logic device is connected to the cathodes of the sixth and seventh diodes, the anode of the sixth diode is connected to the anode of the first diode, the anode of the seventh diode is connected to the Y terminal of the first logic device and the anode of the first indicator light, and the cathode of the first indicator light is grounded.

[0010] As a further embodiment of the present invention: the status detection module further includes a first display device and a second display device; Preferably, the first input terminal of the first display device and the first input terminal of the second display device are respectively connected to the output terminal of the self-locking device, and the second input terminal of the first display device and the second input terminal of the second display device are respectively connected to the anode of the second diode and the anode of the third diode.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: The NOR memory port abnormality protection circuit of the present invention can be powered by the power supply module for data storage. When the memory module needs to detect the status of the port of the memory under test, it controls the power supply module to stop the voltage regulation operation. The timing control timing switching module provides a trigger signal at regular intervals, so that the detection control module provides detection voltage to different ports of the memory module at regular intervals. The status detection module detects whether the voltage of different ports of the memory module is abnormal according to the set first voltage threshold and second voltage threshold, determines whether the internal resistance of the memory under test in the memory module has changed, and when an abnormality occurs, it self-locks the power supply module to stop the voltage regulation operation and displays the abnormal port, thereby improving the safety and detection efficiency of the circuit. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A schematic block diagram of a NOR memory port anomaly protection circuit provided in an embodiment of the present invention; Figure 2 A circuit diagram of a NOR memory port anomaly protection circuit provided for an embodiment of the present invention; Figure 3 The circuit diagram is provided for the state detection module in an embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] In one embodiment, see Figure 1 A NOR memory port abnormality protection circuit includes: a power supply module 1, a memory module 2, a timing switching module 3, a detection and control module 4, and a status detection module 5. Specifically, power module 1 is used to transmit the incoming DC power, perform voltage regulation on the DC power and output the first power. The memory module 2 is connected to the power supply module 1, the timing switching module 3 and the status detection module 5. It is used to receive the first electrical energy and perform data storage and data interaction. When it is necessary to detect the status of the port of the memory under test, it outputs the first control signal and controls the power supply module 1 to stop the voltage regulation work. It cyclically outputs the second control signal and controls the timing switching module 3 to work. It receives the first abnormal signal, the second abnormal signal and the third abnormal signal output by the status detection module 5. The timing switching module 3 is connected to the power supply module 1 and the detection and control module 4. The memory module 2 is used to receive DC power and the second control signal and, according to the number of times the second control signal is received, sequentially outputs the first trigger signal, the second trigger signal and the third trigger signal and controls the detection and control module 4 to switch the signal transmission path. When the second control signal is received for the fourth time, the count is reset. The detection control module 4 is connected to the memory module 2 and is used to switch the signal transmission path and sequentially transmit the provided first detection voltage, second detection voltage and third detection voltage to different ports of the memory to be tested in the memory module 2 when the first contact signal, second contact signal or third contact signal is received. The status detection module 5, connected to the power supply module 1 and the detection control module 4, is used to compare the first detection voltage, the second detection voltage, or the third detection voltage of different ports of the memory under test transmitted to the memory module 2 with the set first voltage threshold and the second voltage threshold. When the first detection signal is greater than the first voltage threshold or less than the second voltage threshold, the module outputs a first abnormal signal and controls the power supply module 1 to stop voltage regulation and perform self-locking illumination. When the second detection signal is greater than the first voltage threshold or less than the second voltage threshold, the module outputs a second abnormal signal and controls the power supply module 1 to stop voltage regulation and perform self-locking illumination. When the third detection signal is greater than the first voltage threshold or less than the second voltage threshold, the module outputs a third abnormal signal and controls the power supply module 1 to stop voltage regulation and perform self-locking illumination.

[0016] In a specific embodiment, the power module 1 can be a power circuit composed of a power interface, a field-effect transistor, a voltage regulator, etc., which can be connected to DC power, power transmission control, and voltage regulation; the memory module 2 can be a memory circuit composed of a memory under test, resistors, a microcontroller, etc., which can perform data storage and data interaction. The microcontroller integrates many components such as an arithmetic unit, a controller, a memory, and input / output devices to realize functions such as signal processing, data storage, module control, and timing control; the timing switching module 3 can be a timing switching circuit composed of a counter, a transistor, and a resistor. It can provide a first trigger signal, a second trigger signal, and a third trigger signal of a high level state sequentially according to the number of times the high-level signal is output by the memory module 2, i.e., the number of times the second control signal is received, and then, upon receiving the second control signal for the fourth time, it will provide the first trigger signal, the second trigger signal, and the third trigger signal of a high level state. When the number is reached, the count is reset; the detection control module 4 can be a detection control circuit composed of analog switches, resistors and voltage regulators. It can switch the signal transmission path according to the state of the first trigger signal, the second trigger signal and the third trigger signal output by the timing switching module 3, and provide the first detection voltage, the second detection voltage and the third detection voltage to different ports of the memory under test of the memory module 2. The voltages of the first detection voltage, the second detection voltage and the third detection voltage are equal; the state detection module 5 can be a state detection circuit composed of comparators, diodes, logic devices, indicator lights, display devices, etc. It can compare the input signal with the set first voltage threshold and the second voltage threshold, and determine whether there is an abnormality in different ports of the memory under test of the memory module 2 according to the comparison result, and illuminate the abnormal ports.

[0017] In this embodiment, please refer to Figure 2 and Figure 3 The power module 1 includes a power interface, a first power transistor Q1, a third resistor R3, and a voltage regulator; the memory module 2 includes a first capacitor C1, a memory under test, a fifth resistor R5, an eighth diode D8, a ninth diode D9, a tenth diode D10, and a first controller U1. Specifically, the first end of the power interface is connected to the source of the first power transistor Q1, the drain of the first power transistor Q1 is connected to the input of the voltage regulator, the output of the voltage regulator is connected to the power supply of the memory under test and one end of the first capacitor C1, and is connected to the first data terminal of the memory under test and the IO1 terminal of the first controller U1 through the fifth resistor R5. The second data terminal of the memory under test is connected to the cathode of the eighth diode D8 and the IO2 terminal of the first controller U1. The third data terminal of the memory under test is connected to the cathode of the ninth diode D9 and the IO3 terminal of the first controller U1. The fourth data terminal of the memory under test is connected to the IO4 terminal of the first controller U1 and the cathode of the tenth diode D10. The ground terminal of the memory under test is connected to the other end of the first capacitor C1, the ground terminal of the voltage regulator, one end of the third resistor R3, the second end of the power interface and the ground terminal. The IO6 terminal of the first controller U1 is connected to the gate of the first power transistor Q1 and the other end of the third resistor R3.

[0018] In a specific embodiment, the first power transistor Q1 can be a P-channel MOSFET; the voltage regulator can be composed of an LM317 voltage regulator to provide the operating voltage required by the memory under test; and the first controller U1 can be an STM32 microcontroller.

[0019] Furthermore, the timing switching module 3 includes a second resistor R2, a first switch V1, a first counter U2, a second switch V2, and a fourth resistor R4; Specifically, one end of the second resistor R2 is connected to one end of the fourth resistor R4, the second end of the power interface, and the eighth and thirteenth ends of the first counter U2. The other end of the second resistor R2 is connected to the fourteenth end of the first counter U2 and the emitter of the first switching transistor V1. The collector of the first switching transistor V1 is connected to the collector of the second switching transistor V2 and the sixteenth end of the first counter U2, and is connected to the first end of the power interface through the first resistor. The base of the second switching transistor V2 is connected to the seventh end of the first counter U2. The emitter of the second switching transistor V2 is connected to the fifteenth end of the first counter U2 and the other end of the fourth resistor R4. The base of the first switching transistor V1 is connected to the IO5 end of the first controller U1.

[0020] In a specific embodiment, both the first switching transistor V1 and the second switching transistor V2 can be NPN transistors; the first counter U2 can be a CD4017 counter.

[0021] Furthermore, the detection and control module 4 includes a sixth resistor R6, a first voltage regulator VCC1, and a first analog switch U3; Specifically, the fifth, eighth, and first terminals of the first analog switch U3 are all connected to the first voltage regulator VCC1 through the sixth resistor R6. The third, sixth, and thirteenth terminals of the first analog switch U3 are connected to the third, second, and fourth terminals of the first counter U2, respectively. The fourth, ninth, and second terminals of the first counter U2 are connected to the anodes of the eighth diode D8, the ninth diode D9, and the tenth diode D10, respectively.

[0022] In a specific embodiment, the first analog switch U3 can be a CD4066 chip; the first voltage regulator VCC1, together with the sixth resistor R6, can provide a first detection voltage, a second detection voltage and a third detection voltage.

[0023] Furthermore, the status detection module 5 includes a first diode D1, a second diode D2, a third diode D3, a first comparator A1, a second comparator A2, a fourth diode D4, a fifth diode D5, a first reference power supply VF1, and a second reference power supply VF2; Specifically, the anodes of the first diode D1, the second diode D2, and the third diode D3 are respectively connected to the anodes of the eighth diode D8, the ninth diode D9, and the tenth diode D10. The cathode of the first diode D1 is connected to the cathodes of the second diode D2 and the third diode D3, the non-inverting input of the first comparator A1, and the inverting input of the second comparator A2. The inverting input of the first comparator A1 and the non-inverting input of the second comparator A2 are respectively connected to the first reference power supply VF1 and the second reference power supply VF2. The outputs of the first comparator A1 and the second comparator A2 are respectively connected to the anodes of the fourth diode D4 and the fifth diode D5. The cathode of the fourth diode D4 is connected to the cathode of the fifth diode D5 and the IO7 terminal of the first controller U1.

[0024] In a specific embodiment, the first reference power supply VF1 provides a first voltage threshold, and the second reference power supply VF2 provides a second voltage threshold. When the internal resistance of different data terminals of the memory under test is normal, the first voltage threshold is greater than the first detection voltage, the second detection voltage, and the third detection voltage, and the second voltage threshold is less than the first detection voltage, the second detection voltage, and the third detection voltage. Both the first comparator A1 and the second comparator A2 can be selected from LM358 comparators.

[0025] Furthermore, the status detection module 5 also includes a self-locking device, a sixth diode D6, a seventh diode D7, a first logic unit J1, and a first indicator LED1; Specifically, the input terminal of the self-locking device is connected to the cathode of the fourth diode D4, the output terminal of the self-locking device is connected to the B terminal of the first logic device J1 and the gate of the first power transistor Q1, the A terminal of the first logic device J1 is connected to the cathode of the sixth diode D6 and the cathode of the seventh diode D7, the anode of the sixth diode D6 is connected to the anode of the first diode D1, the anode of the seventh diode D7 is connected to the Y terminal of the first logic device J1 and the anode of the first indicator LED1, and the cathode of the first indicator LED1 is grounded.

[0026] In a specific embodiment, the above-mentioned self-locking device may be composed of a transistor and a resistor to perform self-locking processing on the input high-level signal; the above-mentioned first logic device J1 may be an AND gate, which, together with the sixth diode D6 and the seventh diode D7, performs single-ended self-locking; the above-mentioned first indicator LED1 may be an LED.

[0027] Furthermore, the status detection module 5 also includes a first display device and a second display device; Specifically, the first input terminal of the first display device and the first input terminal of the second display device are respectively connected to the output terminal of the self-locking device, and the second input terminal of the first display device and the second input terminal of the second display device are respectively connected to the anode of the second diode D2 and the anode of the third diode D3.

[0028] In a specific embodiment, the circuit composition structure of the first display device and the circuit composition structure of the second display device are the same as the circuit composition structure of the self-locking device, the sixth diode D6, the seventh diode D7, the first logic device J1 and the first indicator LED1.

[0029] In this embodiment of a NOR memory port fault protection circuit, DC power is connected through a power interface, transmitted by a first power transistor Q1, regulated by a voltage regulator, and output as the first power. This first power is received by the power supply terminal of the memory under test (MDT). A data interaction channel is established between the first, second, third, and fourth data terminals of the MDT and the IO1, IO2, IO3, and IO4 terminals of the first controller U1 to achieve data interaction. When it is necessary to detect the port status of the MDT, the IO6 terminal of the first controller U1 outputs a first control signal and controls the first power transistor Q1 to turn off, thus de-energizing the circuit. Simultaneously, the IO5 terminal of the first controller U1 cyclically outputs a second control signal at regular intervals. When the second control signal is output, the first switch V1 is turned on, causing the third terminal of the first counter U2 to output the first trigger signal, which in turn turns on the fourth and fifth terminals of the first analog switch U3. The first detection voltage is provided by the first voltage regulator VCC1 and the sixth resistor R6 and transmitted to the second data terminal of the memory under test through the first analog switch U3 and the eighth diode D8. The first comparator A1, the second comparator A2, the first reference power supply VF1, and the second reference power supply VF2 detect the change state of the first detection voltage, that is, whether it is greater than the first voltage threshold set by the first reference power supply VF1 or less than the second voltage threshold set by the second reference power supply VF2. If it is greater, the first comparator A1 outputs... If the voltage level is high, and less than the threshold, the second comparator A2 outputs a high level, which is received by the IO7 terminal of the first controller U1. The self-locking device performs a high-level self-locking, cooperating with the first logic unit J1, the sixth diode D6, and the seventh diode D7 to control the first indicator LED1 for illumination. Similarly, when the second control signal is output for the second time, the second terminal of the first counter U2 provides a second trigger signal, and the ninth and eighth terminals of the first analog switch U3 are turned on, providing a second detection voltage to the third data terminal of the memory under test, and detecting the voltage of the second detection signal relative to the first voltage threshold and the second voltage threshold. If the voltage is greater than the first voltage threshold or less than the second voltage threshold, the first display device displays an abnormality. Similarly, in When the second control signal is output for the third time, the fourth terminal of the first counter U2 provides the third trigger signal, and the first and second terminals of the first analog switch U3 are turned on, providing the third detection power supply to the fourth data terminal of the memory under test, and detecting the voltage of the third detection signal and the first and second voltage thresholds. When the voltage is greater than the first voltage threshold or less than the second voltage threshold, the second display device displays an abnormality. When the self-locking device is self-locking, it will also control the first power transistor Q1 to be turned off, and the voltage regulator will stop working. When the second control signal is output for the fourth time, the seventh terminal of the first counter U2 triggers the second switch to be turned on, and the first counter U2 is reset in conjunction with the fourth resistor, and then the counting work is restarted.

[0030] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0031] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A NOR memory port exception protection circuit, comprising: The circuit includes: a power supply module, a memory module, a timing switching module, a detection and control module, and a status detection module; The power module is used to transmit the incoming DC power, regulate and standardize the DC power, and output the first power. The memory module is connected to the power supply module, the timing switching module and the status detection module. It is used to receive the first electrical energy and perform data storage and data interaction. When it is necessary to detect the status of the port of the memory under test, it outputs the first control signal and controls the power supply module to stop the voltage regulation work. It cyclically outputs the second control signal and controls the timing switching module to work. It receives the first abnormal signal, the second abnormal signal and the third abnormal signal output by the status detection module. The timing switching module is connected to the power supply module and the detection and control module. The memory module is used to receive DC power and the second control signal and, according to the number of times the second control signal is received, sequentially outputs the first trigger signal, the second trigger signal and the third trigger signal and controls the detection and control module to switch the signal transmission path. When the second control signal is received for the fourth time, the count is reset. The detection control module, connected to the memory module, is used to switch the signal transmission path and sequentially transmit the provided first detection voltage, second detection voltage and third detection voltage to different ports of the memory under test of the memory module when a first contact signal, a second contact signal or a third contact signal is received. The status detection module, connected to the power supply module and the detection control module, is used to compare the first detection voltage, second detection voltage, or third detection voltage of different ports of the memory under test transmitted to the memory module with the set first voltage threshold and second voltage threshold. When the first detection signal is greater than the first voltage threshold or less than the second voltage threshold, the module outputs a first abnormal signal and controls the power supply module to stop voltage regulation and perform self-locking illumination. When the second detection signal is greater than the first voltage threshold or less than the second voltage threshold, the module outputs a second abnormal signal and controls the power supply module to stop voltage regulation and perform self-locking illumination. When the third detection signal is greater than the first voltage threshold or less than the second voltage threshold, the module outputs a third abnormal signal and controls the power supply module to stop voltage regulation and perform self-locking illumination.

2. The NOR memory port exception protection circuit of claim 1, wherein, The power module includes a power interface, a first power transistor, a third resistor, and a voltage regulator; the memory module includes a first capacitor, a memory under test, a fifth resistor, an eighth diode, a ninth diode, a tenth diode, and a first controller. The first end of the power interface is connected to the source of the first power transistor. The drain of the first power transistor is connected to the input of the voltage regulator. The output of the voltage regulator is connected to the power supply of the memory under test (MDT) and one end of the first capacitor, and is connected to the first data terminal of the MDT and the IO1 terminal of the first controller via the fifth resistor. The second data terminal of the MDT is connected to the cathode of the eighth diode and the IO2 terminal of the first controller. The third data terminal of the MDT is connected to the cathode of the ninth diode and the IO3 terminal of the first controller. The fourth data terminal of the MDT is connected to the IO4 terminal of the first controller and the cathode of the tenth diode. The ground terminal of the MDT is connected to the other end of the first capacitor, the ground terminal of the voltage regulator, one end of the third resistor, the second end of the power interface, and the ground terminal. The IO6 terminal of the first controller is connected to the gate of the first power transistor and the other end of the third resistor.

3. The NOR memory port exception protection circuit of claim 2, wherein, The timing switching module includes a second resistor, a first switching transistor, a first counter, a second switching transistor, and a fourth resistor; One end of the second resistor is connected to one end of the fourth resistor, the second end of the power interface, and the eighth and thirteenth ends of the first counter. The other end of the second resistor is connected to the fourteenth end of the first counter and the emitter of the first switching transistor. The collector of the first switching transistor is connected to the collector of the second switching transistor and the sixteenth end of the first counter, and is connected to the first end of the power interface through the first resistor. The base of the second switching transistor is connected to the seventh end of the first counter. The emitter of the second switching transistor is connected to the fifteenth end of the first counter and the other end of the fourth resistor. The base of the first switching transistor is connected to the IO5 end of the first controller.

4. The NOR memory port exception protection circuit of claim 3, wherein, The detection and control module includes a sixth resistor, a first voltage regulator, and a first analog switch; The fifth, eighth, and first terminals of the first analog switch are all connected to the first voltage regulator through the sixth resistor. The third, sixth, and thirteenth terminals of the first analog switch are respectively connected to the third, second, and fourth terminals of the first counter. The fourth, ninth, and second terminals of the first counter are respectively connected to the anode of the eighth diode, the anode of the ninth diode, and the anode of the tenth diode.

5. The NOR memory port exception protection circuit of claim 4, wherein, The state detection module includes a first diode, a second diode, a third diode, a first comparator, a second comparator, a fourth diode, a fifth diode, a first reference power supply, and a second reference power supply; The anodes of the first diode, the second diode, and the third diode are respectively connected to the anodes of the eighth diode, the ninth diode, and the tenth diode. The cathode of the first diode is connected to the cathodes of the second and third diodes, the non-inverting input of the first comparator, and the inverting input of the second comparator. The inverting input of the first comparator and the non-inverting input of the second comparator are respectively connected to the first reference power supply and the second reference power supply. The outputs of the first and second comparators are respectively connected to the anodes of the fourth and fifth diodes. The cathode of the fourth diode is connected to the cathode of the fifth diode and the IO7 terminal of the first controller.

6. The NOR memory port exception protection circuit of claim 5, wherein, The status detection module also includes a self-locking device, a sixth diode, a seventh diode, a first logic unit, and a first indicator light; The input terminal of the self-locking device is connected to the cathode of the fourth diode, the output terminal of the self-locking device is connected to the B terminal of the first logic device and the gate of the first power transistor, the A terminal of the first logic device is connected to the cathodes of the sixth diode and the seventh diode, the anode of the sixth diode is connected to the anode of the first diode, the anode of the seventh diode is connected to the Y terminal of the first logic device and the anode of the first indicator light, and the cathode of the first indicator light is grounded.

7. The NOR memory port exception protection circuit of claim 6, wherein, The status detection module also includes a first display device and a second display device; The first input terminal of the first display device and the first input terminal of the second display device are respectively connected to the output terminal of the self-locking device, and the second input terminal of the first display device and the second input terminal of the second display device are respectively connected to the anode of the second diode and the anode of the third diode.

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