Memory power supply control method, circuit and electrical energy metering device

Abstract

This invention discloses a memory power supply control method, circuit, and power metering device. It acquires the current power supply status of the external power supply; if the current power supply status is power-down, a power-down operation is performed on the non-volatile memory; if the current power supply status switches to power-on during the power-down operation, it determines whether the power supply voltage of the non-volatile memory meets the initialization conditions; if the initialization conditions are not met, the power-down operation continues until the initialization conditions are met, and a power-on operation is performed on the non-volatile memory. This effectively ensures that the non-volatile memory completes the correct power-on initialization process under abnormal scenarios such as rapid switching of the external power supply, thereby avoiding data read / write failures caused by incomplete initialization of the non-volatile memory and significantly improving the data storage reliability and system stability of devices containing this non-volatile memory in complex power environments.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a memory power supply control method, circuit, and power metering device. Background Technology

[0002] In low-power electronic devices such as electricity meters that require backup batteries to maintain long-term operation, in order to save energy to the greatest extent, the system usually cuts off the power supply to peripheral devices such as non-volatile memory by the main controller when the external main power supply is disconnected.

[0003] However, in complex real-world power grid environments with transient voltage drops or rapid switching, the aforementioned power management strategies face challenges. When an external power supply experiences a very brief interruption, the main controller rapidly performs power-off and power-on operations on the memory, following the power supply status. Since the reset of the memory chip's internal state depends on a specific change in its supply voltage, in the aforementioned abnormal, uncontrolled, rapid power switching scenarios, the actual state of the memory may become uncertain, causing subsequent access operations by the main controller to fail and severely impacting the reliability of system data storage.

[0004] Currently, in these devices, the main controller's control over the power supply to the memory relies primarily on power status or simple timing logic. It doesn't adequately consider how to ensure the memory can enter a deterministic and stably accessible state under extreme conditions of rapid power fluctuations. Therefore, existing solutions suffer from unreliable memory access when dealing with scenarios involving rapid power switching. Summary of the Invention

[0005] This invention provides a memory power control method, circuit, and power metering device to solve the problem of unreliable memory access in existing solutions when dealing with scenarios of rapid power switching.

[0006] A memory power supply control method, comprising: Obtain the current power supply status of the external power source; If the current power supply state is a power-down state, then a power-down operation is performed on the non-volatile memory; If the current power supply state switches to the power-on state during the power-down operation, then it is determined whether the power supply voltage of the non-volatile memory meets the initialization conditions. If the initialization conditions are not met, the power-down operation continues until the initialization conditions are met, at which point the power-on operation is performed on the non-volatile memory.

[0007] Furthermore, the initialization condition is that the power supply voltage of the non-volatile memory is less than a preset voltage, and the time during which the power supply voltage of the non-volatile memory is less than the preset voltage is greater than a first preset time.

[0008] Furthermore, the preset voltage is 0.7 to 1 volt; the preset time is 0.25 to 0.35 milliseconds.

[0009] Furthermore, the step of performing a power-down operation on the non-volatile memory if the current power supply state is a power-down state includes: Obtain the current power-off time of the external power supply; After a second preset time interval from the current power-down time, a power-down operation is performed on the non-volatile memory.

[0010] A memory power control circuit for implementing the above-mentioned memory power control method includes: a power supply detection circuit, a memory drive circuit, and a logic processing circuit. The power supply detection circuit is connected to the logic processing circuit and is used to connect to an external power supply and output the current power supply status to the logic processing circuit. The logic processing circuit is connected to the memory driving circuit and is used to output a power-down control signal to the memory driving circuit if the current power supply state is a power-down state. The memory drive circuit is connected to the internal power supply terminal and the non-volatile memory, and is used to disconnect the non-volatile memory and the internal power supply terminal according to the power-down control signal, so as to perform a power-down operation on the non-volatile memory. The logic processing circuit is connected to the power supply terminal of the non-volatile memory. If the current power supply state switches to the power-on state during the power-down operation, it determines whether the power supply terminal voltage of the non-volatile memory meets the initialization conditions. If the initialization conditions are not met, it continues to output the power-down control signal to the memory driving circuit until the initialization conditions are met, and then outputs the power-on control signal to the memory driving circuit. The memory driver circuit is also used to turn on the non-volatile memory and the internal power supply terminal according to the power-on control signal, so as to perform a power-on operation on the non-volatile memory.

[0011] Furthermore, the logic processing circuit includes a voltage detection circuit and a main control circuit; The voltage detection circuit is connected to the power supply terminal of the non-volatile memory and is used to detect the power supply terminal voltage of the non-volatile memory. When the power supply terminal voltage of the non-volatile memory is less than a preset voltage, a first level signal is output. The main control circuit is connected to the voltage detection circuit and the memory drive circuit, and is used to determine that the initialization condition is met when the holding time of the first level signal is greater than the first preset time.

[0012] Furthermore, the memory driving circuit includes a first transistor and a first resistor circuit; The first terminal of the first transistor is connected to the internal power supply terminal, the second terminal of the first transistor is connected to the power supply terminal of the non-volatile memory, and the third terminal of the first transistor is coupled to the main control circuit through the first resistor circuit.

[0013] Furthermore, the first transistor is a bipolar transistor.

[0014] An energy metering device includes a non-volatile memory and the aforementioned memory power control circuit. The non-volatile memory is connected to the memory power control circuit.

[0015] Furthermore, the non-volatile memory is a Flash memory.

[0016] This invention provides a memory power control method, circuit, and power metering device. It acquires the current power supply status of the external power supply; if the current power supply status is power-down, a power-down operation is performed on the non-volatile memory; if the current power supply status switches to power-on during the power-down operation, it determines whether the power supply voltage of the non-volatile memory meets the initialization conditions; if the initialization conditions are not met, the power-down operation continues until the initialization conditions are met, and a power-on operation is performed on the non-volatile memory. This effectively ensures that the non-volatile memory completes the correct power-on initialization process under abnormal scenarios such as rapid switching of the external power supply, thereby avoiding data read / write failures caused by incomplete initialization of the non-volatile memory and significantly improving the data storage reliability and system stability of devices containing this non-volatile memory in complex power environments.

[0017] The memory power control circuit includes a power supply detection circuit, a memory drive circuit, and a logic processing circuit. Through the coordinated operation of these circuits, the power supply to the non-volatile memory is reliably cut off when the external power supply is turned off to reduce power consumption. When the external power supply is quickly restored, the power is not immediately restored, but the circuit waits and verifies whether the voltage drop process of the non-volatile memory power supply terminal meets the preset initialization conditions. This ensures that the non-volatile memory can start working from a fully reset and determined state every time it is powered on, effectively solving the problem of unreliable data access in scenarios where the external power supply is quickly switched on and off. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a memory power control method according to an embodiment of the present invention; Figure 2 This is a circuit diagram of a memory power control circuit according to an embodiment of the present invention; Figure 3 This is a circuit diagram of an external power supply in one embodiment of the present invention; Figure 4 This is a timing diagram of a memory power control circuit in one embodiment of the present invention; Figure 5 This is another timing diagram of the memory power control circuit in one embodiment of the present invention.

[0020] In the diagram: 1. Non-volatile memory; 2. Memory driver circuit; 3. Logic processing circuit; 31. Voltage detection circuit; 32. Main control circuit. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0023] To fully understand this invention, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0024] This embodiment provides a memory power control circuit, such as Figure 2 As shown, it includes: a power supply detection circuit (not shown in the figure), a memory driver circuit 2, and a logic processing circuit 3.

[0025] As an example, the power supply detection circuit is connected to logic processing circuit 3 to connect to an external power supply and output the current power supply status to logic processing circuit 3. Exemplarily, this power supply detection circuit is used to detect the voltage status of the external power supply in real time and output a logic signal representing the current power supply status. For example, when the external power supply voltage is normal, it outputs a high level, indicating a powered-on state; when the external power supply voltage drops and power is lost, it outputs a low level, indicating a powered-off state. The power supply detection circuit can be implemented using a resistor divider network in conjunction with a voltage comparator or other conventional power supply monitoring circuits. For example... Figure 3 As shown, the external power supply can be an AC-DC converter connected to the power grid. Resistors R1, R3, and R4 form a resistor voltage divider network connected in series between the output of the AC-DC converter and ground. The voltage divider node POWER_OFF is connected to the main control circuit 32. The voltage comparator inside the main control circuit 32 compares the voltage of the voltage divider node POWER_OFF to determine the current power supply status.

[0026] As an example, the memory driver circuit 2 is connected between the internal power supply terminal VCC-3.3V and the power supply terminal VCC of the non-volatile memory 1, and its control terminal is connected to the main control circuit 32. The memory driver circuit 2 is used to turn on or off the power supply path from the internal power supply terminal VCC-3.3V to the power supply terminal VCC of the non-volatile memory 1 according to the control signal VCC-FLASH-CTRL from the main control circuit 32. The internal power supply terminal VCC-3.3V can come from an external power supply, an LDO (Low Dropout Regulator), or a backup battery.

[0027] As an example, logic processing circuit 3 is connected to memory driver circuit 2, and is used to output a power-down control signal to memory driver circuit 2 if the current power supply state is power-down. Memory driver circuit 2 is connected to the internal power supply terminal VCC-3.3V and non-volatile memory 1, and is used to disconnect non-volatile memory 1 and internal power supply terminal VCC-3.3V according to the power-down control signal to perform a power-down operation on non-volatile memory 1. Logic processing circuit 3 is connected to the power supply terminal VCC of non-volatile memory 1, and is used to determine whether the voltage of power supply terminal VCC of non-volatile memory 1 meets the initialization conditions if the current power supply state switches to power-on state during the power-down operation. If the initialization conditions are not met, it continues to output a power-down control signal to memory driver circuit 2 until the initialization conditions are met, and then outputs a power-on control signal to memory driver circuit 2. Memory driver circuit 2 is also used to turn on non-volatile memory 1 and internal power supply terminal VCC-3.3V according to the power-on control signal to perform a power-on operation on non-volatile memory 1.

[0028] Specifically, the logic processing circuit 3 includes a voltage detection circuit 31 and a main control circuit 32.

[0029] For example, the voltage detection circuit 31 is connected to the power supply terminal VCC of the non-volatile memory 1, and is used to detect the voltage of the power supply terminal VCC of the non-volatile memory 1. When the voltage of the power supply terminal VCC of the non-volatile memory 1 is less than a preset voltage, it outputs a first level signal, such as a low level signal. In a preferred embodiment, the voltage detection circuit 31 can be implemented using a high-precision voltage monitoring chip. The sensing pin SENSE of the voltage detection circuit 31 is connected to the power supply terminal VCC of the non-volatile memory 1. When the voltage of the power supply terminal VCC of the non-volatile memory 1 is detected to be lower than its internal threshold, such as 0.7125V, its reset output pin nRESET is pulled low, thereby generating a first level signal. Figure 2 As shown, its reset output pin nRESET is connected to the internal power supply terminal VCC-3.3V through resistor R2.

[0030] For example, the main control circuit 32 is a microcontroller (MCU). The main control circuit 32 is connected to the voltage detection circuit 31 and the memory drive circuit 2, and is used to receive the current power supply state and a first-level signal, and generate power-down control signals and power-on control signals according to preset logic, and output them to the memory drive circuit 2. Understandably, the preset logic includes determining that the initialization condition is met when the holding time of the first-level signal is greater than a first preset time, and outputting the power-on control signal to the memory drive circuit 2. If the initialization condition is not met, the power-down control signal continues to be output to the memory drive circuit 2 until the initialization condition is met. Figure 2 As shown, the main control circuit 32 can obtain the current power supply status output by the power supply detection circuit through the I / O port.

[0031] As an example, the memory drive circuit 2 includes a first transistor Q1 acting as an electronic switch and a first resistor circuit consisting of a resistor R10. The first terminal of the first transistor Q1 is connected to the internal power supply terminal VCC-3.3V, the second terminal of the first transistor Q1 is connected to the power supply terminal VCC of the non-volatile memory 1, and the third terminal of the first transistor Q1 is coupled to the main control circuit 32 through the first resistor circuit.

[0032] Optionally, the first transistor Q1 is a transistor, such as a PNP transistor. The first terminal of the first transistor Q1 is the emitter, which is connected to the internal power supply terminal VCC-3.3V. The second terminal of the first transistor Q1 is the collector, which is connected to the power supply terminal VCC of the non-volatile memory 1. The third terminal of the first transistor Q1 is the base, which is coupled to the output pin of the main control circuit 32 through the first resistor circuit.

[0033] For example, when the main control circuit 32 outputs a power-down control signal, such as a high level, the first transistor Q1 is turned off, thereby disconnecting the non-volatile memory 1 from the internal power supply terminal VCC-3.3V, thus realizing the power-down operation of the non-volatile memory 1. When the main control circuit 32 outputs a power-on control signal, such as a low level, the first transistor Q1 is turned on, thereby connecting the non-volatile memory 1 to the internal power supply terminal VCC-3.3V, thus realizing the power-on operation of the non-volatile memory 1.

[0034] In this embodiment, the memory power control circuit includes a power supply detection circuit, a memory drive circuit 2, and a logic processing circuit 3. Through the coordinated operation of the above circuits, when the external power supply is powered off, the power supply to the non-volatile memory 1 is reliably cut off to reduce power consumption. When the external power supply is quickly restored, it is not immediately powered on again, but is forced to wait and verify whether the voltage drop process of the power supply terminal of the non-volatile memory 1 meets the preset initialization conditions. This can avoid the problem of data read / write failure caused by the non-volatile memory 1 failing to initialize due to insufficient power drop. This ensures that the non-volatile memory 1 can start working from a fully reset and determined state every time it is powered on, effectively solving the problem of unreliable data access in the scenario of rapid switching of the external power supply.

[0035] This embodiment provides a memory power control method, such as... Figure 1 As shown, the steps include those implemented by the memory power control circuit in the above embodiments: S101: Obtain the current power supply status of the external power supply.

[0036] The current power supply status is detected and output by the power supply detection circuit and read by the main control circuit 32. Optionally, the external power supply is the power grid.

[0037] S102: If the current power supply state is the power-off state, then perform a power-off operation on the non-volatile memory 1.

[0038] Specifically, after determining that the power-off state is reached, the main control circuit 32 outputs a power-off control signal to the memory drive circuit 2, which then performs the power-off operation.

[0039] Optionally, this step may include: obtaining the current power-down time, and then performing the power-down operation after a second preset time interval. This delay can be used by the main control circuit 32 to complete the emergency saving of critical data.

[0040] S103: If the current power supply state is switched to the power-on state during the power-down operation, determine whether the VCC voltage of the power supply terminal of the non-volatile memory 1 meets the initialization conditions. In this embodiment, when the main control circuit 32 detects that the external power supply is quickly restored, that is, the power supply state is switched back to power-on, it will not immediately command to power on, but will start the condition judgment process.

[0041] S104: If the initialization conditions are not met, continue to perform the power-down operation until the initialization conditions are met, and then perform the power-on operation on the non-volatile memory 1.

[0042] That is, when the judgment condition is not met, the main control circuit 32 maintains the output power-down control signal; only when the condition is met will it switch to output the power-on control signal, and the drive circuit will then perform power-on.

[0043] For example, the initialization conditions are specifically as follows: the power supply voltage VCC of the non-volatile memory 1 is less than a preset voltage, and the duration of this voltage being less than the preset voltage is greater than a first preset time. The preset voltage is preferably 0.7V to 1V, and the first preset time is preferably 0.25ms to 0.35ms. These parameters can be set based on the initialization voltage Vpwd and initialization time Tpwd specified in the datasheet of the target non-volatile memory 1.

[0044] like Figure 4 As shown, VDD is the power supply terminal of the main control circuit, and SENSE is the voltage detection circuit 31. When the voltage of its sensing pin SENSE is lower than 0.7125V, its reset output pin nRESET is pulled low, thereby generating the first level signal.

[0045] like Figure 5 As shown, the voltage at the power supply terminal VCC of the non-volatile memory 1 is less than the preset voltage Vpwd and the holding time is tpwd, which satisfies the initialization conditions, and the power-on operation is performed on the non-volatile memory 1.

[0046] In this example, the timing of power-on operations is controlled by co-detecting the voltage drop and duration of the low voltage at the power supply terminal of non-volatile memory 1. This mechanism ensures that every power-on operation on non-volatile memory 1 occurs after its power supply terminal voltage has experienced a change below a preset threshold voltage for more than a preset duration. This process is consistent with the voltage timing requirements specified in the non-volatile memory 1 datasheet, which ensure a complete reset of its internal state.

[0047] In this embodiment, under abnormal scenarios such as rapid switching on and off of external power supply, the above method can effectively ensure that the non-volatile memory 1 completes the correct power-on initialization process, thereby avoiding data read / write failures caused by incomplete initialization of the non-volatile memory 1, and significantly improving the data storage reliability and system stability of the device containing the non-volatile memory 1 in complex power environments.

[0048] This embodiment provides an energy metering device, including a non-volatile memory 1 and a memory power control circuit as described in the above embodiment; the non-volatile memory 1 is connected to the memory power control circuit.

[0049] Preferably, the non-volatile memory 1 is a Flash memory.

[0050] Those skilled in the art will understand that the above embodiments are merely illustrative of the invention and not intended to limit it. For example, the voltage detection circuit 31 is not limited to a dedicated monitoring chip, but can also be implemented using a voltage divider sampling combined with an analog-to-digital converter (ADC) or a window comparator. The first transistor Q1 is not limited to a PNP transistor, but can also be an NPN transistor, a metal-oxide-semiconductor field-effect transistor (MOSFET), or an integrated power switch chip, etc. The function of the main control circuit 32 is not limited to being implemented by a general-purpose MCU, but can also be implemented by a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), or a dedicated digital logic circuit. The external power supply is typically the mains grid, but can also be applied to other DC or AC power supply scenarios where there is a risk of rapid switching on and off.

[0051] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A memory power control method, characterized by, include: Obtain the current power supply status of the external power source; If the current power supply state is a power-down state, then a power-down operation is performed on the non-volatile memory; If the current power supply state switches to the power-on state during the power-down operation, then it is determined whether the power supply voltage of the non-volatile memory meets the initialization conditions. If the initialization conditions are not met, the power-down operation continues until the initialization conditions are met, at which point the power-on operation is performed on the non-volatile memory.

2. The memory power supply control method according to claim 1, wherein The initialization condition is that the power supply voltage of the non-volatile memory is less than a preset voltage, and the time during which the power supply voltage of the non-volatile memory is less than the preset voltage is greater than a first preset time.

3. The memory power supply control method according to claim 2, wherein The preset voltage is 0.7 to 1 volt; the preset time is 0.25 to 0.35 milliseconds.

4. The memory power supply control method of claim 1, wherein, If the current power supply state is a power-down state, then performing a power-down operation on the non-volatile memory includes: Obtain the current power-off time of the external power supply; After a second preset time interval from the current power-down time, a power-down operation is performed on the non-volatile memory.

5. A memory power supply control circuit, comprising: The method for implementing the memory power control method according to any one of claims 1 to 4 includes: a power supply detection circuit, a memory driving circuit, and a logic processing circuit; The power supply detection circuit is connected to the logic processing circuit and is used to connect to an external power supply and output the current power supply status to the logic processing circuit. The logic processing circuit is connected to the memory driving circuit and is used to output a power-down control signal to the memory driving circuit if the current power supply state is a power-down state. The memory drive circuit is connected to the internal power supply terminal and the non-volatile memory, and is used to disconnect the non-volatile memory and the internal power supply terminal according to the power-down control signal, so as to perform a power-down operation on the non-volatile memory. The logic processing circuit is connected to the power supply terminal of the non-volatile memory. If the current power supply state switches to the power-on state during the power-down operation, it determines whether the power supply terminal voltage of the non-volatile memory meets the initialization conditions. If the initialization conditions are not met, it continues to output the power-down control signal to the memory driving circuit until the initialization conditions are met, and then outputs the power-on control signal to the memory driving circuit. The memory driver circuit is also used to turn on the non-volatile memory and the internal power supply terminal according to the power-on control signal, so as to perform a power-on operation on the non-volatile memory.

6. The memory power supply control circuit of claim 5, wherein, The logic processing circuit includes a voltage detection circuit and a main control circuit; The voltage detection circuit is connected to the power supply terminal of the non-volatile memory and is used to detect the power supply terminal voltage of the non-volatile memory. When the power supply terminal voltage of the non-volatile memory is less than a preset voltage, a first level signal is output. The main control circuit is connected to the voltage detection circuit and the memory drive circuit, and is used to determine that the initialization condition is met when the holding time of the first level signal is greater than the first preset time.

7. The memory power supply control circuit of claim 6, wherein, The memory driving circuit includes a first transistor and a first resistor circuit; The first terminal of the first transistor is connected to the internal power supply terminal, the second terminal of the first transistor is connected to the power supply terminal of the non-volatile memory, and the third terminal of the first transistor is coupled to the main control circuit through the first resistor circuit.

8. The memory power supply control circuit of claim 7, wherein, The first transistor is a triode.

9. An electrical energy metering device, characterized by Includes non-volatile memory and the memory power control circuit according to any one of claims 5 to 7; The non-volatile memory is connected to the memory power control circuit.

10. The electricity metering device according to claim 9, characterized in that, The non-volatile memory is a Flash memory.

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