Memory write test method

Abstract

This application provides a memory write test method, comprising: pre-charging the first bit line to the operating voltage, maintaining the voltage of the second bit line at 0V, and connecting the first bit line and the second bit line to the first transmission transistor and the second transmission transistor, respectively; scanning the first bit line from the operating voltage to 0V, with the voltage of the second node at 0V, turning on the second transmission transistor; simultaneously applying a standard operating voltage to the second bit line and the first node, detecting the voltages of the first node and the second node, recording a first output voltage curve of the first node and the second node, and determining the write state based on the first output voltage curve. This application can accurately capture the node voltage flipping process, determine whether the bit line power supply test has been passed by measuring the voltage changes of the first node and the second node, and determine the operating state of the memory cell, providing a technical reference for the design and optimization of large-scale array structures and improving the overall circuit reliability.

Description

Technical Field

[0001] This application relates to the field of memory technology, and specifically to a memory write test method. Background Technology

[0002] In existing technologies, the core unit of static random-access memory (SRAM) adopts a 6T-SRAM structure design. For example... Figure 1 As shown, this structure consists of two pairs of complementary metal-oxide-semiconductor (CMOS) inverters and two transfer transistors. The source terminals of the transfer transistors (PG1, PG2) on the left and right sides are connected to the output terminals of the corresponding inverters, forming the core signal nodes N1 and N2 of the memory cell. This structure achieves static data storage through the cross-coupling of the inverters and completes data read and write interactions with the cooperation of the transfer transistors (PG1, PG2) and bit lines (BL / BLB). It is the mainstream basic architecture in the current static memory field.

[0003] As semiconductor process nodes continue to evolve and device sizes shrink, existing technologies are gradually revealing key performance defects: the potential changes of core signal nodes N1 and N2 directly determine the electrical characteristics of the transistors in the inverter, and are core parameters for measuring the storage stability and operational reliability of 6T-SRAM cells. For example... Figure 2 As shown, existing testing methods struggle to accurately capture the effective flipping states of nodes N1 and N2, and their test fitting curves cannot reflect the complete change process of node potentials and the effectiveness of the flipping. Figure 2 The horizontal axis represents the test time, and the vertical axis represents the N1 node voltage. This defect makes it impossible to accurately evaluate the write performance of static memory cells, which in turn affects the quantitative analysis of the core electrical parameters of the memory cells, hindering the subsequent design optimization and performance verification of the memory array.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] To address the problems in the prior art, the purpose of this application is to provide a memory write test method that can accurately capture the node voltage flipping process, determine whether the bit line power supply test has been passed by measuring the voltage changes of the first node and the second node, and determine the working state of the memory cell. This provides a technical reference for the design and optimization of large-scale array structures and improves the reliability of the overall circuit.

[0006] This application provides a memory write test method, wherein each memory cell includes a first inverter, a second inverter, a first transfer transistor, and a second transfer transistor. The output terminals of the first transfer transistor and the first inverter are connected to a first node, and the output terminals of the second transfer transistor and the second inverter are connected to a second node. The method includes the following steps: The first bit line is precharged to the working voltage, and the second bit line is kept at 0V. The first bit line and the second bit line are respectively connected to the first transmission transistor and the second transmission transistor. The first bit line is scanned from the operating voltage to 0V, the voltage of the second node is 0V, the second transmission transistor is turned on, and a standard operating voltage is applied to the second bit line and the first node respectively. The voltages of the first node and the second node are detected, and the first output voltage curve of the first node and the second node is recorded. The write state is determined based on the first output voltage curve.

[0007] In some embodiments, the horizontal axis of the first output voltage curve corresponds to the voltage value of the first bit line, and the vertical axis corresponds to the voltage values ​​of the first node and the second node.

[0008] In some embodiments, the voltage value of the first bit line corresponding to the intersection of the first output voltage curves of the first node and the second node is the first write margin.

[0009] In some embodiments, the following steps are also included: The second bit line is precharged to the working voltage, while the first bit line is kept at 0V. The second bit line is scanned from the operating voltage to 0V, the voltage of the first node is 0V, the first transmission transistor is turned on, and at the same time, a standard operating voltage is applied to the first bit line and the second node respectively. The second output voltage curves of the first node and the second node are recorded, and the write state is determined according to the second output voltage curve.

[0010] In some embodiments, the horizontal axis of the second output voltage curve corresponds to the voltage value of the second bit line, and the vertical axis corresponds to the voltage values ​​of the first node and the second node.

[0011] In some embodiments, the voltage value of the second bit line corresponding to the intersection of the second output voltage curves of the first node and the second node is a second write margin.

[0012] In some embodiments, before precharging the first bit line to the operating voltage and maintaining the voltage of the second bit line at 0V, the method further includes the following steps: A standard operating voltage is applied to the word line and the power supply terminal, respectively. The word line is connected to the gate of the first transmission transistor and the gate of the second transmission transistor, respectively. The power supply terminal is connected to the first inverter and the second inverter, respectively.

[0013] In some embodiments, the source terminal of the first transmission transistor is connected to the output terminal of the first inverter, the drain terminal of the first transmission transistor is connected to the first bit line, the source terminal of the second transmission transistor is connected to the output terminal of the second inverter, and the drain terminal of the second transmission transistor is connected to the second bit line.

[0014] In some embodiments, the memory is a static memory.

[0015] The memory write test method provided in this application has the following advantages: This application provides a method for testing the write state of a memory. Through step-by-step testing of pre-charge and voltage scanning, it clearly captures the node voltage flipping process, solving the technical problem in the prior art where the fitted curve does not test the successful flipping state. This application can accurately determine whether the memory cell write is successful by observing the node voltage, and at the same time reflects the switching state of the inverter pull-up and pull-down circuits, providing a direct basis for the performance verification of the memory cell. The test results of this application can guide the selection of memory cells for subsequent memory arrays, help screen out memory cells with qualified write performance and strong stability, provide technical reference for the design and optimization of large-scale array structures, and improve the reliability of the overall circuit. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] Figure 1 This is a circuit diagram of a storage cell in a static memory. Figure 2 This is a schematic diagram of the N-node curve obtained using the existing testing scheme; Figure 3 This is a flowchart of a memory write test method according to an embodiment of this application; Figure 4 This is a schematic diagram of the BL high-level toggle obtained using the test method of this application; Figure 5 This is a schematic diagram of the BLB high-level toggling obtained using the test method of this application; Detailed Implementation

[0018] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Although the terms “upper,” “lower,” “between,” etc., may be used in this specification to describe different exemplary features and elements of this application, these terms are used herein only for convenience, such as the orientation of the examples described in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of this application. Although “first” or “second,” etc., are used in this specification to denote certain features, they are merely indicative of function and not as a limitation on the number or importance of specific features.

[0019] It should be further understood that the terms "comprising" or "including" indicate the presence of a feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are interpreted as inclusive, or mean any one or any combination thereof. Exceptions to this definition arise only when a combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0020] This application provides a memory write test method for testing the write process of a memory. Each storage cell of the memory includes a first inverter, a second inverter, a first transfer transistor, and a second transfer transistor. The output terminals of the first transfer transistor and the first inverter are connected to a first node, and the output terminals of the second transfer transistor and the second inverter are connected to a second node.

[0021] Figure 3 This is a flowchart of a memory write test method according to an embodiment of this application. Figure 3 As shown, the memory write test method includes the following steps: S100: Precharge the first bit line to the working voltage, keep the voltage of the second bit line at 0V, and connect the first bit line and the second bit line to the first transmission transistor and the second transmission transistor respectively; this step is the pre-charging process of the first bit line. In this embodiment, the first bit line is a BL line (Bit Line) and the second bit line is a BLB line (Bit Line Bar). S200: The first bit line is scanned from the working voltage to 0V, the voltage of the second node is 0V, the second transmission transistor is turned on, and a standard working voltage is applied to the second bit line and the first node respectively. The voltages of the first node and the second node are detected, and the first output voltage curve of the first node and the second node is recorded. The write state is determined according to the first output voltage curve. This step is the scan test process. In this embodiment, the value of the operating voltage can be selected as needed, such as being set to 1.2V~3.3V, but this application is not limited to this. The value of the operating voltage can be selected according to the process node of the memory, and different operating voltages can be selected for different process nodes. When the first bit line scans from the operating voltage to 0V, the scanning speed can be selected as needed, such as a scanning speed of 10mV / ms~100mV / ms. The numerical ranges listed here are only examples and are not intended to limit the scope of protection of this application.

[0022] By employing the memory write test method of this application, and through step-by-step testing of pre-charging and voltage scanning, the stored charge of the nodes inside the memory cell is evaluated, the working state of the memory cell is determined, and the node voltage flipping process is clearly captured, solving the technical problem in the prior art that the fitted curve does not test the successful flipping state. This application can accurately determine whether the memory cell write is successful through node voltage observation, and at the same time reflect the switching state of the inverter pull-up and pull-down circuits, providing a direct basis for memory cell performance verification. The test results of this application can guide the selection of memory cells for subsequent memory arrays, help screen out memory cells with qualified write performance and strong stability, provide technical reference for the design and optimization of large-scale array structures, and improve the overall circuit reliability.

[0023] In this embodiment, the memory is a static memory, or optionally, a static random access memory. Figure 1 This is a circuit diagram of a storage cell in a static memory. For example... Figure 1As shown, each storage cell of the static memory includes a first inverter, a second inverter, a first transfer transistor PG1, and a second transfer transistor PG2. The first inverter includes adjacent transistors with their gates connected together: transistor PL1 and transistor PD1. The second inverter includes adjacent transistors with their gates connected together: transistor PL2 and transistor PD2. Optionally, transistors PL1 and PL2 are PMOS transistors, and transistors PD1 and PD2 are NMOS transistors, but this application is not limited thereto. The output terminals of the first transfer transistor PG1 and the first inverter are connected to a first node N1, and the output terminals of the second transfer transistor PG2 and the second inverter are connected to a second node N2. Optionally, the source terminal of the first transfer transistor PG1 is connected to the output terminal of the first inverter, and the drain terminal of the first transfer transistor PG1 is connected to the first bit line BL. The source terminal of the second transfer transistor PG2 is connected to the output terminal of the second inverter, and the drain terminal of the second transfer transistor PG2 is connected to the second bit line BLB. Figure 1 The types and connections of the various components shown are merely examples and are not intended to limit the scope of protection of this application.

[0024] For a static memory cell consisting of six transistors, the method for testing successful writes is crucial. This method can clearly demonstrate the power supply test process of the bit line BL and the complementary bit line BLB by monitoring the potential changes of nodes N1 and N2, thereby clarifying the adjustment mechanism of the left first transfer transistor PG1 or the right second transfer transistor PG2 on the potential of nodes N1 and N2.

[0025] Optionally, this write margin testing method can be integrated into the WAT (Wafer Acceptance Test) process. By directly testing the write margin (first / second write margin) of the 6T-SRAM cells at the wafer level, it can quickly determine whether the write performance of the memory cells meets the design requirements, preventing unqualified wafers from flowing into subsequent packaging and reducing overall production costs. WAT refers to the comprehensive electrical testing of the test structure and chip cells on the wafer after all manufacturing processes are completed and before dicing and packaging. The purpose is to screen out qualified wafers, eliminate areas with process defects or substandard performance, and ensure that the yield and cost of subsequent packaging processes are controllable.

[0026] In this embodiment, before step S100—pre-charging the first bit line to the operating voltage and keeping the second bit line at 0V—the following steps are also included: Apply standard operating voltage to the word lines and power supply terminals respectively. For example... Figure 1As shown, the word line WL is connected to the gate of the first transmission transistor PG1 and the gate of the second transmission transistor PG2, respectively, and the power supply terminal Vdd is connected to the first inverter and the second inverter, respectively.

[0027] Figure 4 This is a schematic diagram of the BL high-level toggle obtained using the test method of this application. It shows the first output voltage curves of the first node N1 and the second node N2, where the blue curve represents the first output voltage curve of the first node N1 and the yellow curve represents the first output voltage curve of the second node N2. In this embodiment, the horizontal axis of the first output voltage curve corresponds to the voltage value of the first bit line, and the vertical axis corresponds to the voltage values ​​of the first node and the second node. Figure 4 As shown, in this embodiment, the voltage value of the first bit line corresponding to the intersection of the first output voltage curves of the first node and the second node is the first write margin. It can be seen from the inverted fitting curve that when the first bit line BL is low and the second bit line BLB is high, the output of the second node N2 is high, signifying the completion of writing "1". Therefore, this test method can intuitively quantify the write margin through the intersection of the output voltage curves, providing core data support for evaluating the stability of the memory cell.

[0028] In this embodiment, the memory writing method further includes the following steps: The second bit line is precharged to the working voltage, while the first bit line is kept at 0V. The second bit line is scanned from the operating voltage to 0V, the voltage of the first node is 0V, the first transmission transistor is turned on, and a standard operating voltage is applied to the first bit line and the second node respectively. The second output voltage curves of the first node and the second node are recorded, and the write state is determined based on the second output voltage curves. In this embodiment, the value of the operating voltage can be selected as needed, such as 1.2V~3.3V, but this application is not limited to this. The value of the operating voltage can be selected according to the process node of the memory, and different operating voltages can be selected for different process nodes. When the second bit line is scanned from the operating voltage to 0V, the scan speed can be selected as needed, such as 10mV / ms~100mV / ms. The numerical ranges listed here are only examples and are not intended to limit the scope of protection of this application.

[0029] Figure 5This is a schematic diagram of the BLB high-level toggle obtained using the test method of this application. It shows the second output voltage curves of the first node N1 and the second node N2, where the gray curve represents the second output voltage curve of the second node N2, and the orange curve represents the second output voltage curve of the first node N1. In this embodiment, the horizontal axis of the second output voltage curve corresponds to the voltage value of the second bit line, and the vertical axis corresponds to the voltage values ​​of the first node and the second node. Figure 5 As shown, in this embodiment, the voltage value of the second bit line corresponding to the intersection of the second output voltage curves of the first node and the second node is the second write margin. Simultaneously, when the first bit line BL in the fitted curve is high and the second bit line BLB is low, the second node N2 outputs a low level, signifying the completion of writing "0". Therefore, this test method can intuitively quantify the write margin through the intersection of the output voltage curves, providing core data support for evaluating the stability of the memory cell.

[0030] In 6T-SRAM write testing scenarios, write margin is a core quantitative parameter for measuring the write capability of a memory cell. Essentially, it represents the minimum voltage drive capability required for the bit line (BL / BLB) to successfully complete a "1" or "0" write, directly reflecting the stability and reliability of the write operation. This application solves the problem of existing technologies being unable to accurately assess node flip-flop effectiveness by quantifying write margin, providing a quantifiable performance indicator for memory cell selection and array structure optimization. By selecting cells with write margins that meet design thresholds, the overall write reliability of large-scale SRAM arrays can be significantly improved.

[0031] In summary, in this embodiment, the write margin test for 6T-SRAM adopts a two-stage scheme of T0 pre-charging and T1 voltage scanning: In T0, the standard operating voltage VDD is applied to the word line WL and the power supply terminal Vdd, while the first bit line BL and the second bit line BLB are alternately pre-charged (i.e., when the first bit line BL is connected to VDD, the second bit line BLB is connected to 0V, and vice versa); after entering T1, a differential test for writing "1" and writing "0" is performed: when writing "1", the left first bit line BL is scanned from the operating voltage VDD to 0V, the right second node N2 is connected to 0V to turn on the second transmission transistor PG2, and at the same time, the operating voltage VDD is applied to the second bit line BLB and the first node N1, and the second bit line PG2 is connected to 0V. The output amplifier (OA) acquires the voltage switching state of nodes N1 / N2. Using the first bit line voltage corresponding to the intersection of the two first output voltage curves as the write margin, a "1" is considered written successfully when the first bit line BL is low, the second bit line BLB is high, and the second node N2 outputs a high level. When writing a "0", the right second bit line BLB is scanned from the operating voltage VDD to 0V, and the left first node N1 is connected to 0V to turn on the first transmission transistor PG1. Simultaneously, the operating voltage VDD is applied to the first bit line BL and the second node N2. Similarly, the OA acquires the state of nodes N1 / N2, using the second bit line voltage corresponding to the curve intersection as the write margin. A "0" is considered written successfully when the first bit line BL is high, the second bit line BLB is low, and the second node N2 outputs a low level. The pre-charging step of the first bit line BL corresponds to the test for writing a "1", and the pre-charging step of the second bit line BLB corresponds to the test for writing a "0". The order of the first line BL pre-charging steps and the test steps for writing "1" is not important compared to the order of the second line BLB pre-charging steps and the test steps for writing "0". For example, you can first perform the first line BL pre-charging steps and the test steps for writing "1", and then perform the second line BLB pre-charging steps and the test steps for writing "0"; or you can first perform the second line BLB pre-charging steps and the test steps for writing "0", and then perform the first line BL pre-charging steps and the test steps for writing "1".

[0032] In summary, the memory write test method provided in this application has the following advantages: This application provides a method for testing the write state of a memory. Through step-by-step testing of pre-charge and voltage scanning, it clearly captures the node voltage flipping process, solving the technical problem in the prior art where the fitted curve does not test the successful flipping state. This application can accurately determine whether the memory cell write is successful by observing the node voltage, and at the same time reflects the switching state of the inverter pull-up and pull-down circuits, providing a direct basis for the performance verification of the memory cell. The test results of this application can guide the selection of memory cells for subsequent memory arrays, help screen out memory cells with qualified write performance and strong stability, provide technical reference for the design and optimization of large-scale array structures, and improve the reliability of the overall circuit.

[0033] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A memory write test method, characterized in that, Each storage cell of the memory includes a first inverter, a second inverter, a first transmission transistor, and a second transmission transistor. The output terminals of the first transmission transistor and the first inverter are connected to a first node, and the output terminals of the second transmission transistor and the second inverter are connected to a second node. The method includes the following steps: The first bit line is precharged to the working voltage, and the second bit line is kept at 0V. The first bit line and the second bit line are respectively connected to the first transmission transistor and the second transmission transistor. The first bit line is scanned from the operating voltage to 0V, the voltage of the second node is 0V, the second transmission transistor is turned on, and a standard operating voltage is applied to the second bit line and the first node respectively. The voltages of the first node and the second node are detected, and the first output voltage curve of the first node and the second node is recorded. The write state is determined based on the first output voltage curve.

2. The memory write test method according to claim 1, characterized in that, The horizontal axis of the first output voltage curve corresponds to the voltage value of the first bit line, and the vertical axis corresponds to the voltage values ​​of the first node and the second node.

3. The memory write test method according to claim 2, characterized in that, The voltage value of the first bit line corresponding to the intersection of the first output voltage curves of the first node and the second node is the first write margin.

4. The memory write test method according to claim 1, characterized in that, It also includes the following steps: The second bit line is precharged to the working voltage, while the first bit line is kept at 0V. The second bit line is scanned from the operating voltage to 0V, the voltage of the first node is 0V, the first transmission transistor is turned on, and at the same time, a standard operating voltage is applied to the first bit line and the second node respectively. The second output voltage curves of the first node and the second node are recorded, and the write state is determined according to the second output voltage curve.

5. The memory write test method according to claim 4, characterized in that, The horizontal axis of the second output voltage curve corresponds to the voltage value of the second bit line, and the vertical axis corresponds to the voltage values ​​of the first node and the second node.

6. The memory write test method according to claim 5, characterized in that, The voltage value of the second bit line corresponding to the intersection of the second output voltage curves of the first node and the second node is the second write margin.

7. The memory write test method according to claim 1, characterized in that, Before pre-charging the first bit line to the working voltage and keeping the second bit line at 0V, the following steps are also included: A standard operating voltage is applied to the word line and the power supply terminal, respectively. The word line is connected to the gate of the first transmission transistor and the gate of the second transmission transistor, respectively. The power supply terminal is connected to the first inverter and the second inverter, respectively.

8. The memory write test method according to claim 1, characterized in that, The source terminal of the first transmission transistor is connected to the output terminal of the first inverter, and the drain terminal of the first transmission transistor is connected to the first bit line. The source terminal of the second transmission transistor is connected to the output terminal of the second inverter, and the drain terminal of the second transmission transistor is connected to the second bit line.

9. The memory write test method according to claim 1, characterized in that, The memory is a static memory.

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