A front and back pre-locking frequency ring weighting power grid synchronization method and system based on DSOGI

Abstract

This invention provides a weighted grid synchronization method and system based on DSOGI with pre- and post-stage frequency-locked loops (FLLs), aiming to solve the problems of strong coupling between modules and poor adaptability to various operating conditions in traditional synchronization methods. First, this invention severs the direct signal association between the post-stage synchronous rotating coordinate system phase-locked loop (SRF-PLL) and the pre-stage DSOGI module, constructing a pre- and post-stage dual frequency-locked loop (FLL) architecture. Second, it dynamically adjusts the output weights of the dual FLLs through adaptive weighting coefficients: increasing the weight of the pre-stage FLL during frequency disturbances to improve dynamic response speed, and increasing the weight of the post-stage FLL during high harmonic distortion to improve steady-state synchronization accuracy. The weighted frequency is used as the resonant frequency of the DSOGI module to achieve precise synchronization control. Finally, the post-stage SRF-PLL outputs a stable synchronization phase angle. This invention avoids the coupling defects of traditional architectures and, combined with the performance advantages of dual FLLs, achieves a balance between dynamic tracking performance and steady-state synchronization accuracy under complex grid operating conditions.

Description

Technical Field

[0001] This invention relates to the field of power grid technology, and in particular to a weighted power grid synchronization method and system based on DSOGI with pre- and post-frequency locking loops. Background Technology

[0002] With the large-scale grid connection of distributed power electronic equipment such as new energy power generation (photovoltaic and wind power) and electric vehicle charging piles, the operating conditions of the power grid are becoming increasingly complex. Scenarios such as high harmonic interference, frequency mutations, and rapid load fluctuations occur frequently, placing stringent requirements on the dynamic response speed, harmonic interference resistance, and multi-condition adaptability of power grid frequency synchronization technology. As the core technology for grid-connected operation of power electronic equipment, the performance of frequency synchronization directly determines the stability, power quality, and operational reliability of the grid-connected system. Phase-locked loops (PLLs) are among the most widely used synchronization technologies due to their simplicity and robustness under certain grid fluctuations. In particular, the DSOGI-PLL, with its simple structure, filtering capability, and frequency adaptive characteristics, has gained widespread application. However, the resonant frequency tuning of the DSOGI depends on the frequency signal output by the SRF-PLL, while the phase locking of the SRF-PLL relies on the pure positive-sequence component extracted by the DSOGI. This strong coupling leads to the transmission of disturbances between modules. While this meets the requirements in ideal scenarios with balanced grid voltage and low harmonic content, the increasing complexity of grid conditions as more power electronic devices are connected to the grid, coupled with sudden frequency changes, causes the phase fluctuations of the SRF-PLL to directly affect the filtering characteristics of the DSOGI, resulting in a decrease in harmonic suppression capability. Furthermore, the filtering delay or harmonic interference of the DSOGI exacerbates the phase locking error of the SRF-PLL, creating a vicious cycle. In high-harmonic, dynamic switching scenarios, both dynamic and steady-state performance deteriorate significantly.

[0003] Fixed-frequency DSOGI-PLL (FF-DSOGI-PLL) significantly reduces computational complexity by eliminating the need to update the resonant frequency, while achieving greater bandwidth, better stability margin, and faster dynamic performance. However, if the fixed resonant frequency of the DSOGI is not equal to the actual grid frequency, the PLL's output frequency will contain ripple at twice the grid fundamental frequency. This second harmonic content is closely related to the PLL's bandwidth. If the PLL bandwidth is too large, the total harmonic distortion rate of the output reference signal will increase, leading to a deterioration in the current quality of the grid-connected converter; conversely, if the bandwidth is too small, the settling time will be prolonged, and transient performance will deteriorate.

[0004] To eliminate or reduce the negative impact of grid frequency fluctuations on FF-DSOGI-PLL without affecting PLL bandwidth, several solutions exist, including parallel frequency detector-based methods, phase error compensation methods, and PLL structure improvement methods. Among these, the parallel frequency detector method combines a frequency-locked loop (FLL) with the DSOGI-PLL, replacing the frequency feedback loop or fixed frequency with an additional frequency detector. This achieves decoupled control of the DSOGI and SRF-PLL and updates the resonant frequency based on grid operating conditions. However, a single FLL structure struggles to meet the demands of multiple operating conditions. While the front-end FLL offers fast dynamic response characteristics and can adapt to scenarios with high dynamic requirements such as load changes and frequency disturbances, its input signal is the raw signal without deep filtering. αβ The harmonics and noise contained in the signal can cause large steady-state fluctuations in frequency detection and weak anti-interference ability. The input signal of the post-FLL has excellent anti-harmonic ability and steady-state accuracy through multi-stage signal preprocessing, but due to signal transmission delay and the introduction of filtering stage, the dynamic response speed is slow and cannot meet the frequency tracking requirements when the operating conditions are changed quickly.

[0005] Currently, no effective solution has been proposed that can simultaneously address the synchronization issues of "coupling interference" and "difficulty in meeting the needs of multiple operating conditions." Some solutions attempt to optimize the PI parameters of the FLL or add filtering stages, but these only improve performance under a single operating condition and cannot adapt to complex scenarios where high harmonics and dynamic disturbances coexist. Other solutions employ a parallel structure of multiple FLLs, but without establishing an effective weighting mechanism and failing to resolve the coupling problem between modules, resulting in limited improvement in synchronization performance. Therefore, developing a grid synchronization method that can achieve decoupling between modules and adapt to the complex environment of the power grid has become a critical problem that urgently needs to be solved in the field of power electronics technology. Summary of the Invention

[0006] In view of this, the present invention provides a weighted power grid synchronization method and system based on DSOGI with pre- and post-positioned frequency-locked loops to solve the above problems.

[0007] This invention provides a weighted grid synchronization method based on DSOGI with pre- and post-positioned frequency-locked loops, comprising: acquiring grid voltage, and converting the three-phase voltage into a Clark transformation. αβ shaft voltage 、 The front and rear dual FLLs respectively target the aforementioned αβ shaft voltage 、 and the positive sequence voltage obtained through the DSOGI and PSC modules , Perform frequency tracking detection and output the front and rear frequencies. oh FLL_1, oh FLL_2 Based on the dynamic configuration of weighting coefficients according to the power grid operating conditions, the pre- and post-frequency values ​​are weighted and fused to output a weighted frequency. oh FLL The DSOGI module uses the weighted frequency as the resonant frequency for... αβ shaft voltage 、 The positive sequence voltage is filtered and extracted via PSC. , Transform it into Park transformation dq shaft voltage , ; will the q Shaft voltage input to SRF-PLL generates synchronous phase. i This is fed back to the Park transform.

[0008] In another implementation of the present invention, the front and rear dual FLLs respectively target the... αβ shaft voltage 、 and the positive sequence voltage obtained through the DSOGI and PSC modules , Perform frequency tracking detection and output the front and rear frequencies. oh FLL_1 , oh FLL_2 This includes: built-in DSOGI generation in the pre-fLL. αβ The pre-amplifier quadrature signal group of the axis voltage is used to obtain the phase angle error signal of the pre-amplifier FLL by combining the voltage error with the quadrature signal. The frequency error signal is obtained through calculation. oh 1. With respect to the given frequency value oh Adding 0s together gives the preamplifier frequency. oh FLL_1 In steady state, by controlling This achieves tracking and control of the power grid's base frequency signal; the built-in DSOGI in the post-FLL generates a post-orthogonal signal group of positive sequence voltage, and the phase angle error signal of the post-FLL is obtained by combining the positive sequence voltage error with the orthogonal signal. The frequency error signal is obtained through calculation. oh 2, with the given frequency value oh Adding 0s together gives the post-frequency. oh FLL_2 In steady state, by controlling To achieve tracking and control of the power grid's base frequency signal.

[0009] In another implementation of the present invention, the transfer functions of the built-in DSOGI in the pre- and post-FLLs are respectively:

[0010] in, 、 This is the in-phase signal in the preceding quadrature signal group. 、 These are the orthogonal signals in the preceding orthogonal signal group. k The damping coefficient is... oh FLL_1 This is the preamplifier frequency.

[0011]

[0012] in, v α2 、v β2 For the in-phase signal in the subsequent quadrature signal group, qv α2 、qv β2 These are the quadrature signals in the post-quadrature signal group. k is the damping coefficient.

[0013] In another implementation of the present invention, the weighted frequency is represented as: oh FLL = oh FLL_1 +(1- or ) oh FLL_2 in, or These are the weighting coefficients.

[0014] In another implementation of the invention, the weighting coefficient or Dynamic configuration based on power grid operating conditions includes: acquiring pre- and post-frequency sequences. oh 1( n ), oh 2( n ), n For each sampling point, a moving average filter is applied to obtain a smoothed frequency sequence. Based on the smoothed frequency sequence, the frequency mean is calculated. Frequency fluctuation standard deviation The fluctuation coefficient is obtained. And calculate its mean. According to the threshold T 1，2，3 By comparing the current power grid conditions, the current power grid operating status can be determined and dynamically adjusted. orValue: If the mean of the front and rear fluctuation coefficients Satisfies: T1 < < T2, then the power grid is mainly affected by frequency fluctuations. or As the value increases, the front-end FLL output is mainly used to ensure fast dynamic response; if ≥ T2 and > T3, then the harmonic distortion of the power grid is serious. or The value decreases, and the rear-end FLL output is mainly used to ensure steady-state accuracy and anti-interference ability.

[0015] In another implementation manner of the present invention, the transfer function of the DSOGI module with the weighted frequency as the resonant frequency is:

[0016] Wherein, 、 Is the in-phase signal in the DSOGI orthogonal signal group. 、 Is the quadrature signal in the DSOGI orthogonal signal group. k Is the damping coefficient. oh FLL Is the weighted resonant frequency.

[0017] In another implementation manner of the present invention, the dq Positive-sequence component in the coordinate system is expressed as:

[0018] Wherein, 、 Are respectively the positive-sequence d、q Axis components. i Is the grid synchronization phase output by the SRF-PLL module.

[0019] In another implementation manner of the present invention, the q Axis voltage component is input to the SRF-PLL, and the output synchronization phase i , which is fed back to the Park transformation, includes: Taking the positive-sequence q Axis voltage As the control target, the frequency deviation Is calculated through a PI controller; The actual angular frequency of the power grid is expressed as:

[0020] Wherein, Is the frequency given value. Is the frequency deviation output by the PLL; For ohIntegration yields the synchronization phase i The feedback is sent to the Park conversion module as the conversion angle to complete the grid synchronization.

[0021] Another aspect of the present invention provides a weighted power grid synchronization system based on DSOGI with pre- and post-positioned frequency-locked loops, comprising: a signal conversion module: acquiring the power grid voltage and converting it into a Clark transformation. αβ shaft voltage 、 Dual FLL frequency locking modules: respectively for αβ shaft voltage 、 and the positive sequence voltage obtained through the DSOGI and PSC modules , Perform frequency tracking detection and output the front and rear frequencies. oh FLL_1 , oh FLL_2 Weighted frequency modulation module: Based on the power grid operating conditions, dynamically configure weighting coefficients, perform weighted fusion of the pre- and post-frequency modulation, and output the weighted frequency. oh FLL DSOGI filter module: uses the weighted frequency as the resonant frequency for... αβ shaft voltage 、 The positive sequence voltage is filtered and extracted via PSC. , It is converted to Park transformation dq shaft voltage , SRF-PLL module: q Using shaft voltage as input, synchronous phase is generated. i This is fed back to the Park transform.

[0022] In another aspect, the present invention provides an electronic device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of a DSOGI-based pre- and post-frequency-locked loop weighted power grid synchronization method as described in any of the preceding claims. In another aspect, the present invention provides a computer storage medium storing a computer program that, when executed by a processor, implements the steps of a DSOGI-based weighted grid synchronization method with pre- and post-frequency-locked loops as described in any of the preceding claims.

[0023] The present invention provides a weighted grid synchronization method based on DSOGI with pre- and post-stage frequency-locked loops. This method severs the direct signal association between the SRF-PLL and the pre-stage DSOGI, making them completely independent and avoiding interference transmission between modules. This effectively solves the vicious cycle problem of coupling in traditional solutions. By using a parallel architecture of pre- and post-stage dual FLLs and an adaptive weighting mechanism, combining the fast dynamic response advantage of the pre-stage FLL with the strong anti-interference advantage of the post-stage FLL, the weights can be dynamically adjusted according to the grid operating conditions (frequency fluctuations / harmonic distortion) to achieve a precise balance between "fast response" and "high stability," adapting to the complex grid scenarios brought about by the integration of new energy sources. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. By reading the detailed description of the embodiments below, the advantages and benefits of the solutions will become clear to those skilled in the art. The accompanying drawings are only for illustrating preferred embodiments and are not intended to limit the present invention. In the accompanying drawings: Figure 1 This is a schematic diagram of a weighted power grid synchronization method based on pre- and post-frequency locking loops according to an embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram of the control structure of the pre-FLL according to an embodiment of the present invention.

[0026] Figure 3 This is a schematic diagram comparing the operating performance of a pre- and post-FLL according to an embodiment of the present invention.

[0027] Figure 4 This is a schematic diagram of the pre- and post-FLL weighted structure according to an embodiment of the present invention.

[0028] Figure 5 This is a schematic diagram of the DSOGI and PSC module structure according to an embodiment of the present invention. Detailed Implementation

[0029] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art should fall within the protection scope of the present invention.

[0030] Figure 1 This is a schematic diagram of a weighted power grid synchronization method based on DSOGI with pre- and post-positioned frequency-locked loops, provided as an embodiment of the present invention. Figure 1As shown, this embodiment mainly includes: S101. Acquire the three-phase power grid voltage and convert it to Clark voltage using a Clark converter. αβ Axis voltage component.

[0031] For example, voltage sensors are used to collect the three-phase voltage signals of the power grid (phases A, B, and C). 、 、 This ensures the accuracy and real-time performance of signal acquisition. The acquired three-phase grid voltage is converted to... αβ In coordinate system:

[0032] in, 、 They are respectively α、β shaft voltage, 、 、 These are the three-phase voltages, A, B, and C, respectively.

[0033] The coupling relationship of the three-phase voltages is eliminated, which facilitates subsequent filtering and frequency detection.

[0034] S102, the front and rear dual FLLs respectively for the αβ shaft voltage 、 and the positive sequence voltage obtained through the DSOGI and PSC modules , Perform frequency tracking detection and output the front and rear frequencies. oh FLL_1 , oh FLL_2 .

[0035] For example, such as Figure 2 As shown, the pre-FLL will 、 Input the built-in DSOGI to generate two sets of quadrature signals (in-phase signals). 、 and quadrature signals 、 The FLL phase angle error signal is obtained from the voltage error signal and the quadrature signal. The control signal is achieved by using an integrator with a negative gain coefficient –γ to control the resonant frequency. oh FLL_1The negative feedback. The normalized value of the FLL gain can be a fixed voltage amplitude, etc., based on the grid frequency. oh 0 is used as a feedforward term to accelerate the transient process, ultimately making Output signal oh FLL_1 The frequency is equal to the input signal frequency, thus achieving frequency locking. The pre-amplifier FLL uses the original... αβ With the shaft signal as input, it can quickly capture sudden changes in power grid frequency, overcoming the shortcomings of traditional solutions that are slow to respond under frequency disturbance conditions.

[0036] Rear FLL , Input the built-in DSOGI to generate two sets of quadrature signals (in-phase signals). 、 and quadrature signals 、 The post-FLL phase angle error signal is obtained based on the voltage error signal and the quadrature signal. As a control signal, the output frequency is determined using the same frequency tracking mechanism as the pre-amplifier FLL. Applying a post-filtered FLL to the positive sequence signal can significantly improve the steady-state accuracy and harmonic rejection capability of frequency detection.

[0037] Depend on Figure 3 It can be seen that the dynamic response of the pre-amplifier FLL is equivalent to the first-order response, with no overshoot, and its dynamic performance is better than that of the post-amplifier FLL, but its anti-interference ability is weaker; the post-amplifier FLL has better anti-interference ability and steady-state accuracy than the pre-amplifier FLL because the signal is purified, but its dynamic response is slightly slower.

[0038] S103. Based on the dynamic configuration of weighting coefficients according to the power grid operating conditions, the pre- and post-frequency values ​​are weighted and fused to output the weighted frequency. oh FLL .

[0039] For example, such as Figure 4 As shown, with the previous frequency oh FLL_1 and rear frequency oh FLL_2 As input, the power grid operating condition is determined by the mean of the frequency fluctuation coefficient, and weighting coefficients are dynamically configured. or With 1- or The pre- and post-frequency values ​​are weighted and the weighted frequency is output. oh FLL The frequency is fed back to the DSOGI module as the resonant frequency. Through dynamic weighting, the fast response of the pre-FLL and the high anti-interference performance of the post-FLL are complemented, solving the problem that traditional solutions cannot simultaneously achieve both dynamic response and anti-harmonic performance.

[0040] S104 and DSOGI modules use the weighted frequency as the resonant frequency for... αβ shaft voltage 、 The positive sequence voltage is filtered and extracted via PSC. , Transform it into Park transformation dq shaft voltage , .

[0041] For example, such as Figure 5 As shown, the DSOGI module uses the weighted frequency output by the weighting module as the resonant frequency to filter the input voltage component. αβ The axis voltage components generate two sets of quadrature signals (in-phase signals) through the resonant characteristics of DSOGI. 、 、 ). With the signal αβ Positive sequence components under the axis , :

[0042] It effectively filters out the negative sequence component and some harmonics in the grid voltage, providing the positive sequence extracted signal for the subsequent FLL, thus solving the problem of low synchronization accuracy in high harmonic conditions of traditional solutions.

[0043] The positive-order components are then transformed using the Park transform to... dq In the rotated coordinate system, we obtain , .

[0044] S105, The ascending order q Shaft voltage input to SRF-PLL generates synchronous phase. i This is fed back to the Park transform.

[0045] For example, the SRF-PLL module uses To achieve the control objective, the frequency deviation is calculated using a PI controller. Synthetic power grid actual angular frequency oh ,right oh Integrating to obtain the grid synchronization phase i This is fed back to the Park transformation module as the transformation angle, forming a closed-loop synchronous control.

[0046] The present invention provides a weighted grid synchronization method based on DSOGI with pre- and post-stage frequency-locked loops. This method severs the direct signal association between the SRF-PLL and the pre-stage DSOGI, making them completely independent and avoiding interference transmission between modules. This effectively solves the vicious cycle problem of coupling in traditional solutions. By using a parallel architecture of pre- and post-stage dual FLLs and an adaptive weighting mechanism, combining the fast dynamic response advantage of the pre-stage FLL with the strong anti-interference advantage of the post-stage FLL, the weights can be dynamically adjusted according to the grid operating conditions (frequency fluctuations / harmonic distortion) to achieve a precise balance between "fast response" and "high stability," adapting to the complex grid scenarios brought about by the integration of new energy sources. In another implementation of the present invention, the front and rear dual FLLs respectively target the... αβ shaft voltage 、 and the positive sequence voltage obtained through the DSOGI and PSC modules , Perform frequency tracking detection and output the front and rear frequencies. oh FLL_1 , oh FLL_2 This includes: built-in DSOGI generation in the pre-fLL. αβ The pre-amplifier quadrature signal group of the axis voltage is used to obtain the phase angle error signal of the pre-amplifier FLL by combining the voltage error with the quadrature signal. The frequency error signal is obtained through calculation. oh 1. With respect to the given frequency value oh Adding 0s together gives the preamplifier frequency. oh FLL_1 In steady state, by controlling This enables tracking and control of the power grid's baseband signal. The built-in DSOGI in the post-FLL generates a post-orthogonal signal group of positive-sequence voltages. The phase angle error signal of the post-FLL is obtained by combining the positive-sequence voltage error with the orthogonal signals. The frequency error signal is obtained through calculation. oh 2, with the given frequency value oh Adding 0s together gives the post-frequency. oh FLL_2 In steady state, by controlling To achieve tracking and control of the power grid's base frequency signal.

[0047] In another implementation of the present invention, the transfer function of the built-in DSOGI in the pre-FLL is:

[0048] in, 、 This is the in-phase signal in the preceding quadrature signal group. 、 These are the orthogonal signals in the preceding orthogonal signal group. k The damping coefficient is... oh FLL_1 This is the preamplifier frequency.

[0049] Phase angle error signal of the pre-FLL:

[0050] in, This is the phase angle error signal of the pre-fLL. , They are respectively α、β The voltage deviation signal of the shaft.

[0051] The frequency error signal obtained through calculation Adding this to the given frequency value yields the pre-frequency:

[0052] in, Given a frequency value, This is the frequency error signal of the pre-fLL; control in steady state. To achieve real-time tracking of the power grid's base frequency signal.

[0053] The transfer function of the built-in DSOGI in the post-FLL is:

[0054] in, v α2 、v β2 For the in-phase signal in the subsequent quadrature signal group, qv α2 、qv β2 These are the quadrature signals in the post-quadrature signal group. k The damping coefficient is... oh FLL_2 This is the rear frequency.

[0055] Phase angle error signal of the post-FLL:

[0056] in, e f2 This is the post-FLL phase angle error signal. , They are respectively α、β Voltage error signal of the positive sequence component of the axis.

[0057] The frequency error signal obtained after operation is added to the frequency set value to obtain the post-frequency:

[0058] Wherein, oh 0 is the frequency set value, oh 2 is the frequency error signal of the post-FLL. At steady state, by controlling e f2 = 0, the real-time tracking and control of the power grid fundamental frequency signal are realized.

[0059] In another implementation manner of the present invention, the weighted frequency is expressed as: oh FLL = oh FLL_1 + (1 - or ) oh FLL_2 Wherein, or is the weight coefficient, oh FLL_1 is the pre-frequency, oh FLL_2 is the post-frequency.

[0060] In another implementation manner of the present invention, the weight coefficient or is dynamically configured according to the power grid conditions, including: obtaining the pre-frequency and post-frequency sequences oh 1( n ), oh 2( n ), n is the sampling point, and respectively performing moving average filtering processing to obtain the corresponding smoothed frequency sequences. Based on the smoothed frequency sequences, respectively calculate the frequency mean and the frequency fluctuation standard deviation , obtain the fluctuation coefficient , and calculate its mean . According to the comparison with the threshold T 1，2，3 , judge the current power grid conditions and dynamically adjust the or value: If the pre-frequency and post-frequency fluctuation coefficient means satisfy: T1 < < T2, then the power grid is mainly dominated by frequency fluctuations, or takes a larger value, and mainly uses the output of the pre-FLL to ensure fast dynamic response; if ≥ T2 and > T3, then the power grid has serious harmonic distortion, or takes a smaller value, and mainly uses the output of the post-FLL to ensure steady-state accuracy and anti-interference ability.

[0061] Exemplarily, obtain the pre - and post - frequency sequences oh 1( n )、 oh 2( n ), where n are sampling points. Perform moving average filtering processing respectively, M is the moving window length, and obtain the corresponding smoothed frequency sequences:

[0062] Based on the smoothed frequency sequences, calculate the frequency mean and the standard deviation of frequency fluctuation :

[0063]

[0064] where, N is the total number of sampling points in the analysis window.

[0065] Obtain the fluctuation coefficient , and calculate the mean value of the fluctuation coefficient :

[0066] According to the comparison with the threshold T 1，2，3 , judge the current grid condition and dynamically adjust the or value: If the mean values of the pre - and post - fluctuation coefficients satisfy: T1 < < T2, then the grid is mainly dominated by frequency fluctuation, or the value increases, and the pre - FLL output is mainly used to ensure fast dynamic response; if ≥ T2 and > T3, then the grid has serious harmonic distortion, or the value decreases, and the post - FLL output is mainly used to ensure steady - state accuracy and anti - interference ability.

[0067] In another implementation manner of the present invention, the transfer function of the DSOGI module with the weighted frequency as the resonant frequency is:

[0068] where, 、 is the in - phase signal in the DSOGI orthogonal signal group, 、 is the quadrature signal in the DSOGI orthogonal signal group, k is the damping coefficient, oh FLL is the weighted resonant frequency.

[0069] In another implementation of the present invention, the dq The voltage component in the coordinate system is represented as:

[0070] in, , They are in ascending order. d、q Axis voltage components, i This refers to the grid synchronization phase output by the SRF-PLL module.

[0071] In another implementation of the present invention, the... q The shaft voltage component is input to the SRF-PLL module, and the output is a synchronous phase. i To achieve grid synchronization, including: Ascending order q Axis component input to SRF-PLL module, to To achieve the control objective, the frequency deviation is calculated using a PI controller. ; The actual angular frequency of the power grid is expressed as:

[0072] in, Given a frequency value, This refers to the frequency deviation of the PLL output. right oh Integration yields the synchronization phase i The feedback is sent to the Park conversion module as the conversion angle to complete the grid synchronization.

[0073] By decoupling the SRF-PLL and DSOGI modules, a front-end and rear-end dual FLL parallel architecture is constructed. By utilizing an adaptive weighting mechanism to combine the performance advantages of both, accurate synchronization under complex working conditions is achieved.

[0074] Another aspect of the present invention provides a DSOGI-based weighted grid synchronization system with pre- and post-positioned frequency-locked loops, comprising: Signal conversion module: Acquires grid voltage and converts it to Clark voltage. αβ shaft voltage 、 ; Dual FLL frequency locking module: respectively for αβ shaft voltage 、 and the positive sequence voltage obtained through the DSOGI and PSC modules , Perform frequency tracking detection and output the front and rear frequencies. ohFLL_1 , oh FLL_2 ; Weighted frequency modulation module: Based on the power grid operating conditions, dynamically configure weighting coefficients, perform weighted fusion of the preceding and following frequencies, and output the weighted frequency. oh FLL ; DSOGI filter module: uses the weighted frequency as the resonant frequency, for αβ shaft voltage 、 The positive sequence voltage is filtered and extracted via PSC. , It is converted to Park transformation dq shaft voltage , ; SRF-PLL module: q Using shaft voltage as input, synchronous phase is generated. i This is fed back to the Park transform.

[0075] Each module has a clear functional boundary, and the front and back stages can be debugged independently, reducing debugging difficulty; moreover, there is no need to modify the hardware structure, and it can be directly integrated into the existing grid-connected converter control algorithm, resulting in low engineering implementation cost and strong adaptability.

[0076] The present invention relates to a DSOGI-based pre- and post-dual frequency-locked loop weighted grid synchronization system, which severs the direct signal association between the SRF-PLL and the pre-dual DSOGI, making them completely independent and avoiding interference transmission between modules, effectively solving the vicious cycle problem of coupling in traditional solutions. Through a pre- and post-dual dual FLL parallel architecture and an adaptive weighting mechanism, combining the fast dynamic response advantage of the pre-dual FLL with the strong anti-interference advantage of the post-dual FLL, the weights can be dynamically adjusted according to the grid operating conditions (frequency fluctuations / harmonic distortion) to achieve a balance between "fast response" and "high stability", adapting to the complex grid scenarios brought about by the integration of new energy sources. In another aspect of the present invention, the electronic device includes: a processor, a memory, and a communication bus and a communication interface.

[0077] in: The processor, memory, and communication interface communicate with each other via a communication bus.

[0078] A communication interface is used to communicate with other electronic devices or servers.

[0079] The processor is used to execute programs, specifically the steps of any of the DSOGI-based weighted grid synchronization methods described in the above embodiments.

[0080] Specifically, the program may include program code, which includes computer operation instructions.

[0081] The processor may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. The one or more processors included in the smart device may be processors of the same type, such as one or more CPUs; or they may be processors of different types, such as one or more CPUs and one or more ASICs.

[0082] Memory is used to store programs. Memory may include high-speed RAM, and may also include non-volatile memory, such as at least one disk drive.

[0083] Specifically, the program can be used to cause the processor to execute the steps of any of the DSOGI-based pre- and post-positioned frequency-locked loop weighted power grid synchronization methods described in the embodiments. The specific implementation of each step in the program can be found in the corresponding descriptions of the steps and units executed in any of the DSOGI-based pre- and post-positioned frequency-locked loop weighted power grid synchronization methods described above, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments.

[0084] An exemplary embodiment of this application also provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods of various embodiments of this application.

[0085] The methods described above according to embodiments of the present invention can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code originally stored on a remote recording medium or a non-transitory machine-readable medium and subsequently stored on a local recording medium, downloaded via a network. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the methods shown herein.

[0086] Specific embodiments of the present invention have now been described. Other embodiments are within the scope of the appended claims. In some cases, the actions described in the claims can be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result.

[0087] It should be noted that all directional indications (such as up, down, left, right, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship between the components in a certain specific order (as shown in the figure). If the specific order changes, the directional indication will also change accordingly.

[0088] In the description of this invention, the terms "first" and "second" are used only for convenience in describing different components or names, and should not be construed as indicating or implying a sequential relationship, relative importance, or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" and "second" may explicitly or implicitly include at least one of that feature.

[0089] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0090] It should be noted that although specific embodiments of the present invention have been described in detail with reference to the accompanying drawings, this should not be construed as limiting the scope of protection of the present invention. Various modifications and variations that can be made by those skilled in the art without inventive effort within the scope described in the claims still fall within the scope of protection of the present invention.

[0091] The examples of the embodiments of the present invention are intended to concisely illustrate the technical features of the embodiments of the present invention, so that those skilled in the art can intuitively understand the technical features of the embodiments of the present invention, and are not intended to be an improper limitation of the embodiments of the present invention.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A weighted power grid synchronization method based on DSOGI with pre- and post-positioned frequency-locked loops, characterized in that, include: The grid voltage is collected and converted into three-phase voltage using Clark transformation. αβ shaft voltage 、 ; The front and rear dual FLLs respectively for the αβ shaft voltage 、 and the positive sequence voltage obtained through the DSOGI and PSC modules , Perform frequency tracking detection and output the front and rear frequencies. ω FLL_1 , ω FLL_2 ; Based on the dynamic configuration of weighting coefficients according to power grid operating conditions, the preceding and following frequencies are weighted and fused to output a weighted frequency. ω FLL ; The DSOGI module uses the weighted frequency as its resonant frequency. αβ shaft voltage 、 The positive sequence voltage is filtered and extracted via PSC. , Transform it into Park transformation dq shaft voltage , ; The q Shaft voltage input to SRF-PLL generates synchronous phase. θ This is fed back to the Park transform.

2. The method according to claim 1, characterized in that, The front and rear dual FLLs respectively... αβ shaft voltage 、 and the positive sequence voltage obtained through the DSOGI and PSC modules , Perform frequency tracking detection and output the front and rear frequencies. ω FLL_1 , ω FLL_2 ,include: Built-in DSOGI generation in the pre-FLL αβ The pre-amplifier quadrature signal group of the axis voltage is used to obtain the phase angle error signal of the pre-amplifier FLL by combining the voltage error with the quadrature signal. The frequency error signal is obtained through calculation. ω 1. With respect to the given frequency value ω Adding 0s together gives the preamplifier frequency. ω FLL_1 ; The built-in DSOGI in the post-FLL generates a post-orthogonal signal group of positive sequence voltages. The phase angle error signal of the post-FLL is obtained by combining the positive sequence voltage error with the orthogonal signals. The frequency error signal is obtained through calculation. ω 2, with the given frequency value ω Adding 0s together gives the post-frequency. ω FLL_2 ; In steady state, control , To achieve tracking and control of the power grid's base frequency signal.

3. The method according to claim 2, characterized in that, The transfer functions of the built-in DSOGI in the pre- and post-FLL are as follows: in, 、 This is the in-phase signal in the preceding quadrature signal group. 、 These are the orthogonal signals in the preceding orthogonal signal group. k The damping coefficient; in, v α2 、v β2 For the in-phase signal in the subsequent quadrature signal group, qv α2 ,qv β2 These are the quadrature signals in the post-quadrature signal group. k is the damping coefficient.

4. The method according to claim 2, characterized in that, The weighted frequency is calculated as follows: ω FLL = ηω FLL_1 +(1- η ) ω FLL_2 in, η These are the weighting coefficients.

5. The method according to claim 4, characterized in that, The weighting coefficient η Dynamic configuration based on power grid operating conditions, including: Obtain the pre- and post-frequency sequences ω 1( n ), ω 2( n ), n For each sampling point, a moving average filter is applied to obtain a smoothed frequency sequence. Based on the smoothed frequency sequence, the frequency mean is calculated. Frequency fluctuation standard deviation The fluctuation coefficient is obtained. And calculate its mean. According to the threshold T 1，2，3 By comparing the current power grid conditions, the current power grid operating status can be determined and dynamically adjusted. η value: If the mean values of the front and rear fluctuation coefficients satisfy: T1 < < T2, then the power grid is mainly dominated by frequency fluctuations, η as the value increases, the front FLL output is mainly used to ensure fast dynamic response; like ≥T2 and If the value is greater than T3, then the power grid harmonic distortion is severe. η The value is reduced, and the post-FLL output is mainly used to ensure steady-state accuracy and anti-interference capability.

6. The method according to claim 1, characterized in that, The transfer function of the DSOGI module filter with the weighted frequency as the resonant frequency is: in, 、 The in-phase signal in the DSOGI quadrature signal group. 、 These are the orthogonal signals in the DSOGI orthogonal signal group. k The damping coefficient is... ω FLL This is the weighted resonant frequency.

7. The method according to claim 1, characterized in that, The q Shaft voltage input SRF-PLL, output synchronous phase θ Feedback to the Park transformation includes: In ascending order q shaft voltage To achieve the control objective, the frequency deviation is calculated using a PI controller. ; The actual angular frequency of the power grid is expressed as: in, Given a frequency value, This refers to the frequency deviation of the PLL output. right ω Integration yields the synchronization phase θ The feedback is sent to the Park conversion module as the conversion angle to complete the grid synchronization.

8. A weighted power grid synchronization system based on DSOGI with pre- and post-positioned frequency-locked loops, characterized in that, include: Signal conversion module: Acquires grid voltage and converts it to Clark voltage. αβ shaft voltage 、 ; Dual FLL frequency locking module: respectively for αβ shaft voltage 、 and the positive sequence voltage obtained through the DSOGI and PSC modules , Perform frequency tracking detection and output the front and rear frequencies. ω FLL_1 , ω FLL_2 ; Weighted frequency modulation module: Based on the power grid operating conditions, dynamically configure weighting coefficients, perform weighted fusion of the preceding and following frequencies, and output the weighted frequency. ω FLL ; DSOGI filter module: uses the weighted frequency as the resonant frequency, for αβ shaft voltage 、 The positive sequence voltage is filtered and extracted via PSC. , It is converted to Park transformation dq shaft voltage , ; SRF-PLL module: q Using shaft voltage as input, synchronous phase is generated. θ This is fed back to the Park transform.

9. An electronic device, characterized in that, include: The memory, the processor, and the computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the DSOGI-based pre- and post-frequency-locked loop weighted power grid synchronization method as described in any one of claims 1 to 7.

10. A computer storage medium, characterized in that, The computer storage medium stores a computer program, which, when executed by a processor, implements the steps in the DSOGI-based weighted grid synchronization method with pre- and post-frequency locking loops as described in any one of claims 1 to 7.

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