Voltage conversion circuit and DCDC converter

Abstract

This disclosure provides a voltage conversion circuit and a DC-DC converter, relating to the field of semiconductor technology. The voltage conversion circuit includes: a voltage conversion module comprising a power inductor and an output capacitor, wherein the power inductor outputs an output voltage generated based on the input voltage; a judgment module configured to output a first indication signal to the voltage conversion module upon receiving a power-down enable signal, indicating that the voltage conversion module performs a power-down or switches from an operating mode to a power-down mode; and a feedback selection module configured to receive the node voltage of a switching node, and, upon receiving the power-down enable signal, adjust the feedback voltage of the node voltage fed back to the voltage conversion module, wherein the adjusted feedback voltage is used to set the current valley value of the power inductor to a first preset value, causing the power inductor to generate a negative inductor current to draw charge from the output capacitor. This technical solution improves the problem of the output voltage remaining high and unable to be reset under hard power-down conditions in voltage conversion circuits.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a voltage conversion circuit and a DC-DC converter. Background Technology

[0002] In DC-DC converters using the COT (Constant On-Time) architecture, the circuit operates in DCM (Discontinuous Conduction Mode). For example, under no-load conditions, the circuit performs a power-down operation, and the output energy is stored in the output capacitor. However, since the no-load load consumes almost no energy, the output voltage remains high, which interferes with the normal startup or logic judgment of the back-end circuit, thus affecting the function of the DC-DC converter.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a voltage conversion circuit and a DC-DC converter, which at least to some extent overcomes the problem in the related art that the output voltage of the voltage converter remains high and cannot be lowered when a power-down operation is performed.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a voltage conversion circuit is provided, comprising: a voltage conversion module including a power inductor and an output capacitor, one end of the power inductor being connected to a switching node, and the other end of the power inductor being connected to the output capacitor to output an output voltage generated based on an input voltage; a judgment module connected to the voltage conversion module, configured to output a first indication signal to the voltage conversion module when a power-down enable signal is received, the first indication signal being used to instruct the voltage conversion module to perform a power-down, or to instruct the voltage conversion module to switch from an operating mode to a power-down mode; and a feedback selection module connected to the voltage conversion module, configured to receive the node voltage of the switching node, and, when the power-down enable signal is received, to adjust the feedback voltage (REF_SW_FB) of the node voltage fed back to the voltage conversion module, the adjusted feedback voltage being used to set the current valley value of the power inductor to a first preset value, causing the power inductor to generate a negative inductor current to draw charge from the output capacitor.

[0007] In one embodiment of this disclosure, it further includes: a main control module, connected to the judgment module and the feedback selection module, configured to output the power-down enable signal when the power-down operation is triggered.

[0008] In one embodiment of this disclosure, the main control module is connected to the voltage conversion module to output the power-down enable signal when it receives an error identification signal from the voltage conversion module; and / or the main control module outputs the power-down enable signal when it receives a power-down command.

[0009] In one embodiment of this disclosure, the voltage conversion module further includes: a zero-crossing detection comparator, including a first comparison terminal, a second comparison terminal, and a first output terminal. The first comparison terminal is connected to a zero-crossing detection reference voltage, and the second comparison terminal is connected to the feedback voltage. When the feedback voltage reaches the reference voltage, the first output terminal outputs a zero-crossing detection pulse signal. The voltage division coefficient of the feedback selection module is inversely proportional to the current valley value of the power inductor. When the power-down enable signal is not connected, the feedback selection module outputs the feedback voltage corresponding to the first voltage division coefficient, and the current valley value corresponding to the first voltage division coefficient is close to zero. When the power-down enable signal is connected, the feedback selection module outputs the feedback voltage corresponding to the second voltage division coefficient, where the first voltage division coefficient is greater than the second voltage division coefficient. Based on the inverse relationship, the current valley value corresponding to the second voltage division coefficient becomes a first preset value, causing the power inductor to generate the negative inductor current.

[0010] In one embodiment of this disclosure, the voltage conversion module further includes: a first power transistor and a second power transistor connected in series between the input voltage and ground, wherein the common connection point of the first power transistor and the second power transistor is the switching node, and when the first power transistor is off and the second power transistor is on, the node voltage is determined based on the power inductor.

[0011] In one embodiment of this disclosure, the determination module is further configured to provide a PWM drive signal to the voltage conversion module in the operating mode and a PWM power-down drive signal to the voltage conversion module in the power-down mode. The PWM power-down drive signal is generated based on the PWM drive signal and the zero-crossing detection pulse signal, so that the output capacitor discharges charge in the power-down mode.

[0012] In one embodiment of this disclosure, the voltage conversion module further includes: a logic controller configured to access the PWM drive signal in the operating mode to output a first set of on / off signals to the first power transistor and the second power transistor, and to access the PWM power-down drive signal in the power-down mode to output a second set of on / off signals to the first power transistor and the second power transistor, wherein the first set of on / off signals is used to indicate that the first power transistor and the second power transistor are switched on and off intermittently, and the second set of on / off signals is used to indicate that the first power transistor and the second power transistor are switched on and off continuously.

[0013] In one embodiment of this disclosure, the voltage conversion module further includes a PWM comparator, comprising a third comparison terminal, a fourth comparison terminal, and a second output terminal. The third comparison terminal is used to receive an error amplification signal, the fourth comparison terminal is used to receive a carrier signal, and the second output terminal is used to output the PWM drive signal. The error amplification signal is determined based on the output voltage. In the operating mode, the logic controller receives the PWM drive signal from the judgment module, and in the power-down mode, it receives the PWM power-down drive signal from the judgment module.

[0014] In one embodiment of this disclosure, the determination module includes a first input terminal, a second input terminal, a third input terminal, and a third output terminal. The first input terminal is used to connect to the power-down enable signal, the second input terminal is used to connect to the zero-crossing detection pulse signal, the third input terminal is used to connect to the PWM drive signal, and the third output terminal is used to connect to the PWM drive signal in the operating mode and to connect to the PWM power-down drive signal in the power-down mode.

[0015] In one embodiment of this disclosure, the determination module includes: a first NOR gate, wherein the two inputs of the first NOR gate are respectively used as the second input and the third input; a first NOT gate and a second NOT gate, wherein the inputs of the first NOT gate and the second NOT gate are respectively used as the first input; a second NOR gate, wherein the two inputs of the second NOR gate are respectively connected to the output of the first NOR gate and the output of the first NOT gate; an AND gate, wherein one input of the AND gate is used as the third input and the other input of the AND gate is connected to the output of the second NOT gate; and an OR gate, wherein the two inputs of the OR gate are respectively connected to the output of the second NOR gate and the output of the AND gate, and the output of the OR gate is used as the third output.

[0016] In one embodiment of this disclosure, the feedback selection module includes: a first voltage divider resistor, a second voltage divider resistor, and a third voltage divider resistor connected in series. The first voltage divider resistor is connected to the switching node, and the third voltage divider resistor is grounded. There is a first voltage divider point between the first voltage divider resistor and the second voltage divider resistor, and a second voltage divider point between the second voltage divider resistor and the third voltage divider resistor. A multiplexer has a fourth input terminal, a fifth input terminal, a sixth input terminal, and a fourth output terminal. The fourth input terminal is connected to the main control module, the fifth input terminal is connected to the first voltage divider point, the sixth input terminal is connected to the second voltage divider point, and the fourth output terminal is connected to the second comparison terminal. If the power-down enable signal is not connected, the voltage of the first voltage divider point is selected as the feedback voltage; if the power-down enable signal is connected, the voltage of the second voltage divider point is selected as the feedback voltage.

[0017] In one embodiment of this disclosure, the voltage conversion module further includes: an on-time timer connected to the logic controller and configured to control the on-time of the first power transistor in the operating mode.

[0018] In one embodiment of this disclosure, the error identification signal is generated when the input voltage is lower than an input threshold and / or abnormal power consumption is detected.

[0019] In one embodiment of this disclosure, the operating mode is an intermittent conduction mode.

[0020] According to another aspect of this disclosure, a DC-DC converter is provided, comprising: the voltage conversion circuit provided in the above embodiments.

[0021] The voltage conversion circuit provided in the embodiments of this disclosure, through the coordinated interaction of the judgment module, the feedback selection module, and the voltage conversion module, responds when the power-down enable signal DISCHARGE_EN is valid. The feedback selection module adjusts the feedback voltage REF_SW_FB of the switching node SW, actively setting the current valley value of the power inductor from a near-zero operating mode threshold to a first preset value, creating conditions for the generation of negative inductor current. Simultaneously, after receiving the enable signal, the judgment module DISCHARGE_LOGIC switches the circuit from operating mode to power-down mode, making the switching cycle dominated by the zero-crossing detection signal ZCD_OUT, converting the intermittent switching mode into a continuous switching mode. Under this coordinated mechanism, the voltage conversion circuit can still actively and controllably extract charge from the output capacitor using negative inductor current in scenarios without external discharge loads, such as no-load or light-load conditions. This improves the phenomenon of the output voltage remaining high and unable to reset under hard power-down mode, thereby achieving a safe and reliable soft-stop power-down effect.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0024] Figure 1 A schematic block diagram of a voltage conversion circuit according to an embodiment of the present disclosure is shown; Figure 2 A schematic circuit diagram of a voltage conversion circuit according to an embodiment of the present disclosure is shown; Figure 3 A graph showing a set of signals in a voltage conversion circuit according to an embodiment of this disclosure is provided. Figure 4 A schematic circuit diagram of a power-down control module according to an embodiment of the present disclosure is shown; Figure 5 A graph of another set of signals in the voltage conversion circuit of this disclosure embodiment is shown. Detailed Implementation

[0025] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0026] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0027] In voltage conversion circuits employing a constant on-time (COT) control architecture, when the system operates in DCM (Discontinuous Conduction Mode) and is under no-load or light-load conditions, traditional power-down methods will cause the power transistor to be in the off state. There is no effective discharge path at the output terminal, and the charge stored in the output capacitor cannot be discharged in time, resulting in the output voltage remaining at a high level for a long time without falling back normally. This, in turn, affects the system's functional reset and normal operation after power failure.

[0028] Therefore, there is an urgent need for a soft power-down logic control scheme with a power transistor protection mechanism.

[0029] like Figure 1 As shown, a voltage conversion circuit according to an embodiment of the present disclosure includes: a main control module 102, a judgment module 104, and a feedback selection module 106. The main control module 102 is connected to the judgment module 104 and the feedback selection module 106 respectively. The main control module 102 is configured to output a power-down enable signal when a power-down operation is triggered.

[0030] In some embodiments, the main control module 102 can be a functional module that monitors the circuit's operating status and outputs a power-down enable signal when the power-down conditions are met.

[0031] In some embodiments, the power-down enable signal is used to trigger the circuit to perform a soft power-down operation, and can be generated by the main control module 102 when it detects an input abnormality, a power-down command, or when the system needs to be reset.

[0032] In some embodiments, after receiving the power-down enable signal, the judgment module 104 can switch the drive signal output logic to provide an active control path for the discharge of the output capacitor charge. After receiving the power-down enable signal, the feedback selection module 106 can provide a current path for the discharge of the charge. Through the unified scheduling of the main control module 102, the judgment module 104 and the feedback selection module 106 respond synchronously and complete the mode switching from the drive control and feedback control levels respectively, so as to achieve a safe and controllable soft power-down process.

[0033] like Figure 2 As shown, the voltage conversion circuit also includes a voltage conversion module 108, which includes a power inductor L and an output capacitor Cout. One end of the power inductor L is connected to the switching node SW, and the other end of the power inductor L is connected to the output capacitor Cout to output an output voltage generated based on the input voltage.

[0034] The judgment module 104 is connected to the voltage conversion module 108 and is configured to output a first indication signal DIS_OUT to the voltage conversion module 108 when it receives the power-down enable signal DISCHARGE_EN. The first indication signal is used to instruct the voltage conversion module to perform a power-down, or to instruct the voltage conversion module to switch from the operating mode to the power-down mode.

[0035] When the judgment module 104 receives the power-down enable signal DISCHARGE_EN, it can be understood that a high level is the effective state. When DISCHARGE_EN is high, the judgment module 104 considers that it has received a valid power-down enable signal. When DISCHARGE_EN is low, the judgment module 104 considers that it has not received a power-down enable signal, and maintains the operation mode control of the voltage conversion module.

[0036] In some embodiments, the first indication signal instructs the voltage conversion module to perform a power-down. This can be understood as not depending on the current operating state of the voltage conversion module, but only using the received power-down enable signal as the trigger condition to output the first indication signal to directly drive the voltage conversion module into the power-down process. This scenario is applicable to power-down requirements when the voltage conversion module is in various operating states, such as standby, light load, or even fault protection states. If the voltage conversion module receives the first indication signal, it will directly respond to perform charge discharge of the output capacitor. This control method does not preset the module's previous state and can quickly respond to power-down requests in any operating state.

[0037] In some embodiments, the first indication signal DIS_OUT is used to indicate the switching of the operating state inside the voltage conversion module, so that the circuit switches from the operating mode to the power-down mode.

[0038] In some embodiments, the operating mode is the discontinuous conduction mode (DCM) for normal voltage regulation output of the circuit. In this mode, the switching cycle of the switching transistor in the voltage conversion module is controlled by the PWM signal to achieve stable voltage output. The power-down mode is the continuous conduction mode in which the circuit performs soft power-down. In this mode, the switching cycle of the switching transistor is controlled by the zero-crossing detection signal to achieve rapid and controllable discharge of the output voltage.

[0039] The feedback selection module 106 is connected to the voltage conversion module 108 and is configured to receive the node voltage of the switching node SW, and when a power-down enable signal is received, adjust the feedback voltage REF_SW_FB of the node voltage fed back to the voltage conversion module 108. The adjusted feedback voltage is used to set the current valley value of the power inductor to a first preset value, so that the power inductor generates a negative inductor current to draw charge from the output capacitor.

[0040] The first preset value can be a value near 0 or a non-zero negative value.

[0041] In some embodiments, the circuit operates in discontinuous conduction mode (DCM) during operation, where the current valley of the power inductor is limited to near zero. The zero-crossing detection pulse signal is only used to turn off the power transistor and put the circuit into a standby state. The switching cycle is controlled by the PWM drive signal. When entering power-down mode, the feedback selection module lowers the zero-crossing detection threshold by adjusting the feedback voltage, sets the current valley of the power inductor to a first preset value, and at the same time, the judgment module generates a PWM power-down drive signal based on the zero-crossing detection pulse signal, so that the logic controller immediately starts a new round of switching action at each zero-crossing detection trigger moment, thereby realizing the continuous alternating conduction of the upper and lower power transistors, and gradually extracting and discharging the charge on the output capacitor using the negative inductor current.

[0042] In this embodiment, through the coordinated interaction of the judgment module, the feedback selection module, and the voltage conversion module, when the power-down enable signal DISCHARGE_EN is valid, the feedback selection module responds by adjusting the feedback voltage REF_SW_FB of the switching node SW, actively setting the current valley value of the power inductor from a near-zero operating mode threshold to a first preset value, thus creating conditions for the generation of negative inductor current. Simultaneously, after receiving the enable signal, the judgment module DISCHARGE_LOGIC switches the circuit from operating mode to power-down mode, making the switching cycle dominated by the zero-crossing detection signal ZCD_OUT, converting the intermittent switching mode into a continuous switching mode. Under this coordinated mechanism, the voltage conversion circuit can still actively and controllably extract charge from the output capacitor using negative inductor current in scenarios without external discharge loads, such as no-load or light-load conditions, thereby improving the phenomenon of the output voltage remaining high and unable to reset under hard power-down mode, thus achieving a safe and reliable soft-stop power-down effect.

[0043] In one embodiment of this disclosure, the main control module is connected to the voltage conversion module to output a power-down enable signal when it receives an error identification signal from the voltage conversion module; and / or outputs a power-down enable signal when the main control module receives a power-down command.

[0044] In some embodiments, when the voltage conversion module detects abnormal faults such as overvoltage, undervoltage, overcurrent, and overtemperature and outputs the corresponding first error flag signal VOUT_FAULT, the main control module pulls up the power-down enable signal according to the error flag signal; or when the main control module receives external power-down commands such as system reset command, shutdown command, and power off command, it directly pulls up the power-down enable signal to actively trigger the soft power-down process.

[0045] In some embodiments, the second error identification signal VIN_FAULT includes, but is not limited to, at least one of the following: input overvoltage signal, input undervoltage signal, output overvoltage signal, overcurrent protection signal, and overtemperature protection signal. When any error identification signal is valid, the main control module pulls up the power-down enable signal to make the circuit enter a soft power-down state.

[0046] In some embodiments, the power-down command may also include at least one of the following: system shutdown command, module reset command, power off command, and chip enable shutdown command. When the main control module detects that the power-down command is valid, it immediately outputs a valid power-down enable signal to initiate the active discharge of the output voltage.

[0047] In this embodiment, by having the main control module uniformly monitor the fault status and power-down command, it can promptly and reliably trigger a soft power-down when the circuit is abnormal or the system needs to be reset, ensuring that the output voltage is discharged quickly and preventing the problem of high voltage caused by the inability to release the charge of the output capacitor. At the same time, it can realize current limiting protection for the power transistor during the power-down process, thereby improving the safety and stability of the system.

[0048] like Figure 2 As shown, in one embodiment of this disclosure, the voltage conversion module 108 further includes a zero-crossing detection comparator 202, which includes a first comparison terminal, a second comparison terminal and a first output terminal. The first comparison terminal is connected to the zero-crossing detection reference voltage REF_ZED, and the second comparison terminal is connected to the feedback voltage REF_SW_FB. When the feedback voltage REF_SW_FB is equal to the reference voltage, the first output terminal outputs a zero-crossing detection pulse signal ZCD_OUT.

[0049] like Figure 2 As shown, in some embodiments, the zero-crossing detection comparator 202 is configured to output a trigger signal when the power inductor current IL reaches a preset negative valley value. The judgment module immediately starts a new switching cycle based on the trigger signal to limit the reverse current amplitude. That is, the zero-crossing detection comparator 202 is used to detect the current valley value of the power inductor. The zero-crossing detection reference voltage REF_ZED connected to the first comparison terminal is a preset fixed voltage used to correspond to the target current valley value of the power inductor. The feedback voltage REF_SW_FB connected to the second comparison terminal is related to the current of the power inductor. That is, the change in current will synchronously drive the change in feedback voltage REF_SW_FB. When the feedback voltage REF_SW_FB drops to be equal to the zero-crossing detection reference voltage REF_ZED, it indicates that the power inductor current has reached the preset valley value. The first output terminal of the zero-crossing detection comparator 202 will flip and output a zero-crossing detection pulse signal ZCD_OUT. Based on the zero-crossing detection pulse signal ZCD_OUT, the switching of the subsequent power transistor is triggered to realize the control of the switching cycle.

[0050] Specifically, the voltage division coefficient of the feedback selection module is inversely proportional to the current valley value of the power inductor. When the power-down enable signal is not connected, the feedback selection module outputs a feedback voltage REF_SW_FB corresponding to the first voltage division coefficient, and the current valley value corresponding to the first voltage division coefficient is close to zero. When the power-down enable signal is connected, the feedback selection module outputs a feedback voltage REF_SW_FB corresponding to the second voltage division coefficient. The first voltage division coefficient is greater than the second voltage division coefficient. Based on the inverse relationship, the current valley value corresponding to the second voltage division coefficient becomes the first preset value, causing the power inductor to generate a negative inductor current.

[0051] In some embodiments, the feedback selection module may include a switchable voltage divider circuit, which can change the amplitude of the feedback voltage REF_SW_FB by adjusting the voltage divider coefficient, thereby indirectly controlling the current valley value of the power inductor.

[0052] The larger the voltage division factor of the voltage divider circuit, the higher the output feedback voltage REF_SW_FB. With the zero-crossing detection reference voltage REF_ZCD fixed, the higher the required inductor current valley value is to make the feedback voltage equal to the reference voltage; conversely, the smaller the voltage division factor, the lower the output feedback voltage, and the lower the corresponding inductor current valley value.

[0053] When the circuit is in operating mode and the power-down enable signal DISCHARGE_EN is not connected, the feedback selection module uses a larger first voltage division coefficient to output a higher feedback voltage. This limits the inductor current valley to a near-zero level, preventing the generation of negative current, thus adapting to the discontinuous conduction mode (DCM) of normal voltage regulation.

[0054] When the circuit enters power-down mode and the power-down enable signal DISCHARGE_EN is connected, the feedback selection module switches to a smaller second voltage division coefficient and outputs a lower feedback voltage. Since the voltage division coefficient is inversely proportional to the current valley value, the corresponding inductor current valley value becomes the first preset value, thereby causing the power inductor to generate a negative current flowing from the output terminal to the inductor, providing an active path for the charge discharge of the output capacitor COUT.

[0055] In this embodiment, by configuring a switchable voltage divider coefficient in the feedback selection module, the power inductor current valley value can be flexibly adjusted. In operation mode, the current valley value is kept close to zero to ensure normal voltage regulation. In power-down mode, it switches to a negative current valley value to generate a negative inductor current, which can actively extract the charge from the output capacitor to achieve rapid and controllable discharge of the output voltage. Furthermore, by detecting the negative current valley value through the ZCD comparator, the switch can be triggered in time when the current reaches a preset first value, preventing excessive reverse current from damaging the power transistor. This balances the effectiveness of soft power-down and the protection requirements of the power transistor.

[0056] In one embodiment of this disclosure, the voltage conversion module 108 further includes: a first power transistor VGATEP and a second power transistor VGATEN connected in series between the input voltage VIN and ground. The common connection point of the first power transistor VGATEP and the second power transistor VGATEN is a switching node. When the first power transistor VGATEP is off and the second power transistor VGATEN is on, the node voltage is determined based on the power inductance.

[0057] In one embodiment of this disclosure, the determination module is further configured to connect a PWM drive signal PWM_OUT to the voltage conversion module in the operating mode and a PWM power-down drive signal PWM_MUX_OUT to the voltage conversion module in the power-down mode. PWM_MUX_OUT is generated based on the PWM drive signal and the zero-crossing detection pulse signal so that the output capacitor discharges charge in the power-down mode.

[0058] In some embodiments, the judgment module receives the PWM drive signal PWM_OUT and the zero-crossing detection pulse signal ZCD_OUT, and combines them logically with the valid state of the power-down enable signal to generate a PWM power-down drive signal. In the operating mode, PWM_MUX_OUT follows the PWM drive signal PWM_OUT to control the intermittent switching of the power transistor to achieve voltage regulation. In the power-down mode, PWM_MUX_OUT uses the zero-crossing detection pulse signal ZCD_OUT as the main trigger source. Whenever the zero-crossing detection pulse signal ZCD_OUT detects that the power inductor has reached the negative current valley, it immediately triggers PWM_MUX_OUT to generate a drive pulse. At the same time, it takes into account the valid state of the PWM drive signal PWM_OUT, so that the first power transistor VGATEP and the second power transistor VGATEN are continuously and alternately turned on, and the negative inductor current is used to continuously draw charge from the output capacitor, thereby realizing the rapid discharge of the output capacitor.

[0059] In this embodiment, the PWM_MUX_OUT generated by the judgment module based on the PWM drive signal PWM_OUT and the zero-crossing detection pulse signal ZCD_OUT is triggered by the zero-crossing detection pulse signal ZCD_OUT in power-down mode, realizing continuous switching of the power transistor. With the help of the negative inductor current, the output capacitor charge can be actively discharged to ensure that the output voltage drops quickly, thereby meeting the system's power-down reset requirements. PWM_MUX_OUT takes into account the characteristics of the PWM drive signal, ensuring a smooth transition between the power-down process and the operating mode. Moreover, by controlling the switching cycle through the zero-crossing detection pulse signal, the magnitude of the reverse current can be limited to prevent the power transistor from being damaged due to reverse overcurrent. This effectively solves the problem of the power transistor being turned off and the output capacitor not having an effective discharge path, resulting in a persistently high voltage in the hard power-down mode.

[0060] In one embodiment of this disclosure, the voltage conversion module 108 further includes: a logic controller 204 configured to access a PWM drive signal PWM_OUT in operating mode to output a first set of on / off signals to a first power transistor VGATEP and a second power transistor VGATEN, and to access a PWM power-down drive signal in power-down mode to output a second set of on / off signals to the first power transistor VGATEP and the second power transistor VGATEN. The first set of on / off signals is used to indicate that the first power transistor VGATEP and the second power transistor VGATEN are switched on and off intermittently, and the second set of on / off signals is used to indicate that the first power transistor VGATEP and the second power transistor VGATEN are switched on and off continuously.

[0061] In some embodiments, the intermittent switching mode refers to the following: in the operating mode, after each switching cycle, the second power transistor VGATEN is turned off, and the first power transistor VGATEP remains off, and the circuit enters a waiting state until the next PWM drive signal arrives before the first power transistor VGATEP is turned on again, thus making the switching of the power transistors intermittent. The continuous switching mode refers to the following: in the power-down mode, after each switching cycle, the second power transistor VGATEN is turned off and the first power transistor VGATEP is turned on immediately, without waiting for the PWM drive signal PWM_OUT, so that the first power transistor VGATEP and the second power transistor VGATEN are continuously and alternately turned on, forming an uninterrupted switching action.

[0062] In operating mode, the ZCD_OUT signal input to the logic controller 204 is used to detect the valley value of the power inductor current. When the inductor current drops to a preset threshold close to zero, the zero-crossing detection comparator 202 outputs the ZCD_OUT signal, which is sent to the logic controller 204 to forcibly turn off the second power transistor VGATEN and put the circuit into a waiting state, no longer actively starting the next switching cycle until the PWM_OUT signal arrives, so that the circuit works in discontinuous conduction mode (DCM) to achieve stable voltage output.

[0063] In power-down mode, the feedback selection module adjusts the reference voltage of the ZCD comparator and sets the current valley value to the first preset value. When the inductor current drops to this negative valley value, the zero-crossing detection comparator 202 outputs the ZCD_OUT signal. This signal is sent to the logic controller 204 and serves as the main trigger source for PWM_MUX_OUT. It is used to turn on the upper transistor immediately while turning off the lower transistor, breaking the waiting state in DCM mode and enabling the power transistor to enter a continuous alternating conduction mode. This, combined with the negative inductor current, draws the charge from the output capacitor, achieving rapid discharge of the output voltage, while limiting the magnitude of the reverse current and protecting the power transistor.

[0064] In this embodiment, the logic controller achieves the switching of circuit operating modes by connecting different drive signals in the running mode and the power-down mode and outputting corresponding on / off signals. In the running mode, the PWM drive signal is connected to control the power transistor to switch on and off intermittently, which can effectively adapt to the voltage regulation control logic of the COT architecture. In the power-down mode, the PWM power-down drive signal is connected to control the power transistor to switch on and off continuously, and the negative inductor current is used to build a charge discharge path for the output capacitor.

[0065] like Figure 2 As shown, in one embodiment of this disclosure, the voltage conversion module further includes a PWM comparator 206, which includes a third comparison terminal, a fourth comparison terminal, and a second output terminal. The third comparison terminal is used to receive an error amplification signal VEAO, the fourth comparison terminal is used to receive a carrier signal VRAMP, and the second output terminal is used to output a PWM drive signal. The error amplification signal is determined based on the output voltage.

[0066] In the operating mode, the logic controller 204 receives the PWM drive signal PWM_OUT from the judgment module, and in the power-down mode, it receives the PWM power-down drive signal from the judgment module.

[0067] In this embodiment, the PWM comparator generates a PWM drive signal based on the comparison result between the error amplification signal and the carrier signal. This signal serves as the input of the logic controller 204, controlling the first power transistor VGATEP and the second power transistor VGATEN to switch on and off intermittently, thereby achieving a stable voltage output. When entering the power-down mode, the judgment module generates a PWM power-down drive signal based on the PWM drive signal and the zero-crossing detection pulse signal. This signal serves as the input of the logic controller 204, controlling the first power transistor VGATEP and the second power transistor VGATEN to switch on and off continuously. This, combined with the negative inductor current, actively draws charge from the output capacitor, thereby achieving rapid discharge of the output voltage.

[0068] In one embodiment of this disclosure, the voltage conversion module further includes: an on-time timer 208, connected to the logic controller 204, configured to control the on-time of the first power transistor VGATEP in an operating mode.

[0069] In some embodiments, the on-time timer 208 is connected to the logic controller 204 and is used to control the on-time of the first power transistor VGATEP in the operating mode. When the logic controller 204 receives the PWM_OUT signal and turns on the first power transistor VGATEP, the on-time timer 208 starts timing synchronously. When the preset on-time threshold is reached, the timer outputs the TON signal to the logic controller 204, triggering the first power transistor VGATEP to turn off, thereby realizing the stable voltage regulation function under the constant on-time control architecture. In the power-down mode, the role of the timer is weakened, and the switching cycle is dominated by the zero-crossing detection pulse signal ZCD_OUT to meet the requirement of continuous switching to discharge charge.

[0070] In some embodiments, in the operating mode, i.e., DCM mode, the PWM comparator outputs a PWM drive signal based on the comparison result between the error amplification signal VEAO and the carrier signal VRAMP. This signal triggers the first power transistor VGATEP to turn on via the logic controller 204. The on-time timer 208 starts timing simultaneously with the turn-on of the upper transistor. When the preset on-time is reached, it outputs a TON signal to control the upper transistor to turn off and simultaneously turn on the second power transistor VGATEN. Since the inductor current IL is discontinuous in DCM mode, the zero-crossing detection comparator 202 limits the inductor current valley value to a threshold close to zero, such as REF_ZCD being set to 10mV. When the inductor current IL drops to this threshold, the ZCD comparator outputs a ZCD_OUT signal to control the lower transistor to turn off, thereby ending one cycle of switching action. The corresponding signal logic is as follows: Figure 3 As shown.

[0071] like Figure 3 As shown, the upper transistor drive signal VGATEP is the gate drive signal of the first power transistor VGATEP. A high level indicates that the upper transistor is turned on, and a low level indicates that it is turned off. Turning on is triggered by the PWM_OUT signal, and turning off is controlled by the TON signal output by the on-time timer 208, thereby realizing constant on-time (COT) control.

[0072] The lower transistor drive signal VGATEN is the gate drive signal for the second power transistor VGATEN. A high level indicates that the lower transistor is turned on, and a low level indicates that it is turned off. Its turn-on is synchronized with the turn-off of the upper transistor and is triggered by the TON signal. Its turn-off is controlled by the ZCD_OUT signal, which is used to end the current switching cycle.

[0073] During the conduction of the upper MOSFET, the inductor current IL rises linearly, and during the conduction of the lower MOSFET, the inductor current decreases linearly. In DCM mode, after the current drops to a low value close to zero, the lower MOSFET is turned off, and the current remains at zero until the start of the next PWM cycle, exhibiting discontinuous characteristics.

[0074] The on-time signal TON is the output signal of the on-time timer 208. A high level indicates that during the timing process, when the preset duration is reached, the TON signal is valid, triggering the upper transistor to turn off and the lower transistor to turn on, ensuring that the on-time of the upper transistor is constant.

[0075] PWM, or PWM drive signal, is the output signal of PWM comparator 206, used to trigger the upper transistor to turn on. The generation of the pulse is determined by the comparison result between the error amplification signal VEAO and the carrier signal VRAMP, and it is the core signal for realizing voltage regulation control.

[0076] VFB is the feedback signal of the output voltage, and VEAO is the error amplification signal after comparing VFB with the reference voltage. The amplitude of VEAO reflects the deviation between the output voltage and the target value and is used to adjust the duty cycle of the PWM signal to achieve closed-loop voltage regulation.

[0077] The zero-crossing detection output signal ZCD_OUT is the output signal of the zero-crossing detection comparator 202. When the inductor current drops to the preset valley value (close to zero), ZCD_OUT is valid, controlling the lower transistor to turn off, ending the current cycle, preventing the inductor current from reaching the first preset value, and maintaining DCM mode.

[0078] When the upper transistor is turned on, the voltage at node SW is close to the input voltage VIN; when the lower transistor is turned on, the voltage at node SW is close to ground potential; after the lower transistor is turned off, the voltage at node SW changes slowly with the output voltage until the next cycle begins.

[0079] In one embodiment of this disclosure, the determination module 104 may include a first input terminal, a second input terminal, a third input terminal, and a third output terminal. The first input terminal is used to connect to the power-down enable signal DISCHARGE_EN, the second input terminal is used to connect to the zero-crossing detection pulse signal ZCD_OUT, the third input terminal is used to connect to the PWM drive signal PWM_OUT, and the third output terminal is used to output the PWM drive signal PWM_OUT in the running mode and the PWM power-down drive signal in the power-down mode.

[0080] In some embodiments, by inputting multiple signals to the judgment module, the switching of the drive signal between the operating mode and the power-down mode is realized. In the operating mode, the power-down enable signal is invalid, and the module directly outputs the PWM drive signal PWM_OUT connected to the third input terminal from the third output terminal to provide the logic controller 204 with the intermittent switching control signal required for voltage regulation. In the power-down mode, the power-down enable signal is valid, and the module performs logical combination based on the zero-crossing detection pulse signal ZCD_OUT of the second input terminal and the PWM drive signal PWM_OUT of the third input terminal to generate and output the PWM power-down drive signal. This signal takes the zero-crossing detection pulse signal ZCD_OUT as the dominant trigger source, causing the power transistor to enter a continuous alternating conduction state.

[0081] In this embodiment, the judgment module achieves reliable switching of drive signals between the operating mode and the power-down mode by selecting multiple inputs of the power-down enable signal, the zero-crossing detection pulse signal, and the PWM drive signal. In the operating mode, the original PWM drive signal is directly output to ensure the stability and accuracy of the voltage regulation control. In the power-down mode, a PWM power-down drive signal adapted to the discharge requirements is output. The drive logic can be quickly switched without adding a complex control unit, which simplifies the control architecture and ensures smooth switching between the two operating modes.

[0082] like Figure 4 As shown, in one embodiment of this disclosure, the determination module includes: a first NOR gate 402, the two inputs of which serve as a second input and a third input, respectively; a first NOT gate 404 and a second NOT gate 406, the inputs of which serve as first inputs, respectively; a second NOR gate 408, the two inputs of which are connected to the outputs of the first NOR gate 402 and the first NOT gate 404, respectively; an AND gate 410, one input of which serves as a third input, and the other input of which is connected to the output of the second NOT gate 406; and an OR gate 412, the two inputs of which are connected to the outputs of the second NOR gate 408 and the AND gate 410, respectively, and the output of the OR gate 412 serves as a third output.

[0083] In some embodiments, in the operating mode, DISCHARGE_EN=0, the second NOR gate 408 is forced to clamp the output low level; the output of the second NOT gate 406 is 1, the AND gate 410 is enabled and turns on and follows the PWM_OUT signal output of the third input terminal; the OR gate 412 performs a logical OR operation on the low level of the second NOR gate 408 and the output of the AND gate 410.

[0084] When PWM_OUT is active: AND gate 410 outputs an active level synchronously, the second NOR gate 408 remains low, and the output of OR gate 412 follows PWM_OUT; therefore, PWM_MUX_OUT = PWM_OUT, and the waveform is completely consistent with PWM_OUT, exhibiting sparse and discontinuous pulses; when ZCD_OUT is triggered: the level change of the first NOR gate 402 only affects the input of the second NOR gate 408, the second NOR gate 408 still maintains a low level output, does not affect PWM_MUX_OUT, and the cycle ends.

[0085] In power-down mode, DISCHARGE_EN=1, the output of the first NOT gate 404 is 0, the second NOR gate 408 directly passes the output level of the first NOR gate 402, the first NOR gate 402 performs a NOR logic operation, and the output = !(PWM_OUT|ZCD_OUT); the output of the second NOT gate 406 is 0, making the output of the AND gate 410 = PWM_OUT&0 = 0; the output of the OR gate 412 = (PWM_OUT|ZCD_OUT)|0; when ZCD_OUT is triggered: the change in the ZCD_OUT level causes the output level of the first NOR gate 402 to flip, and the output of the OR gate 412 flips accordingly, generating a new PWM_MUX_OUT pulse; when PWM_OUT is valid: the change in the PWM_OUT level causes the output level of the first NOR gate 402 to flip, and the output of the OR gate 412 flips accordingly, generating a PWM_MUX_OUT pulse.

[0086] like Figure 5 As shown, the curves ZERO_POINT and ZCD_NEG_THRES are reference lines for the zero-crossing detection threshold. ZERO_POINT corresponds to the valley value of the inductor current in the circuit operation mode, which is close to zero. ZCD_NEG_THRES corresponds to the valley value of the negative inductor current in the power-down mode. When the inductor current IL drops to the corresponding threshold, the ZCD_OUT pulse will be triggered to indicate the switching of the power transistor.

[0087] The upper transistor drive signal VGATEP is the gate drive signal of the first power transistor VGATEP. A high level indicates that the upper transistor is turned on, and a low level indicates that it is turned off. In the low operating mode of DISCHARGE_EN, the pulse is triggered by PWM_OUT, with a large interval and is discontinuous. In the power-down mode of high DISCHARGE_EN, the pulse is triggered by ZCD_OUT, with a significantly smaller interval and is in a continuous alternating on state.

[0088] The zero-crossing detection output signal ZCD_OUT is a pulse signal output by the zero-crossing detection comparator, used to detect the current valley value of the power inductor. In the operating mode, the pulse is generated when the inductor current approaches zero, used to end the current cycle and put the circuit into a waiting state; in the power-down mode, the pulse is generated when the inductor current reaches the first preset value, used to immediately start the next switching cycle, realizing continuous switching.

[0089] PWM_OUT is a drive signal generated by the PWM comparator, used to indicate the voltage regulation function of the circuit in the operating mode. It has a large pulse interval, corresponding to the switching cycle in the discontinuous conduction mode (DCM). In the power-down mode, this signal no longer dominates the switching cycle, but participates in the generation of PWM_MUX_OUT as an auxiliary signal.

[0090] The power-down enable signal DISCHARGE_EN is the enable control signal for soft power-down. When it is low, the circuit is in the running mode, and the switching cycle is controlled by PWM_OUT. When it is high, the circuit enters the power-down mode, and the judgment module switches to generate PWM_MUX_OUT based on ZCD_OUT, triggering continuous switching to discharge the output capacitor charge.

[0091] The PWM power-down drive signal PWM_MUX_OUT is the final drive signal output by the judgment module and is the input of the logic controller. In the running mode (DISCHARGE_EN=0), it follows PWM_OUT and controls the power transistor to switch on and off intermittently. In the power-down mode (DISCHARGE_EN=1), it is triggered by ZCD_OUT and controls the power transistor to switch on and off continuously, which, together with the negative inductor current, achieves rapid discharge of the output voltage.

[0092] In this embodiment, by using a combination of pure logic gates consisting of a first NOR gate, a first NOT gate, a second NOT gate, a second NOR gate, an AND gate, and an OR gate, the judgment module can achieve coordinated control and mode selection between the power-down enable signal, the zero-crossing detection pulse signal, and the PWM drive signal using only basic logic devices. Through the combination of logic gates within the judgment module, the switching of drive signals between the operating mode and the power-down mode is realized. In the operating mode, PWM_MUX_OUT follows PWM_OUT, causing the power transistor to switch on and off intermittently, adapting to the DCM voltage regulation requirements and preventing unnecessary switching losses. In the power-down mode, PWM_MUX_OUT is triggered by ZCD_OUT, causing the power transistor to switch on and off continuously. Combined with the negative inductor current, it actively extracts the charge from the output capacitor, solving the problem of the output voltage remaining high for a long time and unable to be reset under the traditional power-down mode. It does not require complex timing control or additional configuration circuits, has a simple structure, and has the advantages of fast response speed and reliable logic switching. It can stably support the smooth switching between the operating mode and the power-down mode, providing a simple, efficient, stable, and reliable drive signal generation and selection function for the entire voltage conversion circuit.

[0093] like Figure 2 As shown in one embodiment of this disclosure, the feedback selection module includes: a first voltage divider resistor R1, a second voltage divider resistor R2, and a third voltage divider resistor R3 connected in series. The first voltage divider resistor R1 is connected to the switch node SW to receive the node voltage, and the third voltage divider resistor R3 is grounded. There is a first voltage divider point between the first voltage divider resistor R1 and the second voltage divider resistor R2, and a second voltage divider point between the second voltage divider resistor R2 and the third voltage divider resistor R3.

[0094] The feedback selection module 106 further includes a multiplexer 210, which has a fourth input terminal, a fifth input terminal, a sixth input terminal, and a fourth output terminal. The fourth input terminal is connected to the main control module, the fifth input terminal is connected to the first voltage divider point, the sixth input terminal is connected to the second voltage divider point, and the fourth output terminal is connected to the second comparison terminal. If no power-down enable signal is connected, the voltage SW_FB1 of the first voltage divider point is selected as the feedback voltage REF_SW_FB. If a power-down enable signal is connected, the voltage SW_FB2 of the second voltage divider point is selected as the feedback voltage REF_SW_FB.

[0095] In some embodiments, the feedback selection module consists of a voltage divider network and a multiplexer. A series voltage divider network composed of a first voltage divider resistor R1, a second voltage divider resistor R2, and a third voltage divider resistor R3 forms two different voltage divider points between the switching node SW and ground. The multiplexer then selects one of these two points based on the power-down enable signal DISCHARGE_EN. In operating mode, the multiplexer selects the first voltage divider point, i.e., the voltage SW_FB1 between the first and second voltage divider resistors R1 and R2, as the feedback voltage REF_SW_FB. This corresponds to a power inductor current valley value close to zero, meeting the requirements of DCM voltage regulation. In power-down mode, the multiplexer switches to the second voltage divider point, i.e., the voltage SW_FB2 between the second and third voltage divider resistors R2 and R3, as the feedback voltage REF_SW_FB. This voltage divider point has an even lower voltage, thus enabling the power inductor current valley value to be set to a first preset value.

[0096] In this embodiment, the switching of feedback voltage can be achieved through basic resistor voltage division and simple multiplexing logic, without the need for complex operational amplifiers or additional control units. It can also ensure the accuracy of current valley setting and response speed in both modes, providing reliable hardware support for actively discharging output capacitor charge during soft power-off, thereby effectively improving the circuit's power-off safety and reset capability in scenarios such as no-load and light-load.

[0097] A DC-DC converter according to an embodiment of the present disclosure includes: a voltage conversion circuit according to any of the above embodiments.

[0098] In this disclosure, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0099] In the description of this disclosure, it should be understood that the terms "upper," "lower," "left," "right," "front," "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0100] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0101] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure. Those skilled in the art will readily conceive of other embodiments of this disclosure after considering the specification and practicing the solutions disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A voltage conversion circuit, characterized in that, include: A voltage conversion module includes a power inductor and an output capacitor. One end of the power inductor is connected to a switching node, and the other end of the power inductor is connected to the output capacitor to output an output voltage generated based on the input voltage. The judgment module, connected to the voltage conversion module, is configured to output a first indication signal to the voltage conversion module when it receives a power-down enable signal. The first indication signal is used to instruct the voltage conversion module to perform a power-down, or to instruct the voltage conversion module to switch from the operating mode to the power-down mode. The feedback selection module, connected to the voltage conversion module, is configured to receive the node voltage of the switching node, and when the power-down enable signal is received, adjust the feedback voltage of the node voltage fed back to the voltage conversion module. The adjusted feedback voltage is used to set the current valley value of the power inductor to a first preset value, so that the power inductor generates a negative inductor current to draw charge from the output capacitor.

2. The voltage conversion circuit according to claim 1, characterized in that, Also includes: The main control module, connected to the judgment module and the feedback selection module, is configured to output the power-down enable signal when the power-down operation is triggered.

3. The voltage conversion circuit according to claim 2, characterized in that, The main control module is connected to the voltage conversion module to output the power-down enable signal when it receives an error identification signal from the voltage conversion module; and / or When the main control module receives a power-down command, it outputs the power-down enable signal.

4. The voltage conversion circuit according to claim 2, characterized in that, The voltage conversion module also includes: A zero-crossing detection comparator includes a first comparison terminal, a second comparison terminal, and a first output terminal. The first comparison terminal is connected to a zero-crossing detection reference voltage, and the second comparison terminal is connected to a feedback voltage. When the feedback voltage reaches the reference voltage, the first output terminal outputs a zero-crossing detection pulse signal. The voltage division coefficient of the feedback selection module is inversely proportional to the current valley value of the power inductor. When the power-down enable signal is not connected, the feedback selection module outputs the feedback voltage corresponding to the first voltage division coefficient, and the current valley value corresponding to the first voltage division coefficient is close to zero. When the power-down enable signal is connected, the feedback selection module outputs the feedback voltage corresponding to the second voltage division coefficient. The first voltage division coefficient is greater than the second voltage division coefficient. Based on the inverse relationship, the current valley value corresponding to the second voltage division coefficient becomes a first preset value, causing the power inductor to generate the negative inductor current.

5. The voltage conversion circuit according to claim 4, characterized in that, The voltage conversion module also includes: A first power transistor and a second power transistor are connected in series between the input voltage and ground. The common connection point of the first power transistor and the second power transistor is the switching node. When the first power transistor is off and the second power transistor is on, the node voltage is determined based on the power inductor.

6. The voltage conversion circuit according to claim 5, characterized in that, The judgment module is further configured to provide a pulse width modulation (PWM) drive signal to the voltage conversion module in the operating mode, and to provide a PWM power-down drive signal to the voltage conversion module in the power-down mode. The PWM power-down drive signal is generated based on the PWM drive signal and the zero-crossing detection pulse signal, so that the output capacitor discharges charge in the power-down mode.

7. The voltage conversion circuit according to claim 6, characterized in that, The voltage conversion module also includes: A logic controller is configured to access the PWM drive signal in the operating mode to output a first set of on / off signals to the first power transistor and the second power transistor, and to access the PWM power-off drive signal in the power-down mode to output a second set of on / off signals to the first power transistor and the second power transistor. The first set of on / off signals is used to indicate that the first power transistor and the second power transistor are switched on and off intermittently, and the second set of on / off signals is used to indicate that the first power transistor and the second power transistor are switched on and off continuously.

8. The voltage conversion circuit according to claim 7, characterized in that, The voltage conversion module also includes: The PWM comparator includes a third comparison terminal, a fourth comparison terminal, and a second output terminal. The third comparison terminal is used to receive an error amplification signal, the fourth comparison terminal is used to receive a carrier signal, and the second output terminal is used to output the PWM drive signal. The error amplification signal is determined based on the output voltage. In the operating mode, the logic controller receives the PWM drive signal from the judgment module; in the power-down mode, the logic controller receives the PWM power-down drive signal from the judgment module.

9. The voltage conversion circuit according to claim 8, characterized in that, The judgment module includes a first input terminal, a second input terminal, a third input terminal, and a third output terminal. The first input terminal is used to receive the power-down enable signal, the second input terminal is used to receive the zero-crossing detection pulse signal, the third input terminal is used to receive the PWM drive signal, and the third output terminal is used to receive the PWM drive signal in the running mode and the PWM power-down drive signal in the power-down mode.

10. The voltage conversion circuit according to claim 9, characterized in that, The judgment module includes: A first NOR gate, wherein the two inputs of the first NOR gate are respectively used as the second input and the third input; The first NOT gate and the second NOT gate, with their input terminals serving as the first input terminal respectively; The second NOR gate has its two inputs connected to the outputs of the first NOR gate and the first NOT gate, respectively. An AND gate, one input of which serves as the third input, and the other input of which is connected to the output of the second NOT gate; The OR gate has its two inputs connected to the outputs of the second NOR gate and the AND gate, respectively, and its output serves as the third output.

11. The voltage conversion circuit according to claim 4, characterized in that, The feedback selection module includes: A first voltage divider resistor, a second voltage divider resistor, and a third voltage divider resistor are connected in series. The first voltage divider resistor is connected to the switch node, and the third voltage divider resistor is grounded. There is a first voltage divider point between the first voltage divider resistor and the second voltage divider resistor, and a second voltage divider point between the second voltage divider resistor and the third voltage divider resistor. A multiplexer has a fourth input terminal, a fifth input terminal, a sixth input terminal, and a fourth output terminal. The fourth input terminal is connected to the main control module, the fifth input terminal is connected to the first voltage divider point, the sixth input terminal is connected to the second voltage divider point, and the fourth output terminal is connected to the second comparator terminal. If the power-down enable signal is not connected, the voltage of the first voltage divider point is selected as the feedback voltage; if the power-down enable signal is connected, the voltage of the second voltage divider point is selected as the feedback voltage.

12. The voltage conversion circuit according to claim 7, characterized in that, The voltage conversion module also includes: An on-time timer, connected to the logic controller, is configured to control the on-time of the first power transistor in the operating mode.

13. The voltage conversion circuit according to claim 3, characterized in that, The error identification signal is generated when the input voltage is lower than the input threshold and / or abnormal power consumption is detected.

14. The voltage conversion circuit according to claim 1, characterized in that, The operating mode is intermittent conduction mode.

15. A DC-to-DC converter, characterized in that, include: The voltage conversion circuit as described in any one of claims 1 to 14.

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