Power supply circuit and semiconductor integrated circuit

Abstract

One embodiment of the present invention provides a power supply circuit and semiconductor integrated circuit that exhibit excellent power efficiency, low output voltage fluctuation, easy output voltage adjustment, and miniaturization. The power supply circuit of one embodiment includes: a first node supplied with an input voltage; a second node outputting a first output voltage; a plurality of DC-DC converters, each having a switched capacitor, connected in parallel between the first node and the second node; and a first control circuit that individually controls the plurality of DC-DC converters such that each of the plurality of DC-DC converters outputs an inherent second output voltage, and the second node outputs the first output voltage obtained by combining the plurality of second output voltages output from the plurality of DC-DC converters.

Description

[0001] This application is a divisional application of patent application No. 202110957548.5, filed on August 18, 2021, entitled "Power Supply Circuit and Semiconductor Integrated Circuit".

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-44843 (filed on March 18, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] One embodiment of the present invention relates to a power supply circuit and a semiconductor integrated circuit. Background Technology

[0004] To reduce power consumption, semiconductor integrated circuits have made progress towards using lower voltage power supplies. The voltage of the power supply used as the voltage source for semiconductor integrated circuits is generated using DC-DC converters, analog LDO regulators, etc. DC-DC converters using switched capacitors (hereinafter referred to as SC-DCDCC) do not require transformers, are easy to integrate, and have good power efficiency, but they suffer from large output voltage fluctuations.

[0005] On the other hand, analog LDO regulators have a simple structure and are easy to integrate. They can suppress output voltage fluctuations and adjust the output voltage, but they suffer from poor power efficiency.

[0006] Thus, both the SC-DCDCC and the analog LDO regulator have their advantages and disadvantages. Therefore, a structure that cascades the SC-DCDCC and the LDO regulator was proposed. This structure offers advantages such as excellent power efficiency, low output voltage fluctuation, and the ability to adjust the output voltage. On the other hand, besides the difficulty in driving high currents due to the cascading of the SC-DCDCC and the analog LDO regulator, there is also the problem of needing to connect a large-capacity output capacitor to the analog LDO regulator to suppress load variations, resulting in a larger circuit area. Summary of the Invention

[0007] One embodiment of the present invention provides a power supply circuit and semiconductor integrated circuit that have excellent power efficiency, low output voltage fluctuation, easy output voltage adjustment, and can be miniaturized.

[0008] A power supply circuit according to one embodiment of the present invention includes: a first node; a second node; a DC-DC converter having a switched capacitor, generating an output voltage based on an input voltage supplied from the first node, and outputting it from the second node; and an regulator connected in parallel with the DC-DC converter between the first node and the second node, adjusting the output current flowing to the second node based on a reference voltage lower than the input voltage. Attached Figure Description

[0009] Figure 1 This is a block diagram showing the general structure of the power supply circuit according to the first embodiment.

[0010] Figure 2 This is a block diagram showing the general structure of a power supply circuit involved in a comparative example.

[0011] Figure 3 yes Figure 1 A block diagram of the first modified example of the power supply circuit.

[0012] Figure 4 yes Figure 1 Block diagram of the second variation of the power supply circuit.

[0013] Figure 5 yes Figure 1 Block diagram of the third variation of the power supply circuit.

[0014] Figure 6 This is a diagram illustrating four intertwined processes.

[0015] Figure 7 yes Figure 1 The block diagram of the fourth variation of the power supply circuit.

[0016] Figure 8 yes Figure 7 The simulated waveforms of various parts within the power supply circuit.

[0017] Figure 9 yes Figure 2 A comparative example involves simulated waveforms of various parts within a power supply circuit.

[0018] Figure 10 This is a diagram showing the output voltage and output current waveforms under four different conditions when the output capacitor of the analog LDO is changed.

[0019] Figure 11A This is a circuit diagram showing an example of the basic structure of an SC-DCDCC circuit with a switched capacitor circuit, and it is a circuit diagram with SW1 and SW2 turned on and switches SW3 and SW4 turned off.

[0020] Figure 11BThis is a circuit diagram showing the state where switches SW1 and SW2 in the switched capacitor circuit are open, and switches SW3 and SW4 are closed.

[0021] Figure 12 yes Figure 11A Power supply status and Figure 11B The voltage waveform diagram under capacitor supply conditions.

[0022] Figure 13 This is a circuit diagram of an SC-DCDCC that can generate three output voltages.

[0023] Figure 14A It indicates that it is used from Figure 13 The circuit diagram shows an example of the switching of the power supply state of the SC-DCDCC switch that generates the output voltage Vin / 2.

[0024] Figure 14B It indicates that it is used from Figure 13 The circuit diagram shows an example of a capacitor supply state switching of an SC-DCDCC converter that generates an output voltage of Vin / 2.

[0025] Figure 15A It indicates that it is used from Figure 13 The circuit diagram shows an example of switching the power supply state of the SC-DCDCC generator to produce the output voltage Vin / 3.

[0026] Figure 15B It indicates that it is used from Figure 13 The circuit diagram shows an example of switching the capacitor supply state for the SC-DCDCC to generate the output voltage Vin / 3.

[0027] Figure 16A It indicates that it is used from Figure 13 The circuit diagram shows an example of switching the power supply state of an SC-DCDCC generator producing an output voltage of 2Vin / 3.

[0028] Figure 16B It indicates that it is used from Figure 13 The circuit diagram shows an example of switching the capacitor supply state of an SC-DCDCC converter that generates an output voltage of 2Vin / 3.

[0029] Figure 17 It connects in parallel between node 1 and node 2, each having the same characteristics as... Figure 13 A schematic block diagram of the power supply circuits for multiple SC-DCDCCs with the same internal structure.

[0030] Figure 18 It is a block diagram of a power supply circuit that includes an SC-DCDCC that outputs a voltage of Vin / 2 and an SC-DCDCC that outputs a voltage of Vin / 3, connected in parallel.

[0031] Figure 19A From Figure 18 The voltage waveform diagram of the output voltage of the power supply circuit.

[0032] Figure 19B It's enlarged. Figure 19A A diagram of a portion of the voltage waveform.

[0033] Figure 20 It is a block diagram of a power supply circuit that includes an SC-DCDCC that outputs a voltage of Vin / 2 and an SC-DCDCC that outputs a voltage of 2Vin / 3, connected in parallel.

[0034] Figure 21A From Figure 20 The voltage waveform diagram of the output voltage of the power supply circuit.

[0035] Figure 21B It's enlarged. Figure 21A A diagram of a portion of the voltage waveform.

[0036] Figure 22A This is a diagram showing the output capacitors from node 2 in the power supply state of a power supply circuit with two SC-DCDCC converters connected in parallel to output voltage Vin / 3.

[0037] Figure 22B This is a diagram showing the output-side capacitance from node 2 in the capacitor-supply state of a power supply circuit with two SC-DCDCC circuits connected in parallel to produce an output voltage Vin / 3.

[0038] Figure 23A This is a block diagram of the first switching state of the first example of the power supply circuit according to the third embodiment.

[0039] Figure 23B This is a block diagram of the second switching state of the first example of the power supply circuit according to the third embodiment.

[0040] Figure 24A This is a diagram showing the output capacitance from the second node in the power supply state of a power supply circuit that has two switched capacitor circuits connected in parallel to produce an output voltage of 2Vin / 3.

[0041] Figure 24B This is a diagram showing the output capacitance from the second node in the power supply circuit, which has two switched capacitor circuits connected in parallel to produce an output voltage of 2Vin / 3.

[0042] Figure 25A This is a block diagram of the first switching state of the second example of the power supply circuit according to the third embodiment.

[0043] Figure 25B This is a block diagram of the second switching state of the second example of the power supply circuit according to the third embodiment.

[0044] Figure 26 It means from Figure 24A and Figure 24B The fluctuation of the output voltage at node 2 and from Figure 25A and Figure 25B A diagram showing the fluctuation of the output voltage of the power supply circuit involved.

[0045] Figure 27A It means from Figure 25A and Figure 25B A diagram showing the waveform of the output voltage from the power supply circuit involved.

[0046] Figure 27B It means from Figure 24A and Figure 24B A diagram showing the waveform of the output voltage from the power supply circuit involved.

[0047] Figure 28A It is a block diagram of the power supply status of a power supply circuit with four SC-DCDCCs that perform interleaving operation.

[0048] Figure 28B This is a block diagram showing the capacitor supply state of a power supply circuit with four SC-DCDCC capacitors that operate in an interleaved manner.

[0049] Figure 29A This diagram illustrates an example of how the four switched capacitor circuits within the power supply circuit operate in the first switching state.

[0050] Figure 29B This diagram illustrates an example of how the four switched capacitor circuits within the power supply circuit operate in the second switching state.

[0051] Figure 30A It is a block diagram of the power supply state of a power supply circuit with four switched capacitor circuits that operate in an interleaved manner.

[0052] Figure 30B It is a block diagram of the capacitor supply state of a power supply circuit with four switched capacitor circuits that can perform interleaved operation.

[0053] Figure 31A This diagram illustrates an example of how the four switched capacitor circuits within the power supply circuit operate in the first switching state.

[0054] Figure 31B This diagram illustrates an example of how the four switched capacitor circuits within the power supply circuit operate in the second switching state.

[0055] Figure 32 It means from Figure 30A and Figure 30B The fluctuation of the output voltage of the power supply circuit involved and from Figure 31A and Figure 31B A diagram showing the fluctuation of the output voltage of the power supply circuit involved.

[0056] Figure 33A It means from Figure 31A and Figure 31B A diagram showing the waveform of the output voltage from the power supply circuit involved.

[0057] Figure 33B It means from Figure 30A and Figure 30B A diagram showing the waveform of the output voltage from the power supply circuit involved.

[0058] Figure 34 This is a block diagram showing the general structure of the power supply circuit according to the fourth embodiment.

[0059] Figure 35 It is a block diagram of a power supply circuit that uses an analog LDO with a PMOS transistor.

[0060] Figure 36 This is a block diagram showing the schematic structure of the power supply circuit according to the fifth embodiment.

[0061] Figure 37 This is a block diagram showing the general structure of the power supply circuit according to the sixth embodiment.

[0062] Figure 38A This is a diagram representing the first operating mode of the power supply circuit.

[0063] Figure 38B This is a diagram representing the second operating mode of the power supply circuit.

[0064] Figure 38C This diagram represents the third operating mode of the power supply circuit.

[0065] Figure 39 This is a block diagram showing the general structure of the power supply circuit according to the seventh embodiment.

[0066] Figure 40 This is a block diagram showing a schematic structure of a semiconductor integrated circuit having the power supply circuits described in embodiments 1 to 7.

[0067] Label Explanation

[0068] 1. 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i, 1j, 1k, 1m, 1n, 1p, 1q, 1r, 1s, 1t, 1u, 1v Power supply circuits; 2. 2a, 2b SC-DCDCC; 3. 3a, 3b Analog LDOs; 4. 4x, 4y Switched capacitor circuits; 4a First switched capacitor circuit; 4b Second switched capacitor circuit; 5 Load circuit; 6 Closed-loop control circuit; 6a Control signal generator; 6b Switching control circuit; 7 Comparator; 7a First comparator; 7b Second comparator; 8 Open-loop control circuit; 9 Current source; 10 Switcher; 12 Voltage source; 13 Clock generation circuit; 21 Up / down counter; 22 Shift register; 23 Switching control circuit; 24 Mode selection circuit; 25 Semiconductor integrated circuit; 26 Application circuit; 100 Power supply circuit Detailed Implementation

[0069] Hereinafter, embodiments of the power supply circuit and semiconductor integrated circuit will be described with reference to the accompanying drawings. The description will focus on the main components of the power supply circuit and semiconductor integrated circuit, but the power supply circuit and semiconductor integrated circuit may contain components and functions not shown or described. The following description does not exclude components and functions not shown or described.

[0070] (First Embodiment)

[0071] Figure 1 This is a block diagram showing the general structure of the power supply circuit 1 according to the first embodiment. Figure 1 The power supply circuit 1 includes a DC-DC converter 2 and an regulator 3 connected in parallel between node 1 n1 and node 2 n2. The power supply circuit 1 has node 1 n1 and node 2 n2. A DC input voltage Vin of a certain voltage level is supplied to node 1 n1. An output voltage Vout of a certain voltage level is output from node 2 n2. Node 1 n1 is the input node of the power supply circuit 1, and node 2 n2 is the output node of the power supply circuit 1.

[0072] Figure 1The DC-DC converter 2 has a switched capacitor circuit 4, which generates an output voltage Vout based on the DC input voltage Vin supplied from the first node n1, and outputs it from the second node n2. The switched capacitor circuit 4 refers to a circuit having a capacitor and a switch that controls the charging and discharging of the capacitor. The number of capacitors and switches included in the switched capacitor circuit 4 is arbitrary. The switches in the switched capacitor circuit 4 are periodically turned on or off. This causes the capacitor to charge or discharge, and the voltage across the capacitor changes. Hereinafter, the DC-DC converter 2 is sometimes referred to as SC-DCDCC2. As described in detail in other embodiments described later, the SC-DCDCC2 generates an output voltage Vout with a voltage level different from the input voltage Vin by periodically turning the switches in the switched capacitor circuit 4 on or off, causing the capacitor in the switched capacitor circuit 4 to charge and discharge.

[0073] Figure 1 The regulator 3 is connected in parallel with the SC-DCDCC2 between node 1 n1 and node 2 n2. The regulator 3 controls the current flowing to node 2 n2 based on a reference voltage Vref that is lower than the input voltage Vin. Hereinafter, the regulator 3 will sometimes be referred to as an analog LDO 3. In this specification, an example where the input voltage Vin supplied to node 1 is the power supply voltage will be described. Here, the power supply voltage refers to the voltage supplied to the power supply terminals of power supply circuit 1.

[0074] A load circuit (Analog Load) 5 is connected at node 2 n2. The specific circuit structure of the load circuit 5 is not limited. The current (I_sc + I_ldo) obtained by adding the current I_sc output from SC-DCDCC2 and the current I_ldo output from analog LDO3 flows in the load circuit 5.

[0075] The power supply circuit 1 also includes a closed-loop control circuit 6, which provides feedback control of the SC-DCDCC2 based on the voltage level of the output voltage Vout. The closed-loop control circuit 6 includes, for example, a control signal generator 6a and a switching control circuit 6b. The control signal generator 6a generates a control signal corresponding to the voltage level of the output voltage Vout. The switching control circuit 6b controls the switching of the switched capacitor circuit 4 based on the control signal.

[0076] The analog LDO3 has a control amplifier 7 and a first transistor Q1. The control amplifier 7 outputs a signal corresponding to the voltage difference between the output voltage Vout and the reference voltage Vref. Figure 1In this example, a reference voltage Vref is applied to the non-inverting input terminal of the control amplifier 7, and an output voltage Vout is applied to the inverting input terminal. The reference voltage Vref is a voltage level lower than the input voltage Vin supplied to the first node n1. Additionally, the input voltage Vin is supplied from the first node n1 to the power supply terminal of the control amplifier 7. The output node of the control amplifier 7 is connected to the first transistor Q1.

[0077] The first transistor Q1 is, for example, an NMOS transistor. The gate of the first transistor Q1 is connected to the output node of the control amplifier 7, the drain of the first transistor Q1 is connected to the first node n1, and the source of the first transistor Q1 is connected to the second node n2 and the inverting input terminal of the control amplifier 7. Thus, the analog LDO3 performs feedback control so that the output voltage Vout matches the reference voltage Vref. The control amplifier 7 and the first transistor Q1 within the analog LDO3 constitute a closed-loop control circuit different from the closed-loop control circuit 6.

[0078] Generally, when using an analog LDO3 alone, a large output capacitor CL is required to suppress load fluctuations in the output voltage Vout from the analog LDO3. In power supply circuit 1, the capacitor CL used as the output capacitor of the analog LDO3 can be the capacitor within the switched capacitor circuit 4 of the SC-DCDCC2. Therefore, a large output capacitor CL is not required, allowing for a reduction in the circuit size of power supply circuit 1.

[0079] Thus, in the power supply circuit 1 according to the first embodiment, the SC-DCDCC2 and the analog LDO3 are connected in parallel between the first node n1 and the second node n2. Therefore, the current obtained by adding the current output from the SC-DCDCC2 and the current output from the analog LDO3 can flow in the load circuit 5, thereby increasing the current flowing in the load circuit 5. More specifically, the size of each transistor in the SC-DCDCC2 and the analog LDO3 can be individually determined according to the current required by the load circuit 5. Therefore, it is not necessary to increase the transistor size of each transistor in the SC-DCDCC2 and the analog LDO3, and the circuit area of ​​the power supply circuit 1 can be reduced.

[0080] Figure 2 This is a block diagram of the schematic structure of a power supply circuit 100 involved in a comparative example. Figure 2The power supply circuit 100 includes an SC-DCDCC2 and an analog LDO3 cascaded between a first node n1 supplying the input voltage Vin and a second node n2 outputting the output voltage Vout. More specifically, the SC-DCDCC2 is connected between the first node n1 and the drain of a first transistor Q1 within the analog LDO3. The source of the first transistor Q1 is connected to the second node n2. A control amplifier 7 supplies a signal to the gate of the first transistor Q1 corresponding to the voltage difference between the reference voltage Vref and the output voltage Vout. In a comparative example, the power supply circuit 100 includes the SC-DCDCC2 and analog LDO3, which have the same structure as those included in the power supply circuit 1 of the first embodiment.

[0081] Figure 2 The comparative example shown involves a power supply circuit 100 with an SC-DCDCC2, which improves power efficiency, and an analog LDO3, which reduces output voltage Vout fluctuations and allows for output voltage Vout adjustment via the analog LDO3. However, since the SC-DCDCC2 and analog LDO3 are cascaded, only the smaller output current of the SC-DCDCC2 and analog LDO3 flows in the load circuit 5. Therefore, to allow a large current to flow in the load circuit 5, the transistor sizes in both the SC-DCDCC2 and analog LDO3 need to be increased, resulting in a larger circuit area for the power supply circuit 100. Furthermore, to suppress load fluctuations, a large output capacitor CL needs to be connected at the output node of the analog LDO3. However, since the SC-DCDCC2 and analog LDO3 are cascaded, the capacitor in the SC-DCDCC2 cannot be used as the output capacitor CL of the analog LDO3. Therefore, the output capacitor CL must be individually configured, further increasing the circuit area of ​​the power supply circuit 100.

[0082] In contrast, Figure 1 Since the power supply circuit 1 has an SC-DCDCC2 and an analog LDO3 connected in parallel between the first node n1 and the second node n2, therefore, it is compatible with... Figure 2 Compared to the power supply circuit 100, it is able to flow a larger current in the load circuit 5. Furthermore, in Figure 1 In the power supply circuit 1, the switched capacitor circuit 4 within SC-DCDCC2 can be used as the output capacitor CL of the analog LDO3. Therefore, with Figure 2 Compared to the power supply circuit 100, the circuit area can be reduced.

[0083] so, Figure 1 The advantages of power supply circuit 1 are compared to Figure 2 The power supply circuit has over 100 components. However, Figure 1The power supply circuit 1 is a dual-loop control system where both the SC-DCDCC2 and the analog LDO3 perform closed-loop control of the DC output voltage Vout. Therefore, it's impossible to determine which control takes precedence, potentially leading to unstable operation. Thus, a power supply circuit that takes this into account will be explained below.

[0084] Figure 3 yes Figure 1 Block diagram of the first modified example of the power supply circuit 1. Figure 3 The power supply circuit 1a and Figure 1 Similarly, it has SC-DCDCC2 and analog LDO3a connected in parallel between node 1 n1 and node 2 n2.

[0085] Figure 3 Simulated internal structure of LDO3a and Figure 1 The simulation LDO3 is different. Figure 3 The analog LDO3a has an open-loop control circuit 8. In addition to the control amplifier 7 and the first transistor Q1, the open-loop control circuit 8 also includes a second transistor Q2, a current source 9, and a switch 10. The second transistor Q2 is, for example, an NMOS transistor.

[0086] The control amplifier 7 outputs a signal corresponding to the voltage difference between node n10 and the reference voltage Vref within the open-loop control circuit 8. The first transistor Q1 receives the output signal from the control amplifier 7 at its gate and adjusts the current flowing to the second node n2 according to the level of the received signal. The second transistor Q2 also receives the output signal from the control amplifier 7 at its gate and adjusts the voltage at node n10 according to the level of the received signal. Node n10 is, for example, connected to the source of the second transistor Q2.

[0087] The drain of the second transistor Q2 is connected to the first node n1, and the gate of the second transistor Q2 is connected to the output node of the control amplifier 7. A current source 9 is connected between the source of the second transistor Q2 and the ground node. The source of the second transistor Q2 is connected to the inverting input terminal of the control amplifier 7 via node n10.

[0088] A switch 10 is connected between the source of the first transistor Q1 and the inverting input terminal of the control amplifier 7. The switch 10 toggles whether the analog LDO3a performs closed-loop control, which provides feedback control over the output voltage Vout. When the switch 10 is on, the source of the first transistor Q1 is connected to the inverting input terminal of the control amplifier 7. When the switch 10 is off, the connection between the source of the first transistor Q1 and the inverting input terminal of the control amplifier 7 is broken. For the open-loop control circuit 8 of the analog LDO3a to function, the switch 10 needs to be off. When the switch 10 is off, the output voltage Vout is not fed back to the input side of the control amplifier 7, and the analog LDO3a performs open-loop control using the second transistor Q2.

[0089] Furthermore, as will be discussed later, Figure 3 The power supply circuit 1a can perform closed-loop control of the analog LDO3a unit by stopping the operation of SC-DCDCC2 and turning on the switch 10.

[0090] Figure 3 The analog LDO3a has a first transistor Q1 and a second transistor Q2 as NMOS transistors, but it can also be constructed from PMOS transistors. Figure 4 yes Figure 1 Block diagram of the second variation of the power supply circuit 1. Figure 4 The power supply circuit 1b makes both the first transistor Q1 and the second transistor Q2 in the analog LDO3b PMOS transistors. Figure 3 The power supply circuit 1a is different. Figure 4 The sources of the first transistor Q1 and the second transistor Q2 are connected to the first node n1. The drain of the first transistor Q1 is connected to the second node n2. A switch 10 is connected between the drain of the first transistor Q1 and the non-inverting input terminal of the control amplifier 7. A reference voltage Vref is applied to the inverting input terminal of the control amplifier 7. The drain of the second transistor Q2 is connected to the non-inverting input terminal of the control amplifier 7 via node n10. Figure 4 The open-loop control circuit 8 includes a control amplifier 7, a first transistor Q1, a second transistor Q2, a current source 9, and a switch 10.

[0091] and Figure 3 Similarly, the simulation of LDO3a, Figure 4 The analog LDO3b can flow a large current in the load circuit 5 without increasing the circuit area, and can also suppress the fluctuation of the output voltage Vout.

[0092] Figure 1 , Figure 3 as well as Figure 4The power supply circuits 1, 1a, and 1b each have only one SC-DCDCC2. However, by setting multiple SC-DCDCC2s in the power supply circuits 1, 1a, and 1b, and having these SC-DCDCC2s work in an interleaved manner, the fluctuation of the output voltage Vout can be further suppressed.

[0093] Figure 5 yes Figure 1 Block diagram of the third variation of the power supply circuit 1. Figure 5 The power supply circuit 1c is connected in parallel between multiple SC-DCDCC2s between the first node n1 and the second node n2. Figure 3 The power supply circuit 1a is different. Figure 5 The multiple SC-DCDCC2s in the power supply circuit 1c are characterized by interleaving operation. Figure 6 This is a diagram that roughly illustrates the interlacing process. In Figure 6 In the example, four SC-DCDCC2p, 2q, 2r, and 2s are set up, each receiving a clock signal with a phase offset. For example, one of the clock signals with phases relative to a reference of 0°, 45°, 90°, and 135° is input to... Figure 6 The system consists of four SC-DCDCC2p, 2q, 2r, and 2s. Each SC-DCDCC2p, 2q, 2r, and 2s switches its respective switched capacitor circuit 4 synchronously with its corresponding clock signal. That is, using staggered clock signals to generate the output voltage Vout from multiple SC-DCDCC2p, 2q, 2r, and 2s is called interleaving. The output nodes of multiple SC-DCDCC2p, 2q, 2r, and 2s are all connected to node 2 n2. The voltage obtained by combining the output voltages Vout from each SC-DCDCC2 is obtained from the output of node 2 n2.

[0094] Figure 6 The four SC-DCDCC2p, 2q, 2r, and 2s have the same circuit structure, but by staggering their phases, they can achieve the same charge transfer as a single SC-DCDCC2 with four times the circuit area of ​​a single SC-DCDCC2. The smaller the circuit area, the smaller the capacitor size within the SC-DCDCC. That is, by using four SC-DCDCC2s, the size of the capacitors constituting each SC-DCDCC is reduced. Therefore, the charge transfer of each segmented SC-DCDCC is reduced, suppressing fluctuations in the output voltage Vout. Thus, by staggering the phases of multiple SC-DCDCC2p, 2q, 2r, and 2s with small circuit areas, fluctuations can be significantly suppressed compared to generating the output voltage Vout using a single SC-DCDCC2 with a large circuit area.

[0095] Figure 7 yes Figure 1 Block diagram of the fourth variation of the power supply circuit 1. Figure 7 The power supply circuit 1d relative to Figure 5 The power supply circuit 1c, and Figure 4 Similarly, the power supply circuit 1b uses PMOS transistors for the first transistor Q1 and the second transistor Q2 in the analog LDO3b. The essential circuit operation and the resulting effects are the same as... Figure 5 The power supply circuit is the same as that of 1c.

[0096] Figure 8 yes Figure 5 The simulated waveforms of each part in the power supply circuit 1c are shown. Figure 8 This represents the waveform when the output capacitor CL is not connected at the output node of the simulated LDO3a. Figure 8 The diagram shows the output current waveform w1 of the SC-DCDCC2, the output current waveform w2 of the simulated LDO3a, and... Figure 5 The voltage waveform w3 shows the output voltage Vout of the power supply circuit 1c. The output current of SC-DCDCC2 changes accordingly with the load current. Synchronously with the rapid increase in the output current of SC-DCDCC2, the output voltage Vout temporarily decreases. However, in situations such as... Figure 5 In such a parallel connection structure, the on-resistance of the output node n2 is small, and it can obtain current assistance through the analog LDO3a when the load current changes. Therefore, the variation of the output voltage Vout when the load current changes can be suppressed to a small extent. As can be seen from the current waveforms w1 and w2, from Figure 5 Most of the current output from the power supply circuit 1c comes from SC-DCDCC2.

[0097] Figure 9 yes Figure 2 A comparative example involves simulated waveforms of various parts within a power supply circuit 100. Figure 9 The diagram shows the output current waveform w4 of the SC-DCDCC2, the output current waveform w5 of the analog LDO3, the output voltage waveform w6 of the SC-DCDCC2, and the waveform from... Figure 2 The output voltage waveform w7 is output by the power supply circuit 100. Figure 2In the power supply circuit 100, an SC-DCDCC2 and an analog LDO3 are cascaded between the first node n1, which is supplied with the input voltage Vin, and the second node n2, which outputs the output voltage Vout. Therefore, as shown in waveforms w6 and w7, the output voltage of the SC-DCDCC2 is inconsistent with the output voltage Vout of the power supply circuit 100. On the other hand, as shown in waveforms w4 and w5, the output current of the SC-DCDCC2 and the output current of the analog LDO3 are approximately the same. Figure 9 and Figure 8 As can be seen from the comparison, in the power supply circuit 100 involved in the comparative example, the change in output voltage Vout when the output current (load current) changes is greater than that of the output current (load current). Figure 5 The power supply circuit is large (1c).

[0098] Figure 10 Indicates in Figure 5 In power supply circuit 1c, with SC-DCDCC2 disabled, the output voltage waveforms w10-w13 and output current waveforms w14-w17 are shown under four different conditions where the output capacitor CL of the analog LDO3a is changed. The output voltage waveforms w10-w13 and the output current waveforms w14-w17 represent the waveforms in order of increasing output capacitor CL. As shown in the figure, the smaller the output capacitor CL, the greater the change in output voltage Vout. Output voltage waveform w13 corresponds to... Figure 8 The output voltage waveform w3 has the same voltage variation, but to obtain the output voltage waveform w13, the output capacitor CL of the analog LDO3a must be, for example, 1000pF or more, and the circuit area of ​​the power supply circuit 1c must be increased.

[0099] If Figure 10 The voltage waveforms w10~w13 and Figure 8 As can be seen from the voltage waveform w3, according to the power supply circuit 1c of this embodiment, even without individually setting the output capacitor CL, a DC output voltage Vout with less fluctuation can be generated.

[0100] Thus, in the first embodiment, the SC-DCDCC2 and the analog LDOs 3, 3a, and 3b are connected in parallel between the first node n1 and the second node n2. Therefore, compared to the case of cascading the SC-DCDCC2 and the analog LDOs 3, 3a, and 3b, a large current can flow in the load circuit 5 without increasing the circuit area. Furthermore, by having the analog LDOs 3, 3a, and 3b connected in parallel, fluctuations in the output voltage Vout can be suppressed compared to a single SC-DCDCC2. Moreover, the capacitors within the switched capacitor circuit 4 of the SC-DCDCC2 can be used as the output capacitors CL of the analog LDOs 3, 3a, and 3b; therefore, it is not necessary to individually set the output capacitors CL, thus reducing the circuit area of ​​the power supply circuit 1.

[0101] In addition, by setting a closed-loop control circuit 6 in SC-DCDCC2 and an open-loop control circuit 8 in analog LDO3a, it does not become a dual-loop control, and the feedback control of the output voltage Vout can be performed more stably.

[0102] Furthermore, by setting multiple SC-DCDCC2s and having them work in an interleaved manner, fluctuations in the output voltage Vout can be further suppressed.

[0103] (Second Implementation)

[0104] Figure 11A and Figure 11B This is a circuit diagram illustrating an example of the basic structure of an SC-DCDCC2 with a switched capacitor circuit 4. For example... Figure 11A As shown, the SC-DCDCC2 has switches SW1 to SW4 and a capacitor Cfly disposed between a first node n1 connected to a voltage source 12 and a second node n2 connected to a load circuit 5. The voltage source 12 supplies the SC-DCDCC2 with an input voltage Vin as its power supply voltage. Switches SW1 and SW4 are connected in series between the first node n1 and the second node n2. A capacitor Cfly and a switch SW3 are connected in series between the third node n3 (connected to switches SW1 and SW4) and a ground node. A switch SW2 is connected between the fourth node n4 (connected to capacitor Cfly and switch SW3) and the second node n2.

[0105] Figure 11A This indicates that switches SW1 to SW4 have been switched so that the input voltage (power supply voltage) Vin from voltage source 12 is supplied to one end of capacitor Cfly. In this specification, this state is referred to as the power supply state. In the power supply state, switches SW1 and SW2 are on, and switches SW3 and SW4 are off. Therefore, in Figure 11ACurrent flows through the dashed path, and capacitor Cfly is charged. When the voltage V(Cfly) across capacitor Cfly and the output voltage Vout are used, the input voltage Vin is represented by the following equation (1).

[0106] Vin=V(Cfly)+Vout…(1)

[0107] Figure 11B This is a circuit diagram showing the state where switches SW1 and SW2 in the switched capacitor circuit 4 are open, and switches SW3 and SW4 are open. Figure 11B In this state, no input voltage (power supply voltage) Vin is supplied to capacitor Cfly. The charge in capacitor Cfly is discharged and supplied to node 2 n2. Therefore, this is referred to as the capacitor supply state in this specification.

[0108] In the capacitor-supply state, switches SW1 and SW2 are open, while switches SW3 and SW4 are closed. Therefore, the accumulated charge in capacitor Cfly... Figure 11B The DC output voltage Vout is expressed by the following equation (2) when the voltage across capacitor Cfly before capacitor Cfly begins to discharge is set to V(Cfly).

[0109] Vout=V(Cfly) …(2)

[0110] By substituting equation (2) into equation (1), the output voltage Vout is represented by the following equation (3).

[0111] Vout = Vin / 2 …(3)

[0112] Thus, in Figure 11A and Figure 11B In the switched capacitor circuit 4, an output voltage Vout can be obtained at half the voltage level of the input voltage Vin.

[0113] Figure 12 yes Figure 11A Power supply status and Figure 11B Voltage waveforms of various parts under capacitor supply conditions. Figure 12 The diagram shows the waveform w19 of the output voltage Vout and the waveform w20 of the voltage across the capacitor Cfly. Figure 12t1 to t2 represent the power supply state, and t2 to t3 represent the capacitor supply state. The switched capacitor circuit 4 alternates between the power supply state and the capacitor supply state over time. For example, the switched capacitor circuit 4 is synchronized with a clock signal with a duty cycle of 50:50, for example, it becomes the power supply state during the period when the clock signal is at the first logic level (e.g., high level), and becomes the capacitor supply state during the period when the clock signal is at the second logic level (e.g., low level), which is different from the first logic level.

[0114] like Figure 12 As shown, during the power supply state (times t1 to t2), charge gradually accumulates in capacitor Cfly. Therefore, as shown by waveform w20, the voltage V(Cfly) across capacitor Cfly gradually increases. Additionally, current flows from node 2 n2 to load circuit 5. Therefore, as shown by waveform w19, the DC output voltage Vout from node 2 n2 gradually decreases.

[0115] Furthermore, in the capacitor-supply state (times t2 to t3), at the timing when switches SW3 and SW4 are turned on (time t2), one end of capacitor Cfly is short-circuited with node 2 n2, therefore, the output voltage Vout rises sharply. Then, current flows from node 2 n2 to load circuit 5, therefore, as shown by waveforms w19 and w20, the output voltage Vout and the voltage V(Cfly) across capacitor Cfly maintain the same voltage level while gradually decreasing.

[0116] so, Figure 11A and Figure 11B The switched capacitor circuit 4 shown periodically charges and discharges the capacitor Cfly, therefore, its corresponding output voltage Vout also varies periodically. Thus, the output voltage Vout of the SC-DCDCC2 with the switched capacitor circuit 4 will, in principle, contain fluctuations.

[0117] exist Figure 11A and Figure 11B In the switched capacitor circuit 4 shown, an output voltage Vout = Vin / 2 can be generated relative to the input voltage Vin, but an output voltage Vout of other voltage levels cannot be generated.

[0118] In contrast, by using two Figure 11A and Figure 11B The switched capacitor circuit 4 shown controls the switching of each switch to generate three different DC output voltages Vout with different voltage levels.

[0119] Figure 13 This is the circuit diagram of the SC-DCDCC2a, which can generate three output voltages Vout. Figure 13 The SC-DDCDCC has the following structure: using two Figure 11A and Figure 11B The switched capacitor circuit 4 shown has a switch SW9 positioned between the two switched capacitor circuits 4. In the following... Figure 13 The two switched capacitor circuits 4 are referred to as the first switched capacitor circuit 4b and the second switched capacitor circuit 4c, and are collectively referred to as the switched capacitor circuit 4a. Both the first switched capacitor circuit 4b and the second switched capacitor circuit 4c have the same characteristics as... Figure 11A and Figure 11B The switched capacitor circuit 4 shown has the same circuit structure. More specifically, the first switched capacitor circuit 4b has switches SW1 to SW4 and capacitor Cfly1. The second switched capacitor circuit 4c has switches SW5 to SW8 and capacitor Cfly2. The input voltage Vin is supplied to the first node n1, which is one end of each of switches SW1 and SW5. The fifth node n5, which is one end of each of switches SW3 and SW7, is connected to the ground node. The load circuit 5 is connected to the second node n2, which is one end of each of switches SW2, SW4, SW6, and SW8.

[0120] A capacitor Cfly1 is connected between connection node n3 of switches SW1 and SW2 and connection node n4 of switches SW3 and SW4. A capacitor Cfly2 is connected between connection node n6 of switches SW5 and SW6 and connection node n7 of switches SW7 and SW8. A switch SW9 is connected between connection node n4 of switches SW3 and SW4 and connection node n6 of switches SW5 and SW6.

[0121] Figure 14A and Figure 14B It indicates that it is used for Figure 13 The circuit diagram shows an example of switching SW1 to SW9 using the SC-DCDCC2a to generate the output voltage Vout of Vin / 2. Figure 14A This is a circuit diagram showing the power supply status. Figure 14B This is a circuit diagram showing the capacitor supply state. Figure 13 The SC-DCDCC2a, for example, becomes during the period when the clock signal is logic level 1 (e.g., high level). Figure 14A The power supply state becomes [a state where] the clock signal is a second logic (e.g., low level) that is different from the first logic. Figure 14B The capacitor supply state. Figure 14A and 14B In this process, control signals φ1 and φ2, which are equivalent to the clock signal, are used. Control signal φ1 is a signal with the same phase as the clock signal, and control signal φ2 is a signal with the opposite phase to the clock signal. Figure 14A and Figure 14B In this circuit, switches SW1, SW4, SW5, and SW8 are switched by switch control signal φ1, while switches SW2, SW3, SW6, and SW7 are switched by switch control signal φ2. Additionally, switch SW9 is in the off state.

[0122] exist Figure 14A Under the power supply condition, switches SW1, SW4, SW5, and SW8 are on, while switches SW2, SW3, SW6, and SW7 are off. SW9 remains off. Therefore, capacitors Cfly1 and Cfly2 are connected in parallel between node 1 (n1) and node 2 (n2). In this case, when the capacitance of both capacitors Cfly1 and Cfly2 is set to C, the capacitance on the output side as viewed from node 2 (n2) becomes C + C = 2C.

[0123] exist Figure 14A Under the power supply condition, when the voltage between the two ends of capacitors Cfly1 and Cfly2 is set to V(Cfly), the input voltage Vin is represented by the following equation (4).

[0124] Vin=V(Cfly)+Vout…(4)

[0125] exist Figure 14B Under the capacitor supply state, with Figure 14A Conversely, switches SW2, SW3, SW6, and SW7 are turned on, while switches SW1, SW4, SW5, and SW8 are turned off. SW9 remains off. Therefore, capacitors Cfly1 and Cfly2 are connected in parallel between ground node n5 and the second node n2. In this case, the capacitance on the output side as viewed from the second node n2 becomes C + C = 2C.

[0126] exist Figure 14B Under the condition of capacitor supply, the output voltage Vout is represented by the following equation (5).

[0127] Vout = V(Cfly) …(5)

[0128] When equation (5) is substituted into V(Cfly) of equation (4), the following equation (6) is obtained.

[0129] Vout = Vin / 2 … (6)

[0130] exist Figure 14A Under the power supply condition, capacitors Cfly1 and Cfly2 are connected in parallel between node 1 n1 and node 2 n2. Therefore, the output capacitance from node 2 n2 is 2C. Figure 14BUnder the capacitor supply state, capacitors Cfly1 and Cfly2 are connected in parallel between node 5 (ground node) and node 2 n2. Therefore, the output capacitance from node 2 n2 is 2C.

[0131] Thus, when using SC-DCDCC2a to output an output voltage Vout = Vin / 2, the output-side capacitance as viewed from node 2 n2 remains the same at 2C in both power-supply and capacitor-supply states. Therefore, even when switching between power-supply and capacitor-supply states, the capacitance remains unchanged, thereby suppressing fluctuations in the output voltage Vout.

[0132] Figure 15A and Figure 15B It indicates that it is used for Figure 13 The circuit diagram shows an example of switching SW1 to SW9 using the SC-DCDCC2a to generate the output voltage Vout of Vin / 3. Figure 15A This is a circuit diagram showing the power supply status. Figure 15B This is a circuit diagram showing the capacitor supply state. Figure 15A and 15B In, also with Figure 14A and 14B Similarly, control signals φ1 and φ2, which are equivalent to clock signals, are used. Figure 15A and Figure 15B In the circuit, switches SW1, SW8, and SW9 are switched by switch control signal φ1, switches SW2, SW3, SW6, and SW7 are switched by switch control signal φ2, and switches SW4 and SW5 are in the off state.

[0133] exist Figure 15A Under the power supply condition, switches SW1, SW8, and SW9 are turned on, while switches SW2, SW3, SW6, and SW7 are turned off. SW4 and SW5 remain off. Therefore, capacitors Cfly1 and Cfly2 are connected in series between the first node n1, where the input voltage Vin is supplied, and the second node n2, where the output voltage Vout is output. When the capacitances of capacitors Cfly1 and Cfly2 are equal, and the voltage across Cfly1 and Cfly2 is set to V(Cfly), the input voltage Vin is represented by the following equation (7).

[0134] Vin=2V(Cfly)+Vout…(7)

[0135] exist Figure 15BUnder the capacitor supply condition, switches SW2, SW3, SW6, and SW7 are on, while switches SW1, SW8, and SW9 are off. Additionally, SW4 and SW5 remain off. Therefore, capacitors Cfly1 and Cfly2 are connected in parallel between ground node n5 and the second node n2. Thus, in Figure 15B Under the condition of capacitor supply, the output voltage Vout is expressed by the above equation (5).

[0136] When equation (5) is substituted into V(Cfly) of equation (7), the following equation (8) is obtained.

[0137] Vout = Vin / 3 … (8)

[0138] exist Figure 15A Under the power supply condition, capacitors Cfly1 and Cfly2 are connected in series between node 1 n1 and node 2 n2. Therefore, the capacitance on the output side as viewed from node 2 n2 is C / 2. Figure 15B Under the capacitor supply state, capacitors Cfly1 and Cfly2 are connected in parallel between node 5 (ground node) and node 2 n2. Therefore, the output capacitance from node 2 n2 is 2C.

[0139] Therefore, when using SC-DCDCC2a to output an output voltage Vout = Vin / 3, the capacitance on the output side, viewed from node 2 n2, will change significantly under both power supply and capacitor supply conditions. Consequently, the fluctuation of the output voltage Vout may increase. Countermeasures will be described later.

[0140] Figure 16A and Figure 16B It indicates that it is used for Figure 13 The circuit diagram shows an example of switching SW1 to SW9 using the SC-DCDCC2a to generate an output voltage Vout of 2Vin / 3. Figure 16A This is a circuit diagram showing the power supply status. Figure 16B This is a circuit diagram showing the capacitor supply state. Figure 16A and 16B Similarly, control signals φ1 and φ2, which are equivalent to clock signals, are used in this process. Figure 16A and Figure 16B In the circuit, switches SW1, SW4, SW5, and SW8 are switched by switch control signal φ1, switches SW2, SW7, and SW9 are switched by switch control signal φ2, and switches SW3 and SW6 are in the off state.

[0141] exist Figure 16AUnder the power supply condition, switches SW1, SW4, SW5, and SW8 are turned on, while switches SW2, SW7, and SW9 are turned off. SW3 and SW6 remain off. Therefore, capacitors Cfly1 and Cfly2 are connected in parallel between the first node n1, where the input voltage Vin is supplied, and the second node n2, where the output voltage Vout is output. When the voltage across capacitors Cfly1 and Cfly2 is set to V(Cfly), the input voltage Vin is represented by the following equation (9).

[0142] Vin=V(Cfly)+Vout…(9)

[0143] exist Figure 16B Under the capacitor supply condition, switches SW2, SW7, and SW9 are turned on, while switches SW1, SW4, SW5, and SW8 are turned off. Additionally, SW3 and SW6 remain off. Therefore, capacitors Cfly1 and Cfly2 are connected in series between node n2 and ground node n5. The output voltage Vout is expressed by the following equation (10).

[0144] Vout=2V(Cfly)…(10)

[0145] By substituting equation (9) into V(Cfly) of equation (10), we can obtain the following equation (11).

[0146] Vout=2(Vin-Vout)…(11)

[0147] By transforming equation (11), we can obtain the following equation (12).

[0148] Vout = 2Vin / 3 … (12)

[0149] exist Figure 16A Under the power supply condition, capacitors Cfly1 and Cfly2 are connected in parallel between node 1 n1 and node 2 n2. Therefore, the output capacitance from node 2 n2 is 2C. Figure 16B Under the capacitor supply state, capacitors Cfly1 and Cfly2 are connected in series between node 5 (ground node) and node 2 n2. Therefore, the output capacitance from node 2 n2 is C / 2.

[0150] Thus, when using the SC-DCDCC2a to output a voltage of 2Vin / 3, the capacitance on the output side, viewed from node 2 n2, changes significantly under both power supply and capacitor supply conditions. Consequently, the fluctuation of the output voltage Vout may increase. Countermeasures will be described later.

[0151] so, Figure 13 The SC-DCDCC2a can output one of three output voltages Vout = Vin / 2, Vin / 3, or 2Vin / 3 by individually controlling the on and off states of switches SW1 to SW9.

[0152] Figure 17 It is a parallel connection between node 1 n1 and node 2 n2, with respectively having and Figure 13 A schematic block diagram of the power supply circuit 1e for multiple SC-DCDCC2a with the same internal structure. There is no particular limitation on the number of SC-DCDCC2a connected in parallel. Each of the multiple SC-DCDCC2a connected in parallel can individually power... Figure 13 The switching on and off of switches SW1 to SW9 controls the output of one of three output voltages: Vout = Vin / 2, Vin / 3, or 2Vin / 3. Multiple output nodes of SC-DCDCC2a are connected to node 2 n2. Therefore, the output voltage Vout is obtained by combining the output voltages generated by multiple SC-DCDCC2a from node 2 n2.

[0153] In addition, Figure 17 The text omits the part in the middle. Figure 3 The simulated LDO3a and 3b have been described in the previous section, but they can also be connected in parallel with multiple SC-DCDCC2a to simulate LDO3a and 3b.

[0154] Figure 17 This example illustrates an alternating configuration of SC-DCDCC2a outputting a voltage of Vin / 2 and another outputting a voltage of 2Vin / 3, but this is merely an example. By arbitrarily switching the ratio of the number of SC-DCDCC2a outputting the three voltages Vin / 2, Vin / 3, or 2Vin / 3, an output voltage Vout of any voltage level between 2Vin / 3 and Vin / 3 can be generated.

[0155] Figure 18 This is a block diagram of a power supply circuit 1f consisting of two parallel-connected components: SC-DCDCC2a, which outputs voltage Vin / 2, and SC-DCDCC2a, which outputs voltage Vin / 3. Figure 18 An example is shown where SC-DCDCC2a outputting Vin / 2 voltage and SC-DCDCC2a outputting Vin / 3 voltage are alternately configured, but the ratio of the number of SC-DCDCC2a outputting Vin / 2 voltage to the number of SC-DCDCC2a outputting Vin / 3 voltage can be arbitrarily adjusted. Therefore, it is possible to... Figure 18 The output voltage Vout of the power supply circuit 1f is set to any voltage level between Vin / 2 and Vin / 3.

[0156] Figure 19A From Figure 18 The voltage waveform diagram of the output voltage Vout of the power supply circuit 1f. Figure 19B It's enlarged. Figure 19A A portion of the voltage waveform diagram. For example... Figure 19A and Figure 19B As shown, by arbitrarily... Figure 18 The ratio of the number of SC-DCDCC2a outputting output voltage Vin / 2 to the number of SC-DCDCC2a outputting output voltage Vin / 3 within the power supply circuit 1f can be switched, enabling the switching between Vin / 2 and Vin / 3. Figure 18 The output voltage Vout of the power supply circuit 1f is set to a voltage level corresponding to the ratio. Figure 19A The voltage waveform w21 is Vin / 2, and the voltage waveform w29 is Vin / 3. The more SC-DCDCC2a outputs Vin / 3, the more gradually the voltage level of the output voltage Vout can be reduced to the voltage waveforms w22 to w28. Figure 19B The waveforms w31 to w39 correspond to Figure 19A The waveforms w21 to w29, voltage waveform w31 is Vin / 2, voltage waveform w39 is Vin / 3. The more SC-DCDCC2a outputs Vin / 3, the more gradually the voltage level of the output voltage Vout can be reduced to the voltage waveforms w32 to w38.

[0157] Figure 20 This is a block diagram of a power supply circuit 1g consisting of two parallel-connected SC-DCDCC2a units, one outputting an output voltage of Vin / 2 and the other outputting an output voltage of 2Vin / 3. Figure 20 The example shown alternately configures SC-DCDCC2a that outputs at an output voltage of Vin / 2 and SC-DCDCC2a that outputs at an output voltage of 2Vin / 3. The ratio of the number of SC-DCDCC2a outputting at Vin / 2 to the number of SC-DCDCC2a outputting at 2Vin / 3 can be arbitrarily adjusted. Therefore, it is possible to... Figure 20 The output voltage Vout of the power supply circuit 1g is set to any voltage level between Vin / 2 and 2Vin / 3.

[0158] Figure 21A From Figure 20The voltage waveform diagram of the output voltage Vout of the power supply circuit 1g. Figure 21B It's enlarged. Figure 21A A portion of the voltage waveform diagram. For example... Figure 21A and Figure 21B As shown, by arbitrarily... Figure 20 The ratio of the number of SC-DCDCC2a outputting at output voltage Vin / 2 to the number of SC-DCDCC2a outputting at output voltage 2Vin / 3 within the power supply circuit 1g can be switched, allowing the output voltage to be transferred between Vin / 2 and 2Vin / 3. Figure 20 The output voltage Vout of the power supply circuit 1g is set to a voltage level corresponding to the ratio. Figure 21A The voltage waveform w41 is 2Vin / 3, and the voltage waveform w49 is Vin / 2. The more SC-DCDCC2a outputs Vin / 2, the more gradually the voltage level of the output voltage Vout can be reduced to the voltage waveforms w42 to w48. Figure 21B The waveforms w51 to w59 correspond to Figure 21A The waveforms w41 to w49, voltage waveform w51 is 2Vin / 3, voltage waveform w59 is Vin / 2. The more SC-DCDCC2a outputs Vin / 2, the more gradually the voltage level of the output voltage Vout can be reduced to the voltage waveforms w52 to w58.

[0159] It can also be done in Figure 17 , Figure 18 as well as Figure 20 In the power supply circuits 1e, 1f, and 1g, the timing of switching on multiple SC-DCDCC2a connected in parallel is staggered step by step. Therefore, as described above, fluctuations in the output voltage Vout from each SC-DCDCC2a can be suppressed.

[0160] The power supply circuits 1e, 1f, and 1g in the second embodiment described above can be configured similarly to the power supply circuits 1, 1a, 1b, 1c, and 1d in the first embodiment, with multiple SC-DCDCC2a and analog LDO3a connected in parallel between the first node n1 and the second node n2. For example, Figure 17 , Figure 18 or Figure 20 As shown, in the second embodiment, the power supply circuits 1e, 1f, and 1g are connected in parallel between the first node n1 and the second node n2. Therefore, by simulating LDO3a by connecting these SC-DCDCC2a in parallel, the same effect as in the first embodiment can be obtained.

[0161] Thus, in the power supply circuits 1e, 1f, and 1g according to the second embodiment, multiple SC-DCDCC2a outputting a certain level of output voltage Vout from a variety of voltage levels are connected in parallel to the first node n1 and the second node n2. Therefore, by changing the ratio of the number of SC-DCDCC2a outputting different output voltages Vout, the voltage level of the output voltage Vout from the power supply circuits 1e, 1f, and 1g can be finely adjusted. According to this embodiment, the voltage level of the output voltage Vout can be finely adjusted while maintaining a simple structure with multiple SC-DCDCC2a with identical internal structures connected in parallel. Furthermore, the voltage level adjustment can be easily achieved by simply controlling the on / off state of switches SW1 to SW9 within each SC-DCDCC2a.

[0162] (Third implementation)

[0163] Figure 13 The SC-DCDCC2a has a switched capacitor circuit 4 that alternately switches between a power supply state and a capacitor supply state in sync with a clock signal to generate an output voltage Vout. When switching between the power supply state and the capacitor supply state, as described above, the output voltage Vout fluctuates more when the capacitance on the output side changes as seen from the output node (node ​​n2) of the SC-DCDCC2a.

[0164] Figure 22A This diagram shows the output capacitance of power supply circuit 1h as viewed from node n2 in the power supply state. Power supply circuit 1h connects two capacitors in parallel, such as... Figure 15A and Figure 15B The diagram shows an SC-DCDCC2a with a switched capacitor circuit 4 that outputs a voltage Vin / 3. In this case, the capacitance of each switched capacitor circuit 4 is C / 2; therefore, from... Figure 22A The output capacitance from the second node n2 is C / 2 + C / 2 = C.

[0165] Figure 22B This diagram shows the output capacitance as viewed from node n2 in the capacitor-supply state of power supply circuit 1h. This power supply circuit 1h has two switched capacitor circuits 4 connected in parallel to output voltage Vin / 3. In this case, the capacitance of each switched capacitor circuit 4 is 2C. Therefore, the output capacitance as viewed from node n2, which shares the output nodes of each SC-DCDCC2a, is 2C + 2C = 4C.

[0166] Thus, when the capacitance on the output side, viewed from the output node (second node n2) of SC-DCDCC2a, changes significantly under both power supply and capacitor supply conditions, the fluctuations in the output voltage Vout output from the second node n2 increase. Therefore, the power supply circuit 1i according to the third embodiment described below is characterized in that the capacitance on the output side, viewed from the second node n2 of the output DC output voltage Vout, remains unchanged under both power supply and capacitor supply conditions.

[0167] Figure 23A and Figure 23B This is a block diagram of the power supply circuit 1i according to the first example of the third embodiment. Figure 23A Indicates the first switching state. Figure 23B This indicates the second switching state. Figure 23A and Figure 23B The power supply circuit 1i has two SC-DCDCC2a. Both SC-DCDCC2a have, for example, the same as... Figure 13 The circuit structure is the same. One of the two SC-DCDCC2a operates in power-supply mode, while the other operates in capacitor-supply mode. Hereinafter, one of the switched capacitor circuits in each of the two SC-DCDCC2a is sometimes referred to as switched capacitor circuit 4x, and the other as switched capacitor circuit 4y.

[0168] For example in Figure 23A In the first switching state, the switched capacitor circuit 4x operates in the power supply state, and the switched capacitor circuit 4y operates in the capacitor supply state. Figure 23B In the second switching state, the switched capacitor circuit 4x operates in capacitor supply mode, and the switched capacitor circuit 4y operates in power supply mode. The output capacitance, viewed from the second node n2 in the first switching state, becomes 2C + C / 2 = 5C / 2. Furthermore, the output capacitance, viewed from the second node n2 in the second switching state, becomes 2C + C / 2 = 5C / 2.

[0169] Thus, in this embodiment, by operating a portion of the multiple parallel-connected switched capacitor circuits 4 in the power supply state and the rest in the capacitor supply state, even when switching between the first switching state and the second switching state, the capacitance on the output side as seen from the second node n2 remains unchanged, thereby suppressing fluctuations in the output voltage Vout.

[0170] Figure 24A This indicates that two are connected in parallel, such as... Figure 16A and Figure 16BThe diagram shows the output capacitance of the power supply circuit 1j of the switched capacitor circuit 4 that outputs a voltage of 2Vin / 3, as viewed from the second node n2 in the power supply state. In this case, the capacitance of each switched capacitor circuit 4 is 2C, therefore, the output capacitance viewed from the second node n2 of SC-DCDCC2a is 2C + 2C = 4C.

[0171] Figure 24B This diagram shows the output capacitance as viewed from node n2 in the capacitor-supply state in a power supply circuit 1j consisting of two parallel switched capacitor circuits 4 that output voltage 2Vin / 3. In this case, the capacitance of each switched capacitor circuit 4 is C / 2; therefore, the output capacitance as viewed from node n2 of SC-DCDCC2a is C / 2 + C / 2 = C.

[0172] Thus, in Figure 24A and Figure 24B In the SC-DCDCC2a shown, which outputs a voltage of 2Vin / 3, the capacitance on the output side as seen from node 2 n2 is significantly different in the power supply state and the capacitor supply state, thus causing fluctuations in the output voltage Vout.

[0173] Figure 25A and Figure 25B This is a block diagram of the power supply circuit 1k involved in the second example of the third embodiment. Figure 25A Indicates the first switching state. Figure 25B This indicates the second switching state. Figure 25A and Figure 25B The power supply circuit 1k has two SC-DCDCC2a. That is, Figure 25A and Figure 25B The power supply circuit 1k has a switched capacitor circuit 4x and a switched capacitor circuit 4y connected in parallel between a first node n1, where the input voltage Vin is supplied, and a second node n2, where the output voltage Vout is produced. One of the switched capacitor circuits 4x and 4y operates in power supply mode, and the other operates in capacitor supply mode. Figure 25A and Figure 25B In the power supply circuit 1k, it is also related to Figure 23A and Figure 23B Similarly, the power supply circuit 1i can make the capacitance on the output side as seen from the second node n2 equal in the first switching state and the second switching state.

[0174] also, Figure 23A and Figure 23B Switched capacitor circuits 4x, 4y and Figure 25A and Figure 25BThe switched capacitor circuits 4x and 4y are synchronized with the clock signal to periodically switch between the first switching state and the second switching state. For example, the switched capacitor circuits 4 (4x, 4y) operate in the first switching state when the clock signal is the first logic, and operate in the second switching state when the clock signal is the second logic, which is different from the first logic.

[0175] Figure 26 It means from Figure 24A and Figure 24B The fluctuation component of the output voltage Vout from the second node n2 of the power supply circuit 1j involved, and from... Figure 25A and Figure 25B A graph showing the fluctuation components of the output voltage Vout at node n2 of the power supply circuit 1k. Figure 26 The waveform w61 indicates from Figure 24A and Figure 24B The fluctuation component of the output voltage Vout of the power supply circuit 1j involved is represented by waveform w62. Figure 25A and Figure 25B The fluctuation component of the output voltage Vout of the power supply circuit 1k is involved. As can be seen by comparing waveforms w61 and w62, Figure 25A and Figure 25B The power supply circuit involved is 1k and Figure 24A and Figure 24B Compared to the power supply circuit 1j, it can significantly suppress the fluctuation components of the output voltage Vout.

[0176] Figure 27A It means from Figure 25A and Figure 25B The diagram shows the waveform of the output voltage Vout of the power supply circuit 1k. Figure 27B It means from Figure 24A and Figure 24B The waveform of the output voltage Vout of the power supply circuit 1j involved is shown in the figure. Figure 27A The vertical axis and Figure 27B The vertical axis represents voltage, showing the same voltage range. Figure 27A Waveforms w63 to w68 represent the voltage waveforms corresponding to six different variations in the load current that causes the output voltage Vout from the power supply circuit 1k. Similarly, Figure 27B The waveforms w71 to w76 represent the voltage waveforms corresponding to six different variations in the load current that causes the output voltage Vout from the power supply circuit 1j to change.

[0177] For comparison Figure 27A Waveforms w63~w68 and Figure 27B As can be seen from waveforms w71 to w76, from Figure 25A and Figure 25BThe voltage variation ratio of the output voltage Vout of the power supply circuit 1k is from... Figure 24A and Figure 24B The output voltage Vout of the power supply circuit 1j involved has little voltage variation.

[0178] The above example illustrates an example where one of the two switched capacitor circuits 4 within the power supply circuits 1i and 1k operates in a power supply state and the other operates in a capacitor supply state. However, it is also possible to provide three or more switched capacitor circuits 4 within the power supply circuits 1i and 1k. In this case, the capacitance on the output side as viewed from the second node n2 is equal in the first switching state and the second switching state. Specifically, it is assumed that in the first switching state, there are switched capacitor circuits 4 operating in the power supply state and switched capacitor circuits 4 operating in the capacitor supply state, and in the second switching state, each switched capacitor circuit 4 is in a state opposite to that in the first switching state.

[0179] In addition, the multiple switched capacitor circuits 4 in the power supply circuits 1i and 1k involved in this embodiment can also operate in an interleaved manner in order to suppress fluctuations in the output voltage Vout.

[0180] Figure 28A and Figure 28B This is a block diagram of a power supply circuit 1m with four SC-DCDCC2a units performing interleaving operation. Each SC-DCDCC2a has... Figure 13 The same circuit structure is used for switched capacitor circuit 4. Figure 28A and Figure 28B This example illustrates how four switched capacitor circuits 4 within a 1m power supply circuit can simultaneously be in either a power supply state or a capacitor supply state. Figure 28A Indicates the power supply status. Figure 28B This indicates the capacitor supply status. Figure 28A and Figure 28B The power supply circuit has 4 switched capacitors within 1m, for example, with... Figure 15A and Figure 15B Similarly, switching switches SW1 to SW9 allows for the output voltage Vout, which is 3 times Vin. Figure 28A and Figure 28B The four switched capacitor circuits 4 are connected to a clock generation circuit 13 that generates four clock signals, each shifted by 45° in phase. The corresponding clock signals are input to each switched capacitor circuit 4. Each switched capacitor circuit 4 is synchronized with the input clock signals to alternately switch between power supply and capacitor supply states.

[0181] exist Figure 28A Under the power supply condition, the output capacitance viewed from node 2 n2 becomes C / 2 × 4 = 2C. Figure 28B Under the condition of capacitor supply, the output capacitance from the perspective of node 2 n2 becomes 2C×4=8C.

[0182] like Figure 28A and Figure 28B In that case, even if all the switching capacitor circuits 4 within 1m of the power supply circuit are interleaved and simultaneously in either the power supply state or the capacitor supply state, the capacitance on the output side as seen from the second node n2 will be significantly different in the power supply state and the capacitor supply state, resulting in fluctuations in the output voltage Vout.

[0183] Therefore, with Figure 23A and Figure 23B Similarly, consider switching multiple switching capacitor circuits 4 within the power supply circuit 1m alternately to either the first switching state or the second switching state to make them work.

[0184] Figure 29A This diagram illustrates an example of how the four switched capacitor circuits 4 within the power supply circuit 1n operate in the first switching state. Figure 29B This diagram illustrates an example of the four switched capacitor circuits 4 within the power supply circuit 1n operating in the second switching state. Figure 29A and Figure 29B The four switched capacitors 4 in the power supply circuit 1n can be connected with... Figure 28A and Figure 28B Similarly, output the output voltage Vout of Vin / 3.

[0185] like Figure 29A As shown, in the first switching state, the odd-numbered (ODD) switched capacitor circuit 4 operates in the power supply state, and the even-numbered (EVEN) switched capacitor circuit 4 operates in the capacitor supply state. Additionally, as... Figure 29B As shown, in the second switching state, the odd-numbered (ODD) switching capacitor circuit 4 is operated in the capacitor supply state, and the even-numbered (EVEN) switching capacitor circuit 4 is operated in the power supply state.

[0186] The output capacitance from node n2 of the switched capacitor circuit 4 operating in power supply mode is C / 2, and the output capacitance from node n2 of the switched capacitor circuit 4 operating in capacitor supply mode is 2C. In either the first or second switching state, two of the four switched capacitor circuits 4 operate in power supply mode, and the remaining two operate in capacitor supply mode. Therefore, in either the first or second switching state, the output capacitance from node n2 is C / 2 × 2 + 2C × 2 = 5C.

[0187] Thus, in Figure 29A and Figure 29B In the power supply circuit 1n, the capacitance on the output side as viewed from the second node n2 is made equal in both the first and second switching states.

[0188] Figure 30A and Figure 30B It is a block diagram of a power supply circuit 1p with four switched capacitor circuits 4 (SC-DCDCC2a) that perform interleaved operation. Figure 30A and Figure 30B This represents an example where the four switched capacitor circuits 4 within the power supply circuit 1p are simultaneously in either a power supply state or a capacitor supply state. Figure 30A Indicates the power supply status. Figure 30B This indicates the capacitor supply state. The internal structures of all switched capacitor circuits 4 are identical, for example, they have the following characteristics: Figure 13 That kind of circuit structure. Figure 30A and Figure 30B The power supply circuit 1p contains 4 switched capacitors and 4... Figure 16A and Figure 16B Similarly, switching switches SW1 to SW9 can output an output voltage Vout of 2Vin / 3. (See figure for 30A and...) Figure 30B The four switched capacitor circuits 4 are connected to a clock generation circuit 13 that generates four clock signals with different phases.

[0189] exist Figure 30A Under the power supply condition, the output capacitance viewed from node 2 n2 becomes 2C × 4 = 8C. Figure 30B Under the condition of capacitor supply, the output capacitance from the perspective of node 2 n2 becomes C / 2×4=2C.

[0190] like Figure 30A and Figure 30B In that case, even if all the switched capacitor circuits 4 in the power supply circuit 1p are working in an interleaved manner and simultaneously in either a power supply state or a capacitor supply state, the capacitance on the output side as seen from the second node n2 will be significantly different in the power supply state and the capacitor supply state, resulting in fluctuations in the output voltage Vout.

[0191] Therefore, with Figure 25A and Figure 25B Similarly, consider switching multiple switching capacitor circuits 4 within the power supply circuit 1p alternately to either the first switching state or the second switching state to make it work.

[0192] Figure 31A This diagram illustrates an example of how the four switched capacitor circuits 4 within the power supply circuit 1q operate in the first switching state. Figure 31BThis diagram illustrates an example of the four switched capacitor circuits 4 within the power supply circuit 1q operating in the second switching state. Figure 31A and Figure 31B The four switched capacitors in the power supply circuit 1q can be connected with... Figure 30A and Figure 30B Similarly, output voltage Vout is 2Vin / 3.

[0193] like Figure 31A As shown, in the first switching state, the odd-numbered (ODD) switched capacitor circuit 4 operates in the power supply state, and the even-numbered (EVEN) switched capacitor circuit 4 operates in the capacitor supply state. Additionally, as... Figure 31B As shown, in the second switching state, the odd-numbered (ODD) switching capacitor circuit 4 is operated in the capacitor supply state, and the even-numbered (EVEN) switching capacitor circuit 4 is operated in the power supply state.

[0194] The output capacitance from node n2 of the switched capacitor circuit 4 operating in power supply mode is 2C, and the output capacitance from node n2 of the switched capacitor circuit 4 operating in capacitor supply mode is C / 2. In either the first or second switching state, two of the four switched capacitor circuits 4 operate in power supply mode, and the remaining two operate in capacitor supply mode. Therefore, in either the first or second switching state, the input capacitance from node n2 is C / 2 × 2 + 2C × 2 = 5C.

[0195] Thus, in Figure 31A and Figure 31B In the power supply circuit 1q, the capacitance on the output side as viewed from the second node n2 is made equal in both the first and second switching states.

[0196] Figure 32 It means from Figure 30A and Figure 30B The fluctuation component of the output voltage Vout of the power supply circuit 1p involved and from Figure 31A and Figure 31B The graph shows the fluctuation components of the output voltage Vout of the power supply circuit 1q involved. Figure 32 The waveform w77 indicates from Figure 30A and Figure 30B The fluctuation component of the output voltage Vout of the power supply circuit 1p involved is represented by waveform w78. Figure 31A and Figure 31B The fluctuation component of the output voltage Vout of the power supply circuit 1q is involved. As can be seen by comparing waveforms w77 and w78, Figure 31A and Figure 31B The power supply circuit involved is 1q and Figure 30A and Figure 30B Compared to the power supply circuit 1p involved, it can significantly suppress fluctuation components.

[0197] Figure 33A It means from Figure 31A and Figure 31B The diagram shows the waveform of the output voltage Vout from the power supply circuit 1q involved. Figure 33B It means from Figure 30A and Figure 30B The waveform of the output voltage Vout of the power supply circuit 1p involved is shown in the figure. Figure 33A The vertical axis and Figure 33B The vertical axis represents voltage, showing the same voltage range. Figure 33A Waveforms w81 to w87 represent the voltage waveforms corresponding to seven different variations in the load current that causes the output voltage Vout from power supply circuit 1q to change. Similarly, Figure 33B The waveforms w91 to w97 represent the voltage waveforms corresponding to seven different variations in the load current that causes the output voltage Vout from the power supply circuit 1p.

[0198] For comparison Figure 33A and Figure 33B As can be seen from the waveform, from Figure 31A and Figure 31B The voltage variation ratio of the output voltage Vout of the power supply circuit 1q involved is from... Figure 30A and Figure 30B The output voltage Vout of the power supply circuit 1p has less voltage fluctuation, which can make the voltage level more stable.

[0199] Thus, in the power supply circuits 1i, 1k, 1n, and 1q according to the third embodiment, a plurality of switched capacitor circuits 4 connected in parallel between the first node n1, which is supplied with input voltage Vin, and the second node n2, which outputs output voltage Vout, are alternately switched to either a first switching state or a second switching state. In either the first or second switching state, the same number of switched capacitor circuits 4 operating in the power supply state and the same number of switched capacitor circuits 4 operating in the capacitor supply state are included. Therefore, the capacitance on the output side as viewed from the second node n2 can be made equal in both the first and second switching states. This suppresses fluctuations in the output voltage Vout.

[0200] Furthermore, in the power supply circuits 1n and 1q according to the third embodiment, the multiple switched capacitor circuits 4 connected in parallel can be interleaved, thus further suppressing the fluctuation of the output voltage Vout.

[0201] The power supply circuits 1i, 1k, 1n, and 1q in the third embodiment described above can be configured similarly to the power supply circuit 1 in the first embodiment, with an SC-DCDCC2a and an analog LDO3a connected in parallel between the first node n1 and the second node n2. For example, Figure 31A As shown, in the third embodiment, the power supply circuits 1i, 1k, 1n, and 1q are connected in parallel between the first node n1 and the second node n2, thus, by simulating LDO3a by connecting them in parallel, the same effect as in the first embodiment can be obtained.

[0202] (Fourth implementation)

[0203] Figure 34 This is a block diagram showing the schematic structure of the power supply circuit 1r according to the fourth embodiment. Figure 34 The power supply circuit 1r includes multiple SC-DCDCC2b, multiple analog LDO3a, a first comparator 7a, a second comparator 7b, a ramp counter 21, a shift register 22, a switch control circuit 23, and a clock generation circuit 13. The first comparator 7a, the second comparator 7b, the ramp counter 21, the shift register 22, and the switch control circuit 23 constitute a closed-loop control circuit 6. The shift register 22 corresponds to... Figure 1 The control signal generator 6a and the switch control circuit 23 correspond to Figure 1 The switching control circuit 6b.

[0204] Each SC-DCDCC2b is either SC-DCDCC2 or SC-DCDCC2a described in one of the embodiments from the first to the third embodiment. Each simulated LDO3a has the same characteristics as... Figure 3 The simulated LDO3a has the same internal structure. For example... Figure 3 As shown, Figure 34 Each SC-DCDCC2b and each analog LDO3a are connected in parallel between the first node n1, which is supplied with input voltage Vin, and the second node n2, which outputs output voltage Vout. Figure 34 This represents an example with multiple SC-DCDCC2b and multiple simulated LDO3a, but there is no particular limitation on the number of SC-DCDCC2b and simulated LDO3a. Multiple SC-DCDCC2b are, for example, as shown below. Figure 18 or Figure 20 That's how it's structured. Also, as... Figure 31A and Figure 31B In this way, multiple SC-DCDCC2b can also work by alternately switching between the first switching state and the second switching state.

[0205] The first comparator 7a outputs a signal corresponding to the voltage difference between the output voltage Vout output from the second node n2 of the power supply circuit 1r and the first reference voltage Vref1. The first reference voltage Vref1 is a voltage that defines the upper limit of the output voltage Vout. When the output voltage Vout becomes higher than the first reference voltage Vref1, the first comparator 7a outputs, for example, a high-level down signal.

[0206] The second comparator 7b outputs a signal corresponding to the voltage difference between the output voltage Vout output from the second node n2 of the power supply circuit 1r and the second reference voltage Vref2. The second reference voltage Vref2 is a voltage that defines the lower limit voltage of the output voltage Vout. The second reference voltage Vref2 is a voltage level lower than the first reference voltage. When the output voltage Vout becomes lower than the second reference voltage Vref2, the second comparator 7b outputs, for example, a high-level up signal.

[0207] The ramp counter 21 decreases its count value when a down signal is output from the first comparator 7a, and increases its count value when a up signal is output from the second comparator 7b. The shift register 22 shifts the control signal according to the count value of the ramp counter 21.

[0208] The switching control circuit 23 switches the operating states of multiple SC-DCDCC2b based on the control signal output from the shift register 22. For example, when multiple SC-DCDCC2b can output DC voltage Vin / 2 or Vin / 3, the ratio of the number of SC-DCDCC2b outputting Vin / 2 to the number outputting Vin / 3 is controlled based on the state of the control signal from the shift register 22, thus enabling... Figure 19A and Figure 19B As shown, finely adjust the voltage level of the output voltage Vout.

[0209] Clock generation circuit 13 generates clock signals that are supplied to the plurality of SC-DCDCC2b respectively. Clock generation circuit 13 may be configured, for example, as a ring oscillator (Ring VCO). When the plurality of SC-DCDCC2b are interleaved, clock signals with different phases are supplied to each SC-DCDCC2b. Each SC-DCDCC2b periodically switches between voltage supply state and capacitor supply state in sync with its corresponding clock signal. As described in the third embodiment, the plurality of SC-DCDCC2b may also be divided into a first switching state and a second switching state for alternating operation.

[0210] exist Figure 34In the power supply circuit 1r, the capacitor in the switched capacitor circuit 4 of SC-DCDCC2b can be used as the output capacitor CL of the analog LDO3a. Therefore, it is not necessary to set the output capacitor CL of the analog LDO3a separately, which can reduce the circuit area.

[0211] Figure 34 The analog LDO3a in the power supply circuit 1r has a first transistor Q1 and a second transistor Q2 composed of NMOS transistors, but it can also be set as a PMOS transistor.

[0212] Figure 35 This is a block diagram of a power supply circuit 1s that uses an analog LDO3b with a PMOS transistor. Figure 35 The power supply circuit 1s, except that it makes the first transistor Q1 and the second transistor Q2 in the analog LDO3b PMOS transistors and reverses the wiring connected to the inverting and non-inverting input terminals of the control amplifier 7, is similar to... Figure 34 The power supply circuit 1r is the same.

[0213] exist Figure 34 and Figure 35 In the power supply circuits 1r and 1s, multiple SC-DCDCC2b and multiple analog LDO3a and 3b are connected in parallel between the first node n1 and the second node n2. Therefore, the power supply circuits 1r and 1s can flow the current corresponding to the load circuit 5, and can flow a sufficient amount of current in the load circuit 5 without unnecessarily increasing the circuit area of ​​the SC-DCDCC2b and analog LDO3a and 3b. Furthermore, as... Figure 3 As shown, the SC-DCDCC2b is controlled by the closed-loop control circuit 6, and the analog LDO3a and 3b are controlled by the open-loop control circuit 8. Therefore, the dual-loop control can be avoided and the operation can be stabilized.

[0214] Furthermore, by interleaving multiple SC-DCDCC2b within 1r and 1s of the power supply circuit, fluctuations in the output voltage Vout can be suppressed.

[0215] (Fifth implementation)

[0216] Figure 36 This is a block diagram showing the general structure of the power supply circuit 1t according to the fifth embodiment. Figure 36 The power supply circuit 1t includes multiple SC-DCDCC2b, multiple analog LDO3a, a first comparator 7a, a second comparator 7b, a ramp counter 21, a shift register 22, a switch control circuit 23, and a clock generation circuit 13. Among them, the first comparator 7a, the second comparator 7b, the ramp counter 21, the shift register 22, and the clock generation circuit 13 constitute a closed-loop control circuit 6.

[0217] exist Figure 34 In the power supply circuit 1r, based on the control signal output from the shift register 22, the switch control circuit 23 switches the operating states of multiple SC-DCDCC2b, but... Figure 36 In the power supply circuit 1t, the control signal output from the shift register 22 is not input to the switch control circuit 23, but rather to the clock generation circuit 13. Based on the control signal output from the shift register 22, the clock generation circuit 13 switches the number of clock signals supplied to the multiple SC-DCDCC2b. The multiple SC-DCDCC2b cannot output voltage unless they are supplied with their corresponding clock signals from the clock generation circuit 13. Therefore, the more clock signals generated by the clock generation circuit 13, the higher the combined driving capability of the multiple SC-DCDCC2b, and the more controllable the driving capability of the output voltage Vout can be according to the load.

[0218] In addition, Figure 36 In the power supply circuit 1t, the control operation of the switch control circuit 23 is set to be fixed. Therefore, the control operation of the switch control circuit 23 does not need to be changed, which simplifies the internal structure of the switch control circuit 23.

[0219] Thus, in the fifth embodiment, the number of clock signals generated in the clock generation circuit 13 is adjusted according to the voltage level of the output voltage Vout output from the second node n2 of the power supply circuit 1t. Therefore, the driving capability of the multiple SC-DCDCC2b can be controlled according to the voltage level of the output voltage Vout, and the driving capability of the output voltage Vout can be controlled.

[0220] (Sixth implementation)

[0221] Figure 37 This is a block diagram showing the schematic structure of the power supply circuit 1u according to the sixth embodiment. Figure 37 The power supply circuit 1u includes multiple SC-DCDCC2b, multiple analog LDO3a, a first comparator 7a, a second comparator 7b, a ramp counter 21, a shift register 22, a switch control circuit 23, and a clock generation circuit 13. Among them, the first comparator 7a, the second comparator 7b, the ramp counter 21, the shift register 22, the switch control circuit 23, and the clock generation circuit 13 constitute a closed-loop control circuit 6.

[0222] Figure 37The power supply circuit 1u controls the output voltage Vout based on the control signals output from the shift register 22 by both the switch control circuit 23 and the clock generation circuit 13. The switch control circuit 23 switches the operating states of the multiple SC-DCDCC2s based on the control signals output from the shift register 22. The clock generation circuit 13 controls the frequency of multiple clock signals supplied to the multiple SC-DCDCC2b based on the control signals output from the shift register 22. By controlling the frequency of the clock signals supplied to each SC-DCDCC2b, the output voltage output from each SC-DCDCC2b can be controlled. Each SC-DCDCC2b generates a voltage synchronously with its corresponding clock signal. By varying the frequency according to the load, voltage adjustment corresponding to the load can be performed.

[0223] Thus, in Figure 37 In the power supply circuit 1u, based on the control signal output from the shift register 22, the switch control circuit 23 controls the switching of the operating states of multiple SC-DCDCC2, and the clock generation circuit 13 controls the frequency of multiple clock signals. This allows for more precise control of the output voltage Vout, and by making the frequency variable according to the load, improved power efficiency can be achieved.

[0224] (Seventh implementation)

[0225] In the first to sixth embodiments described above, examples of closed-loop control of SC-DCDCC2, 2a, and 2b and open-loop control of simulated LDO3, 3a, and 3b were mainly described. In contrast, the power supply circuit 1V involved in the seventh embodiment described below has three operating modes (first operating mode to third operating mode).

[0226] Figure 38A , Figure 38B as well as Figure 38C This is for what is described later. Figure 39 The diagram illustrates the first to third operating modes of the power supply circuit 1V according to the seventh embodiment. Figure 38A The first operating mode shown is a mode in which SC-DCDCC2b performs closed-loop control and simulates LDO3a for open-loop control. Figure 38B The second operating mode shown is the mode in which SC-DCDCC2b performs closed-loop control and simulates the LDO3a stopping operation. Figure 38C The third operating mode shown is a mode that simulates LDO3a for closed-loop control and stops SC-DCDCC2b. Figure 38A , Figure 38B , Figure 38CThis represents an example of selecting one of the operating modes from 1 to 3 in the mode selection circuit 24, but setting up the mode selection circuit 24 is not mandatory.

[0227] The first operating mode is selected, for example, when both power efficiency and high PSRR (Power Supply Rejection Ratio) are required. The second operating mode is selected, for example, when high power efficiency is particularly required. The third operating mode is selected, for example, when high PSRR is required.

[0228] Figure 39 This is a block diagram showing the schematic structure of the power supply circuit 1V according to the seventh embodiment. Figure 39 The power supply circuit is 1V in relation to Figure 34 The power supply circuit 1r, with the same structure, includes a mode selection circuit 24. The mode selection circuit 24 selects one of the aforementioned first to third operating modes. When stopping the operation of multiple SC-DCDCC2b, the mode selection circuit 24, for example, stops the generation of the clock signal in the clock generation circuit 13. Furthermore, when stopping the operation of multiple analog LDO3a, the mode selection circuit 24, for example, disables the control amplifier 7 within each analog LDO3a.

[0229] Thus, in the seventh embodiment, multiple operating modes are provided for switching between the operation of SC-DCDCC2b and the analog LDO3a. Therefore, SC-DCDCC2b and the analog LDO3a can be used separately according to different usage scenarios. This expands the application range of the 1V power supply circuit and increases its utilization value.

[0230] (Eighth embodiment)

[0231] The power supply circuit 1 described in the first to seventh embodiments above can be used for various applications. In particular, the power supply circuit 1 described in the first to seventh embodiments has excellent power efficiency, low fluctuation of the output voltage Vout, and can finely control the voltage level of the output voltage Vout. Therefore, it can be applied to a power supply circuit 1 for semiconductor integrated circuits driven with low power consumption and low voltage. At that time, the entire power supply circuit 1 can be formed on a semiconductor substrate, including the capacitor in the switched capacitor circuit 4.

[0232] Figure 40 This is a block diagram showing a schematic structure of a semiconductor integrated circuit 25 having the power supply circuit 1 according to embodiments 1 to 7. Figure 40The semiconductor integrated circuit 25 includes a power supply circuit 1 and an application circuit 26 as described in embodiments 1 to 7. The specific circuit structure of the application circuit 26 is not limited. The application circuit 26 can be any circuit that uses the output voltage Vout from the power supply circuit 1, and can be either a digital circuit or an analog circuit. For example, the application circuit 26 can also be a processor, a controller, or its peripheral circuitry. Alternatively, the application circuit 26 can also be a semiconductor memory, a memory controller, or its peripheral circuitry. Alternatively, the application circuit 26 can also be a signal transmission circuit, a communication circuit, an interface circuit, etc.

[0233] Thus, the power supply circuit 1 according to the first to seventh embodiments can be installed inside various semiconductor integrated circuits 25, and therefore can be incorporated into various ICs (Integrated Circuits).

[0234] The technical solutions disclosed herein are not limited to the various embodiments described above, but also include various modifications that can be conceived by those skilled in the art, and the effects of this disclosure are not limited to the above content. That is, various additions, changes, and partial deletions can be made without departing from the conceptual idea and spirit of this disclosure derived from the content specified in the claims and their equivalents.

Claims

1. A power supply circuit, comprising: The first node is supplied with the input voltage; The second node outputs the first output voltage. Multiple DC-DC converters, each having a switched capacitor, are connected in parallel between the first node and the second node; and The first control circuit individually controls the plurality of DC-DC converters, causing each of the plurality of DC-DC converters to output an inherent second output voltage. The second node outputs the first output voltage obtained by combining the multiple second output voltages output from the multiple DC-DC converters.

2. The power supply circuit according to claim 1, It includes a clock generation circuit, which is associated with the plurality of DC-DC converters and outputs multiple clock signals with different phases. The plurality of DC-DC converters each generate the second output voltage synchronously with the corresponding clock signal among the plurality of clock signals.

3. The power supply circuit according to claim 2, The system includes a second control circuit that controls whether to output each of the plurality of clock signals from the clock generation circuit based on the voltage level of the first output voltage. The DC-DC converter among the plurality of DC-DC converters that is supplied with the corresponding clock signal from the clock generation circuit outputs the corresponding second output voltage. The second node outputs the first output voltage obtained by combining the second voltage output from the DC-DC converters supplied with the clock signal among the plurality of DC-DC converters.

4. The power supply circuit according to any one of claims 1 to 3, The plurality of DC-DC converters includes a first DC-DC converter and a second DC-DC converter. The value of the second output voltage output by the first DC-DC converter is different from the value of the second output voltage output by the second DC-DC converter.

5. The power supply circuit according to any one of claims 1 to 3, Each of the plurality of DC-DC converters has a first switched capacitor circuit and a second switched capacitor circuit having the same configuration as the first switched capacitor circuit. The first switched capacitor circuit and the second switched capacitor circuit are connected in parallel between the first node and the second node.

6. A power supply circuit, comprising: The first node is supplied with the input voltage; The second node will output the voltage. Multiple DC-DC converters are connected in parallel between the first node and the second node; as well as A control circuit individually controls the plurality of DC-DC converters, causing each of the plurality of DC-DC converters to output its inherent voltage. Each of the plurality of DC-DC converters has: The first DC-DC converter circuit includes a first switched capacitor circuit; and The second DC-DC converter circuit includes a second switched capacitor circuit having the same structure as the first switched capacitor circuit. The control circuit alternates between a first switching state and a second switching state. The first switching state is a state in which the first capacitor in the first switched capacitor circuit is charged and the second capacitor in the second switched capacitor circuit is discharged. The second switching state is a state in which the second capacitor in the second switched capacitor circuit is charged and the first capacitor in the first switched capacitor circuit is discharged.

7. The power supply circuit according to claim 6, The control circuit switches the first switched capacitor circuit and the second switched capacitor circuit so that the capacitance of the second node side in the first switching state is equal to the capacitance of the second node side in the second switching state.

8. The power supply circuit according to claim 6 or 7, It includes a clock generation circuit, which is associated with the plurality of DC-DC converters and outputs multiple clock signals with different phases. Each of the plurality of DC-DC converters switches the first switching state and the second switching state of its respective switched capacitor circuit according to the logic of the corresponding clock signal among the plurality of clock signals.

9. The power supply circuit according to claim 6 or 7, Each of the plurality of DC-DC converters has a third switched capacitor circuit and a fourth switched capacitor circuit having the same configuration as the third switched capacitor circuit. The third switched capacitor circuit and the fourth switched capacitor circuit are connected in parallel between the first node and the second node.

10. A semiconductor integrated circuit, comprising: The power supply circuit according to any one of claims 1 to 9; and The circuit operates based on the voltage output from the power supply circuit.

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