Power converter

Abstract

This disclosure relates to a power converter including a first converter stage that receives a first clock signal and a second converter stage that receives a second clock signal. The power converter also includes a clock circuit that generates the first clock signal, the clock circuit being configured to adjust the frequency of the first clock signal based on a load current.

Description

Technical Field

[0001] This disclosure relates to power converters, and more particularly to multi-stage power converters. background Two-stage power converters can be used in a variety of applications, such as to reduce input voltage in two consecutive steps. Existing circuits are limited by relatively poor efficiency, especially under light loads.

[0002] The purpose of this disclosure is to address one or more of the limitations mentioned above.

[0003] Overview According to a first aspect of this disclosure, a power converter is provided, comprising: a first converter stage adapted to receive a first clock signal; a second converter stage adapted to receive a second clock signal; and a clock circuit configured to generate the first clock signal and adjust the frequency of the first clock signal based on a load current.

[0004] Optionally, the clock circuit is configured to increase the frequency of the first clock signal to a frequency higher than the default frequency when the load current increases to a level higher than the first threshold, and to decrease the frequency of the first clock signal to a frequency lower than the default frequency when the load current decreases to a level lower than the second threshold.

[0005] Optionally, the clock circuit is configured to estimate the load current based on a sensing signal from the second converter stage.

[0006] Optionally, the sensing signal includes a voltage indicating the inductor current of the second converter stage.

[0007] Optionally, the clock circuit includes an operating frequency control loop coupled to the oscillator, the operating frequency control loop being configured to generate a control signal to adjust the frequency of a first clock signal generated by the oscillator.

[0008] Optionally, the clock circuit includes multiple comparators, each configured to compare a sensed signal from the second converter stage with a reference value associated with the comparator and provide a comparison signal.

[0009] Optionally, the operating frequency control loop is configured to use a lookup table to estimate the load current, which lists multiple load current values ​​associated with the corresponding sense signal values.

[0010] Optionally, the power converter includes a clock generator configured to generate a second clock signal.

[0011] Optionally, the first converter stage includes one or more capacitive dividers; and the second converter stage includes one or more buck converters.

[0012] Optionally, the first converter stage includes a plurality of series-coupled capacitive voltage dividers, and a clock circuit is configured to provide a first clock signal to at least one capacitive voltage divider.

[0013] Optionally, the first converter stage includes one or more charge pumps; and the second converter stage includes one or more boost converters.

[0014] Optionally, the second converter stage includes multiple phases, and the power converter further includes an integrator configured to sum the sensed signals from each phase.

[0015] According to a second aspect of this disclosure, a method for operating a power converter having a first converter stage and a second converter stage is provided, the method comprising: Generate a first clock signal for the first converter stage; and The frequency of the first clock signal is adjusted based on the load current.

[0016] Optionally, the first clock signal has a default frequency, and the method further includes: Estimate the load current; When the load current increases to above the first threshold, the frequency of the first clock signal is increased to above the default frequency; and When the load current decreases below the second threshold, the frequency of the first clock signal is reduced to below the default frequency.

[0017] Optionally, the method includes maintaining a first clock signal at a default frequency when the load current is between a first threshold and a second threshold. Attached Figure Description

[0018] The present disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which: Figure 1 This is a diagram of a two-stage power converter based on existing technology; Figure 2 yes Figure 1 A diagram of a modified version of a two-stage power converter; Figure 3 This is a flowchart of a method for operating a two-stage power converter according to the present disclosure; Figure 4 It is a diagram of a two-stage power converter according to this disclosure; Figure 5 yes Figure 4 Example implementation of a power converter; Figure 6AThis is an example implementation of a voltage clock control system; Figure 6B It is a lookup table used by the operating frequency control loop circuit; Figure 6C It is used for Figure 6A Example implementation of an oscillator in a circuit; Figure 6D It is shown Figure 6C A graph showing the operation of the oscillator; Figure 7 It is shown Figure 6A The flowchart of the operation of the operating frequency control loop circuit; Figure 8A The diagram is of a multi-output power converter according to this disclosure; Figure 8B This is a diagram of a multiphase single-output power converter; Figure 9 It is used for Figure 8A and Figure 8B Example implementation of a voltage integrator in a circuit; Figure 10A This is a diagram of a power converter with multiple capacitor voltage dividers according to the present disclosure; Figure 10B yes Figure 10A A modified version of the power converter; Figure 11 It is used for Figure 5 Or a diagram of an exemplary capacitive voltage divider in the circuit of Figure 8.

[0019] describe Figure 1 This is a diagram of a two-stage power converter based on existing technology. The first stage includes a capacitive voltage divider for dividing the rail voltage VDD by a predetermined ratio and outputting VDD / N. For example, the capacitive voltage divider could be 2:1 to divide VDD by 2, or 3:1 to divide VDD by 3, and so on.

[0020] The second stage includes a buck converter that receives the output VDD / N from the first stage and provides an output voltage Vout. A capacitive voltage divider receives a first clock signal CLK1 from a first clock generator. Similarly, the buck converter receives a second clock signal CLK2 from a second clock generator. Both clock signals CLK1 and CLK2 are fixed.

[0021] Figure 2 yes Figure 1 A diagram of a modified version of a two-stage power converter. In this example, a single clock generator is used to generate fixed clock signals CLK1 and CLK2. Figure 1 and Figure 2In the described circuit, the capacitive voltage divider has high gate drive losses under light loads, thus reducing the system efficiency.

[0022] Figure 3 This is a flowchart of a method for operating a power converter having a first converter stage and a second converter stage according to the present disclosure. At step 310, a first clock signal for the first converter stage is generated. At step 320, the frequency of the first clock signal is adjusted based on the load current.

[0023] For example, before adjusting the frequency of the first clock signal, the load current can be estimated and compared with a predetermined threshold. Two load current thresholds can be used: a first threshold, also known as the high threshold; and a second threshold, also known as the low threshold.

[0024] In this example, the frequency of the first clock signal is increased when the load current (or estimated value) increases above a first threshold, and the frequency of the first clock signal is decreased when the load current (or estimated value) decreases below a second threshold. This method allows for improved efficiency under light current loads. It also improves drive capability under heavy loads.

[0025] Figure 4 This is a diagram of a two-stage power converter according to the present disclosure. The power converter 400 includes two converter stages 410 and 420 and a clock circuit 430. The first converter stage 410 is adapted to receive a first clock signal. The second converter stage 420 is adapted to receive a second clock signal. The clock circuit 430 is configured to generate the first clock signal and adjust the frequency of the first clock signal based on the load current. A clock generator 440 is provided to generate the second clock signal.

[0026] The power converter 400 can be implemented as a step-down converter. In this case, the first converter stage 410 will include one or more capacitive voltage dividers, and the second stage 420 will include one or more buck converters.

[0027] The power converter 400 can also be implemented as a step-up converter. In this case, the first converter stage 410 will include one or more charge pumps, and the second stage 420 will include one or more boost converters.

[0028] In operation, clock circuit 430 receives a sensing signal, such as current sensing voltage Vcs, from second converter stage 420 and provides clock signal CLK1_VCCS to first converter stage 410. Current sensing voltage Vcs indicates the current IL passing through the inductor of second converter stage 420.

[0029] Figure 5 is Figure 4 An example implementation of a power converter. In this example, the first converter stage 510 includes a capacitive voltage divider, and the second converter stage 520 includes a buck converter. The clock circuit 530 is implemented as a voltage clock control system (VCCS).

[0030] In operation, the VCCS 530 receives the current sense voltage Vcs from the buck converter 520 and provides the clock signal CLK1_VCCS to the capacitive voltage divider 510. The current sense voltage Vcs indicates the current IL through the inductor of the buck converter. The voltage Vcs can be obtained in different ways. For example, Vcs can be related to the drain-to-source voltage Vds of the high-side power switch or the low-side power switch of the buck converter.

[0031] Figure 6A is an example implementation of a voltage clock control system. The voltage clock control system 600 includes a plurality of K + 1 comparators 610 - 61K coupled to an operating frequency control loop (OFCL) 620. Each comparator has a first input terminal (e.g., non-inverting input terminal) for receiving the voltage Vcs and a second input terminal (e.g., inverting input terminal) for receiving a reference voltage Vrefi, where Vrefi is a reference voltage specific to the comparator. The comparator 610 has a reference voltage Vref0, the comparator 611 has a reference voltage Vref1, and the comparator 61K has a reference voltage VrefK. The voltages Vref0, Vref1,..., VrefK can be selected such that Vref0 < Vref1 < Vref2... < VrefK. In a numerical example, K = 7, and each reference voltage increases by an equal amount of 0.1V, such that Vref0 = 0.1V, Vref1 = 0.2V, Vref7 = 0.8V.

[0032] The output of each comparator is a comparison signal indicating whether Vcs is less than Vref or greater than Vref. If Vcs is less than Vref, the comparator output has a comparison signal with a logical low (logical 0). If Vcs is greater than Vref, the comparator output has a comparison signal with a logical high (logical 1).

[0033] The OFCL 620 receives the comparison signals S0, S1,..., SK from each of the comparators 610 - 61K and generates a control signal Freq_sel<1:0> to adjust the frequency of the clock signal generated by the oscillator 630. The OFCL 620 can be implemented as a digital circuit.

[0034] Figure 6BAn exemplary lookup table for use in the operating frequency control loop is shown. For different Vcs voltage values, the lookup table provides the corresponding load current value iLoad. OFCL uses comparison signals S0, S1…SK to identify Vcs and the corresponding current load. Different iLoad ranges correspond to different control signal values. The frequency of the first clock is then adjusted using the control signal Freq_sel<1:0>. In this example, Freq_sel<1:0> = 01 maintains the frequency at 1MHz. When Freq_sel<1:0> = 00, the frequency decreases to 0.5MHz, and when Freq_sel<1:0> = 10 / 11, the frequency increases to 1.5MHz.

[0035] Figure 6C It is used for Figure 6A An example implementation of an oscillator in a circuit. In this example, oscillator 630 includes two current sources 631 and 632, which are coupled at node O and provide currents Iup and Idn, respectively. A variable capacitor 633 has a first terminal coupled to node O and a second terminal coupled to ground. A Schmitt trigger has an input coupled to node O and an output coupled to a buffer at node O'. The output of the buffer provides a clock signal CLK1_VCCS. A first switch M1 connects 631 to the input voltage, and a second switch M2 connects 632 to ground. The gate of M1 is coupled to the gate of M2 at node O' and to the output of the Schmitt trigger.

[0036] Figure 6D It is shown Figure 6C The graph shows the operation of the oscillator, including the voltage Va at node O, the voltage Vb at node O', and the clock signal CLK1_VCCS. During operation, the control signal Freq_sel<1:0> is used to change the capacitance C of the variable capacitor 633, thereby adjusting the frequency of the clock signal CLK1_VCCS.

[0037] Figure 7 It is shown Figure 6A The flowchart shows the operation of the operating frequency control loop circuit. Various parameters are defined as follows: Vth1 is the first threshold voltage used to set the number N (i.e., the ratio N:1 of the capacitive voltage divider). Vth2 is the second threshold voltage used to set the number N. The default frequency is a predefined value, such as 1MHz.

[0038] Period_H is the time period during which a higher frequency equal to the default frequency * Rate_H is maintained.

[0039] Period_L is the period of time during which a lower frequency equal to the default frequency * Rate_L is maintained.

[0040] Period_M is the time period during which the intermediate frequency is maintained at 100% of the default frequency.

[0041] Rate_H is the ratio with a higher frequency. Rate_L is the ratio with a lower frequency. The ratio can be expressed as a percentage of the default frequency, such as greater than 100% or less than 100%.

[0042] I_TH_H is the load current threshold used to switch to a higher operating frequency of the capacitive voltage divider. I_TH_L is the load current threshold used to switch to a lower operating frequency of the capacitive voltage divider.

[0043] Initially, OFCL selects the ratio N:1 of the capacitive voltage divider based on the threshold voltages Vth1 and Vth2, making... (VOUT+Vth1)>(VIN / N)>(VOUT+Vth2).

[0044] Then, the clock signal CLK1_VCCS is set to the default frequency. The function to adjust the clock frequency can be activated as ON / OFF based on the efficiency of the power converter. This function is enabled at relatively low efficiency. The frequency of the clock signal is then adjusted based on two current thresholds, I_TH_H and I_TH_L.

[0045] When ILoad is between I_TH_H and I_TH_L, the clock signal frequency is maintained at the default frequency.

[0046] When ILoad is greater than I_TH_H, the frequency of the clock signal is increased. The switching frequency of the capacitive voltage divider becomes higher to provide sufficient drive capability.

[0047] When ILoad is lower than I_TH_L, the frequency of the clock signal is reduced. Therefore, the switching frequency of the capacitive voltage divider becomes lower, thereby reducing gate drive losses.

[0048] In the example numerical example, the above parameter can be set to the following values: Vth1: 1V, Vth2: 0.3V Default frequency: 1MHz Period_H: 1ms, Period_L: 1ms, Period_M: 1ms Rate_H: 150%, Rate_L: 50% I_TH_H: 2.8A, I_TH_L: 1.2A supply Figure 7The flowchart above is for the case where a power converter is implemented for buck conversion. For a power converter implemented for boost conversion, the flowchart will remain the same except for the first step (after the start). In this scenario, after the start, OFCL will select the charge pump factor N based on the threshold voltages Vth1 and Vth2, such that (VOUT+Vth1)>(VIN*N)>(VOUT+Vth2).

[0049] Figure 8A This is a diagram of a multi-output power converter according to this disclosure. The power converter 800 is similar to... Figure 5 The power converter 500, however, in this example, the second converter stage includes multiple buck converters coupled to the voltage integrator 850.

[0050] The power converter 800 includes a first converter stage 810, which includes a capacitive voltage divider. A second converter stage includes M buck converters 821-82M, thus providing multiple outputs: OUT1, OUT2, ..., OUTM. A clock generator 840 is provided to generate a second clock signal to be received by each of the buck converters 821-82M. A voltage integrator 850 is provided to couple the multiple buck converters to a voltage clock control system 830.

[0051] In operation, the voltage integrator 850 receives current-sensing voltages Vcs_1 to Vcs_M from the buck converters 821-82M and generates a summed voltage Vcs_sum, which is equal to the sum of voltages Vcs_1 to Vcs_M. The VCCS 830 uses the voltage Vcs_sum to obtain the total load current iLoad_total for the outputs (OUT1-OUTM). Therefore, Vcs_sum corresponds to iLoad_total = IOUT1 + IOUT2 ​​+ ... + IOUTM.

[0052] VCCS 830 receives the summed voltage Vcs_sum and generates a first clock signal CLK_VCCS for use by the capacitive voltage divider 810. As described above, VCCS 830 also adjusts the frequency of the clock signal CLK_VCCS received by the capacitive voltage divider 810. Therefore, the capacitive voltage divider 810 has good efficiency under light loads and good drive capability under heavy loads.

[0053] Figure 8B This is a diagram of a multiphase single-output power converter. The power converter 800' is similar to... Figure 8A The power converter is 800, but in this example, the output of each buck converter is combined to provide a single output. In this case, Vcs_sum corresponds to iLoad (=IOUT).

[0054] Figure 9 It is used for Figure 8A and Figure 8B An example implementation of a voltage integrator in a circuit. The voltage integrator 900 includes M cells, each formed by a current mirror coupled to a resistor Ri. For example, cell 910 has a current mirror coupled to resistor R1 and outputs a current Ics_1.

[0055] The output of the first unit is connected to the output of the second unit, and so on, to obtain a total current Itotal equal to the sum of Ics_1 to Ics_M. The total current Itotal is then sent to the output resistor Rout. The resistor Rout is chosen to be equal for each unit and equal to the output resistor Rout, such that Vcs_sum = Vcs_1 + Vcs_2 + ... + Vcs_M.

[0056] Figure 10A This is a diagram of a power converter with multiple capacitor voltage dividers according to this disclosure. The power converter 1000 is similar to... Figure 5 The power converter 500 uses the same reference numerals to denote corresponding components, but in this example, the first converter stage includes multiple capacitive voltage dividers. In this example, two capacitive voltage dividers 1010 and 1011 are provided, and VCCS 530 provides a first clock signal CLK1_VCCS to the first capacitive voltage divider 1010.

[0057] Figure 10B yes Figure 10A This is a modified version of the power converter. In this example, the VCCS 530 provides a first clock signal CLK1_VCCS to the second capacitive voltage divider 1011. The VCCS 530 adjusts the CLK_VCCS frequency to adjust one of the capacitive voltage divider's capabilities to achieve good efficiency under light loads and good drive capability under heavy loads.

[0058] In alternative implementations, similar to Figure 10A and Figure 10B In its design, the VCCS 530 is configured to send the clock signal to both capacitive voltage dividers 1010 and 1011. It should be understood that the number of capacitive voltage dividers can be extended to more than two, and the VCCS 530 can be implemented to send the clock signal CLK1_VCCS to only one capacitive voltage divider, or to two capacitive voltage dividers, or to more than two capacitive voltage dividers, or to all capacitive voltage dividers present in the circuit.

[0059] The power converter disclosed herein can maintain high efficiency under light current loads and improve drive capability under heavy loads.

[0060] use Figure 10A or Figure 10B The design facilitates the implementation of capacitive voltage divider circuits. For example, in Figure 5 In this example, the capacitive voltage divider 510 may require a switching circuit coupled to several capacitors, and the switches of this switching circuit are operated (open or close) to select a desired ratio N:1, such as 4:1. This switching circuit may require several switches with significant power ratings.

[0061] A simpler design can be achieved by using multiple capacitive voltage dividers in series. For example, a desired ratio of 4:1 can be obtained by using a first capacitive voltage divider with a 2:1 ratio and a second capacitive voltage divider with a 2:1 ratio.

[0062] Figure 11 It is used for Figure 5 Or a diagram of an exemplary capacitive voltage divider in the circuit of Figure 8. The capacitive voltage divider 1100 has two capacitors Cf and eight switches SW1-SW8, which can operate between phase 1 (Ф1) and phase 2 (Ф2) to provide a 2:1 ratio.

[0063] As referenced above Figure 4 As explained, when the power converter 400 is implemented as a boost converter, the first converter stage will include one or more charge pumps, and the second converter stage will include one or more boost converters.

[0064] Therefore, those skilled in the art will understand that variations in the disclosed arrangement are possible without departing from this disclosure. Thus, the above description of specific embodiments has been made by way of example only and not for limiting purposes. Those skilled in the art will appreciate that minor modifications can be made without significantly altering the described operation.

Claims

1. A power converter, comprising A first converter stage, adapted to receive a first clock signal; A second converter stage, adapted to receive a second clock signal; and A clock circuit is configured to generate the first clock signal and adjust the frequency of the first clock signal based on the load current.

2. The power converter according to claim 1, wherein, The clock circuit is configured to increase the frequency of the first clock signal to a frequency higher than a default frequency when the load current increases to a level higher than a first threshold, and to decrease the frequency of the first clock signal to a frequency lower than the default frequency when the load current decreases to a level lower than a second threshold.

3. The power converter according to claim 1, wherein, The clock circuit is configured to estimate the load current based on a sensing signal from the second converter stage.

4. The power converter according to claim 3, wherein, The sensing signal includes a voltage indicating the inductor current of the second converter stage.

5. The power converter according to claim 3, wherein, The clock circuit includes an operating frequency control loop coupled to an oscillator, the operating frequency control loop being configured to generate a control signal to adjust the frequency of the first clock signal generated by the oscillator.

6. The power converter according to claim 5, wherein, The clock circuit includes a plurality of comparators, each comparator being configured to compare the sensed signal from the second converter stage with a reference value associated with the comparator and provide a comparison signal.

7. The power converter according to claim 6, wherein, The operating frequency control loop is configured to use a lookup table to estimate the load current, the lookup table listing multiple load current values ​​associated with corresponding sense signal values.

8. The power converter of claim 1, further comprising a clock generator configured to generate the second clock signal.

9. The power converter according to claim 1, wherein, The first converter stage includes one or more capacitive voltage dividers; and the second converter stage includes one or more buck converters.

10. The power converter according to claim 1, wherein, The first converter stage includes a plurality of series-coupled capacitive voltage dividers, wherein the clock circuit is configured to provide the first clock signal to at least one of the capacitive voltage dividers.

11. The power converter according to claim 1, wherein, The first converter stage includes one or more charge pumps; and the second converter stage includes one or more boost converters.

12. The power converter according to claim 1, wherein, The second converter stage includes multiple phases, and the power converter further includes an integrator configured to sum the sensed signals from each phase.

13. A method of operating a power converter, the power converter having a first converter stage and a second converter stage, the method comprising: Generate a first clock signal for the first converter stage; as well as The frequency of the first clock signal is adjusted based on the load current.

14. The method according to claim 13, wherein, The first clock signal has a default frequency, and the method further includes: Estimate the load current; When the load current increases to a level higher than the first threshold, the frequency of the first clock signal is increased to a level higher than the default frequency; and When the load current decreases to below the second threshold, the frequency of the first clock signal is reduced to below the default frequency.

15. The method of claim 14, further comprising maintaining the first clock signal having the default frequency when the load current is between the first threshold and the second threshold.

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