Charge boosting circuit and control method thereof, and power management chip

Abstract

This application provides a charge boosting circuit and its control method, as well as a power management chip. The charge boosting circuit includes a main charge boosting module and an auxiliary charge boosting module. The output terminal of the main charge boosting module is configured to output a boosted voltage. The first and second control terminals of the auxiliary charge boosting module are configured to receive a second clock signal and a second inverted clock signal, respectively, and the input terminal is configured to input a bus voltage. The output terminal of the auxiliary charge boosting module is electrically connected to the substrate of the field-effect transistor (FET) of the main charge boosting module and is configured to output a bias voltage to the substrate of the FET of the main charge boosting module to boost the substrate voltage of the FET. Embodiments of this application can reduce the threshold voltage of the FET of the main charge boosting module, thereby improving the voltage conversion efficiency of the main charge boosting module.

Description

Technical Field

[0001] This application relates to the field of chip circuit technology, and more specifically, to a charge boosting circuit and its control method, as well as a power management chip. Background Technology

[0002] In recent years, with the miniaturization and high performance of electronic devices, the demand for efficient and stable power management chips has been increasing. Traditional charge boosting circuits mostly adopt a cascaded structure of multi-stage capacitors and MOSFETs (field-effect transistors) that are electrically connected and are equivalent to diodes, and achieve voltage boosting step by step through two-phase clock control.

[0003] However, in traditional charge boosting circuits, each charge boosting unit needs to overcome the threshold voltage of the MOSFET, which causes the output voltage to decrease nonlinearly with the number of stages, resulting in low voltage conversion efficiency of the charge boosting circuit. Summary of the Invention

[0004] This application addresses the shortcomings of existing methods by proposing a charge boosting circuit, its control method, and a power management chip to solve the technical problem of low voltage conversion efficiency in charge boosting circuits.

[0005] In a first aspect, embodiments of this application provide a charge boosting circuit, comprising: The main charge boosting module has a first control terminal and a second control terminal configured to receive a first clock signal and a first inverted clock signal, respectively. The input terminal is configured to input the bus voltage, and the output terminal is configured to output the boosted voltage. The auxiliary charge boosting module has a first control terminal and a second control terminal configured to receive a second clock signal and a second inverted clock signal, respectively; an input terminal configured to input a bus voltage; and an output terminal electrically connected to the substrate of the field-effect transistor of the main charge boosting module, configured to output a bias voltage to the substrate of the field-effect transistor of the main charge boosting module to boost the substrate voltage of the field-effect transistor of the main charge boosting module.

[0006] Optionally, the main charge boosting module includes: a first N-type field-effect transistor and a second N-type field-effect transistor with cross-coupled electrical connection, a first P-type field-effect transistor and a second P-type field-effect transistor with cross-coupled electrical connection, and a first pump capacitor and a second pump capacitor; The input terminal of the main charge boosting module includes the first terminal of each of the first N-type field-effect transistor and the second N-type field-effect transistor; The gates of the second N-type field-effect transistor and the first P-type field-effect transistor are each electrically connected to the first terminal of the first pump capacitor; The gates of the first N-type field-effect transistor and the second P-type field-effect transistor are each electrically connected to the first terminal of the second pump capacitor; The output terminal of the main charge boosting module includes the first terminal of each of the first P-type field-effect transistor and the second P-type field-effect transistor; The first control terminal and the second control terminal of the main charge boosting module respectively include the second terminal of the first pump capacitor and the second terminal of the second pump capacitor.

[0007] Optionally, the substrate and the first terminal of the first P-type field-effect transistor are electrically connected; The substrate of the second P-type field-effect transistor is electrically connected to the first terminal.

[0008] Optionally, both the first N-type field-effect transistor and the second N-type field-effect transistor are N-type field-effect transistors; Both the first P-type field-effect transistor and the second P-type field-effect transistor are P-type field-effect transistors.

[0009] Optionally, the main charge boosting module further includes: The main charge boosting module includes a first terminal of the output capacitor at its input terminal and a second terminal of the output capacitor at its output terminal.

[0010] Optionally, the auxiliary charge boosting module includes: a third N-type field-effect transistor and a fourth N-type field-effect transistor with cross-coupled electrical connection, a third P-type field-effect transistor and a fourth P-type field-effect transistor with cross-coupled electrical connection, and a third pump capacitor and a fourth pump capacitor. The input terminal of the auxiliary charge boosting module includes the first terminal of the third N-type field-effect transistor and the first terminal of the fourth N-type field-effect transistor, which are electrically connected. The gates of the fourth N-type field-effect transistor and the third P-type field-effect transistor are each electrically connected to the first terminal of the third pump capacitor. The gates of the third N-type field-effect transistor and the fourth P-type field-effect transistor are each electrically connected to the first terminal of the fourth pump capacitor. The output terminal of the auxiliary charge boosting module includes the first terminal of each of the third P-type field-effect transistor and the fourth P-type field-effect transistor; The first control terminal and the second control terminal of the auxiliary charge boosting module respectively include the second terminal of the third pump capacitor and the second terminal of the fourth pump capacitor.

[0011] Optionally, both the third N-type field-effect transistor and the fourth N-type field-effect transistor are N-type field-effect transistors; Both the third and fourth P-type field-effect transistors are P-type field-effect transistors.

[0012] Optionally, the channel widths of the first N-type field-effect transistor, the second N-type field-effect transistor, the first P-type field-effect transistor, and the second P-type field-effect transistor are all greater than the channel widths of the third N-type field-effect transistor, the fourth N-type field-effect transistor, the third P-type field-effect transistor, and the fourth P-type field-effect transistor. And / or, the capacitance values ​​of the first pump capacitor and the second pump capacitor are both greater than the capacitance values ​​of the third pump capacitor and the fourth pump capacitor.

[0013] Optionally, the charge boosting circuit further includes: The fifth P-type field-effect transistor has its first terminal electrically connected to the output terminal of the auxiliary charge boosting module; the gate and second terminal of the fifth P-type field-effect transistor are both electrically connected to the output terminal of the main charge boosting module.

[0014] Optionally, the fifth P-type field-effect transistor is a P-type field-effect transistor.

[0015] Optionally, the start time of the second clock signal and the second inverted clock signal is earlier than the start time of the first clock signal and the first inverted clock signal.

[0016] Optionally, it may include cascaded multi-stage main charge boosting modules; The input terminal of the charge boosting circuit includes the input terminal of the first-stage main charge boosting module; The output terminal of the main charge boosting module of the previous stage is electrically connected to the input terminal of the main charge boosting module of the next stage; The output terminal of the charge boosting circuit includes the output terminal of the last stage main charge boosting module.

[0017] Optionally, the auxiliary charge boosting module includes multiple modules; The output terminal of each of the auxiliary charge boosting modules is electrically connected to the substrate of the field-effect transistor of the corresponding main charge boosting module.

[0018] Optionally, the auxiliary charge boosting module includes two modules; The output terminal of one of the auxiliary charge boosting modules is electrically connected to the substrate of the field-effect transistor of the first-stage main charge boosting module; The output of another auxiliary charge boosting module is electrically connected to the substrate of the field-effect transistor of the last stage main charge boosting module.

[0019] Optionally, the boost circuit may also include: The voltage clamping unit includes at least one Zener diode; The input terminal of the charge boosting circuit also includes the first terminal of the voltage clamping unit; the output terminal of the charge boosting circuit also includes the second terminal of the voltage clamping unit.

[0020] The boost circuit includes a voltage clamping unit comprising a first Zener diode and a second Zener diode connected in series.

[0021] Secondly, embodiments of this application provide a power management chip, including an oscillator and a charge boosting circuit as described above; The oscillator includes: The first clock output terminal and the first inverted clock output terminal are electrically connected to the first control terminal and the second control terminal of the main charge boosting module of the charge boosting circuit, respectively. The second clock output terminal and the second inverted clock output terminal are electrically connected to the first control terminal and the second control terminal of the auxiliary charge boosting module of the charge boosting circuit, respectively.

[0022] Thirdly, embodiments of this application provide a control method for a charge boosting circuit, applied to the charge boosting circuit described above, including: A second clock signal and a second inverted clock signal are respectively input to the first control terminal and the second control terminal of the auxiliary charge boosting module of the charge boosting circuit, so that the auxiliary charge boosting module outputs a bias voltage to the substrate of the field-effect transistor of the main charge boosting module, thereby raising the substrate voltage of the field-effect transistor of the main charge boosting module. A first clock signal and a first inverted clock signal are respectively input to the first control terminal and the second control terminal of the main charge boosting module of the charge boosting circuit, so that the main charge boosting module outputs the boosted voltage.

[0023] Optionally, the start time of the second clock signal and the second inverted clock signal is earlier than the start time of the first clock signal and the first inverted clock signal.

[0024] The beneficial technical effects of the technical solutions provided in this application include: The charge boosting circuit in this embodiment adds an auxiliary charge boosting module. The output terminal of the auxiliary charge boosting module is electrically connected to the substrate of the field-effect transistor of the main charge boosting module, and outputs a bias voltage to the substrate of the field-effect transistor of the main charge boosting module to raise the substrate voltage of the field-effect transistor of the main charge boosting module. By providing a high potential bias to the substrate of the field-effect transistor of the main charge boosting module, the problem of threshold voltage rise caused by substrate bias effect (i.e., body effect) of the field-effect transistor can be improved, the threshold voltage of the field-effect transistor of the main charge boosting module can be reduced, the on-resistance of the field-effect transistor of the main charge boosting module can be reduced, thereby improving the voltage conversion efficiency of the main charge boosting module, and thus improving the voltage conversion efficiency of the charge boosting circuit.

[0025] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0026] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic diagram of the framework structure of a charge boosting circuit provided in an embodiment of this application; Figure 2 A schematic diagram of the circuit structure of a charge boosting circuit and an oscillator provided in the embodiments of this application; Figure 3 A schematic diagram of the frame structure of another charge boosting circuit provided in an embodiment of this application; Figure 4 A schematic diagram of the circuit structure of a cascaded multi-stage main charge boosting module in another charge boosting circuit provided in an embodiment of this application; Figure 5 A schematic diagram of the framework structure of another charge boosting circuit provided in an embodiment of this application; Figure 6 This is a schematic flowchart illustrating a control method for a charge boosting circuit provided in an embodiment of this application.

[0027] Explanation of reference numerals in the attached figures: 111 - Main charge boosting module; 112 - Auxiliary charge boosting module. Detailed Implementation

[0028] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0029] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in this application's specification means the presence of the stated steps, operations, elements, and / or components, but does not exclude other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, "connected" or "coupled" as used herein may include wireless connection or wireless coupling. The term "and / or" as used herein means at least one of the items defined by the term; for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0031] In recent years, with the miniaturization and high performance of electronic devices, the demand for efficient and stable power management chips has been increasing. Traditional charge boosting circuits mostly adopt a cascaded structure of multi-stage capacitors and diode-connected MOSFETs (field-effect transistors), and achieve voltage boosting in stages through two-phase clock control.

[0032] However, in traditional charge boosting circuits, each stage of the charge boosting unit must overcome the threshold voltage of the MOSFET, causing the output voltage to decrease non-linearly with increasing stage number, resulting in low voltage conversion efficiency. This threshold voltage loss problem is particularly pronounced in low power supply voltage scenarios, severely impacting the overall performance of the charge boosting circuit.

[0033] Furthermore, the substrate bias effect of the MOSFET will further increase the threshold voltage of the MOSFET, exacerbating the decrease in voltage conversion efficiency.

[0034] In addition, the charge boosting circuit is prone to charge backflow during operation, which affects output stability and output efficiency.

[0035] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0036] This application provides a charge boosting circuit, such as... Figures 1 to 4As shown, the charge boosting circuit includes a main charge boosting module 111 and an auxiliary charge boosting module 112.

[0037] The first control terminal and the second control terminal of the main charge boosting module 111 are configured to receive the first clock signal CLK0 and the first inverted clock signal CLKN0 respectively. The input terminal of the main charge boosting module 111 is configured to input the bus voltage VS, and the output terminal VSUP1 of the main charge boosting module 111 is configured to output the boosted voltage. The first and second control terminals of the auxiliary charge boosting module 112 are configured to receive the second clock signal CLK1 and the second inverted clock signal CLKN1, respectively; the input terminal of the auxiliary charge boosting module 112 is configured to input the bus voltage VS; the output terminal VSP1_b of the auxiliary charge boosting module 112 is electrically connected to the substrate of the field-effect transistor of the main charge boosting module 111 and is configured to output a bias voltage to the substrate of the field-effect transistor of the main charge boosting module 111 to boost the substrate voltage of the field-effect transistor of the main charge boosting module 111.

[0038] By adding an auxiliary charge boosting module 112, the output terminal of which is electrically connected to the substrate of the field-effect transistor of the main charge boosting module 111, a bias voltage is output to the substrate of the field-effect transistor of the main charge boosting module 111 to raise the substrate voltage of the field-effect transistor of the main charge boosting module 111. By providing a high potential bias to the substrate of the field-effect transistor of the main charge boosting module 111, the problem of threshold voltage rise caused by substrate bias effect (i.e., body effect) of the field-effect transistor can be improved, the threshold voltage of the field-effect transistor of the main charge boosting module 111 can be reduced, the on-resistance of the field-effect transistor of the main charge boosting module 111 can be reduced, and the voltage conversion efficiency of the main charge boosting module 111 can be improved.

[0039] In some embodiments, the first clock signal CLK0 and the first inverted clock signal CLKN0 are two-phase non-overlapping clock signals; the second clock signal CLK1 and the second inverted clock signal CLKN1 are two-phase non-overlapping clock signals.

[0040] In some embodiments, at the initial moment of power-on of the power management chip, the external enable signal ENA is high, and when the enable signal ENP output by the CTRL_LOGIC module (control logic module) becomes high, the oscillator CP_OSC starts to oscillate and generates high-frequency non-overlapping clock signals (e.g., the first clock signal CLK0 and the first inverted clock signal CLKN0, and the second clock signal CLK1 and the second inverted clock signal CLKN1).

[0041] In some embodiments, the output terminal of the auxiliary charge boosting module 112 is electrically connected to the substrate of the P-type field-effect transistor of the main charge boosting module 111, and is configured to output a bias voltage to the substrate of the P-type field-effect transistor of the main charge boosting module 111 to boost the substrate voltage of the field-effect transistor of the main charge boosting module 111.

[0042] See Figure 2 and Figure 4 Optionally, in some embodiments, the main charge boosting module 111 includes: a first N-type field-effect transistor MN1 and a second N-type field-effect transistor MN2 that are cross-coupled and electrically connected, a first P-type field-effect transistor MP1 and a second P-type field-effect transistor MP2 that are cross-coupled and electrically connected, and a first pump capacitor C2 and a second pump capacitor C3.

[0043] The input terminal of the main charge boosting module 111 includes the first terminal of each of the first N-type field-effect transistor MN1 and the second N-type field-effect transistor MN2.

[0044] The gates of the second N-type field-effect transistor MN2 and the first P-type field-effect transistor MP1 are each electrically connected to the first terminal of the first pump capacitor C2.

[0045] The gates of the first N-type field-effect transistor MN1 and the second P-type field-effect transistor MP2 are both electrically connected to the first terminal of the second pump capacitor C3.

[0046] The output terminal of the main charge boosting module 111 includes the first terminal of each of the first P-type field-effect transistor MP1 and the second P-type field-effect transistor MP2.

[0047] The first control terminal and the second control terminal of the main charge boosting module 111 respectively include the second terminal of the first pump capacitor C2 and the second terminal of the second pump capacitor C3.

[0048] In some embodiments, the input terminal of the main charge boosting module 111 includes the first terminal of a first N-type field-effect transistor MN1 and the first terminal of a second N-type field-effect transistor MN2 that are electrically connected.

[0049] The second terminal of the first N-type field-effect transistor MN1, the gate of the second N-type field-effect transistor MN2, the gate of the first P-type field-effect transistor MP1, the second terminal of the second P-type field-effect transistor MP2, and the first terminal of the first pump capacitor C2 are electrically connected to the first node A1.

[0050] The second terminal of the second N-type field-effect transistor MN2, the gate of the first N-type field-effect transistor MN1, the gate of the second P-type field-effect transistor MP2, the second terminal of the first P-type field-effect transistor MP1, and the first terminal of the second pump capacitor C3 are electrically connected to the second node A2.

[0051] The first terminal of the first P-type field-effect transistor MP1 and the first terminal of the second P-type field-effect transistor MP2 are both electrically connected to the first output node.

[0052] The output terminal VSUP1 of the main charge boosting module 111 includes a first output node.

[0053] The first control terminal of the main charge boosting module 111 includes the second terminal of the first pump capacitor C2.

[0054] The second control terminal of the main charge boosting module 111 includes the second terminal of the second pump capacitor C3.

[0055] In other words, the output terminal of the auxiliary charge boosting module 112 is electrically connected to the substrate of the first P-type field-effect transistor MP1 and the substrate of the second P-type field-effect transistor MP2 of the main charge boosting module 111.

[0056] See also Figure 2 and Figure 4 Optionally, in some embodiments, the substrate of the first P-type field-effect transistor MP1 is electrically connected to the first terminal; the substrate of the second P-type field-effect transistor MP2 is electrically connected to the first terminal.

[0057] That is, the substrate of the first P-type field-effect transistor MP1 is electrically connected to the first terminal of the first P-type field-effect transistor MP1; the substrate of the second P-type field-effect transistor MP2 is electrically connected to the first terminal of the second P-type field-effect transistor MP2.

[0058] In some embodiments, the first terminal of each switching device can be the source, and the second terminal of each switching device can be the drain.

[0059] See Figure 2 and Figure 4 Optionally, in some embodiments, the main charge boosting module 111 further includes an output capacitor C1, the input terminal of the main charge boosting module 111 includes the first terminal of the output capacitor C1, and the output terminal VSUP1 of the main charge boosting module 111 includes the second terminal of the output capacitor C1.

[0060] The working principle of the main charge boosting module 111 includes: (1) In the first stage of a clock cycle, the first clock signal CLK0 is at the first level and the first inverted clock signal CLKN0 is at the second level.

[0061] Since the first inverting clock signal CLKN0 is at the second level, the second pump capacitor C3 is charged; when the first terminal of the second pump capacitor C3 is charged to a high voltage, the first P-type field-effect transistor MP1 is turned on, and the bus voltage VS charges the first pump capacitor C2 through the first P-type field-effect transistor MP1.

[0062] The first terminal of the first pump capacitor C2 provides a voltage to the gate of the first P-type field-effect transistor MP1. Initially, the first terminal of the first pump capacitor C2 is at a low voltage, and the first P-type field-effect transistor MP1 is turned on. The second pump capacitor C3 charges the output capacitor C1 through the first P-type field-effect transistor MP1 in a charge-sharing manner. As the first pump capacitor C2 is charged, the gate voltage of the first P-type field-effect transistor MP1 gradually increases. When the first terminal of the first pump capacitor C2 is at a high voltage, the first P-type field-effect transistor MP1 is turned off, and the second pump capacitor C3 stops charging the output capacitor C1.

[0063] (2) In the second stage of a clock cycle, the first clock signal CLK0 becomes the second level and the first inverted clock signal CLKN0 becomes the first level.

[0064] As the first clock signal CLK0 changes to the second level, the first pump capacitor C2 is charged, and the voltage at the first terminal of the first pump capacitor C2 increases further from the existing voltage.

[0065] As the first inverting clock signal CLKN0 changes to the first level, the second pump capacitor C3 discharges. When the first terminal of the second pump capacitor C3 discharges to a low voltage, the first P-type field-effect transistor MP1 is turned off, and the first pump capacitor C2 stops charging.

[0066] The first terminal of the second pump capacitor C3 provides a voltage to the gate of the second P-type field-effect transistor MP2. As the second pump capacitor C3 discharges, the gate voltage of the second P-type field-effect transistor MP2 gradually decreases. When the first terminal of the second pump capacitor C3 is at a low voltage, the second P-type field-effect transistor MP2 is turned on, and the first pump capacitor C2 charges the output capacitor C1 through charge sharing.

[0067] Repeat multiple clock cycles, with each clock cycle repeating the first and second phases described above.

[0068] For example, in the first stage of the next clock cycle, the first clock signal CLK0 is at the first level and the first inverted clock signal CLKN0 is at the second level.

[0069] Since the first inverting clock signal CLKN0 is at the second level, the second pump capacitor C3 is charging. As the second pump capacitor C3 charges, the gate voltage of the second P-type field-effect transistor MP2 gradually increases. When the first terminal of the second pump capacitor C3 is at a high voltage, the second P-type field-effect transistor MP2 is turned off, and the first pump capacitor C2 stops charging the output capacitor C1.

[0070] Since the first clock signal CLK0 is at the first level, the first pump capacitor C2 discharges, the body diode of the first P-type field-effect transistor MP1 is turned on, and the second pump capacitor C3 charges the output capacitor C1 through the first P-type field-effect transistor MP1.

[0071] When the clock switching frequency is relatively fast, the first pump capacitor C2 begins to charge before it can fully discharge. As a result, the voltage across C2 continues to rise, allowing for continuous charge accumulation and voltage multiplication. During high-frequency switching, the alternating charging and discharging of the pump capacitors causes the output capacitor C1 to continuously receive charge, gradually increasing the output voltage until it reaches a stable value.

[0072] In some embodiments, the first level is low and the second level is high.

[0073] In other words, the working principle of the main charge boosting module can also be understood in the following way.

[0074] Phase 1: After the oscillator CP_OSC starts oscillating, the first clock signal CLK0 becomes the low level VS-VDZ of the floating voltage rail, and the first inverting clock signal CLKN0 becomes the high level VS. As the first clock signal CLK0 becomes the low level VS-VDZ, the drain of the first N-type field-effect transistor MN1 is coupled to a potential lower than the source potential VS by the first pump capacitor C2. The body diode of the first N-type field-effect transistor MN1 conducts to charge the first pump capacitor C2, generating a voltage difference ΔV2 across the first pump capacitor C2.

[0075] Phase Two: After the first inverting clock signal CLKN0 becomes the low level VS-VDZ of the floating voltage rail, the first clock signal CLK0 rises to the high level VS. The gates of the second N-type field-effect transistor MN2 and the first P-type field-effect transistor MP1 are coupled to VS+ΔV2 by the first pump capacitor C2. The gate-source voltage of the second N-type field-effect transistor MN2 is ΔV2. If ΔV2 reaches the threshold voltage of the second N-type field-effect transistor MN2, the second N-type field-effect transistor MN2 will conduct. The bus voltage VS charges the second pump capacitor C3 through the channel of the second N-type field-effect transistor MN2, causing a voltage difference ΔV3 across the second pump capacitor C3. The gate voltage of the fourth switch MP2 is VS-VDZ+ΔV3. The first N-type field-effect transistor MN1 remains off, the fourth switch MP2 conducts, and the third switch MP1 is off. The first pump capacitor C2 charges the output capacitor C1 through the fourth switch MP2 in a charge-sharing manner.

[0076] Phase Three (Phase One of the Next Clock Cycle): The first clock signal CLK0 changes back to the low level VS-VDZ of the floating voltage rail, and the first inverting clock signal CLKN0 is at the high level VS. The gate of the first N-type field-effect transistor MN1 is coupled to VS+ΔV3 by the second pump capacitor C3. The gate-source voltage of the first N-type field-effect transistor MN1 is ΔV3. If ΔV3 is greater than the threshold voltage of the first N-type field-effect transistor MN1, the first N-type field-effect transistor MN1 is turned on. The bus voltage VS charges the second pump capacitor C3 through the channel of the first N-type field-effect transistor MN1, further increasing the voltage difference ΔV3 across the second pump capacitor C3. The gate voltage of the third switch MP1 is VS-VDZ+ΔV2. The second switch MN2 remains off, the third switch MP1 is turned on, and the fourth switch MP2 is turned off. The second pump capacitor C3 charges the output capacitor C1 through the third switch MP1 in a charge-sharing manner.

[0077] Repeatedly cycling through multiple clock cycles, under the control of the oscillator clock, the switching devices are repeatedly switched to alternately charge the first pump capacitor C2, the second pump capacitor C3, and the output capacitor C1. Finally, the voltage across the first pump capacitor C2 and the second pump capacitor C3 becomes VDZ, and the output voltage VSUP1 of the output capacitor C1 becomes VS+VDZ.

[0078] VS represents the bus voltage, and VDZ represents the breakdown voltage of the Zener diode in the clock drive circuit.

[0079] See also Figure 2 and Figure 4 Optionally, in some embodiments, the auxiliary charge boosting module 112 includes: a third N-type field-effect transistor MN3b and a fourth N-type field-effect transistor MN4b that are cross-coupled electrically connected, a third P-type field-effect transistor MP1b and a fourth P-type field-effect transistor MP2b that are cross-coupled electrically connected, and a third pump capacitor C2b and a fourth pump capacitor C3b.

[0080] The input terminals of the auxiliary charge boosting module 112 include the first terminal of the third N-type field-effect transistor MN3b and the first terminal of the fourth N-type field-effect transistor MN4b, which are electrically connected.

[0081] The gates of the fourth N-type field-effect transistor MN4b and the third P-type field-effect transistor MP1b are both electrically connected to the first terminal of the third pump capacitor C2b.

[0082] The gates of the third N-type field-effect transistor MN3b and the fourth P-type field-effect transistor MP2b are both electrically connected to the first terminal of the fourth pump capacitor C3b.

[0083] The output terminal of the auxiliary charge boosting module 112 includes the first terminal of each of the third P-type field-effect transistor MP1b and the fourth P-type field-effect transistor MP2b.

[0084] The first control terminal and the second control terminal of the auxiliary charge boosting module 112 respectively include the second terminal of the third pump capacitor C2b and the second terminal of the fourth pump capacitor C3b.

[0085] In some embodiments, the input terminal of the auxiliary charge boosting module 112 includes the first terminal of a third N-type field-effect transistor MN3b and the first terminal of a fourth N-type field-effect transistor MN4b that are electrically connected.

[0086] The second terminal of the third N-type field-effect transistor MN3b, the gate of the fourth N-type field-effect transistor MN4b, the gate of the third P-type field-effect transistor MP1b, the second terminal of the fourth P-type field-effect transistor MP2b, and the first terminal of the third pump capacitor C2b are electrically connected to the third node A3.

[0087] The second terminal of the fourth N-type field-effect transistor MN4b, the gate of the third N-type field-effect transistor MN3b, the gate of the fourth P-type field-effect transistor MP2b, the second terminal of the third P-type field-effect transistor MP1b, and the first terminal of the fourth pump capacitor C3b are electrically connected to the fourth node A4.

[0088] The first control terminal of the auxiliary charge boosting module 112 includes the second terminal of the third pump capacitor C2b.

[0089] The second control terminal of the auxiliary charge boosting module 112 includes the second terminal of the fourth pump capacitor C3b.

[0090] The substrate and first terminal of the third P-type field-effect transistor MP1b, and the substrate and first terminal of the fourth P-type field-effect transistor MP2b are all electrically connected to the second output node.

[0091] The output terminal VSP1_b of the auxiliary charge boosting module 112 includes a second output node.

[0092] In some embodiments, the second output node is electrically connected to the first output node.

[0093] It should be noted that the auxiliary charge boosting module 112 has a similar circuit topology and working principle to the main charge boosting module 111, so it will not be described again here.

[0094] Optionally, in some embodiments, the channel widths of the first N-type field-effect transistor MN1, the second N-type field-effect transistor MN2, the first P-type field-effect transistor MP1, and the second P-type field-effect transistor MP2 are all greater than the channel widths of the third N-type field-effect transistor MN3b, the fourth N-type field-effect transistor MN4b, the third P-type field-effect transistor MP1b, and the fourth P-type field-effect transistor MP2b; and / or, the capacitance values ​​of the first pump capacitor C2 and the second pump capacitor C3 are both greater than the capacitance values ​​of the third pump capacitor C2b and the fourth pump capacitor C3b.

[0095] This configuration allows the voltage at the output terminal VSP1_b of the auxiliary charge boosting module 112 to be quickly pulled up to a higher potential, thereby providing a high potential bias to the substrate of the P-type field-effect transistor of the main charge boosting module 111.

[0096] For example, when the driver chip is powered on, the auxiliary charge boosting module 112 can quickly pump to a high voltage, thereby providing a high potential bias to the substrate of the PMOS (P-type field-effect transistor) of the main charge boosting module 111 in the early stage of power-on, which can reduce the threshold voltage of the P-type field-effect transistor of the main charge boosting module 111, reduce the on-resistance of the P-type field-effect transistor of the main charge boosting module 111, thereby improving the voltage conversion efficiency of the main charge boosting module 111 and increasing the power-on speed of the main charge boosting module 111.

[0097] See Figure 2 and Figure 4 Optionally, in some embodiments, the charge boosting circuit further includes a fifth P-type field-effect transistor MP3, the first terminal of which is electrically connected to the output terminal VSP1_b of the auxiliary charge boosting module 112; the gate and the second terminal of the fifth P-type field-effect transistor MP3 are both electrically connected to the output terminal VSUP1 of the main charge boosting module 111.

[0098] The fifth P-type field-effect transistor MP3, connected via a diode, couples the output voltage of the auxiliary charge boosting module 112 to the output terminal VSUP1 of the main charge boosting module 111. This provides a high-potential bias to the substrate of the P-type field-effect transistor in the main charge boosting module 111, effectively preventing backflow, ensuring unidirectional voltage transmission, and improving system stability.

[0099] In some embodiments, each switching device (e.g., NMOS and PMOS) is equipped with a high-voltage isolation trap and can withstand voltages above 65V to ground through an ISO isolation ring, thereby enabling the charge boosting circuit to operate normally in the high-voltage domain.

[0100] Optionally, in some embodiments, the start time of the second clock signal CLK1 and the second inverted clock signal CLKN1 is earlier than the start time of the first clock signal CLK0 and the first inverted clock signal CLKN0.

[0101] By prioritizing the startup of the auxiliary charge boosting module 112 during the initial power-on phase (i.e., the clock signal drive of the auxiliary charge boosting module 112 is earlier than that of the main charge boosting module 111), the auxiliary charge boosting module 112 can quickly establish a high voltage output, rapidly increasing the substrate voltage of the P-type field-effect transistor in the main charge boosting module 111. This causes the coupling capacitor to charge and discharge, ensuring that the P-type field-effect transistor in the main charge boosting module 111 operates in a saturated state, thereby reducing the impact of the body effect of the P-type field-effect transistor in the main charge boosting module 111.

[0102] See Figure 1 and Figure 2 In some embodiments, the charge boosting circuit includes a single-stage main charge boosting module 111.

[0103] The input terminal of the charge boosting circuit includes the input terminal of the main charge boosting module 111.

[0104] The output terminal of the charge boosting circuit includes the output terminal of the main charge boosting module 111.

[0105] See Figures 3 to 5 Optionally, in some other feasible embodiments, the charge boosting circuit includes cascaded multi-stage main charge boosting modules 111.

[0106] The input terminal of the charge boosting circuit includes the input terminal of the first-stage main charge boosting module 111.

[0107] The output terminal of the preceding main charge boosting module 111 is electrically connected to the input terminal of the following main charge boosting module 111.

[0108] The output of the charge boosting circuit includes the output of the last stage main charge boosting module 111, VSUP1.

[0109] Since the charge boosting circuit in this embodiment adopts a multi-stage cascaded structure, the output voltage of each main charge boosting module 111 is passed sequentially and gradually increases the voltage, thereby improving the gain of the output voltage and meeting the high voltage output requirements.

[0110] During the voltage boosting process of the charge boosting circuit, the non-overlapping clock signal generated by the oscillator controls the directional transmission and storage of charge. Each main charge boosting module 111 achieves voltage multiplication through the alternating charging and discharging of multiple capacitors.

[0111] Figures 3 to 5Taking the three-stage main charge boosting module 111 as an example, the charge boosting circuit includes a first-stage main charge boosting module, a second-stage main charge boosting module, and a third-stage main charge boosting module that are connected in sequence. VSUP1, VSUP2, and VSUP3 represent the output terminals of the first-stage main charge boosting module, the second-stage main charge boosting module, and the third-stage main charge boosting module, respectively.

[0112] Figures 3 to 5 The total output voltage Vout of the charge boosting circuit is equal to the output voltage VS+3 of the third-stage main charge boosting module's output terminal VSUP3. VDZ ΔVloss, the conduction loss ΔVloss, is caused by the on-resistance of the switching transistor and the parasitic capacitance effect.

[0113] It should be noted that the number of stages can be flexibly configured to achieve different voltage gain requirements. For example, a four-stage cascade can make the total output voltage of the charge booster circuit reach VS+4. VDZ-ΔVloss; Five-stage cascading allows the total output voltage of the charge booster circuit to reach VS+5. VDZ-ΔVloss; N-stage cascading allows the total output voltage of the charge booster circuit to reach VS+N. VDZ-ΔVloss.

[0114] See Figure 3 Optionally, in some embodiments, the auxiliary charge boosting module 112 includes multiple modules; the output terminal of each auxiliary charge boosting module 112 is electrically connected to the substrate of the field-effect transistor of the corresponding main charge boosting module 111.

[0115] In other words, the auxiliary charge boosting module 112 corresponds one-to-one with the main charge boosting module 111, and each main charge boosting module 111 is configured with an auxiliary charge boosting module 112, thereby providing dynamic substrate bias for the corresponding stage field-effect transistor and effectively suppressing the threshold voltage rise caused by the bulk effect.

[0116] See Figure 5 Optionally, in some other feasible embodiments, the auxiliary charge boosting module 112 includes two: the output terminal of one auxiliary charge boosting module 112 is electrically connected to the substrate of the field-effect transistor of the first-stage main charge boosting module 111; and the output terminal of the other auxiliary charge boosting module 112 is electrically connected to the substrate of the field-effect transistor of the last-stage main charge boosting module 111.

[0117] This configuration ensures the startup stability of the first-stage main charge boosting module 111, guarantees the high-voltage withstand capability of the last-stage main charge boosting module 111, and avoids overly complex circuitry, thereby reducing chip area and power consumption.

[0118] Optionally, in some embodiments, only one auxiliary charge boosting module 112 may be configured. The output of the auxiliary charge boosting module 112 is electrically connected to the field-effect transistor substrate of the intermediate main charge boosting module 111 to balance the overall threshold voltage shift and suppress the gain attenuation caused by the bulk effect.

[0119] Optionally, in some embodiments, an auxiliary charge boosting module 112 may be configured every preset number of stages.

[0120] For example, in the five-stage cascaded main charge boosting module 111, the output terminals of the three auxiliary charge boosting modules 112 are electrically connected to the substrates of the field-effect transistors of the first-stage main charge boosting module 111, the third-stage main charge boosting module 111, and the fifth-stage main charge boosting module 111, respectively.

[0121] For example, in a seven-stage cascaded structure, three auxiliary charge boosting modules can be electrically connected to the field-effect transistor substrates of the second-stage main charge boosting module 111, the fourth-stage main charge boosting module 111, and the sixth-stage main charge boosting module 111, respectively.

[0122] Of course, the auxiliary charge boosting module 112 can also be flexibly configured according to actual needs. As long as the output terminal of at least one auxiliary charge boosting module 112 is electrically connected to the field-effect transistor substrate of at least one main charge boosting module 111, the basic bulk effect compensation function can be realized, thereby maintaining stable gain characteristics and output accuracy over a wide input voltage range.

[0123] It should be noted that, Figure 4 The labeling of each component in the first-stage main charge boosting module is the same as... Figure 2 Similar to the first-stage main charge boosting module, the components in the second-stage and third-stage main charge boosting modules are numbered sequentially. The working principles of the second-stage and third-stage main charge boosting modules are similar to those of the first-stage main charge boosting module, and will not be elaborated upon here.

[0124] Optionally, in some embodiments, the charge boosting circuit further includes a voltage clamping unit, which includes at least one Zener diode; the input terminal of the charge boosting circuit also includes a first terminal of the voltage clamping unit; and the output terminal of the charge boosting circuit also includes a second terminal of the voltage clamping unit.

[0125] The voltage clamping unit can clamp the total output voltage Vout of the charge boosting circuit within a preset voltage range, so that the driving capability of the power management chip is constant (stable gate charging current) and the logic threshold is reliable (avoiding false triggering due to power drop).

[0126] For example, the voltage clamping unit can clamp the total output voltage Vout of the charge boosting circuit within VS+13.5V, ensuring that the output voltage is stable at around VS+12.5V.

[0127] In some embodiments, the Zener diode may be a Zener diode.

[0128] Optionally, in some embodiments, the voltage clamping unit includes a first Zener diode and a second Zener diode connected in series.

[0129] In some embodiments, the first Zener diode and the second Zener diode can be connected in series in the same direction (both the first Zener diode and the second Zener diode operate in the reverse breakdown region), thereby superimposing the regulated voltage value.

[0130] The charge boosting circuit in this application embodiment is particularly suitable for electronic devices that require high-precision, high-efficiency voltage boosting, such as high-precision power modules and portable electronic products.

[0131] The beneficial technical effects of the technical solutions provided in this application include: The charge boosting circuit in this embodiment adds an auxiliary charge boosting module 112. The output terminal of the auxiliary charge boosting module 112 is electrically connected to the substrate of the field-effect transistor of the main charge boosting module 111, and outputs a bias voltage to the substrate of the field-effect transistor of the main charge boosting module 111 to raise the substrate voltage of the field-effect transistor of the main charge boosting module 111. By providing a high potential bias to the substrate of the field-effect transistor of the main charge boosting module 111, the problem of threshold voltage rise caused by substrate bias effect (i.e., body effect) of the field-effect transistor can be improved, the threshold voltage of the field-effect transistor of the main charge boosting module 111 can be reduced, the on-resistance of the field-effect transistor of the main charge boosting module 111 can be reduced, and the voltage conversion efficiency of the main charge boosting module 111 can be improved.

[0132] By using a dual-capacitor (first pump capacitor C2 and second pump capacitor C3) alternating operation mode, the dependence on the capacitance value of a single capacitor can be reduced, thereby helping to reduce the area of ​​the power management chip.

[0133] Furthermore, since each main charge boosting module 111 has two capacitors (first pump capacitor C2 and second pump capacitor C3) that alternately charge and discharge, there is always charge output at the output terminal of each main charge boosting module 111, which can effectively reduce charge backflow phenomenon. Through this interlocked dual-path structure, the output ripple can be reduced and the stability and reliability of the output voltage can be improved.

[0134] In addition, since the switching devices (such as NMOS and PMOS transistors) in the charge boosting circuit are equipped with high-voltage isolation traps, the charge boosting circuit can operate normally in the high-voltage domain.

[0135] Based on the same inventive concept, embodiments of this application provide a power management chip, including an oscillator and a charge boosting circuit as described above.

[0136] The oscillator includes a first clock output terminal, a first inverted clock output terminal, a second clock output terminal, and a second inverted clock output terminal.

[0137] The first clock output terminal and the first inverted clock output terminal are electrically connected to the first control terminal and the second control terminal of the main charge boosting module of the charge boosting circuit, respectively.

[0138] The second clock output terminal and the second inverted clock output terminal are electrically connected to the first control terminal and the second control terminal of the auxiliary charge boosting module of the charge boosting circuit, respectively.

[0139] This embodiment is a power management chip embodiment corresponding to the aforementioned charge boosting circuit embodiment. It includes the charge boosting circuit in the aforementioned embodiment, and its implementation principle, technical details and technical effects are similar, so they will not be repeated here.

[0140] Based on the same inventive concept, embodiments of this application provide a control method for a charge boosting circuit, applied to the charge boosting circuit described above, such as... Figure 6 As shown, the control method of this charge boosting circuit includes the following steps: S101: Input a second clock signal and a second inverted clock signal to the first control terminal and the second control terminal of the auxiliary charge boosting module of the charge boosting circuit, respectively, so that the auxiliary charge boosting module outputs a bias voltage to the substrate of the field-effect transistor of the main charge boosting module, thereby raising the substrate voltage of the field-effect transistor of the main charge boosting module.

[0141] S102: Input a first clock signal and a first inverted clock signal to the first control terminal and the second control terminal of the main charge boosting module of the charge boosting circuit, respectively, so that the main charge boosting module outputs the boosted voltage.

[0142] Optionally, in some embodiments, the start time of the second clock signal and the second inverted clock signal is earlier than the start time of the first clock signal and the first inverted clock signal.

[0143] This embodiment is a control method embodiment corresponding to the aforementioned charge boosting circuit embodiment. Its implementation principle and technical details are similar, and its technical effects are also similar, so it will not be repeated here.

[0144] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in related technologies that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0145] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0146] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A charge boosting circuit, characterized in that, include: The main charge boosting module has a first control terminal and a second control terminal configured to receive a first clock signal and a first inverted clock signal, respectively. The input terminal is configured to input the bus voltage, and the output terminal is configured to output the boosted voltage. The auxiliary charge boosting module has a first control terminal and a second control terminal configured to receive a second clock signal and a second inverted clock signal, respectively. The input terminal is configured to input the bus voltage; the output terminal is electrically connected to the substrate of the field-effect transistor of the main charge boosting module and is configured to output a bias voltage to the substrate of the field-effect transistor of the main charge boosting module to raise the substrate voltage of the field-effect transistor of the main charge boosting module.

2. The charge boosting circuit according to claim 1, characterized in that, The main charge boosting module includes: a first N-type field-effect transistor and a second N-type field-effect transistor with cross-coupled electrical connection, a first P-type field-effect transistor and a second P-type field-effect transistor with cross-coupled electrical connection, and a first pump capacitor and a second pump capacitor. The input terminal of the main charge boosting module includes the first terminal of each of the first N-type field-effect transistor and the second N-type field-effect transistor; The gates of the second N-type field-effect transistor and the first P-type field-effect transistor are each electrically connected to the first terminal of the first pump capacitor; The gates of the first N-type field-effect transistor and the second P-type field-effect transistor are each electrically connected to the first terminal of the second pump capacitor; The output terminal of the main charge boosting module includes the first terminal of each of the first P-type field-effect transistor and the second P-type field-effect transistor; The first control terminal and the second control terminal of the main charge boosting module respectively include the second terminal of the first pump capacitor and the second terminal of the second pump capacitor.

3. The charge boosting circuit according to claim 2, characterized in that, The substrate and the first terminal of the first P-type field-effect transistor are electrically connected; The substrate of the second P-type field-effect transistor is electrically connected to the first terminal.

4. The charge boosting circuit according to claim 2, characterized in that, The main charge boosting module also includes: The main charge boosting module includes a first terminal of the output capacitor at its input terminal and a second terminal of the output capacitor at its output terminal.

5. The charge boosting circuit according to claim 2, characterized in that, The auxiliary charge boosting module includes: a third N-type field-effect transistor and a fourth N-type field-effect transistor with cross-coupled electrical connection, a third P-type field-effect transistor and a fourth P-type field-effect transistor with cross-coupled electrical connection, and a third pump capacitor and a fourth pump capacitor. The input terminal of the auxiliary charge boosting module includes the first terminal of the third N-type field-effect transistor and the first terminal of the fourth N-type field-effect transistor, which are electrically connected. The gates of the fourth N-type field-effect transistor and the third P-type field-effect transistor are each electrically connected to the first terminal of the third pump capacitor. The gates of the third N-type field-effect transistor and the fourth P-type field-effect transistor are each electrically connected to the first terminal of the fourth pump capacitor. The output terminal of the auxiliary charge boosting module includes the first terminal of each of the third P-type field-effect transistor and the fourth P-type field-effect transistor; The first control terminal and the second control terminal of the auxiliary charge boosting module respectively include the second terminal of the third pump capacitor and the second terminal of the fourth pump capacitor.

6. The charge boosting circuit according to claim 5, characterized in that, The channel widths of the first N-type field-effect transistor, the second N-type field-effect transistor, the first P-type field-effect transistor, and the second P-type field-effect transistor are all greater than the channel widths of the third N-type field-effect transistor, the fourth N-type field-effect transistor, the third P-type field-effect transistor, and the fourth P-type field-effect transistor. And / or, the capacitance values ​​of the first pump capacitor and the second pump capacitor are both greater than the capacitance values ​​of the third pump capacitor and the fourth pump capacitor.

7. The charge boosting circuit according to claim 1, characterized in that, Also includes: The fifth P-type field-effect transistor, wherein the first terminal of the fifth P-type field-effect transistor is electrically connected to the output terminal of the auxiliary charge boosting module; The gate and second terminal of the fifth P-type field-effect transistor are both electrically connected to the output terminal of the main charge boosting module.

8. The charge boosting circuit according to claim 1, characterized in that, The start times of the second clock signal and the second inverted clock signal are earlier than the start times of the first clock signal and the first inverted clock signal.

9. The charge boosting circuit according to claim 1, characterized in that, Includes cascaded multi-stage main charge boosting modules; The input terminal of the charge boosting circuit includes the input terminal of the first-stage main charge boosting module; The output terminal of the main charge boosting module of the previous stage is electrically connected to the input terminal of the main charge boosting module of the next stage; The output terminal of the charge boosting circuit includes the output terminal of the last stage main charge boosting module.

10. The charge boosting circuit according to claim 9, characterized in that, The auxiliary charge boosting module includes multiple modules; The output terminal of each of the auxiliary charge boosting modules is electrically connected to the substrate of the field-effect transistor of the corresponding main charge boosting module.

11. The charge boosting circuit according to claim 9, characterized in that, The auxiliary charge boosting module includes two modules; The output terminal of one of the auxiliary charge boosting modules is electrically connected to the substrate of the field-effect transistor of the first-stage main charge boosting module; The output of another auxiliary charge boosting module is electrically connected to the substrate of the field-effect transistor of the last stage main charge boosting module.

12. The charge boosting circuit according to claim 9, characterized in that, Also includes: The voltage clamping unit includes at least one Zener diode; The input terminal of the charge boosting circuit also includes the first terminal of the voltage clamping unit; the output terminal of the charge boosting circuit also includes the second terminal of the voltage clamping unit.

13. The charge boosting circuit according to claim 12, characterized in that, The voltage clamping unit includes a first Zener diode and a second Zener diode connected in series.

14. A power management chip, characterized in that, Includes an oscillator and a charge boosting circuit as described in any one of claims 1-13; The oscillator includes: The first clock output terminal and the first inverted clock output terminal are electrically connected to the first control terminal and the second control terminal of the main charge boosting module of the charge boosting circuit, respectively. The second clock output terminal and the second inverted clock output terminal are electrically connected to the first control terminal and the second control terminal of the auxiliary charge boosting module of the charge boosting circuit, respectively.

15. A control method for a charge boosting circuit, applied to the charge boosting circuit as described in any one of claims 1-13, characterized in that, include: A second clock signal and a second inverted clock signal are respectively input to the first control terminal and the second control terminal of the auxiliary charge boosting module of the charge boosting circuit, so that the auxiliary charge boosting module outputs a bias voltage to the substrate of the field-effect transistor of the main charge boosting module, thereby raising the substrate voltage of the field-effect transistor of the main charge boosting module. A first clock signal and a first inverted clock signal are respectively input to the first control terminal and the second control terminal of the main charge boosting module of the charge boosting circuit, so that the main charge boosting module outputs the boosted voltage.

16. The control method for the charge boosting circuit according to claim 15, characterized in that, The start times of the second clock signal and the second inverted clock signal are earlier than the start times of the first clock signal and the first inverted clock signal.

Images