Inductance capacitance voltage controlled oscillator with temperature compensation

Abstract

A temperature-compensated inductively coupled voltage-controlled oscillator (ICVCO) is disclosed. The ICVCO includes an ICVCO core circuit and a temperature compensator. The ICVCO core circuit outputs a clock signal using a first differential oscillation output node and a second differential oscillation output node, and includes a first capacitor and a second capacitor connected in series between these output nodes. The first and second capacitors are voltage-controlled variable capacitors, and their connection points receive an oscillation control voltage to adjust the frequency of the clock signal. The temperature compensator generates at least one temperature-compensated voltage, coupled to the ICVCO core circuit, to influence the first and second capacitors, thereby adjusting a voltage-frequency diagram (VF diagram) of the oscillation control voltage and the oscillation frequency of the clock signal in at least one dimension.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit (IC) technology, and particularly to an inductor-capacitor voltage-controlled oscillator (LC-VCO). Background Technology

[0002] Inductor-capacitor voltage-controlled oscillator (LC-VCO) achieves oscillation by utilizing the resonance of an inductor (L) and a capacitor (C), effectively suppressing phase noise, and is therefore widely used in high-speed communication systems.

[0003] Traditional inductor-capacitor voltage-controlled oscillators (LC-VCOs) have a narrow frequency modulation range. In common applications (such as 16G PCIe SerDes PHYs), LC-VCOs typically only cover a single frequency point, limiting their application flexibility. With the development of chiplet interconnect technology, the system's requirements for clock frequency flexibility are increasing, necessitating the implementation of wide-range frequency adjustment with "stepless speed control."

[0004] Besides the need for a wide bandwidth, inductor-capacitor voltage-controlled oscillators (LC-VCOs) also face a severe temperature drift problem. The characteristics of the components in an LC oscillation circuit change with temperature, causing the frequency coverage of the same frequency band to shift under varying temperatures (e.g., from 0°C to 110°C). This leads to phase-locked loops (PLLs) losing lock under extreme high and low temperature conditions, failing to meet mass production requirements. However, existing temperature compensation schemes often introduce large parasitic capacitances, which significantly reduce the maximum oscillation frequency and tuning range of the LC-VCO.

[0005] This technical field requires an inductor-capacitor voltage-controlled oscillator (LC-VCO) that can achieve frequency range coverage and temperature compensation without significantly increasing parasitic load. Summary of the Invention

[0006] This application provides an inductor-capacitor voltage-controlled oscillator (LC-VCO) with a wide bandwidth coverage, which provides one or even two-dimensional temperature compensation to address phase-locked loop (PLL) lock-up issues that may occur in different temperature ranges. In particular, this application avoids excessively incorporating parasitic parameters.

[0007] According to one embodiment of the present invention, the inductor-capacitor voltage-controlled oscillator includes an inductor-capacitor oscillation core circuit and a temperature compensator. The inductor-capacitor oscillation core circuit outputs a clock signal using a first differential oscillation output node and a second differential oscillation output node, and includes a first capacitor and a second capacitor connected in series between these output nodes. The first and second capacitors are voltage-controlled variable capacitors, and their connection points receive an oscillation control voltage to adjust the frequency of the clock signal. The temperature compensator generates at least one temperature-related temperature compensation voltage, coupled to the inductor-capacitor oscillation core circuit to influence the first and second capacitors, thereby adjusting a voltage-frequency diagram (VF Diagram) of the oscillation control voltage and the oscillation frequency of the clock signal in at least one dimension.

[0008] In one embodiment, this application employs a two-dimensional compensation mechanism. For frequency axis compensation, the temperature compensator includes a frequency axis compensation circuit that sums a zero-temperature coefficient current and a positive temperature coefficient current to generate a frequency axis compensation voltage with a positive temperature coefficient (PTAT). The inductor-capacitor oscillation core circuit is further configured with additional third and fourth capacitors (voltage-controlled variable capacitors) connected in parallel to the first and second capacitors, and receives the frequency axis compensation voltage to offset frequency drop at high temperatures.

[0009] For voltage axis compensation, the temperature compensator includes a voltage axis compensation circuit that subtracts a positive temperature coefficient current from a zero temperature coefficient current to obtain a voltage axis compensation voltage with a negative temperature coefficient (NTAT). The inductor-capacitor oscillation core circuit receives the voltage axis compensation voltage through a first resistor and a second resistor to adjust the DC bias points of the first and second capacitors and correct the effective range of the oscillation control voltage.

[0010] Furthermore, the core circuit of this inductor-capacitor oscillation can use AC coupling capacitors (the fifth and sixth capacitors) to isolate the output node from the varactor tube / bias circuit, and combine it with a switched capacitor array to perform sub-band switching, thereby achieving a wideband and temperature-stable clock signal output.

[0011] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating an inductor-capacitor voltage-controlled oscillator (LC-VCO) 100 implemented according to one embodiment of this application;

[0013] Figure 2 The voltage-frequency diagram (VF diagram) is used to illustrate the switching of the corresponding switched capacitor array 108, providing oscillation control of 128 sub-bands in the frequency range of 12G~16G (Hz);

[0014] Figure 3 The circuit details of the frequency axis compensation circuit 104 are illustrated according to one embodiment of this application; and

[0015] Figure 4 The circuit details of the voltage axis compensation circuit 106 are illustrated according to one embodiment of this application.

[0016] [Symbol Explanation]

[0017] 100: Inductor-capacitor voltage-controlled oscillator

[0018] 101: Temperature compensator

[0019] 102: Core Circuit of Inductor-Capacitor (LC) Oscillator

[0020] 104: Frequency axis compensation circuit

[0021] 106: Voltage axis compensation circuit

[0022] AVDD: Power supply voltage

[0023] C1…C7: Capacitors

[0024] I1: Zero temperature coefficient current

[0025] I2: Negative temperature coefficient current

[0026] IP50U: Zero Temperature Coefficient Reference Current

[0027] IPTAT50U: Positive Temperature Coefficient Reference Current

[0028] L1, L2: Differential inductors

[0029] M1…M28: Transistors

[0030] MixNode: Mixed Bias Control Node

[0031] OP, ON: Differential oscillation output nodes

[0032] R1…R6: Resistors

[0033] VBN_IP and VBP_IP: Zero Temperature Coefficient Bias Voltage

[0034] VBN_ IPT: Positive Temperature Coefficient Bias Voltage

[0035] VCN: Oscillation Control Voltage

[0036] VNTAT: Voltage axis compensation voltage

[0037] VPTAT: Frequency axis compensation voltage

[0038] VPT_TC <n:0>、VPT_TCB <n:0>、VNT_TC <n:0>、VNT_TCB <n:0>、VNT_ABS <n:0>Digital control code Detailed Implementation

[0039] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the following content is only for illustrating the general principles of this disclosure and is not intended to limit the scope of this disclosure. The actual scope of protection of this disclosure shall be determined by the scope defined in the appended claims. The various functional blocks described herein can be implemented by hardware, software, firmware, or a combination thereof, and may also include dedicated circuitry. Furthermore, these functional blocks are not limited to individual implementations, and resources and functions may be integrated or shared as appropriate.

[0040] This application addresses the lockout problem caused by temperature drift in existing wideband inductor-capacitor voltage-controlled oscillators (LC-VCOs) under high and low temperature environments. Compared to traditional compensation circuits, this application does not introduce excessive parasitic parameters.

[0041] Figure 1 This is a block diagram illustrating an inductor-capacitor voltage-controlled oscillator (LC-VCO) 100 implemented according to one embodiment of this application. It employs an inductor-capacitor (LC) oscillation core circuit 102, which, under the operation of the oscillation control voltage VCN, forms a clock signal (CLK) between the differential oscillation output nodes OP and ON. The oscillation control voltage VCN specifies the oscillation frequency (F) of the clock signal (CLK) to form a voltage-frequency diagram (VF diagram). This application proposes a temperature drift compensation scheme; the LC-VCO 100 has a temperature compensator 101 that generates at least one temperature-related temperature compensation voltage (frequency-axis compensation voltage VPTAT, or voltage-axis compensation voltage VNTAT) to the inductor-capacitor (LC) oscillation core circuit 102 for temperature compensation. The illustrated temperature compensator 101 includes a frequency-axis compensation circuit 104 and a voltage-axis compensation circuit 106, which respectively generate the frequency-axis compensation voltage VPTAT and the voltage-axis compensation voltage VNTAT to compensate for temperature drift in two dimensions.

[0042] The inductor-capacitor (LC) oscillation core circuit 102 includes a pair of cross-coupled transistors M1 and M2, a current source transistor M3, and a pair of differential inductors L1 and L2. The current source transistor M3 (e.g., a PMOS transistor) is coupled between the power supply voltage AVDD and the connection point of the differential inductors L1 and L2, and is controlled by the bias voltage VPBIAS to provide the bias current required for oscillation. The differential inductors L1 and L2 are connected to the drains of transistors M1 and M2, respectively, and their connection points form a pair of differential oscillation output nodes OP and ON, providing a clock signal (CLK). Transistors M1 and M2 (e.g., NMOS transistors) form a cross-coupled negative resistance structure; the gate of transistor M1 is coupled to the drain of transistor M2, and the gate of transistor M2 is coupled to the drain of transistor M1. This cross-coupled configuration of transistors M1 and M2 generates negative resistance to compensate for parasitic resistance losses in the inductor-capacitor (LC) resonant circuit, thereby maintaining the continuous oscillation of the circuit.

[0043] To achieve frequency tunability and temperature compensation, the LC resonant circuit also includes a capacitor network connected in parallel with inductors L1 and L2, as discussed below.

[0044] The voltage-controlled variable capacitors (VRCs) C1 and C2 are primarily responsible for frequency fine-tuning and are coupled between the differential oscillation output nodes OP and ON. The capacitance of VRCs C1 / C2 changes with the voltage across their terminals. This application inputs an oscillation control voltage VCN at the connection point between VRCs C1 and C2, changing the equivalent capacitance of VRCs C1 and C2 to adjust the oscillation frequency of the clock signal (CLK) observed between the differential oscillation output nodes OP and ON. In particular, this application not only uses the oscillation control voltage VCN to set the clock signal (CLK) frequency, but also designs two additional control voltages for temperature compensation in both dimensions of the voltage-frequency diagram (VF diagram): a frequency-axis compensation voltage VPTAT and a voltage-axis compensation voltage VNTAT.

[0045] Temperature compensation for the corresponding frequency axis: The inductor-capacitor (LC) oscillation core circuit 102 includes another pair of voltage-controlled variable capacitors C3 and C4, connected in parallel with voltage-controlled variable capacitors C1 and C2. The connection point of the series-connected voltage-controlled variable capacitors C3 and C4 receives the frequency axis compensation voltage VPTAT, which originates from the frequency axis compensation circuit 104.

[0046] The frequency axis compensation voltage VPTAT is configured as a voltage signal with a positive temperature coefficient. When the operating ambient temperature rises, the inherent oscillation frequency of the inductor-capacitor (LC) oscillation core circuit 102 typically decreases due to device characteristic drift (i.e., the VF curve shifts downwards overall). At this time, the positive temperature coefficient frequency axis compensation voltage VPTAT increases with temperature, changing the bias potential difference across the voltage-controlled variable capacitors C3 / C4, thereby adjusting their effective capacitance value. This capacitance change is designed to offset the frequency drop caused by temperature increases, equivalent to shifting the voltage-frequency diagram (VF diagram) of the clock signal (CLK) along the frequency axis (Y-axis) (e.g., pulling the frequency curve upwards), ensuring that the oscillation frequency remains within the target range at high temperatures under the same oscillation control voltage VCN, preventing phase-locked loop (PLL) lockout.

[0047] For temperature compensation of the corresponding voltage axis, the inductor-capacitor (LC) oscillation core circuit 102 includes a pair of bias resistors R1 and R2, which are also connected in parallel with the aforementioned voltage-controlled variable capacitors C1 and C2. The connection point of the series bias resistors R1 and R2 receives the voltage axis compensation voltage VNTAT, which originates from the voltage axis compensation circuit 106.

[0048] The voltage axis compensation voltage VNTAT is configured as a voltage signal with a negative temperature coefficient. As the ambient operating temperature rises, the negative temperature coefficient voltage axis compensation voltage VNTAT decreases with increasing temperature (or is adjusted according to the design), altering the DC operating point of the voltage-controlled variable capacitors C1 / C2. This change in DC bias is designed to correct the effective control range of the voltage-controlled variable capacitors C1 / C2, equivalent to shifting the voltage-frequency diagram (VF diagram) of the clock signal (CLK) along the voltage axis (X-axis) (e.g., shifting the control curve back to the lockout range of the phase-locked loop), ensuring that the original oscillation control voltage VCN can still effectively regulate the frequency at high temperatures, preventing frequency dead zones or unlocking. In particular, compared to the frequency axis compensation voltage VNTAT received via the voltage-controlled variable capacitors C3 / C4, the negative temperature coefficient voltage axis compensation voltage VNTAT is connected to the oscillation core via a DC path provided by the high-impedance bias resistors R1 / R2, preventing the oscillation signal from grounding and stopping.

[0049] The illustrated inductor-capacitor (LC) oscillation core circuit 102 also includes AC coupling capacitors C5 and C6 to isolate the high voltage of the power supply voltage AVDD. In one embodiment, the voltage-controlled variable capacitors C1 to C4 are NMOS varactors. The source / drain of the series-connected voltage-controlled variable capacitors C3 and C4 receives the frequency axis compensation voltage VPTAT. The gates of the voltage-controlled variable capacitors C1 and C3 are coupled to the differential oscillation output node OP via the AC coupling capacitor C5. The gates of the voltage-controlled variable capacitors C2 and C4 are coupled to the differential oscillation output node ON via the AC coupling capacitor C6. In addition, the differential oscillation output node OP is coupled to the bias resistor R1 via the AC coupling capacitor C5, and the differential oscillation output node ON is coupled to the bias resistor R2 via the AC coupling capacitor C6. In this way, the voltage-controlled variable capacitors C1 to C4 operate stably under the protection of the AC coupling capacitors C5 and C6.

[0050] To extend the frequency tuning range of the inductor-capacitor voltage-controlled oscillator (LC-VCO) 100 to meet the broadband requirements of diverse applications such as chiplet interconnect systems or PCIe, the capacitor network in this embodiment also includes a switched capacitor array 108. This switched capacitor array 108 is connected in parallel between the differential oscillation output nodes OP and ON, and consists of multiple (e.g., 128) independently controllable capacitor branches (such as MOM capacitors), each with a control switch. Selectively turning on or off specific capacitor branches can change the total capacitive load of the resonant circuit; the overall oscillation frequency range of the inductor-capacitor voltage-controlled oscillator (LC-VCO) 100 is divided into multiple (e.g., 128) sub-bands, facilitating more precise control to achieve wide-range oscillation.

[0051] Figure 2 The switching of the switched capacitor array 108 is illustrated using a voltage-frequency diagram (VF diagram), providing oscillation control across 128 sub-bands in the frequency range of 12 GHz to 16 GHz. Each sub-band corresponds to a specific configuration of the switched capacitor array 108, and adjacent sub-bands are designed to have a partial frequency overlap. This overlap design allows the system to smoothly switch to the appropriate sub-band without frequency dead zones during process variations and changes in the operating environment, thanks to the Automatic Frequency Calibration (AFC) mechanism. This is further enhanced by the oscillation control voltage VCN for fine frequency locking, including the corresponding frequency axis compensation voltage VPTAT and the voltage axis compensation voltage VNTAT for two-dimensional temperature compensation (two-dimensional shift of the VF line). This architecture allows a single inductor-capacitor voltage-controlled oscillator (LC-VCO) 100 to cover an extremely wide frequency range, achieving stepless speed regulation and high flexibility of the clock frequency (CLK).

[0052] Figure 3 The circuit details of the frequency axis compensation circuit 104 are illustrated according to one embodiment of this application. The frequency axis compensation circuit 104 is configured to generate the aforementioned frequency axis compensation voltage VPTAT with a positive temperature coefficient, and this positive temperature coefficient is adjustable. The frequency axis compensation circuit 104 receives two reference current inputs: one is a zero temperature coefficient reference current IP50U (Zero Temperature Coefficient Current), whose current value does not change significantly with temperature; the other is a positive temperature coefficient reference current IPTAT50U (Proportional To Absolute Temperature Current), whose current value increases with increasing temperature.

[0053] The frequency axis compensation circuit 104 utilizes current mirroring and switch-controlled transistor array technology to mix the two current paths. The zero-temperature coefficient reference current IP50U is mirrored via (NMOS) transistors M4 and M5 to (PMOS) transistor M6, and then mirrored from transistor M6 to the first transistor array (PMOS, including transistors M7 to M8, with potentially more paths). The positive temperature coefficient reference current IPTAT50U is mirrored via (NMOS) transistors M13 and M12 to (PMOS) transistor M11, and then mirrored from transistor M11 to the second transistor array (PMOS, including transistors M9 to M10, with potentially more paths). This application uses the digital control code VPT_TC. <n:0>The number of switches turned on in the first transistor array (M7…M8) is controlled to generate a zero-temperature coefficient current based on the zero-temperature coefficient reference current IP50U. This application uses the digital control code VPT_TC. <n:0>complementary signal VPT_TCB <n:0>The number of switches turned on in the second transistor array (M9…M10) is controlled to generate a positive temperature coefficient current based on the positive temperature coefficient reference current IPTAT50U. The zero temperature coefficient current and the positive temperature coefficient current generated by the transistor array are summed to adjust the zero temperature coefficient reference current IP50U and the positive temperature coefficient reference current IPTAT50U.

[0054] The combined current is injected into the load resistor R4 through the summing point, converting the current signal into a voltage signal. Since the combined current contains a positive temperature coefficient component, the voltage generated at this summing point also possesses positive temperature coefficient characteristics. This is achieved by changing the digital control code VPT_TC. <n:0>By adjusting the weighting of the positive temperature coefficient reference current IPTAT50U, the slope of the output voltage change with temperature can be altered to match the frequency drift under different process conditions. Finally, after high-frequency noise is filtered out by a low-pass filter composed of resistor R3 and capacitor C7, a stable frequency axis compensation voltage VPTAT is output and supplied to the aforementioned voltage-controlled variable capacitors C3 and C4.

[0055] Figure 4 The circuit details of the voltage axis compensation circuit 106 are illustrated according to one embodiment of this application. The voltage axis compensation circuit 106 is configured to generate the aforementioned voltage axis compensation voltage VNTAT with a negative temperature coefficient, and this negative temperature coefficient is adjustable. Similar to the aforementioned frequency axis compensation circuit 104, the voltage axis compensation circuit 106 also operates based on a reference current, but employs a subtraction structure in the current processing logic to obtain the negative temperature coefficient characteristic. The voltage axis compensation circuit 106 uses a third transistor array (M18…M19), a fourth transistor array (M20…M22), a fifth transistor array (M14…M16), and a sixth transistor array (M24…M26).

[0056] The aforementioned frequency axis compensation circuit 104 generates two zero-temperature coefficient bias voltages, VBN_IP and VBP_IP, using a zero-temperature coefficient correlated current mirror, and generates a positive temperature coefficient bias voltage, VBN_IPT, using a positive temperature coefficient correlated current mirror. These three bias signals are also supplied to the voltage axis compensation circuit 106. The voltage axis compensation circuit 106 employs a current subtraction structure to synthesize the desired temperature characteristics.

[0057] For setting the basic DC operating point, transistors M14 to M16 biased by the zero temperature coefficient bias voltage VBN_IP form the fifth transistor array, which is responsible for setting the basic absolute voltage level (zero temperature dependent) of the voltage axis compensation voltage VNTAT.

[0058] To address the negative temperature coefficient (TTC) characteristic, PMOS transistor M23 and NMOS transistor M28 form a subtractive bias stage. The gate of PMOS transistor M23 receives a zero-temperature coefficient bias voltage VBP_IP, operating as a current source injecting a zero-temperature coefficient current. The gate of NMOS transistor M28 receives a positive temperature coefficient bias voltage VBN_IPT, operating as a current well drawing a positive temperature coefficient current. The drains of PMOS transistor M23 and NMOS transistor M28 are interconnected, forming a mixed bias control node (MixNode). The current flowing into NMOS transistor M27 is determined by the difference between the zero-temperature coefficient current (M23) and the positive temperature coefficient current (M28), thus exhibiting a negative temperature coefficient characteristic. NMOS transistors M24 to M26 form a sixth transistor array, with their gates connected to the gate of transistor M27. Through this connection structure, transistors M24 to M26 can mirror and replicate the negative temperature coefficient current flowing through transistor M27.

[0059] Numeric control code VNT_ABS <n:0>This is used to set the number of transistors on the fifth and sixth transistor arrays (transistors M15 to M16 and transistors M24 to M25), thereby adjusting the magnitude of the base current. Specifically, the fifth transistor array (composed of M14 to M16) draws a zero-temperature coefficient current I1. This current flows through the diode-connected PMOS transistor M17 and is then mirrored to the third transistor array (PMOS, including transistors M18 to M19, which can have a greater number of paths). Similarly, the sixth transistor array (NMOS, composed of M24 to M26, which can have a greater number of paths) draws a negative-temperature coefficient current I2. This current flows through the diode-connected PMOS transistor M22 and is then mirrored to the fourth transistor array (PMOS, including transistors M20 to M21, which can have a greater number of paths). This application uses the digital control code VNT_TC. <n:0>(and its complementary signal VNT_TCB) <n:0>The conduction state of the switches in the third and fourth transistor arrays is controlled, thereby adjusting the weighted mixing ratio of the zero temperature coefficient current I1 and the negative temperature coefficient current I2 injected into the output node.

[0060] The weighted and mixed total current is injected into resistor R5, converting the current signal into a voltage signal. Because this mixed current contains a negative temperature coefficient component, the voltage generated at this node has an adjustable negative temperature coefficient characteristic. This can be achieved by changing the digital control code VNT_TC. <n:0>By adjusting the weighting of the negative temperature coefficient current I2, the slope of the output voltage change with temperature can be altered to match the frequency drift under different process conditions. Finally, after high-frequency noise is filtered out by a low-pass filter composed of resistor R6 and capacitor C8, a stable voltage axis compensation voltage VNTAT is supplied to the aforementioned bias resistors R1 and R2.

[0061] It is worth noting that although this embodiment illustrates a specific circuit configuration of the frequency axis compensation circuit 104 and the voltage axis compensation circuit 106, those skilled in the art will understand that the invention is not limited thereto. In practical applications, the frequency axis compensation circuit 104 and the voltage axis compensation circuit 106 can be implemented using various known bandgap reference circuit topologies or bias generation circuits, as long as they can generate voltage signals with positive and negative temperature coefficients, respectively. In short, any circuit structure capable of providing a frequency axis compensation voltage VPTAT that increases with temperature and a voltage axis compensation voltage VNTAT that decreases with temperature is covered within the scope of this invention, thereby providing the necessary temperature reference for the subsequent dual compensation mechanism of the oscillation circuit on both the frequency and voltage axes.

[0062] Although this disclosure has been provided above with reference to embodiments, it is not intended to limit this disclosure. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the scope defined in the appended claims.

Claims

1. An inductor-capacitor voltage-controlled oscillator, comprising: An inductor-capacitor oscillation core circuit outputs clock signals at a first differential oscillation output node and a second differential oscillation output node. This circuit includes a first capacitor and a second capacitor connected in series between the first and second differential oscillation output nodes. The first and second capacitors are voltage-controlled variable capacitors, and the connection point of the first and second capacitors receives an oscillation control voltage. A temperature compensator generates at least one temperature-compensated voltage related to temperature, coupled to the inductor-capacitor oscillation core circuit, affecting the first capacitor and the second capacitor, to adjust the voltage-frequency diagram of the oscillation control voltage and the oscillation frequency of the clock signal in at least one dimension.

2. The inductor-capacitor voltage-controlled oscillator as described in claim 1, wherein: The temperature compensator includes a frequency axis compensation circuit to generate a frequency axis compensation voltage with a positive temperature coefficient, which serves as the temperature compensation voltage; and The frequency axis compensation circuit sums the zero temperature coefficient current and the positive temperature coefficient current to generate a frequency axis compensation voltage with a positive temperature coefficient.

3. The inductor-capacitor voltage-controlled oscillator as described in claim 1, wherein: The temperature compensator includes a voltage axis compensation circuit to generate a voltage axis compensation voltage with a negative temperature coefficient, which serves as the temperature compensation voltage; and The voltage axis compensation circuit subtracts the positive temperature coefficient current from the zero temperature coefficient current to generate the voltage axis compensation voltage with a negative temperature coefficient.

4. The inductor-capacitor voltage-controlled oscillator as described in claim 1, wherein, The core circuit for this inductor-capacitor oscillation also includes: A third and a fourth capacitor connected in series are connected in parallel with the first and the second capacitors. The third and the fourth capacitors are voltage-controlled variable capacitors, and the connection point of the third and the fourth capacitors receives a frequency axis compensation voltage with a positive temperature coefficient.

5. The inductor-capacitor voltage-controlled oscillator as described in claim 4, wherein, The core circuit for this inductor-capacitor oscillation also includes: A first resistor and a second resistor connected in series achieve DC bias and are connected in parallel with the first capacitor and the second capacitor. The connection point of the first resistor and the second resistor receives a voltage axis compensation voltage with a negative temperature coefficient.

6. The inductor-capacitor voltage-controlled oscillator as described in claim 5, wherein, The core circuit for this inductor-capacitor oscillation also includes: The fifth capacitor is coupled between the first capacitor and the first differential oscillation output node to achieve AC coupling; and The sixth capacitor is coupled between the second capacitor and the second differential oscillation output node to achieve AC coupling.

7. The inductor-capacitor voltage-controlled oscillator as described in claim 6, wherein, The core circuit for this inductor-capacitor oscillation also includes: A switched capacitor array is coupled between the first differential oscillation output node and the second differential oscillation output node to allow switching of sub-bands.

8. The inductor-capacitor voltage-controlled oscillator as described in claim 7, wherein, The core circuit for this inductor-capacitor oscillation also includes: The first transistor and the second transistor are cross-coupled and connected to the first differential oscillation output node and the second differential oscillation output node respectively via their drains; The third transistor is used as a current source; and A first differential inductor and a second differential inductor are connected in series between the first differential oscillation output node and the second differential oscillation output node, wherein the connection point of the first differential inductor and the second differential inductor is coupled to the drain of the third transistor.

9. The inductor-capacitor voltage-controlled oscillator as described in claim 8, wherein, The frequency axis compensation circuit includes: A first transistor array, coupled to a zero temperature coefficient current source, is used to generate an adjustable first zero temperature coefficient current with weights. The second transistor array is coupled to a positive temperature coefficient current source to generate an adjustable positive temperature coefficient current. The first load resistor receives the first zero-temperature coefficient current and the positive temperature coefficient current through the first summing point; and A first low-pass filter is coupled to the first summing point to generate the frequency axis compensation voltage.

10. The inductor-capacitor voltage-controlled oscillator as described in claim 9, wherein: The number of transistors in the first transistor array that are turned on is controlled by a first digital control code; and The number of transistors in the second transistor array that are turned on is controlled by the complementary signal of the first digital control code.

11. The inductor-capacitor voltage-controlled oscillator as described in claim 9, wherein: The zero-temperature coefficient current source includes a fourth transistor, a fifth transistor, and a sixth transistor. The fourth and fifth transistors, implemented in NMOS, are current mirror structures, and the sixth transistor, implemented in PMOS, is a diode with its drain connected to the drain of the fifth transistor and its gate connected to the first transistor array. A zero-temperature coefficient reference current is input to the drain of the fourth transistor and, through the fifth and sixth transistors, is mirrored to the first transistor array to generate an adjustable first zero-temperature coefficient current, wherein the first transistor array includes at least one seventh transistor and an eighth transistor.

12. The inductor-capacitor voltage-controlled oscillator as described in claim 11, wherein: The second transistor array includes at least a ninth transistor and a tenth transistor; The positive temperature coefficient current source includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The twelfth and thirteenth transistors, implemented in NMOS, are current mirror structures, while the eleventh transistor, implemented in PMOS, is a diode with its drain connected to the drain of the twelfth transistor and its gate connected to the second transistor array. A positive temperature coefficient reference current is input to the drain of the thirteenth transistor, and then mirrored to the second transistor array via the twelfth and eleventh transistors to generate an adjustable positive temperature coefficient current.

13. The inductor-capacitor voltage-controlled oscillator as described in claim 12, wherein, The voltage axis compensation circuit includes: A third transistor array is used to generate an adjustable second zero-temperature coefficient current with weights. A fourth transistor array is used to generate an adjustable negative temperature coefficient current using weighting. The second load resistor receives the second zero-temperature coefficient current and the negative temperature coefficient current through the second summing point; and A second low-pass filter is coupled to the second summing point to generate the voltage axis compensation voltage.

14. The inductor-capacitor voltage-controlled oscillator as described in claim 13, wherein: The number of transistors in the third transistor array that are turned on is controlled by a second digital control code; and The number of transistors in the fourth transistor array that are turned on is controlled by the complementary signal of the second digital control code.

15. The inductor-capacitor voltage-controlled oscillator as described in claim 13, wherein, The voltage axis compensation circuit also includes: A fifth transistor array, sharing a gate bias with the fifth transistor, is used to generate an adjustable third zero temperature coefficient current, which is then mirrored to the third transistor array to form the second zero temperature coefficient current.

16. The inductor-capacitor voltage-controlled oscillator as described in claim 15, wherein: The fifth transistor array includes at least one fourteenth transistor, a fifteenth transistor, and a sixteenth transistor implemented in NMOS, with their gates connected to the gate of the fifth transistor; The voltage axis compensation circuit also includes at least one seventeenth transistor implemented in PMOS, which is connected to the drain of the fifth transistor array; The third transistor array includes at least an eighteenth transistor and a nineteenth transistor implemented in PMOS, with their gates connected to the gate of the seventeenth transistor.

17. The inductor-capacitor voltage-controlled oscillator as described in claim 16, wherein: The fourth transistor array includes at least one twentieth transistor and a twenty-first transistor implemented in PMOS. The voltage axis compensation circuit also includes a 22nd transistor and a 23rd transistor implemented by PMOS, wherein the 22nd transistor is gate-connected to the 4th transistor array and the 23rd transistor is gate-connected to the 6th transistor. The voltage axis compensation circuit further includes a sixth transistor array, which includes at least one twenty-fourth transistor, a twenty-fifth transistor, and a twenty-sixth transistor implemented in NMOS, connected to the drain of the twenty-second transistor; and The voltage axis compensation circuit also includes a 27th transistor and a 28th transistor, wherein the 27th transistor and the 28th transistor implemented in NMOS are connected to the drain of the 23rd transistor, the gate of the 28th transistor is connected to the gate of the 13th transistor, and the diode-type 27th transistor is connected to the sixth transistor array by a gate.

18. The inductor-capacitor voltage-controlled oscillator as described in claim 17, wherein: The fifth transistor array and the sixth transistor array are operated by a third digital control code.

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