Oscillator and device

Abstract

The present application provides an oscillator and a device that can balance clock signal output and data communication. The oscillator includes a vibrator, an oscillation circuit that generates an oscillation signal using the vibrator, a clock output terminal, an output circuit that outputs a clock signal to an external processing device via the clock output terminal, a first terminal, and an interface circuit that communicates with the processing device by a data signal, in which the output circuit outputs the clock signal to the processing device as a master device of the communication, and the interface circuit as a slave device of the communication receives a data signal transmitted from the processing device in synchronization with the clock signal via the first terminal, or transmits a data signal to the processing device in synchronization with the clock signal via the first terminal.

Description

Technical Field

[0001] This invention relates to oscillators and related devices. Background Technology

[0002] Patent Document 1 discloses an electronic circuit device that enables serial communication even when the number of external terminals is limited, through asynchronous serial communication. Furthermore, Patent Document 1 also discloses an electronic circuit device that prevents erroneous identification of serial communication as having begun due to noise in the data signal, and that initiates serial communication upon detecting a burst signal input to an external terminal.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2008-250576

[0004] Since the electronic circuit device shown in Patent Document 1 is an asynchronous serial communication device, it is possible that adverse conditions may occur in serial communication due to noise. Summary of the Invention

[0005] One aspect of this disclosure relates to an oscillator comprising: an oscillator; an oscillation circuit that generates an oscillation signal using the oscillator; a clock output terminal; an output circuit that outputs a clock signal to an external processing device via the clock output terminal; a first terminal; and an interface circuit that communicates with the processing device via a data signal, wherein, in the communication, the output circuit outputs the clock signal to the processing device, which is the master device of the communication, and the interface circuit, which is the slave device of the communication, receives, via the first terminal, the data signal transmitted from the processing device and synchronized with the clock signal, or transmits the data signal to the processing device, synchronized with the clock signal, via the first terminal.

[0006] Another aspect of this disclosure relates to a device comprising: a clock signal generation circuit that generates a clock signal; a clock output terminal; an output circuit that outputs the clock signal to an external processing device via the clock output terminal; a first terminal; and an interface circuit that communicates with the processing device via a data signal, wherein, in the communication, the output circuit outputs the clock signal to the processing device, which is the master device of the communication, and the interface circuit, which is the slave device of the communication, receives, via the first terminal, the data signal transmitted from the processing device and synchronized with the clock signal, or transmits the data signal to the processing device, synchronized with the clock signal, via the first terminal. Attached Figure Description

[0007] Figure 1 This is a structural example of the oscillator in this embodiment.

[0008] Figure 2 This is an explanatory diagram of the oscillation mode in the comparative example of this embodiment.

[0009] Figure 3 This is an explanatory diagram of the communication mode in the comparative example of this embodiment.

[0010] Figure 4 This is an explanatory diagram of the communication mode in this embodiment.

[0011] Figure 5 This is an example of the structure of the I / O circuit of the interface circuit.

[0012] Figure 6 This is an explanatory diagram of a communication protocol example in this embodiment.

[0013] Figure 7 This is a signal waveform diagram illustrating a communication example of this embodiment.

[0014] Figure 8 This is a signal waveform diagram illustrating a communication example of this embodiment.

[0015] Figure 9 This is a detailed first structural example of the oscillator in this embodiment.

[0016] Figure 10 This is a detailed second structural example of the oscillator in this embodiment.

[0017] Figure 11 This is an example of a bit pattern representing logic levels "0" and "1".

[0018] Figure 12 This is an explanatory diagram illustrating the case where this embodiment is not applied in a 6-terminal oscillator.

[0019] Figure 13 This is an explanatory diagram illustrating the application of this embodiment in a 6-terminal oscillator.

[0020] Figure 14 This is a structural example of the device in this embodiment.

[0021] Figure 15 This is the first construction example of an oscillator.

[0022] Figure 16 This is the second construction example of an oscillator.

[0023] Label Explanation

[0024] 4: Oscillator; 5: Device; 6: First substrate; 7: Second substrate; 8: Third substrate; 10: Vibrator; 15: Package; 16: Base; 17: Cover; 18: External terminal; 19: External terminal; 20: Circuit device; 30: Oscillator circuit; 32: Variable capacitor circuit; 34: Clock signal generation circuit; 36: PLL circuit; 40: Temperature sensor circuit; 60: Temperature compensation circuit; 80: Interface circuit; 82: I / O circuit; 90: Output circuit; 100: Processing device; 110: Interface circuit; 112: I / O circuit; 200: Processing system; BF: Input buffer; BMP: Bump; CDC1, CDC2: Connection part; CK: Clock signal; DA: Data signal; DFS: Frequency setting data; DT D: Temperature detection data; ECK: Clock input terminal; EDA: Data terminal; EGND: Ground terminal; EVDD: Power terminal; GND: Ground voltage; IN: Input signal; IV: Inverter; OSC: Oscillator signal; OUT: Output signal; PCK: Clock output connection disk; PDA: Connection disk 1; PGND: Ground connection disk; PVDD: Power connection disk; PX1: Connection disk; PX2: Connection disk; RP: Resistor; SA: External device; SB: External device; SCK: Serial clock signal; TCK: Clock output terminal; TDA: Terminal 1; TGND: Ground terminal; TOE: Output enable terminal; TR: Transistor; TSCK: Serial clock input terminal; TVDD: Power terminal; VDD: Power supply voltage. Detailed Implementation

[0025] The embodiments will now be described. Furthermore, the embodiments described below do not unduly limit the scope of the claims. Also, not all structures described in these embodiments are necessarily essential structural elements.

[0026] 1. Oscillator

[0027] Figure 1 An example of the structure of the oscillator 4 in this embodiment is shown. Furthermore, in Figure 1 The diagram also shows a structural example of a processing system 200 including an oscillator 4 and a processing device 100. The oscillator 4 is capable of communicating with the processing device 100. The oscillator 4 includes an oscillator 10 and a circuit device 20.

[0028] The oscillator 10 is a component that generates mechanical vibration through an electrical signal. The oscillator 10 can be implemented, for example, using a quartz resonator or similar vibrating plate. For instance, the oscillator 10 can be implemented using a quartz resonator with a shearing angle of AT or SC, a tuning fork type quartz resonator, or a double tuning fork type quartz resonator. For example, the oscillator 10 can be an oscillator built into a temperature-compensated quartz oscillator (TCXO) without a thermostatic bath, or an oscillator built into a thermostatically controlled quartz oscillator (OCXO) with a thermostatic bath. Alternatively, the oscillator 10 can be an oscillator built into an SPXO (Simple Packaged Crystal Oscillator). Furthermore, the oscillator 10 of this embodiment can also be implemented using various vibrating plates, such as those other than shearing type, tuning fork type, or double tuning fork type, or piezoelectric resonators made of materials other than quartz. For example, the oscillator 10 can also be a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro Electromechanical Systems) oscillator formed using a silicon substrate. The oscillator 10 is electrically connected to the circuit device 20. For example, the oscillator 10 and the circuit device 20 can be electrically connected using internal wiring, bonding wires, or metal bumps in a package that houses the oscillator 10 and the circuit device 20.

[0029] The circuit device 20 generates and outputs the clock signal CK in the oscillator 4. Furthermore, the circuit device 20 is also capable of data communication via the data signal DA. The circuit device 20 includes an oscillator circuit 30, an output circuit 90, and an interface circuit 80. The circuit device 20 is, for example, an IC (Integrated Circuit) manufactured using semiconductor technology, which is a semiconductor chip on a semiconductor substrate with circuit elements formed thereon.

[0030] The oscillation circuit 30 is a circuit that causes the oscillator 10 to oscillate. For example, the oscillation circuit 30 generates an oscillation signal OSC by causing the oscillator 10 to oscillate. The oscillation signal OSC is an oscillation clock signal. As an example, the oscillation circuit 30 generates an oscillation signal OSC with a frequency of, for example, 32 kHz. However, the oscillation frequency is not limited to 32 kHz. For example, the oscillation circuit 30 can be implemented using an oscillation drive circuit and passive components such as capacitors or resistors electrically connected to one end and the other end of the oscillator 10. The drive circuit can be implemented, for example, using a CMOS inverter circuit or a bipolar transistor. The drive circuit is the core circuit of the oscillation circuit 30, and the drive circuit drives the oscillator 10 with voltage or current, thereby causing the oscillator 10 to oscillate. As the oscillation circuit 30, various types of oscillation circuits such as inverter type, Pierce type, Colpitts type, or Hartley type can be used, for example. The oscillation circuit 30 is electrically connected to the oscillator 10 via connecting pads PX1 and PX2. Connecting pads PX1 and PX2 are connecting pads for connecting the oscillator. The oscillation drive circuit of the oscillation circuit 30 is disposed between the connecting disks PX1 and PX2. Furthermore, the connection in this embodiment is an electrical connection. An electrical connection is a connection capable of transmitting electrical signals and transmitting information via electrical signals. An electrical connection can also be a connection via passive components, etc.

[0031] Output circuit 90 outputs a clock signal CK based on the oscillation signal OSC. For example, output circuit 90 buffers the oscillation clock signal, i.e., the oscillation signal OSC, output from oscillation circuit 30 and outputs it as clock signal CK to clock output connector PCK. Then, this clock signal CK is output to the outside via the clock output terminal TCK of oscillator 4. For example, output circuit 90 outputs clock signal CK in single-ended CMOS signal form. Alternatively, output circuit 90 can also output clock signal CK in a signal form other than CMOS.

[0032] The interface circuit 80 is a circuit that serves as an interface with an external processing device 100, etc. For example, the interface circuit 80 is used for... Figure 1 The circuit shown communicates with the external processing device 100. In this embodiment, in Figure 1 In this process, data communication, synchronized with the clock signal CK, occurs between the oscillator 4 and the processing device 100 via the first terminal TDA. Specifically, as described later... Figure 9 , Figure 10 As described above, temperature detection data DTD can be sent to processing device 100 via the first terminal TDA, or frequency setting data DFS for setting the oscillation frequency generated by oscillation circuit 30 can be received from processing device 100 via the first terminal TDA. Interface circuit 80 can be implemented, for example, via a serial interface circuit for serial interface communication.

[0033] The power connector PVDD is the connector to which the power supply voltage VDD is supplied. The connector is a terminal of the circuit device 20, which is a semiconductor chip. For example, in the connector area, a metal layer is exposed from a passivation film that serves as an insulating layer, and this exposed metal layer forms the connector as a terminal of the circuit device 20. For example, the power supply voltage VDD from an external power supply device is supplied to the power connector PVDD. The ground connector PGND is the terminal to which the ground voltage GND is supplied. GND can also be called VSS, and the ground voltage is, for example, the ground potential. In this embodiment, ground is appropriately referred to as GND. The power connector PVDD, ground connector PGND, clock output connector PCK, and first connector PDA are electrically connected to the external terminals of the oscillator 4, namely the power terminal TVDD, ground terminal TGND, clock output terminal TCK, and first terminal TDA. For example, these connectors and terminals are electrically connected using internal wiring of the package, bonding wires, or metal bumps.

[0034] Figure 1 The processing system 200 shown includes an oscillator 4 and a processing device 100 electrically connected to the oscillator 4. Additionally, the processing system 200 may also include, for example, a device that operates according to the clock signal CK of the oscillator 4. The oscillator 4 and the processing device 100 are electrically connected via wiring on a circuit board. This processing system 200 is, for example, assembled in an electronic device. The electronic device may be, for example, a network-related device such as a base station or router, a high-precision measuring device for measuring physical quantities such as distance, time, flow rate, or flow volume, a biological information measuring device for measuring biological information, or an in-vehicle device. Furthermore, the electronic device may also be a sensor mesh network device, an IoT (Internet of Things) device, a wearable device such as a head-mounted display or watch-related device, a robot, a printing device, a projection device, a portable information terminal such as a smartphone, a content provider for publishing content, or an imaging device such as a digital camera or camcorder.

[0035] As described above, the processing device 100 communicates with the interface circuit 80 of the oscillator 4. Specifically, the processing device 100 includes an interface circuit 110, which facilitates communication between the interface circuit 80 of the oscillator 4 and the interface circuit 110 of the processing device 100. The processing device 100 has a data terminal EDA for input / output data signals DA, a clock input terminal ECK for input clock signals CK, a power supply terminal EVDD for supplying VDD, and a ground terminal EGND for supplying GND.

[0036] The processing device 100 can be implemented, for example, by a processor such as an MPU (Micro Processor Unit), an MCU (Micro Controller Unit), or a CPU (Central Processing Unit), or a circuit device such as an ASIC (Application Specific Integrated Circuit). For example, the processing device 100, as an external device, may also include such a circuit device and a circuit board on which the circuit device is mounted.

[0037] The interface circuit 110 of the processing device 100 communicates with the interface circuit 80 of the oscillator 4 via a clock signal CK input to the clock input terminal ECK and a data signal DA input / output via the data terminal EDA. In this communication, the output circuit 90 of the oscillator 4, acting as a slave device, outputs the clock signal CK to the processing device 100, which acts as the master device. Here, the master device in the communication refers to the device responsible for controlling or operating multiple devices when they operate in coordination, and the slave device refers to the device operating under the control of the master device. Hereinafter, the processing device 100 will be described only as the master device, and the interface circuit 80 or the oscillator 4 will be described only as the slave device. The master device receives the clock signal CK and sends the data signal DA, synchronized with the received clock signal CK, to the slave device. Furthermore, the slave device receives the data signal DA, synchronized with the clock signal CK, via the first terminal TDA. In addition, the slave device transmits the data signal DA synchronously with the clock signal CK, and the master device receives the data signal DA from the slave device based on the received clock signal CK. In this way, based on the clock signal CK output by the slave device, data communication synchronized with the clock signal CK is carried out between the master device and the slave device.

[0038] As described above, the oscillator 4 of this embodiment includes: an oscillator 10; an oscillation circuit 30 that generates an oscillation signal OSC using the oscillator 10; a clock output terminal TCK; an output circuit 90 that outputs a clock signal CK to an external processing device 100 via the clock output terminal TCK; a first terminal TDA; and an interface circuit 80 that communicates with the processing device 100 via a data signal DA.

[0039] Furthermore, in this communication, the output circuit 90 outputs a clock signal CK to the processing device 100, which acts as the communication master device. That is, normally the master device outputs a clock signal for communication; in contrast, in this embodiment, the output circuit 90 on the slave device side outputs the clock signal CK. The interface circuit 80, acting as the communication slave device, receives a data signal DA transmitted from the processing device 100, synchronized with the clock signal CK, via the first terminal TDA. In other words, the processing device 100, acting as the master device, transmits the data signal DA synchronously with the clock signal CK from the slave device, and the interface circuit 80, acting as the slave device, receives the transmitted data signal DA. Alternatively, the interface circuit 80, acting as the communication slave device, transmits the data signal DA synchronously with the clock signal CK to the processing device 100 via the first terminal TDA. That is, the interface circuit 80, acting as the slave device, transmits the data signal DA synchronously with the clock signal CK, and the processing device 100, acting as the master device, receives the transmitted data signal DA. Thus, synchronous communication of the data signal DA can be performed between the processing device 100, acting as the communication master device, and the interface circuit 80, acting as the communication slave device, based on the clock signal CK output from the slave device side.

[0040] In addition, Figure 1 In this circuit, a pull-up resistor RP is provided between the data line of the data signal DA and the power line of VDD. This pulls up the data line connecting the processing device 100 and the interface circuit 80. That is, the data line is pulled up to the VDD power supply voltage level. Thus, even when neither the interface circuit 80 nor the processing device 100 drives the data line to a low level, the data line is pulled up to the VDD power supply voltage level, i.e., a high level. Specifically, the interface circuit 80 includes the following... Figure 5 In the case of the I / O circuit 82 with an open-drain N-type transistor TR shown, and the interface circuit 110 including the I / O circuit 112, the data line is pulled up to a high level when the transistor TR is turned off. This enables serial data communication using the data line.

[0041] In addition, Figure 1 In this configuration, a pull-up resistor RP is provided between the data line of the data signal DA and the power line of VDD, but it can also be configured without such a pull-up resistor RP.

[0042] Figure 1 The oscillator 4 shown is a 4-terminal oscillator with a power supply terminal TVDD, a ground terminal TGND, a clock output terminal TCK, and a first terminal TDA. In such an oscillator 4 with a small number of terminals, how to achieve communication with an external processing device 100 becomes a challenge.

[0043] For example, as Figure 1In a comparative example, consider a method for switching the operating mode of oscillator 4 to oscillation mode and communication mode. For example, the method is as follows: by switching the operating mode to communication mode during manufacturing and inspection, communication with the external processing device 100 can be achieved even with a smaller number of terminals. Figure 2 and Figure 3 This indicates its summary.

[0044] Figure 2 The diagram illustrates the operation of oscillator 4 in oscillation mode. In oscillation mode, the clock signal CK based on the oscillation signal OSC from oscillation circuit 30 is sent to external processing device 100, external device SA, and external device SB via the clock output terminal TCK. Processing device 100 and the others operate based on this clock signal CK. That is, processing device 100, as the master device, and other external devices SA operate based on the clock signal CK output from oscillator 4, which is a slave device.

[0045] Figure 3 The diagram illustrates the operation of oscillator 4 in communication mode. In communication mode, the clock output terminal TCK is switched to the serial clock input terminal TSCK for communication, and the first terminal TDA, which is the output enable terminal TOE, is switched to the terminal for data communication. In communication mode, oscillator 4 communicates with processing device 100 via a serial interface, for example. Specifically, oscillator 4 receives the serial clock signal SCK output by processing device 100 via the serial clock input terminal TSCK, and performs data signal DA communication via the first terminal TDA, which has been switched to the terminal for data communication. However, in the method of this comparative example, in communication mode, the clock output terminal TCK is switched to the serial clock input terminal TSCK for data communication, so the clock signal CK of oscillator 4 cannot be output from the clock output terminal TCK to, for example, processing device 100. Therefore, when processing device 100 operates based on the clock signal CK, or when there is an external device SA or the like that operates using the clock signal CK, in communication mode, processing device 100 or other external devices SA or the like cannot operate based on the clock signal CK. That is, in communication mode, it is impossible to simultaneously maintain the data communication between the processing unit 100 as the master device and the oscillator 4 as the slave device, as well as the continued operation of the processing unit 100, which operates based on the clock signal CK, and external devices such as SA.

[0046] Figure 4 It shows that it has been applied. Figure 1The communication state under this embodiment. As described above, according to the structure of this embodiment, data communication between the processing device 100 as the master device and the oscillator 4 as the slave device is performed using the clock signal CK output by the oscillator 4 as the slave device. Therefore, it is not necessary to set the operating state to communication mode and switch the clock output terminal TCK to the serial clock input terminal TSCK for data communication as in the comparative example described above. Therefore, the oscillator 4 can output the clock signal CK from the clock output terminal TCK to the processing device 100 or external device SA, etc., while simultaneously performing data communication with the processing device 100 synchronized with the clock signal CK. Therefore, it is possible to simultaneously realize data communication between the processing device 100 as the master device and the oscillator 4 as the slave device, and maintain the operating state of the processing device 100, external device SA, etc., which operate based on the clock signal CK.

[0047] Furthermore, in this embodiment, the oscillator 4, acting as a slave device, continues to output the clock signal CK, thus maintaining a constant power consumption. This allows the oscillator 4 to output a more stable frequency clock signal CK. That is, while the oscillator 4 continuously outputs the clock signal CK, the heat generated by the oscillator 4 itself remains constant, and the thermal relationship between the oscillator 4 and the external environment remains constant. However, when the oscillator 4 interrupts the output of the clock signal CK, the thermal relationship with the external environment changes, and the temperature of the oscillator 4 cannot remain constant. Here, when the temperature of the oscillator 4 changes, it is necessary to utilize the method described later... Figure 9 The temperature compensation circuit 60 performs temperature correction, which affects the generation of a stable frequency clock signal CK. Therefore, the frequency of the clock signal CK fluctuates, and the clock frequency characteristics of the oscillator 4 deteriorate. Therefore, according to this embodiment, the oscillator 4 continuously outputs the clock signal CK, thereby enabling the output of a clock signal CK with a stable frequency. This allows for data communication between the oscillator 4 and the processing device 100, and enables the continuous supply of a high-quality clock signal CK with high frequency characteristics to the processing device 100 or other external devices SA.

[0048] For example, in serial data communication, as mentioned above Figure 3In this way, the master device typically outputs a serial clock signal SCK used in data communication to the slave device. Here, the master device outputs the serial clock signal SCK to the slave device during the data communication period. Outside of this communication period, the serial clock signal SCK, used to synchronize data communication with the slave device, is not needed to suppress unnecessary power consumption. Specifically, the communication period refers to the period during which the master device writes data signal DA to the slave device or reads data signal DA from the slave device. On the other hand, in this embodiment, during data communication, the slave device acts as the one that outputs the clock signal CK instead of the master device. Here, unlike the master device, the slave device needs to continue outputting the clock signal CK even when not communicating with the master device in order to maintain the operating state of external devices such as SA included in the processing system 200. Thus, in this embodiment, the oscillator 4 of the slave device has an output circuit 90 that outputs the clock signal CK even outside of the data communication period.

[0049] Furthermore, the oscillator 4 in this embodiment has four external terminals for external connection: a power supply terminal TVDD, a ground terminal TGND, a clock output terminal TCK, and a first terminal TDA. The power supply terminal TVDD is supplied with, for example, the power supply voltage VDD from an external power supply device. The ground terminal TGND is supplied with GND, which is the ground voltage. Here, the ground voltage GND is, for example, the ground potential. The clock output terminal TCK is used to output the clock signal CK generated by the output circuit 90 to the outside. The first terminal TDA is used by the oscillator 4 and the slave device for data communication with the master device.

[0050] Furthermore, as described above, the power supply terminal TVDD, ground terminal TGND, clock output terminal TCK, and first terminal TDA of the oscillator 4 are electrically connected to the power connection disk PVDD, ground connection disk PGND, clock output connection disk PCK, and first connection disk PDA of the circuit device 20, respectively.

[0051] According to this embodiment, in an oscillator 4 with only 4 external terminals, an accurate clock signal CK can be continuously output from the oscillator 4 to the processing device 100 or an external device SA, regardless of whether data communication is taking place between the processing device 100 and the oscillator 4.

[0052] Furthermore, in the oscillator 4 of this embodiment, the first terminal TDA can also be the output enable terminal TOE, which switches between enabling and disabling the output of the clock signal CK.

[0053] When terminal TDA is used as the output enable terminal TOE, and terminal TDA is set to an active level such as high, the output circuit 90 outputs the clock signal CK to the outside. On the other hand, when terminal TDA is set to an inactive level such as low, the output circuit 90 sets the clock signal CK to a fixed voltage level such as low. In this way, terminal TDA can function not only as a data signal transceiver terminal, but also as a terminal for controlling the on / off state of the oscillator's clock signal output.

[0054] Figure 5 Show Figure 1 Example of the structure of the I / O circuit 82 included in the interface circuit 80. The I / O circuit 82 includes an open-drain N-type transistor TR and an input buffer BF. Additionally, Figure 5 The IN / OUT terminals and Figure 1 Terminal 1, TDA, corresponds to the data terminal of oscillator 4.

[0055] The output signal OUT from the internal circuitry is buffered, for example, by an inverter IV, and then input to the gate of transistor TR. For instance, when the output signal OUT is low and the gate of transistor TR is high, transistor TR is turned on, and the data line is driven low. Conversely, when the output signal OUT is high and the gate of transistor TR is low, transistor TR is turned off. In this case, the data line is in a state of... Figure 1 The resistor RP is pulled high. This allows the transmission of the data signal DA using the output signal OUT. Furthermore, the IN / OUT terminal is connected to the input buffer BF, and the input signal IN at the IN / OUT terminal is buffered by the input buffer BF before being input to the internal circuit. This allows the reception of the data signal DA using the input signal IN.

[0056] In addition, when using the unset Figure 1 In the case of a pull-up resistor RP structure, in Figure 5 In the I / O circuit 82, instead of the open-drain N-type transistor TR, a push-pull output circuit consisting of a P-type transistor and an N-type transistor can be set up, for example, in series between VDD and GND.

[0057] Furthermore, the I / O circuit 112 included in the interface circuit 110 of the processing device 100 also becomes related to... Figure 5 It has the same structure as the I / O circuit 82.

[0058] The following describes the data communication between the master device and the slave device in the processing system 200 of this embodiment. Figure 6This is an explanatory diagram of a communication protocol example in this embodiment. Figure 6 The upper part of the diagram represents the communication protocol for data writing. Figure 6 The diagram below illustrates the communication protocol for data reading. In the communication protocol for data writing, the master device sends a communication start key, which is received by the interface circuit 80, which acts as the slave device. In this case, the master device sends the communication start key synchronously with the clock signal CK from the slave device. Then, the interface circuit 80, acting as the slave device, receives the communication start key synchronized with the clock signal CK, determines whether the received communication start key is a key with the appropriate code according to the protocol, and determines that communication has started if it is a key with the appropriate code. In communication protocols such as data reading, the determination of communication start is performed using the same steps. Thus, in this embodiment, the interface circuit 80 starts communication based on receiving a communication start key from the processing device 100. This prevents the erroneous situation where communication between the master device and the slave device is started based on the master device sending a communication start key with the appropriate code to the slave device, thus avoiding the undesirable situation where communication is mistakenly determined to have started due to noise or other factors contained in the data signal.

[0059] Figure 7 and Figure 8 This is a signal waveform diagram illustrating a communication example of this embodiment. Figure 7 This is a signal waveform diagram showing the data write operation from the master device to the slave device. This data write operation from the master device corresponds to the data reception operation of the slave device's interface circuit 80. Figure 8 This is a signal waveform diagram showing the data read operation when the master device reads data from the slave device. This data read operation by the master device corresponds to the data transmission of the slave device's interface circuit 80. Furthermore, in... Figure 7 and Figure 8 In order to distinguish between the low level output of the master device and the low level output of the slave device, the low level of the slave device is schematically represented as a potential lower than the low level of the master device.

[0060] exist Figure 7 During data writing, after sending the communication start key, the master device outputs an R / XW indicating whether it is writing or reading. In this R / XW, X represents negative logic; the master device outputs a high level during data reading and a low level during data writing. Figure 7 The data is written in the middle, therefore the master device outputs a low level as the XW of R / XW. That is, by making Figure 5The open-drain N-type transistor of the master device's I / O circuit 112 is turned on and outputs a low level. Thus, when the master device outputs a low level after the communication start key, the slave device outputs an SLA indicating its acknowledgment. Specifically, the slave device outputs a low level as the SLA. As described above, the slave device's low level is designed to distinguish it from the master device's low level. Figure 7 The diagram illustrates a low level, which is a lower potential.

[0061] When the slave device outputs a low level as the SLA, the master device writes an address to the slave device. This address specifies the address of the slave device's register that will become the destination for the data write. During this address write, the master device sends the address information as the data signal DA, and the slave device receives this address information.

[0062] After writing the address, the master device outputs P / XC. P stands for Stop, and XC stands for Continue. Additionally, the X in XC indicates negative logic. Figure 7 In the process, to continue communication, the master device outputs a low level as XC for P / XC. Then, the master device sends the data to be written to the specified address as the data signal DA. This writes data from the master device to the register at the specified address in oscillator 4. Here, the write address is automatically updated in the slave device. Therefore, whenever the slave device outputs XC indicating continuation of communication, data is sequentially written to the updated address. Additionally, in... Figure 6 as well as Figure 7 In this process, each transmitted data is marked as 8 bits, but it can also be a specified number of bits, such as 4 bits or 16 bits. Furthermore, if the next piece of data to be written disappears, the master device outputs a 1-bit "P" indicating that communication has stopped, thus ending the data writing communication.

[0063] exist Figure 8 In the case of data reading, the master device first sends a communication start key, which the slave device then receives. Here, in the case of data reading, as... Figure 6 As shown in the next section, firstly, in write mode, communication occurs to specify the address to which data to be read is written. That is, the master device sends an XW signal indicating write mode after the communication start key. Then, the slave device outputs an SLA indicating acknowledgment. Specifically, the slave device outputs a low level as the SLA. Upon receiving the SLA signal, the master device sends the specified address information to the slave device. Upon receiving the address information, the slave device outputs a 1-bit P indicating communication stop, temporarily halting communication in write mode. Figure 8This represents the waveform of the subsequent data communication between the master and slave devices. The master device resends the communication start key and then outputs a high level as R to indicate a read. Upon receiving this information, the slave device outputs an SLA indicating acknowledgment. Then, the slave device reads the information written to the specified address and sends it to the master device. Next, the master device sends an XC indicating continuation of communication. Here, the address being read is automatically updated in the slave device. Therefore, whenever the master device outputs an XC indicating continuation of communication, the slave device sequentially reads data from the next address and sends it to the master device. Additionally, in Figure 6 as well as Figure 8 In this process, each transmitted data is marked as 8 bits, but it can also be a specified number of bits, such as 4 bits or 16 bits. Then, when the next piece of data read disappears, the master device outputs a 1-bit P indicating that communication has stopped, thus ending the data reading communication.

[0064] Thus, in this embodiment, in Figure 6 , Figure 7 When data is written, after the interface circuit 80 receives the first data of a specified number of bits, if the processing device 100 outputs a low level, it determines that communication continues and receives the next second data of the specified number of bits. That is, in Figure 6 , Figure 7 In the data writing process of the master device, the interface circuit 80, acting as the slave device, receives the first data, consisting of 8 bits, as a predetermined number of bits. Specifically, the first data sent by the master device is received and written into a register. Furthermore, the predetermined number of bits is not limited to 8 bits; it can also be 16 bits, 32 bits, etc. Moreover, when the processing device 100 outputs a low level as an indication of continued communication (XC) after sending the first data, the interface circuit 80 determines that communication continues. Furthermore, when the processing device 100 sends the second data after outputting a low level as XC, the interface circuit 80 receives the sent second data and writes it into a register. Thus, after receiving the first data, the interface circuit 80 detects whether the processing device 100 outputs a low level, thereby determining whether communication continues and being able to receive the next second data. Therefore, the interface circuit 80 can continuously receive multiple data sets of a predetermined number of bits, such as the first data and the second data. Furthermore, if the processing device 100 does not output a low level after sending the first data, such as... Figure 5 As shown, the data line is pulled up by resistor RP and set to a high level. Therefore, interface circuit 80 can determine that communication will not continue and stop.

[0065] Furthermore, in this embodiment, in Figure 6 , Figure 8During data reading, after the interface circuit 80 sends the first data of a specified number of bits, when the processing device 100 outputs a low level, it determines that communication continues and sends the next second data of the specified number of bits. That is, in Figure 6 , Figure 8 In the data reading process of the master device, the interface circuit 80, acting as the slave device, sends the first data, consisting of 8 bits, as a predetermined number of bits. Then, when the processing device 100 outputs a low level as an indication to continue communication (XC), the interface circuit 80 determines that communication should continue and sends the next second data. Thus, after the first data is sent, the interface circuit 80 detects whether the processing device 100 outputs a low level, thereby determining whether communication should continue and enabling the transmission of the next second data. Therefore, the interface circuit 80 can continuously send multiple data sets of the predetermined number of bits, such as the first and second data. Furthermore, if the processing device 100 does not output a low level after the first data is sent by the interface circuit 80, the data line is pulled up by the resistor RP and set to a high level; therefore, the interface circuit 80 can determine that communication should not continue and stop.

[0066] 2. Detailed structural example

[0067] Figure 9 This is a detailed first structural example of the oscillator 4 in this embodiment. The oscillator 4 in this detailed first structural example, besides... Figure 1 In addition to its structure, it also includes a temperature sensor circuit 40 and a temperature compensation circuit 60.

[0068] Temperature sensor circuit 40 measures the ambient temperature and other temperatures of oscillator 10 and circuit device 20, and outputs the result as temperature detection data DTD. Here, temperature detection data DTD is data used to determine the detected temperature, and is data corresponding to the detected temperature. Temperature detection data DTD is data that monotonically increases or decreases relative to temperature within the operating temperature range of oscillator 4. Temperature sensor circuit 40 can be implemented, for example, by utilizing the temperature dependence of the oscillation frequency of a ring oscillator. Specifically, temperature sensor circuit 40 includes a ring oscillator and a counter. The counter counts the output pulse signal of the ring oscillator's oscillation signal during a counting period defined by a clock signal CK based on the oscillation signal OSC from oscillation circuit 30, and outputs the count value as temperature detection data DTD. Furthermore, temperature sensor circuit 40 is not limited to the above description, and may also include, for example, an analog temperature sensor that outputs a temperature detection voltage utilizing the temperature dependence of the forward voltage of a PN junction; and an A / D conversion circuit that performs A / D conversion on the temperature detection voltage to output temperature detection data DTD.

[0069] The temperature compensation circuit 60 performs temperature compensation processing based on the temperature detection data DTD from the temperature sensor circuit 40. This temperature compensation processing includes, for example, suppressing and compensating for fluctuations in the oscillation frequency caused by temperature variations. Specifically, the temperature compensation circuit 60 performs temperature compensation processing on the oscillation frequency of the oscillation circuit 30, ensuring that the frequency remains constant even in the presence of temperature variations. More specifically, the temperature compensation circuit 60 performs temperature compensation processing based on digital calculations, which are performed using the temperature detection data DTD from the temperature sensor circuit 40.

[0070] In this embodiment, the oscillation circuit 30 includes a variable capacitor circuit 32. The oscillation frequency of the oscillation circuit 30 can be adjusted by adjusting the capacitance of the variable capacitor circuit 32. The variable capacitor circuit 32 includes, for example, a capacitor array and a switch array connected to the capacitor array. Alternatively, the variable capacitor circuit 32 can be implemented using a variable capacitor element such as a varactor diode. The switches of the switch array of the variable capacitor circuit 32 are turned on and off according to frequency adjustment data from the temperature compensation circuit 60. For example, the variable capacitor circuit 32 includes a first capacitor array having multiple capacitors whose capacitance values ​​are binary-weighted. Furthermore, the variable capacitor circuit 32 includes a first switch array, each switch of which has multiple switches for turning on and off the connection between each capacitor of the first capacitor array and the connection disk PX1. Additionally, the variable capacitor circuit 32 may also include: a first variable capacitor circuit having a first capacitor array and a first switch array connected to the connection disk PX1; and a second variable capacitor circuit having a second capacitor array and a second switch array connected to the connection disk PX2. The switches in the first and second switch arrays are turned on and off according to frequency adjustment data.

[0071] That is, in Figure 9 In the detailed first structural example shown, the temperature sensor circuit 40 measures the ambient temperature and other temperatures of the oscillator 10 and the circuit device 20, and outputs the results as temperature detection data DTD to the temperature compensation circuit 60 and the interface circuit 80. Furthermore, the temperature compensation circuit 60 performs processing to suppress and compensate for fluctuations in the oscillation frequency of the oscillation signal OSC caused by temperature variations, based on the temperature detection data DTD received from the temperature sensor circuit 40. Specifically, frequency adjustment data is calculated based on the temperature detection data DTD, and the capacitance value of the variable capacitor circuit 32 of the oscillation circuit 30 is adjusted based on the calculated frequency adjustment data. Thus, in the oscillator 4 of this embodiment, temperature compensation processing of the oscillation frequency output by the oscillation circuit 30 is possible.

[0072] Furthermore, the interface circuit 80 transmits the temperature detection data DTD as a data signal DA to the external processing device 100 via the first terminal TDA. Specifically, the processing device 100 has an interface circuit 110 that receives the temperature detection data DTD. Thus, in the oscillator 4 of this embodiment, the temperature detection data DTD is transmitted from the interface circuit 80 to the external processing device 100 via the first terminal TDA. Therefore, it is possible to measure the temperature corresponding to the temperature detection data DTD.

[0073] As Figure 9 An application example of the detailed first structural example shown is considered as follows: A 32kHz clock signal CK from an oscillator 4 is supplied to the RTC circuit of a processing device 100, such as a microcomputer, to realize calendar timing processing in the RTC. In this case, the calendar timing processing needs to be executed continuously; therefore, the clock signal CK from the oscillator 4 needs to be continuously supplied to the RTC circuit of the processing device 100. On the other hand, the processing device 100 sometimes performs such calendar timing processing while detecting, for example, the ambient temperature, and performs warning notification processing if the temperature exceeds the upper limit or falls below the lower limit. In this case, the processing device 100 effectively utilizes the temperature detection data DTD from the temperature sensor circuit 40 of the oscillator 4, and detects the temperature based on the temperature detection data DTD output from the oscillator 4 via the interface circuit 80, thereby enabling the execution of warning notification processing. In such a case, according to Figure 9 The structure allows the temperature detection data (DTD) from the oscillator 4 to be sent to the processing device 100. Simultaneously, during and outside of this data communication, the clock signal CK of the oscillator 4 is continuously provided to the RTC circuit of the processing device 100. Therefore, calendar timing processing can be implemented. That is, the processing device 100 can simultaneously perform temperature detection based on the temperature detection data (DTD) and calendar timing processing based on the clock signal CK.

[0074] Figure 10 This is a detailed second structural example of the oscillator 4 in this embodiment. The oscillator 4 in this detailed second structural example, besides... Figure 1 In addition to its structure, it also includes a PLL circuit 36.

[0075] PLL circuit 36 ​​generates a clock signal CK that multiplies the frequency of the oscillation signal OSC, which serves as the reference clock signal. Specifically, PLL circuit 36 ​​has a voltage-controlled oscillator circuit that compares the phase of the oscillation signal OSC, which serves as the reference clock signal, with the phase of the feedback clock signal to generate the clock signal CK with the multiplied frequency. As PLL circuit 36, for example, a fractional-N type PLL circuit capable of fractional frequency multiplication can also be used.

[0076] PLL circuit 36 ​​is disposed between oscillation circuit 30 and output circuit 90. First, interface circuit 80, acting as a slave device, receives frequency setting data DFS sent by processing device 100, acting as a master device, via terminal TDA. Here, frequency setting data DFS contains information for setting the clock frequency of the clock signal CK output by oscillator 4, and the content of this data can be set in processing device 100. Next, the frequency setting data DFS received by interface circuit 80 is set in PLL circuit 36. For example, a control circuit (not shown) sets the frequency setting data DFS in PLL circuit 36. Then, in PLL circuit 36, processing is performed to generate a clock signal CK of a specified frequency based on the frequency setting data DFS. Furthermore, the clock signal CK generated by PLL circuit 36 ​​is input to output circuit 90 and interface circuit 80. Output circuit 90 outputs the clock signal CK to processing device 100 via clock output terminal TCK, and this clock signal CK is used as the operating clock of processing device 100. Alternatively, the clock signal CK may also be used as the operating clock of other external devices such as SA. Furthermore, the clock signal CK is also used as a serial clock signal in serial data communication between the master and slave devices. That is, according to the detailed second structural example of this embodiment, the frequency of the clock signal CK output by the oscillator 4 can be set to the desired frequency using the frequency setting data DFS, and various frequencies of clock signals CK required by the processing device 100 or other external devices SA can be generated.

[0077] Additionally, in the case of, for example Figure 10 With such a structure, if the frequency of the clock signal CK is set to a higher frequency, communication between the processing device 100 and the oscillator 4 will use the higher frequency clock signal CK, which may prevent proper communication. In such a case, for example, using... Figure 11 The method described in the text is sufficient.

[0078] For example, in Figure 11 The diagram illustrates the cases where the waveforms of the specified bit patterns are defined as logic levels "0" and "1", respectively. Figure 11 The waveform pattern in the upper segment is, for example, the waveform pattern corresponding to the logic level "0". Figure 11The waveform pattern of the lower segment is, for example, the waveform pattern corresponding to logic level "1". The waveform pattern corresponding to logic level "0" is, for example, the pattern of a high-level data signal DA for 4 clock cycles after a low-level data signal DA for 8 clock cycles of the output clock signal CK. The waveform pattern corresponding to logic level "1" is, for example, the pattern of a high-level data signal DA for 8 clock cycles of the output clock signal CK after a low-level data signal DA for 4 clock cycles of the output clock signal CK. That is, logic levels "0" and "1" are determined by judging the ratio of the low-level pulse length to the high-level pulse length. Furthermore, when n is set to an integer greater than or equal to 1, n clock cycles refer to the period of n clock cycles of the clock signal CK.

[0079] For example in Figure 7 , Figure 8 In this context, the communication period of one bit is defined as the length of one clock cycle. When the frequency of the clock signal CK is relatively low, such as 32kHz, communication can proceed without problems even if the communication period of one bit is one clock cycle. However, when the frequency of the clock signal CK is high, such as several MHz to tens of MHz, the clock cycle becomes shorter, and the communication period of one bit becomes shorter, resulting in communication errors. For example, communication errors may occur such as the slave device failing to receive one bit of information sent by the master device, or the master device failing to receive one bit of information sent by the slave device. In such cases, when the logic level of the bit is "0", for example... Figure 11 The waveform pattern in the upper segment communicates information. When the logic level of a bit is "1", for example... Figure 11 The lower segment of the waveform pattern communicates information. This prevents communication errors such as the slave device failing to receive a 1-bit message sent by the master device, or the master device failing to receive a 1-bit message sent by the slave device. Therefore, highly reliable and stable communication between the master and slave devices can be achieved.

[0080] In the oscillator 4 of this embodiment, sometimes the output frequency is a clock signal CK that is higher than the frequency required for serial communication. For example, such as... Figure 10 The diagram shows the case where the oscillator 4 outputs a clock signal CK, which is the frequency of the oscillation signal from the oscillation circuit 30 after being multiplied by the PLL circuit 36. Thus, when the frequency of the clock signal CK output by the oscillator 4 is high, such as... Figure 11 The method of communication, which defines a specified waveform pattern corresponding to logic levels "0" and "1" as shown, is effective.

[0081] The above explanation uses the case where the oscillator 4 has four external terminals as an example. However, the number of external terminals of the oscillator 4 is not limited to four; it can also have five or more terminals. For example, using... Figure 12 , Figure 13 The case where the number of external terminals of oscillator 4 is 6 terminals will be explained.

[0082] Figure 12 This is a diagram showing the state of the communication mode of the oscillator 4 when this embodiment is not applied. Figure 12 Oscillator 4 is an oscillator with six terminals: power supply terminal TVDD, ground terminal TGND, clock output terminal TCK, output enable terminal TOE, first terminal TDA (as a data terminal), and serial clock input terminal TSCK. Additionally, in Figure 12 In oscillator 4, structural elements other than external terminals are simplified in designation due to differences in communication states. Regarding... Figure 13 The same applies.

[0083] exist Figure 12 In this circuit, oscillator 4 outputs a clock signal CK to an external processing device 100 (which acts as the master device) or an external device SA, etc. Furthermore, the processing device 100, acting as the master device, outputs a serial clock signal SCK via the serial clock input terminal ESCK as a communication clock for data communication with the oscillator 4, which acts as a slave device. Here, the frequency of the serial clock signal SCK output by the processing device 100 is usually different from the frequency of the clock signal CK output by the oscillator 4. Therefore, the communication serial clock signal SCK interferes with the clock signal CK, generating jitter noise and other noise in the clock signal CK. That is, because the clock signal CK output from the oscillator 4 is out of sync with the communication serial clock signal SCK from the processing device 100, the noise generated by the communication serial clock signal SCK is superimposed on the clock signal CK, thus generating jitter noise and other noise relative to the clock signal CK. As a result, the clock signal characteristics of the clock signal CK deteriorate, adversely affecting the operation of the processing device 100, the external device SA, and the external device SB, which operate based on the clock signal CK.

[0084] Regarding this point, such as Figure 13 As shown, in the structure applying this embodiment, instead of the serial clock signal SCK output by the master device for communication, the clock signal CK output by the oscillator 4, which is the slave device, is used for data communication. That is, the clock signal CK output by the oscillator 4 is used as a clock signal for the operation of the processing device 100, etc., and is also used as a clock signal for communication between the master device and the slave device. Therefore, as Figure 12In such cases, it can effectively prevent the following problems: noise caused by the serial clock signal SCK used for communication is superimposed on the clock signal CK, resulting in a deterioration of the clock signal characteristics.

[0085] 3. Devices

[0086] Figure 14 An example of the structure of device 5 in this embodiment is shown. Additionally, in Figure 14 The diagram also shows the structure of a processing system 200 including device 5 and processing device 100. Device 5 communicates with processing device 100. Device 5 includes circuitry 20. Circuitry 20 includes interface circuitry 80, output circuitry 90, and clock signal generation circuitry 34.

[0087] Figure 14 The device 5 shown in this embodiment includes: a clock signal generation circuit 34 that generates a clock signal CK; a clock output terminal TCK; an output circuit 90 that outputs the clock signal CK to an external processing device 100 via the clock output terminal TCK; a first terminal TDA; and an interface circuit 80 that communicates with the processing device 100 via a data signal DA. During communication, the output circuit 90 outputs the clock signal CK to the processing device 100, which acts as the master device for communication. Furthermore, the interface circuit 80, acting as the slave device for communication, receives the data signal DA transmitted from the processing device 100, synchronized with the clock signal CK, via the first terminal TDA, or transmits the data signal DA synchronously with the clock signal CK to the processing device 100 via the first terminal TDA.

[0088] Here, the clock signal generation circuit 34 is a circuit that generates the clock signal CK. The clock signal generation circuit 34 generates the clock signal CK by means of, for example, a quartz oscillator, an LC oscillator, a CR oscillator, or an oscillator using ceramic components.

[0089] According to this embodiment, data communication between the processing device 100 and the device 5 can be performed using the clock signal CK output by the device 5. Therefore, even when the number of external terminals of the device 5 is small, both the output of the clock signal CK from the device 5 and data communication between the processing device 100 and the device 5 can be performed simultaneously. Alternatively, as described above... Figure 12 , Figure 13 As explained, it can prevent the noise generated by the serial clock signal SCK used for communication from superimposing with the clock signal CK, which would cause a deterioration in the clock signal characteristics.

[0090] In addition, as Figure 14In addition to the oscillator 4, various other devices can be conceived for the device 5. For example, device 5 can be a sensor device such as a gyroscope sensor or an accelerometer, a display device that displays images on a display panel, a communication device that communicates using a specified communication standard, a driver device that drives a specified mechanism for a printer, or a power supply device that supplies or controls power. Furthermore, the circuit device 20 of this embodiment is not limited to being assembled into device 5, but can also be an IC (Integrated Circuit) assembled into the aforementioned sensor device, display device, communication device, or power supply device. For example, if device 5 is a gyroscope sensor, circuit device 20 can include a drive circuit that drives the oscillator of the gyroscope sensor, a detection circuit that detects the sensor signal from the oscillator 10, etc. If device 5 is an accelerometer sensor, circuit device 20 can include a drive circuit or a detection circuit for an acceleration sensor element implemented by a MEMS (Micro Electromechanical Systems), etc. If the sensor is a display device, circuit device 20 can include a drive circuit for the display panel or a logic circuit for processing display data, etc.

[0091] When the sensor is a communication device, the circuit device 20 can include physical layer circuitry, data link layer circuitry, and logic circuitry for communication. Thus, various circuit structures can be employed as the circuit device 20. Furthermore, in each of the above cases, the circuit device 20 has an interface circuit 80 for data communication with the processing device 100, which is the main device.

[0092] Figure 15 The first construction example of the oscillator 4 according to this embodiment is shown. The oscillator 4 includes an oscillator 10, a circuit device 20, and a package 15 for housing the oscillator 10 and the circuit device 20. The package 15 is formed, for example, of ceramic, and has a housing space inside, in which the oscillator 10 and the circuit device 20 are housed. The housing space is hermetically sealed, preferably in a near-vacuum state, i.e., a depressurized state. Through the package 15, the oscillator 10 and the circuit device 20 can be appropriately protected from the effects of impact, dust, heat, moisture, etc.

[0093] Package 15 includes a base 16 and a cover 17. Specifically, package 15 comprises a base 16 supporting the oscillator 10 and the circuit device 20, and a cover 17 engaged with the upper surface of the base 16 to form a receiving space between the cover and the base 16. The oscillator 10 is supported on a stepped portion provided inside the base 16 via terminal electrodes. The circuit device 20 is disposed on the inner bottom surface of the base 16. Specifically, the circuit device 20 is disposed with its active surface facing the inner bottom surface of the base 16. The active surface is the surface of the circuit device 20 where circuit elements are formed. Furthermore, bumps BMP are formed on the terminals of the circuit device 20. The circuit device 20 is supported on the inner bottom surface of the base 16 via conductive bumps BMP. The conductive bumps BMP are, for example, metal bumps, through which the oscillator 10 and the circuit device 20 are electrically connected. Furthermore, the circuit device 20 is electrically connected to the external terminals 18 and 19 of the oscillator 4 via the bump BMP or the internal wiring of the package 15. The external terminals 18 and 19 are formed on the outer bottom surface of the package 15. The external terminals 18 and 19 are connected to external devices via external wiring. The external wiring is, for example, wiring formed on a circuit board on which the external device is mounted. Thus, clock signals can be output to external devices.

[0094] In addition, Figure 15 In this embodiment, the circuit device 20 is mounted upside down with its active surface facing downwards, but this embodiment is not limited to this mounting. For example, the circuit device 20 can also be mounted with its active surface facing upwards. That is, the circuit device 20 is mounted with its active surface facing the oscillator 10.

[0095] Figure 16 A second construction example of the oscillator 4 is shown. The oscillator 4 includes an oscillator 10, a circuit device 20, and a package 15 for housing the oscillator 10 and the circuit device 20. The package 15 has a base 16 and a cover 17. The base 16 has a first substrate 6 serving as an intermediate substrate, a second substrate 7 stacked on the upper surface of the first substrate 6 in a generally rectangular frame shape, and a third substrate 8 stacked on the bottom surface of the first substrate 6 in a generally rectangular frame shape. The cover 17 is bonded to the upper surface of the second substrate 7, and the oscillator 10 is housed in a housing space S1 formed by the first substrate 6, the second substrate 7, and the cover 17. For example, the housing space S1 is hermetically sealed to house the oscillator 10, preferably in a near-vacuum state, i.e., a depressurized state. This allows the oscillator 10 to be appropriately protected from impacts, dust, heat, moisture, etc. In addition, the circuit device 20, which serves as a semiconductor chip, is housed in a housing space S2 formed by the first substrate and the third substrate 8. In addition, external terminals 18 and 19, which serve as external connections for the oscillator 4, are formed on the bottom surface of the third substrate 8.

[0096] Furthermore, in the storage space S1, the oscillator 10 is connected to a first electrode terminal (not shown) and a second electrode terminal (not shown) formed on the upper surface of the first substrate 6 via conductive connecting portions CDC1 and CDC2. The conductive connecting portions CDC1 and CDC2 can be implemented, for example, by conductive bumps such as metal bumps, or by conductive adhesives. Specifically, for example, a first electrode connecting plate (not shown) formed at one end of the tuning fork oscillator 10 is connected to the first electrode terminal formed on the upper surface of the first substrate 6 via the conductive connecting portion CDC1. The first electrode terminal is also electrically connected to the connecting plate PX1 of the circuit device 20. Additionally, a second electrode connecting plate (not shown) formed at the other end of the tuning fork oscillator 10 is connected to the second electrode terminal formed on the upper surface of the first substrate 6 via the conductive connecting portion CDC2. The second electrode terminal is also electrically connected to the connecting plate PX2 of the circuit device 20. Therefore, one end of the oscillator 10 and the other end can be electrically connected to the connection pads PX1 and PX2 of the circuit device 20 via conductive connection portions CDC1 and CDC2. Furthermore, conductive bumps BMP are formed on the multiple connection pads of the circuit device 20, which are semiconductor chips, and these conductive bumps BMP are connected to multiple electrode terminals formed on the bottom surface of the first substrate 6. Moreover, the electrode terminals connected to the connection pads of the circuit device 20 are electrically connected to the external terminals 18 and 19 of the oscillator 4 via internal wiring or the like.

[0097] Alternatively, the oscillator 4 can also be a wafer-level packaged (WLP) oscillator. In this case, the oscillator 4 includes: a base having a semiconductor substrate and a through electrode penetrating between a first surface and a second surface of the semiconductor substrate; an oscillator 10 fixed to the first surface of the semiconductor substrate via conductive bonding members such as metal bumps; and external terminals disposed on the second surface of the semiconductor substrate via an insulating layer such as a redistribution wiring layer. Furthermore, an integrated circuit forming a circuit device 20 is formed on either the first or second surface of the semiconductor substrate. In this case, by bonding a first semiconductor wafer with multiple bases on which the oscillator 10 and the integrated circuit are disposed to a second semiconductor wafer with multiple covers, the multiple bases and multiple covers are joined, and then the oscillator 4 is monolithically produced using a dicing machine or the like. In this way, a wafer-level packaged oscillator 4 can be realized, enabling the manufacture of the oscillator 4 with high productivity and low cost.

[0098] As described above, this embodiment relates to an oscillator comprising: an oscillator; an oscillation circuit that generates an oscillation signal using the oscillator; a clock output terminal; an output circuit that outputs a clock signal to an external processing device via the clock output terminal; a first terminal; and an interface circuit that communicates with the processing device via a data signal. In the communication, the output circuit outputs a clock signal to the processing device, which is the master device for communication, and the interface circuit, which is the slave device for communication, receives a data signal synchronized with the clock signal sent from the processing device via the first terminal, or sends a data signal synchronized with the clock signal to the processing device via the first terminal.

[0099] According to this embodiment, data communication between the processing device and the oscillator can be performed using the clock signal output by the oscillator. Therefore, it is possible to balance the output of the clock signal from the oscillator and the data communication between the external device as the master device and the oscillator as the slave device.

[0100] Alternatively, in this embodiment, the first terminal may be an output enable terminal that switches between enabling and disabling the clock signal output.

[0101] In this way, the first terminal can not only function as a data signal transceiver terminal, but also as a terminal for controlling the on / off state of the oscillator's clock signal output.

[0102] Alternatively, in this embodiment, the interface circuit may start communication upon receiving a communication start key from the processing device.

[0103] In this way, communication between the master and slave devices begins on the condition that the master device sends an appropriate code to the slave device using a communication start key. This prevents erroneous judgments of communication start due to noise or other issues contained in the data signal.

[0104] Alternatively, in this embodiment, it can also be a 4-terminal oscillator including a power supply terminal, a ground terminal, a clock output terminal, and a first terminal.

[0105] In this way, in an oscillator with only 4 external terminals, a clock signal can be continuously output from the oscillator regardless of whether data communication is taking place between the external device as the master device and the oscillator as the slave device.

[0106] Alternatively, in this embodiment, the output circuit may also output a clock signal during periods other than the communication period.

[0107] In this way, the oscillator outputs a clock signal as a slave device in communication, thereby maintaining the working state of the processing device or other external devices.

[0108] Alternatively, in this embodiment, the data line connecting the processing device and the interface circuit may be pulled up, and the interface circuit may include an I / O circuit having an open-drain N-type transistor.

[0109] In this way, even if neither the master nor the slave device drives the data line of the data signal to a low level through an open-drain N-type transistor, the data line is also pulled up to a high level, thus enabling serial data communication using the data line.

[0110] Alternatively, in this embodiment, after the interface circuit receives the first data of a specified number of bits, the processing device outputs a low level, determines that communication continues, and receives the next second data of the specified number of bits.

[0111] In this way, the interface circuit can continuously receive data signals in units of a specified number of bits, and can determine that communication has stopped if the processing device does not output a low level.

[0112] Alternatively, in this embodiment, after the interface circuit sends the first data of a specified number of bits, when the processing device outputs a low level, it determines that communication continues and sends the next second data of a specified number of bits.

[0113] In this way, the interface circuit can continuously send data signals in units of a specified number of bits, and can determine that communication has stopped if the processing device does not output a low level.

[0114] Alternatively, this embodiment may also include: a temperature sensor circuit that outputs temperature detection data; and a temperature compensation circuit that performs temperature compensation on the oscillation frequency of the oscillation signal based on the temperature detection data, and an interface circuit that sends the temperature detection data to the processing device via the first terminal.

[0115] In this way, temperature compensation based on the oscillation frequency of temperature detection data can be performed, and temperature detection using temperature detection data can also be performed in the processing unit, which is the main device.

[0116] Alternatively, in this embodiment, the interface circuit may receive frequency setting data of the clock signal from the processing device via the first terminal.

[0117] In this way, while the oscillator is outputting a clock signal, the frequency of the clock signal output by the oscillator can be set to the desired frequency using frequency setting data from the processing device.

[0118] Additionally, this embodiment relates to a device comprising: a clock signal generation circuit that generates a clock signal; a clock output terminal; an output circuit that outputs the clock signal to an external processing device via the clock output terminal; a first terminal; and an interface circuit that communicates with the processing device via a data signal. In the communication, the output circuit outputs the clock signal to the processing device, which is the master device for communication, and the interface circuit, which is the slave device for communication, receives a data signal synchronized with the clock signal sent from the processing device via the first terminal, or sends the data signal synchronized with the clock signal to the processing device via the first terminal.

[0119] According to this embodiment, data communication between the processing device and the device can be performed using the clock signal output by the device. Therefore, it is possible to balance the output of the clock signal from the device and the data communication between the external device as the master device and the device as the slave device.

[0120] Furthermore, although this embodiment has been described in detail above, those skilled in the art will readily understand that various modifications can be made without substantially departing from the novel aspects and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, in the specification or drawings, any term that is described at least once with a different term that is more general or synonymous can be replaced with that different term anywhere in the specification or drawings. Additionally, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. Furthermore, the structure, operation, etc., of oscillators, devices, and processing apparatuses are not limited to those described in this embodiment, and various modifications can be implemented.

Claims

1. An oscillator, characterized in that, This oscillator is a 4-terminal oscillator comprising a power supply terminal, a ground terminal, a clock output terminal, and an output enable terminal, including: Vibrator; An oscillating circuit that uses the oscillator to generate an oscillating signal; An output circuit that outputs a clock signal based on the oscillation signal to an external processing device via the clock output terminal; Interface circuit; Temperature sensor circuit, which outputs temperature detection data; as well as A temperature compensation circuit, based on the temperature detection data, performs temperature compensation on the oscillation frequency of the oscillation signal. Before the interface circuit receives the communication start key from the processing device via the output enable terminal, the output circuit switches the output of the clock signal to enable or disable based on the potential of the output enable terminal. The interface circuit initiates communication with the processing device upon receiving the communication start key from the processing device via the output enable terminal. The output circuit outputs the clock signal to the processing device, which is the master device in the communication. The interface circuit, which is the slave device in the communication, receives a data signal synchronized with the clock signal from the processing device via the output enable terminal, or sends the data signal synchronized with the clock signal to the processing device via the output enable terminal. In the communication, the interface circuit sends the temperature detection data to the processing device via the output enable terminal.

2. The oscillator according to claim 1, characterized in that, The output circuit also outputs the clock signal during periods other than the communication period.

3. The oscillator according to claim 1, characterized in that, The data line connecting the processing device and the interface circuit is pulled up. The interface circuit includes I / O circuitry, which has an open-drain N-type transistor.

4. The oscillator according to claim 1, characterized in that, After receiving the first data of a specified number of bits, the interface circuit determines that the communication will continue when the processing device outputs a low level, and then receives the next second data of the specified number of bits.

5. The oscillator according to claim 1, characterized in that, After the interface circuit sends the first data of a specified number of bits, when the processing device outputs a low level, it determines that the communication continues and sends the next second data of the specified number of bits.

6. The oscillator according to claim 1, characterized in that, In the communication, the interface circuit receives frequency setting data of the clock signal from the processing device via the output enable terminal. The data signal corresponds to 1 bit for each of the multiple pulses of the clock signal. The logic level of the 1 bit is defined according to the ratio of the number of pulses with low level to the number of pulses with high level in the multiple pulses.

7. A device, characterized in that, This device is a four-terminal device comprising a power supply terminal, a ground terminal, a clock output terminal, and an output enable terminal, and includes: A clock signal generation circuit that generates a clock signal; An output circuit that outputs the clock signal to an external processing device via the clock output terminal; as well as The interface circuit communicates with the processing device via data signals. Before the interface circuit receives the communication start key from the processing device via the output enable terminal, the output circuit switches the output of the clock signal to enable or disable based on the potential of the output enable terminal. The interface circuit initiates communication with the processing device upon receiving the communication start key from the processing device via the output enable terminal. The output circuit outputs the clock signal to the processing device, which is the master device in the communication. The interface circuit, which is the slave device in the communication, receives a data signal synchronized with the clock signal from the processing device via the output enable terminal, or sends the data signal synchronized with the clock signal to the processing device via the output enable terminal.

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