A multi-chip device and electronic apparatus

Abstract

The embodiment of the application discloses a kind of multi-chip device and electronic equipment, it is related to chip field, can promote phased array performance.Specific scheme is: multi-chip device includes the first chip with first built-in signal generator and first frequency multiplier, the second chip with second built-in signal generator and second frequency multiplier;Second frequency multiplier includes first receiving circuit, second receiving circuit and load circuit, the input end of first receiving circuit is coupled to the output end of first built-in signal generator, the input end of second receiving circuit is coupled to the output end of second built-in signal generator, the output end of first receiving circuit and the output end of second receiving circuit are coupled to the input end of load circuit;Second frequency multiplier is used to receive the first local signal generated by first built-in signal generator by first receiving circuit, receive the second local signal generated by second built-in signal generator by second receiving circuit, and for the frequency multiplication of first local signal or second local signal.

Description

Technical Field

[0001] This application relates to the field of chips, and more particularly to a multi-chip device and electronic device. Background Technology

[0002] Fifth-generation (5G) mobile communication operates in the millimeter-wave band, which boasts abundant spectrum resources and a wide operating bandwidth, but suffers from high propagation loss. To reduce transmission loss during millimeter-wave communication, phased array beamforming technology can be used to enhance signal gain. Besides the 5G millimeter-wave band, phased arrays are also increasingly being used in indoor communication, automotive communication, and other fields.

[0003] However, the performance of phased arrays in existing technologies is limited, which affects the quality of wireless communication. Therefore, obtaining higher performance from phased arrays has become an urgent problem to be solved. Summary of the Invention

[0004] This application provides a multi-chip device and electronic device for improving phased array performance.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] A first aspect of this application provides a multi-chip device, comprising a first chip and a second chip. The first chip includes a first built-in signal generator and a first frequency multiplier coupled to the first built-in signal generator. The second chip includes a second frequency multiplier, which is coupled to the first built-in signal generator via input / output pins between the first and second chips. The first built-in signal generator generates a first local oscillator signal, and the first and second frequency multipliers receive and multiply the first local oscillator signal. Based on this solution, since the first local oscillator signal generated by the first built-in signal generator can be input to the first frequency multiplier or input to the second frequency multiplier via the input / output pins between the first and second chips, both the local oscillator signals of the first and second chips originate from the first built-in signal generator. Therefore, the signal sources of the local oscillator signals of the first and second chips are the same. When using the first and second chips for phased array splicing, the signals of the first and second chips can be superimposed, improving the phased array gain.

[0007] In conjunction with the first aspect, in one possible implementation, the multi-chip device further includes a power divider. This power divider includes a first output terminal and a second output terminal. The input terminal of the power divider is coupled to the output terminal of the first built-in signal generator. The first and second output terminals of the power divider are respectively coupled to the first frequency multiplier and the second frequency multiplier. Based on this solution, by setting a power divider in the multi-chip device, the signal paths of the first local oscillator signal input to the first frequency multiplier and the first local oscillator signal input to the second frequency multiplier are completely identical. Therefore, the phase, amplitude, and frequency of the local oscillator signal of the first chip and the local oscillator signal of the second chip are all the same, ensuring phase alignment between the first chip and the second chip.

[0008] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the first chip further includes an output driver coupled to the output terminal of the first built-in signal generator. This output driver is used to amplify the first local oscillator signal. Based on this solution, the first local oscillator signal in the first chip can be amplified by the output driver and externally input to the second chip, thereby making the signal sources of the local oscillator signals of the first chip and the second chip the same. Optionally, the first local oscillator signal input to the output driver can be a differential signal, and the first local oscillator signal output by the output driver can be a single-ended signal.

[0009] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the second chip further includes a second built-in signal generator coupled to the second frequency multiplier. This second built-in signal generator generates a second local oscillator signal. The second frequency multiplier also receives the second local oscillator signal and multiplies its frequency. Based on this solution, the second frequency multiplier can be used to receive either the first or the second local oscillator signal. That is, the second frequency multiplier supports both built-in signal input (the second local oscillator signal) and external signal input (the first local oscillator signal). Therefore, when receiving the first local oscillator signal, the second frequency multiplier can multiply the first local oscillator signal; when receiving the second local oscillator signal, the second frequency multiplier can multiply the second local oscillator signal.

[0010] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the second chip further includes a selector, through which the second built-in signal generator is coupled to the second frequency multiplier; the second frequency multiplier is used to select, via the selector, the reception of the first local oscillator signal and the second local oscillator signal. Based on this scheme, the second frequency multiplier can select, via the selector, the reception of built-in signal input and external signal input, and then multiply the received signals. In this implementation, the selector and frequency multiplier in the second chip are two-stage circuits.

[0011] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the second frequency multiplier includes a first receiving circuit, a second receiving circuit, and a load circuit. The input terminal of the first receiving circuit is coupled to the first built-in signal generator through the input / output pins of the first and second chips. The input terminal of the second receiving circuit is coupled to the output terminal of the second built-in signal generator. The output terminals of the first and second receiving circuits are coupled to the input terminal of the load circuit. The first receiving circuit receives a first local oscillator signal, and the second receiving circuit receives a second local oscillator signal. Based on this scheme, the first and second receiving circuits in the frequency multiplier allow the second frequency multiplier to selectively receive both the first and second local oscillator signals. In this implementation, the second chip only needs the second frequency multiplier to achieve both selection and frequency multiplication functions. Compared to the previous implementation where the second chip requires both a selector and a frequency multiplier to achieve these functions, this implementation reduces the chip area and power consumption.

[0012] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the first receiving circuit includes a conversion circuit and a first differential circuit. The input terminal of the conversion circuit is the input terminal of the first receiving circuit, and the two output terminals of the conversion circuit are respectively coupled to the input terminal of the first differential circuit. The output terminal of the first differential circuit is the output terminal of the first receiving circuit. The conversion circuit is used to convert the input first local oscillator signal into a differential signal. The differential circuit is used to receive the differential signal and output the differential signal to the aforementioned load circuit. Based on this scheme, the first local oscillator signal can be converted into a differential signal by the conversion circuit, and then the differential signal can be input into the differential circuit to achieve the receiving function. Optionally, the output signal of the first differential circuit can be a single-ended signal or a differential signal.

[0013] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the first differential circuit includes a first metal-oxide-semiconductor (MOS) transistor and a second MOS transistor. The first terminals of the first and second MOS transistors serve as the input terminals of the first differential circuit. The second terminals of both MOS transistors are grounded or connected to a first power supply. The third terminals of both MOS transistors serve as the output terminals of the first receiving circuit. Based on this solution, the receiving function can be achieved by inputting the differential signal output from the conversion circuit into a pair of differential transistors.

[0014] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the first MOSFET and the second MOSFET are N-type MOSFETs. The first terminal of the first MOSFET is the gate, the second terminal is the source, and the third terminal is the drain. The first terminal of the second MOSFET is the gate, the second terminal is the source, and the third terminal is the drain. The sources of both the first and second MOSFETs are grounded. Based on this scheme, the first differential circuit can be composed of two N-type MOSFETs. After the differential signal output from the conversion circuit is input into the differential circuit composed of these two N-type MOSFETs, the receiving function can be realized, and the loss is low.

[0015] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the conversion circuit includes a first transformer. One end of the primary coil of the first transformer serves as the input terminal of the first receiving circuit, the second end of the primary coil is grounded, and the two ends of the secondary coil serve as the two output terminals of the conversion circuit. Based on this scheme, a single-ended signal can be converted into a differential signal using a transformer, and this differential signal can be input into a pair of differential transistors to achieve the receiving function.

[0016] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the second receiving circuit includes a second differential circuit for receiving the second local oscillator signal and outputting the second local oscillator signal to the load circuit. Based on this scheme, by receiving the second local oscillator signal through a differential circuit, the output signal of the second receiving circuit can be either a single-ended signal or a differential signal.

[0017] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the second differential circuit includes a third MOSFET and a fourth MOSFET. The first terminals of the third and fourth MOSFETs are the two input terminals of the second receiving circuit. The second terminals of the third and fourth MOSFETs are grounded or connected to a second power supply. The third terminals of the third and fourth MOSFETs are the output terminals of the second receiving circuit. Based on this scheme, the second local oscillator signal is received through a pair of differential transistors, allowing the output signal of the second receiving circuit to be either a single-ended signal or a differential signal.

[0018] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the third and fourth MOSFETs are N-type MOSFETs. The first terminal of the third MOSFET is the gate, the second terminal is the source, and the third terminal is the drain. The first terminal of the fourth MOSFET is the gate, the second terminal is the source, and the third terminal is the drain. The sources of the third and fourth MOSFETs are grounded. Based on this scheme, the second differential circuit can be composed of two N-type MOSFETs. After the second local oscillator signal is input to the differential circuit composed of these two N-type MOSFETs, the receiving function can be realized, and the loss is low.

[0019] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the load circuit includes a second transformer. One end of the primary coil of the second transformer is connected to a third power supply, and the other end of the primary coil is the input terminal of the load circuit. The two ends of the secondary coil of the first transformer are the output terminals of the load circuit. Based on this scheme, since both the first and second receiving circuits include a pair of differential transistors, when the first receiving circuit receives the first local oscillator signal or the second receiving circuit receives the second local oscillator signal, the corresponding differential transistors will alternately conduct, causing the signal frequency to double. Thus, the second transformer converts the single-ended signal into a differential signal and outputs a double-frequency signal.

[0020] Combining the first aspect and the above possible implementations, in another possible implementation, the load circuit includes a third transformer and a fifth MOSFET. One end of the primary coil of the third transformer is coupled to the fourth power supply and the first end of the fifth MOSFET, respectively. The other end of the primary coil of the third transformer is coupled to the third end of the fifth MOSFET. The second end of the fifth MOSFET is the input terminal of the load circuit, and the two ends of the secondary coil of the third transformer are the output terminals of the load circuit. Based on this scheme, since both the first and second receiving circuits include a pair of differential transistors, when the first receiving circuit receives the first local oscillator signal or the second receiving circuit receives the second local oscillator signal, the corresponding differential transistors will alternately conduct, driving the single-ended cascode transistor M5. After passing through the third transformer, the single-ended signal is converted into a differential signal and output as a second-harmonic signal.

[0021] Combining the first aspect and the above possible implementations, in another possible implementation, the fifth MOSFET is an N-type MOSFET, with its first terminal as the gate, its second terminal as the source, its third terminal as the drain, and its source grounded. Based on this scheme, since both the first and second receiving circuits include a pair of differential transistors, when the first receiving circuit receives the first local oscillator signal or the second receiving circuit receives the second local oscillator signal, the corresponding differential transistors will alternately conduct, driving the single-ended cascode transistor M5. The single-ended signal is then converted into a differential signal by the third transformer, and a second-harmonic signal is output.

[0022] Optionally, the load circuit described above can be an oscillating circuit, and this solution does not limit the specific circuit structure of the oscillating circuit. When the load circuit is an oscillating circuit, the resonant frequency of the oscillating circuit can be n times the frequency of the first local oscillator signal or the frequency of the second local oscillator signal. The oscillating circuit is used to multiply the frequency of the first local oscillator signal or the frequency of the second local oscillator signal by n times. n can be an odd number greater than 1. This application embodiment does not limit the specific circuit structure of the oscillating circuit.

[0023] In conjunction with the first aspect and the above possible implementations, in another possible implementation, the load circuit includes a sixth MOSFET, a seventh MOSFET, and a first LC circuit. The first terminal of the sixth MOSFET is coupled to the third terminal of the seventh MOSFET. The second terminal of the sixth MOSFET is grounded or connected to a fifth power supply. The third terminal of the sixth MOSFET is coupled to the first terminal of the seventh MOSFET. The first terminals of the sixth and seventh MOSFETs are respectively the two input terminals of the load circuit. The two input terminals of the first LC circuit are coupled to the sixth power supply. The two output terminals of the first LC circuit are respectively coupled to the third terminals of the sixth and seventh MOSFETs. The two output terminals of the first LC circuit are the output terminals of the load circuit. Based on this scheme, since both the first and second receiving circuits include a pair of differential transistors, when the first receiving circuit receives the first local oscillator signal or the second receiving circuit receives the second local oscillator signal, the high-order odd-order differential current signal generated by the nonlinearity of the differential pair is injected into the negative resistance resonant cavity formed by the sixth MOSFET, the seventh MOSFET, and the first LC circuit. The resonant cavity resonates and amplifies the high-order odd-order signal to achieve frequency multiplication output.

[0024] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the sixth and seventh MOSFETs are N-type MOSFETs. The first terminal of the sixth MOSFET is the gate, the second terminal is the source, and the third terminal is the drain. Similarly, the first terminal of the seventh MOSFET is the gate, the second terminal is the source, and the third terminal is the drain. The sources of both the sixth and seventh MOSFETs are grounded. Based on this scheme, the two MOSFETs in the load circuit are two N-type MOSFETs. Since NMOS transistors have lower losses, the losses in the load circuit are also lower.

[0025] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the first LC circuit is a transformer. Based on this solution, the first LC circuit in the load circuit can be replaced with a transformer to achieve frequency multiplication output. Optionally, the first LC circuit may also include an inductor and a capacitor, or it may be in other forms; this solution does not limit the specific circuit structure of the first LC circuit.

[0026] Combining the first aspect and the above possible implementations, in another possible implementation, the load circuit includes an eighth MOSFET, a ninth MOSFET, and a second LC circuit. The first terminal of the eighth MOSFET is coupled to the third terminal of the ninth MOSFET, and the third terminal of the eighth MOSFET is coupled to the first terminal of the ninth MOSFET. The second terminals of the eighth and ninth MOSFETs are the two input terminals of the load circuit, respectively. The two input terminals of the second LC circuit are coupled to a seventh power supply, and the two output terminals of the second LC circuit are coupled to the third terminals of the eighth and ninth MOSFETs, respectively. The two output terminals of the second LC circuit are the output terminals of the load circuit. Based on this scheme, since both the first and second receiving circuits include a pair of differential transistors, when the first receiving circuit receives the first local oscillator signal or the second receiving circuit receives the second local oscillator signal, the high-order odd-order differential current signal generated by the nonlinearity of the differential pair is injected into the negative resistance resonant cavity formed by the eighth MOSFET, the ninth MOSFET, and the second LC circuit. The resonant cavity resonates and amplifies this high-order odd-order signal to achieve frequency multiplication output.

[0027] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the eighth and ninth MOS transistors are N-type MOS transistors. The first terminal of the eighth MOS transistor is the gate, the second terminal is the source, and the third terminal is the drain. Similarly, the first terminal of the ninth MOS transistor is the gate, the second terminal is the source, and the third terminal is the drain. The sources of the eighth and ninth MOS transistors are grounded. Based on this scheme, the two MOS transistors in the load circuit are two N-type MOS transistors. Since NMOS transistors have lower losses, the losses in the load circuit are also lower.

[0028] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the second LC circuit is a transformer. Based on this scheme, the second LC circuit in the load circuit can be replaced with a transformer to achieve frequency multiplication output. Optionally, the second LC circuit may also include an inductor and a capacitor, or it may be in other forms; this scheme does not limit the specific circuit structure of the second LC circuit.

[0029] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the resonant frequency of the load circuit is n times the frequency of the first local oscillator signal or the frequency of the second local oscillator signal, where n is an odd number greater than 1. Based on this scheme, the frequency multiplier output can be achieved by setting the resonant frequency in the load circuit.

[0030] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the first chip further includes multiple first phased array channels and a first mixer, wherein the multiple first phased array channels are coupled to the first frequency multiplier via the first mixer; the second chip further includes multiple second phased array channels and a second mixer, wherein the multiple second phased array channels are coupled to the second frequency multiplier via the second mixer. Based on this solution, the first and second receiving circuits in the second frequency multiplier allow the second frequency multiplier to selectively receive the first local oscillator signal and the second local oscillator signal, thus reducing the chip area and lowering chip power consumption.

[0031] A second aspect of this application provides a frequency multiplier, which includes a first receiving circuit, a second receiving circuit, and a load circuit. The input terminal of the first receiving circuit is used to receive a first local oscillator signal, the input terminal of the second receiving circuit is used to receive a second local oscillator signal, and the output terminals of the first and second receiving circuits are coupled to the input terminal of the load circuit.

[0032] In conjunction with the second aspect, in one possible implementation, the first receiving circuit includes a conversion circuit and a first differential circuit. The input terminal of the conversion circuit is the input terminal of the first receiving circuit, and the two output terminals of the conversion circuit are respectively coupled to the input terminal of the first differential circuit. The output terminal of the first differential circuit is the output terminal of the first receiving circuit. The conversion circuit is used to convert the input first local oscillator signal into a differential signal. The differential circuit is used to receive the differential signal and output the differential signal to the load circuit.

[0033] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the first differential circuit includes a first metal-oxide-semiconductor MOSFET and a second MOSFET. The first terminal of the first MOSFET and the first terminal of the second MOSFET are the input terminals of the first differential circuit. The second terminals of the first MOSFET and the second terminals of the second MOSFET are grounded or connected to a first power supply. The third terminals of the first MOSFET and the second terminals of the second MOSFET are the output terminals of the first receiving circuit.

[0034] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the first MOSFET and the second MOSFET are N-type MOSFETs. The first terminal of the first MOSFET is the gate, the second terminal of the first MOSFET is the source, and the third terminal of the first MOSFET is the drain. The first terminal of the second MOSFET is the gate, the second terminal of the second MOSFET is the source, and the third terminal of the second MOSFET is the drain. The source of the first MOSFET and the source of the second MOSFET are grounded.

[0035] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the conversion circuit includes a first transformer, one end of the primary coil of the first transformer being the input terminal of the first receiving circuit, the second end of the primary coil of the first transformer being grounded, and the two ends of the secondary coil of the first transformer being the two output terminals of the conversion circuit.

[0036] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the second receiving circuit includes a second differential circuit for receiving the second local oscillator signal and outputting the second local oscillator signal to the load circuit.

[0037] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the second differential circuit includes a third MOSFET and a fourth MOSFET. The first terminals of the third MOSFET and the fourth MOSFET are the two input terminals of the second receiving circuit. The second terminals of the third MOSFET and the fourth MOSFET are grounded or connected to a second power supply. The third terminals of the third MOSFET and the fourth MOSFET are the output terminals of the second receiving circuit.

[0038] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the third MOS transistor and the fourth MOS transistor are N-type MOS transistors. The first terminal of the third MOS transistor is the gate, the second terminal of the third MOS transistor is the source, and the third terminal of the third MOS transistor is the drain. The first terminal of the fourth MOS transistor is the gate, the second terminal of the fourth MOS transistor is the source, and the third terminal of the fourth MOS transistor is the drain. The source of the third MOS transistor and the source of the fourth MOS transistor are grounded.

[0039] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the load circuit includes a second transformer, one end of the primary coil of the second transformer is connected to a third power source, the other end of the primary coil of the second transformer is the input terminal of the load circuit, and the two ends of the secondary coil of the first transformer are the output terminals of the load circuit.

[0040] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the load circuit includes a third transformer and a fifth MOSFET. One end of the primary coil of the third transformer is coupled to the fourth power supply and the first end of the fifth MOSFET, respectively. The other end of the primary coil of the third transformer is coupled to the third end of the fifth MOSFET. The second end of the fifth MOSFET is the input terminal of the load circuit, and the two ends of the secondary coil of the third transformer are the output terminals of the load circuit.

[0041] In combination with the second aspect and the above possible implementations, in another possible implementation, the fifth MOS transistor is an N-type MOS transistor, with the first terminal of the fifth MOS transistor being the gate, the second terminal of the fifth MOS transistor being the source, the third terminal of the fifth MOS transistor being the drain, and the source of the fifth MOS transistor being grounded.

[0042] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the load circuit includes a sixth MOSFET, a seventh MOSFET, and a first LC circuit. The first terminal of the sixth MOSFET is coupled to the third terminal of the seventh MOSFET. The second terminal of the sixth MOSFET and the second terminal of the seventh MOSFET are grounded or connected to a fifth power supply. The third terminal of the sixth MOSFET is coupled to the first terminal of the seventh MOSFET. The first terminals of the sixth MOSFET and the first terminals of the seventh MOSFET are respectively the two input terminals of the load circuit. The two input terminals of the first LC circuit are coupled to the sixth power supply. The two output terminals of the first LC circuit are respectively coupled to the third terminals of the sixth MOSFET and the seventh MOSFET. The two output terminals of the first LC circuit are the output terminals of the load circuit.

[0043] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the sixth and seventh MOS transistors are N-type MOS transistors. The first terminal of the sixth MOS transistor is the gate, the second terminal is the source, and the third terminal is the drain. The first terminal of the seventh MOS transistor is the gate, the second terminal is the source, and the third terminal is the drain. The sources of the sixth and seventh MOS transistors are grounded.

[0044] In combination with the second aspect and the above possible implementations, in another possible implementation, the first LC circuit is a transformer.

[0045] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the load circuit includes an eighth MOSFET, a ninth MOSFET, and a second LC circuit. The first terminal of the eighth MOSFET is coupled to the third terminal of the ninth MOSFET, and the third terminal of the eighth MOSFET is coupled to the first terminal of the ninth MOSFET. The second terminals of the eighth MOSFET and the ninth MOSFET are respectively the two input terminals of the load circuit. The two input terminals of the second LC circuit are coupled to a seventh power supply, and the two output terminals of the second LC circuit are respectively coupled to the third terminals of the eighth MOSFET and the ninth MOSFET. The two output terminals of the second LC circuit are the output terminals of the load circuit.

[0046] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the eighth MOS transistor and the ninth MOS transistor are N-type MOS transistors. The first terminal of the eighth MOS transistor is the gate, the second terminal of the eighth MOS transistor is the source, and the third terminal of the eighth MOS transistor is the drain. The first terminal of the ninth MOS transistor is the gate, the second terminal of the ninth MOS transistor is the source, and the third terminal of the ninth MOS transistor is the drain. The source of the eighth MOS transistor and the source of the ninth MOS transistor are grounded.

[0047] In combination with the second aspect and the above possible implementations, in another possible implementation, the second LC circuit is a transformer.

[0048] In combination with the second aspect and the above possible implementations, in another possible implementation, the resonant frequency of the load circuit is n times the frequency of the first local oscillator signal or the frequency of the second local oscillator signal, where n is an odd number greater than 1.

[0049] The description of the effects in the second aspect above can be referred to in the description of the effects in the first aspect above, and will not be repeated here.

[0050] A third aspect of the embodiments of this application provides a communication device, the communication device including a first chip as described in any implementation of the first aspect, a second chip as described in any implementation of the first aspect, a plurality of first antenna units, and a plurality of second antenna units, wherein the plurality of first antenna units are coupled to the plurality of first phased array channels one by one, and the plurality of second antenna units are coupled to the plurality of second phased array channels one by one.

[0051] A fourth aspect of this application provides an electronic device including a baseband chip and a multi-chip device as described in any implementation of the first aspect above. Attached Figure Description

[0052] Figure 1 This is a schematic diagram of a phased array beamforming structure provided in an embodiment of this application;

[0053] Figure 2 This is a schematic diagram of a multi-chip array structure provided in an embodiment of this application;

[0054] Figure 3 This is a schematic diagram of the structure of a multi-chip device provided in an embodiment of this application;

[0055] Figure 4 This is a schematic diagram of another multi-chip device provided in an embodiment of this application;

[0056] Figure 5A This is a schematic diagram of another multi-chip device provided in an embodiment of this application;

[0057] Figure 5B This is a schematic diagram of another multi-chip device provided in an embodiment of this application;

[0058] Figure 6 A circuit diagram of a second frequency multiplier provided in an embodiment of this application;

[0059] Figure 7 A schematic diagram of another circuit structure of a second frequency multiplier provided in an embodiment of this application;

[0060] Figure 8 A schematic diagram of another circuit structure of a second frequency multiplier provided in an embodiment of this application;

[0061] Figure 9 A schematic diagram of another circuit structure of a second frequency multiplier provided in an embodiment of this application;

[0062] Figure 10 This is a schematic diagram of another multi-chip device provided in an embodiment of this application;

[0063] Figure 11This is a schematic diagram of the circuit structure of a selector provided in an embodiment of this application;

[0064] Figure 12 A schematic diagram of another circuit structure of a second frequency multiplier provided in an embodiment of this application;

[0065] Figure 13 A schematic diagram of another circuit structure of a second frequency multiplier provided in an embodiment of this application;

[0066] Figure 14 This is a schematic diagram of another multi-chip device provided in an embodiment of this application. Detailed Implementation

[0067] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple. Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order. For example, "first" in "first chip" and "second" in "second chip" in the embodiments of this application are only used to distinguish different chips. The descriptions of "first" and "second" appearing in the embodiments of this application are only for illustrative purposes and to distinguish the described objects; they do not indicate any order and do not represent a special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0068] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0069] Currently, 5G operates in the millimeter-wave band. While the millimeter-wave band offers abundant spectrum resources and a wide operating bandwidth, it suffers from high propagation loss. Phased array beamforming technology is typically used to improve signal gain and reduce transmission loss during millimeter-wave communication. Besides the 5G millimeter-wave band, phased array beamforming technology is also finding widespread application in indoor communication, automotive communication, and other fields.

[0070] For example, such as Figure 1 The phased array receiver shown in (a) receives an incident signal from a certain direction via its antenna. A phase shifter controls the phase of each channel, aligning the signal phases in that direction before superposition, thus increasing the signal gain in that direction. The superimposed signal is then input to a mixer for down-mixing with the signal output from a frequency multiplier, shifting the signal to a lower frequency (e.g., the baseband chip frequency). Figure 1 The phased array transmitter shown in (b) can use a mixer to shift the frequency of the baseband chip to a higher frequency and output it to multiple channels. Then, a phase shifter controls the phase of each channel and transmits the phase-shifted signal through the transmitting antenna to improve the signal gain in a fixed direction and achieve beamforming.

[0071] Since signal gain is directly proportional to the number of channels, the more channels there are, the greater the gain of the phased array. To obtain higher phased array gain, multiple chips can be combined to create a larger number of channels. For example, such as... Figure 2 (a) and Figure 2 As shown in (b), by arranging chips 1 to N in a matrix, a greater number of channels can be obtained. The signal phases of these N chips are superimposed, further enhancing the signal gain.

[0072] For signals from different chips to be superimposed, their local oscillator signals must have the same phase, amplitude, and frequency. However, the phase, amplitude, and frequency of the local oscillator signals from different chips may differ, preventing signal superposition. For example, ... Figure 2 As shown, the local oscillator signal of each chip from chip 1 to chip N is generated by the signal generator within that chip. The local oscillator signals generated by the signal generators in different chips may be out of sync, which will cause the signals from chip 1 to chip N to not be superimposed. Therefore, the performance of the phased array is limited, which affects the quality of wireless communication.

[0073] To improve the performance of phased arrays, embodiments of this application provide a multi-chip device. This multi-chip device can improve the phased array gain, reduce signal transmission loss, and improve wireless communication quality by synchronizing the local oscillator signals of multiple chips.

[0074] Figure 3A multi-chip device provided in the embodiments of this application, such as Figure 3 As shown, the multi-chip device includes a first chip and a second chip. The first chip includes a first built-in signal generator and a first frequency multiplier coupled to the first built-in signal generator. The second chip includes a second frequency multiplier, which is coupled to the first built-in signal generator via input / output pins between the first and second chips. The first built-in signal generator generates a first local oscillator signal, and the first and second frequency multipliers receive and multiply the first local oscillator signal.

[0075] Optionally, the first chip may further include an output driver coupled to the output of a first built-in signal generator, the output driver being used to amplify the first local oscillator signal. The output driver may also convert the first local oscillator signal from a differential signal to a single-ended signal. For example, as... Figure 3 As shown, the first local oscillator signal generated by the first built-in signal generator is amplified by the output driver and then input to the second frequency multiplier through the output pin of the first chip and the external input port of the second chip. For the second chip, the first local oscillator signal input to the second chip is the external input signal.

[0076] Understandably, the first local oscillator signal generated by the aforementioned first built-in signal generator can be input to the first frequency multiplier, or it can be input to the second frequency multiplier through the input / output pins between the first chip and the second chip. That is, the local oscillator signals of the first chip and the second chip both originate from the first built-in signal generator. Therefore, the signal sources of the local oscillator signals of the first chip and the second chip are the same. When using the first chip and the second chip for phased array splicing, the signals of the first chip and the second chip can be superimposed to improve the phased array gain.

[0077] The aforementioned multi-chip device may include one second chip or multiple second chips; the embodiments of this application are not limited in this respect. Figure 3 The following example illustrates a multi-chip device comprising a single second chip. When the multi-chip device includes multiple second chips, the first local oscillator signal generated by the first built-in signal generator can be input to the second chip through the input / output pins between the first chip and each of the second chips. This ensures that the signal sources of the first chip and the multiple second chips are the same, allowing the signals from the first chip and the multiple second chips to be superimposed.

[0078] Optional, such as Figure 4As shown, the second chip includes a second built-in signal generator coupled to a second frequency multiplier. The second built-in signal generator generates a second local oscillator signal, and the second frequency multiplier receives and multiplies this second local oscillator signal. That is, the second frequency multiplier can receive both the first local oscillator signal generated by the first built-in signal generator and the second local oscillator signal generated by the second built-in signal generator. In other words, the second frequency multiplier supports both built-in signal input and external signal input.

[0079] For example, the aforementioned second frequency multiplier may include a first receiving circuit, a second receiving circuit, and a load circuit. The input terminal of the first receiving circuit is coupled to a first built-in signal generator via the input / output pins of a first chip and a second chip. The input terminal of the second receiving circuit is coupled to a second built-in signal generator. The output terminals of the first and second receiving circuits are coupled to the input terminal of the load circuit. The first receiving circuit receives a first local oscillator signal, and the second receiving circuit receives a second local oscillator signal. That is, the second frequency multiplier can selectively receive the first and second local oscillator signals via the first and second receiving circuits.

[0080] Figure 5A A circuit diagram of a second frequency multiplier provided in an embodiment of this application is shown below. Figure 5A As shown, the input terminal of the first receiving circuit can be coupled to the first built-in signal generator through the output pin of the first chip and the external input terminal of the second chip to receive the first local oscillator signal. The input terminal of the second receiving circuit is coupled to the output terminal of the second built-in signal generator to receive the second local oscillator signal. The output terminals of both the first and second receiving circuits are coupled to the load circuit. Figure 5A As shown, when the local oscillator signal of the second chip is the first local oscillator signal, the first receiving circuit of the second frequency multiplier receives the first local oscillator signal. When the local oscillator signal of the second chip is the second local oscillator signal, the second receiving circuit of the second frequency multiplier receives the second local oscillator signal. That is, the second frequency multiplier can receive both the first local oscillator signal generated by the first built-in signal generator through the first receiving circuit and the second local oscillator signal generated by the second built-in signal generator through the second receiving circuit. In other words, the second frequency multiplier has the ability to selectively receive both the first and second local oscillator signals.

[0081] For example, the signal output from the first receiving circuit can be either a single-ended signal or a differential signal. Similarly, the signal output from the second receiving circuit can also be either a single-ended signal or a differential signal. Whether the signals output from the first and second receiving circuits are single-ended or differential depends on the frequency multiplication principle of the second frequency multiplier and the specific structure of the load circuit. Understandably, when both the first and second receiving circuits output single-ended signals, the load circuit has only one input terminal, and both the output terminals of the first and second receiving circuits are coupled to the input terminal of the load circuit. When both the first and second receiving circuits output differential signals, the load circuit has two input terminals (i.e., a pair of differential input terminals), and the two output terminals of the first receiving circuit are coupled to the two input terminals of the load circuit, and the two output terminals of the second receiving circuit are coupled to the two input terminals of the load circuit, respectively.

[0082] For example, such as Figure 5B As shown, the first receiving circuit includes a conversion circuit and a first differential circuit. The input terminal of the conversion circuit is also the input terminal of the first receiving circuit. The two output terminals of the conversion circuit are respectively coupled to the input terminal of the first differential circuit, and the output terminal of the first differential circuit is the output terminal of the first receiving circuit. The conversion circuit is used to convert the input first local oscillator signal into a differential signal. The differential circuit is used to receive the differential signal and output it to the load circuit.

[0083] Optionally, the first differential circuit includes a first metal-oxide-semiconductor field-effect transistor (MOSFET), referred to as the first MOSFET and the second MOSFET. The first terminal of the first MOSFET and the first terminal of the second MOSFET are the input terminals of the first differential circuit. The first terminal of the first MOSFET and the first terminal of the second MOSFET are respectively coupled to the two output terminals of the conversion circuit. The second terminal of the first MOSFET and the second terminal of the second MOSFET are grounded or connected to a first power supply. The third terminal of the first MOSFET and the third terminal of the second MOSFET are the output terminals of the first receiving circuit.

[0084] Optionally, the first and second MOSFETs can be either N-type or P-type MOSFETs. When the first and second MOSFETs are NMOS transistors, the first terminal of the first MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the first terminal of the second MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the sources of both the first and second MOSFETs are grounded. When the first and second MOSFETs are PMOS transistors, the first terminal of the first MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the first terminal of the second MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the sources of both the first and second MOSFETs are connected to a first power supply. Optionally, the first and second MOSFETs can also be of different types. The following embodiment uses NMOS transistors as an example.

[0085] For example, the above-mentioned conversion circuit may include a first transformer, one end of the primary coil of the first transformer being the input terminal of the first receiving circuit, the second end of the primary coil of the first transformer being grounded, and the two ends of the secondary coil of the first transformer being the two output terminals of the conversion circuit. The first transformer is used to convert the first local oscillator signal received by the first receiving circuit into a differential signal. It should be noted that the embodiments of this application do not limit the specific circuit structure of the conversion circuit; the following embodiments only illustrate the conversion circuit using a transformer as an example.

[0086] For example, Figure 6 This is a circuit structure diagram of a second frequency multiplier provided in an embodiment of this application, combined with... Figure 5B and Figure 6 As shown, the conversion circuit includes a first transformer T1, and the first differential circuit includes a first MOSFET M1 and a second MOSFET M2. One end a of the primary coil of the first transformer T1 is the input terminal of the first receiving circuit, which is used to input the first local oscillator signal. The other end b of the primary coil of the first transformer T1 is grounded. The two ends c and d of the secondary coil of the first transformer T1 are coupled to the gates of the first MOSFET M1 and the second MOSFET M2, respectively. The sources of the first MOSFET M1 and the second MOSFET M2 are grounded, and the drains of the first MOSFET M1 and the second MOSFET M2 are the output terminals of the first receiving circuit. Figure 6 In the first receiving circuit shown, the signal output from the output terminal of the first receiving circuit is a single-ended signal, and the drain of the first MOS transistor M1 is coupled to the drain of the second MOS transistor M2.

[0087] For example, such as Figure 5BAs shown, the second receiving circuit includes a second differential circuit, which is used to receive the second local oscillator signal and output the second local oscillator signal to the load circuit.

[0088] Optionally, the second differential circuit includes a third MOSFET and a fourth MOSFET. The first terminals of the third MOSFET and the fourth MOSFET are the two input terminals of the second receiving circuit. The second terminals of the third MOSFET and the fourth MOSFET are grounded or connected to a second power supply. The third terminals of the third MOSFET and the fourth MOSFET are the output terminals of the second receiving circuit.

[0089] For example, when the third and fourth MOSFETs are N-type MOSFETs, the first terminal of the third MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the first terminal of the fourth MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the sources of both the third and fourth MOSFETs are grounded. When the third and fourth MOSFETs are P-type MOSFETs, the first terminal of the third MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the first terminal of the fourth MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the sources of both the third and fourth MOSFETs are grounded. Optionally, the third and fourth MOSFETs can be of different types. The following embodiments use NMOS transistors as an example.

[0090] For example, such as Figure 6 As shown, the second differential circuit includes a third MOSFET M3 and a fourth MOSFET M4. The gates of the third MOSFET M3 and the fourth MOSFET M4 are the two input terminals of the second receiving circuit, and are used to input the first local oscillator signal. The sources of the third MOSFET M3 and the fourth MOSFET M4 are grounded, and the drains of the third MOSFET M3 and the fourth MOSFET M4 are the output terminals of the second receiving circuit. Figure 6 In the second receiving circuit shown, the output signal of the second receiving circuit is a single-ended signal, and the drain of the third MOS transistor M3 is coupled to the drain of the fourth MOS transistor M4.

[0091] In the first implementation, the load circuit includes a second transformer, one end of the primary coil of the second transformer is connected to a third power source, the other end of the primary coil of the second transformer is the input terminal of the load circuit, and the two ends of the secondary coil of the first transformer are the output terminals of the load circuit.

[0092] For example, such as Figure 6As shown, one end e of the primary coil of the second transformer T2 is connected to the third power supply V3, and the other end f of the primary coil of the second transformer T2 is the input terminal of the load circuit. The two ends g and h of the secondary coil of the first transformer are the two output terminals of the load circuit (that is, the two output terminals of the second frequency multiplier). Figure 6 The input signal of the load circuit shown is a single-ended signal. The input terminal f of the load circuit is coupled to the output terminal of the first receiving circuit (the drain of M1 and M2) and the output terminal of the second receiving circuit (the drain of M3 and M4).

[0093] like Figure 6 As shown, when the local oscillator signal of the second chip is the first local oscillator signal, M3 and M4 in the second receiving circuit are in the off state. The first transformer T1 converts the first local oscillator signal into a differential signal, which is input to the gates of M1 and M2 respectively. Since the gates of M1 and M2 input a pair of differential signals, M2 is off when M1 is on, and M1 is off when M2 is on. That is, M1 and M2 can be turned on alternately, doubling the frequency. Therefore, transformer T2 converts the single-ended signal into a differential signal and outputs a double-frequency signal. Similarly, when the local oscillator signal of the second chip is the second local oscillator signal, M1 and M2 in the first receiving circuit are in the off state, and the second local oscillator signal is input to the gates of M3 and M4. Since the gates of M3 and M4 input a pair of differential signals, M4 is off when M3 is on, and M3 is off when M4 is on. That is, M3 and M4 can be turned on alternately, doubling the frequency. Therefore, transformer T2 converts the single-ended signal into a differential signal and outputs a double-frequency signal.

[0094] In the second implementation, the load circuit includes a third transformer and a fifth MOSFET. One end of the primary coil of the third transformer is coupled to the fourth power supply and the first end of the fifth MOSFET, respectively. The other end of the primary coil of the third transformer is coupled to the third end of the fifth MOSFET. The second end of the fifth MOSFET is the input end of the load circuit, and the two ends of the secondary coil of the third transformer are the output ends of the load circuit.

[0095] Optionally, when the fifth MOSFET is an N-type MOSFET, its first terminal is the gate, its second terminal is the source, its third terminal is the drain, and the source is grounded. When the fifth MOSFET is a P-type MOSFET, its first terminal is the gate, its second terminal is the source, its third terminal is the drain, and the source is connected to a fourth power supply. The following embodiments use an NMOS transistor as an example for illustration.

[0096] For example, Figure 7 A schematic diagram of another circuit structure of a second frequency multiplier provided in an embodiment of this application is shown below. Figure 7 As shown, the structures of the first receiving circuit and the second receiving circuit are similar. Figure 6The first and second receiving circuits in the second frequency multiplier shown have the same structure, so they will not be described again here. Only the structure of the load circuit will be explained.

[0097] like Figure 7 As shown, the load circuit includes a third transformer T3 and a fifth MOSFET M5. One end i of the primary coil of the third transformer T3 is coupled to the fourth power supply V4 and the gate of the fifth MOSFET M5, respectively. The other end j of the primary coil of the third transformer T3 is coupled to the drain of the fifth MOSFET M5. The source of the fifth MOSFET M5 is the input terminal of the load circuit. The two ends k and l of the secondary coil of the third transformer T3 are the output terminals of the load circuit. Figure 7 The input signal of the load circuit shown is a single-ended signal. The input terminal of the load circuit (the source of M5) is coupled to the output terminal of the first receiving circuit (the drain of M1 and M2) and the output terminal of the second receiving circuit (the drain of M3 and M4).

[0098] like Figure 7 As shown, when the local oscillator signal of the second chip is the first local oscillator signal, M3 and M4 in the second receiving circuit are in the off state. The first transformer T1 converts the first local oscillator signal into a differential signal, which is input to the gates of M1 and M2 respectively. Since the gates of M1 and M2 input a pair of differential signals, M2 is off when M1 is on, and M1 is off when M2 is on. That is, M1 and M2 can be turned on alternately, driving the single-ended cascode transistor M5, and after passing through T3, the single-ended signal is converted into a differential signal and output as a frequency-doubled signal. Similarly, when the local oscillator signal of the second chip is the second local oscillator signal, M1 and M2 in the first receiving circuit are in the off state, and the second local oscillator signal is input to the gates of M3 and M4. Since the gate inputs of M3 and M4 are a pair of differential signals, M4 is turned off when M3 is on, and M3 is turned off when M4 is on. That is, M3 and M4 can be turned on alternately to drive the single-ended cascode transistor M5, and after passing through T3, the single-ended signal is converted into a differential signal and output as a double frequency signal.

[0099] It should be noted that the above Figure 6 and Figure 7 The frequency multiplier shown employs a push-push structure. Differential signals are input into differential pair transistors M1, M2 or M3, M4. The single-ended output of the differential pair transistors is sent to a transformer or a single-ended cascode transistor M5. The transformer converts the single-ended signal into a differential signal, generating a second-harmonic signal. This application does not limit the specific circuit structure of the load circuit in the second frequency multiplier when using the push-push second-harmonic principle; only the load circuit is described here. Figure 6 or Figure 7 The circuit structure shown is used as an example for explanation.

[0100] Optionally, the load circuit in the second frequency multiplier can be an oscillation circuit, the resonant frequency of which can be n times the frequency of the first local oscillator signal or the frequency of the second local oscillator signal. This oscillation circuit is used to multiply the frequency of the first local oscillator signal or the frequency of the second local oscillator signal by n times. Optionally, n is an odd number greater than 1. This application does not limit the specific circuit structure of the oscillation circuit; two oscillation circuits are described below as examples.

[0101] In the third implementation, the load circuit includes a sixth MOSFET, a seventh MOSFET, and a first LC circuit. The first terminal of the sixth MOSFET is coupled to the third terminal of the seventh MOSFET. The second terminals of the sixth and seventh MOSFETs are grounded or connected to a fifth power supply. The third terminal of the sixth MOSFET is coupled to the first terminal of the seventh MOSFET. The first terminals of the sixth and seventh MOSFETs are the two input terminals of the load circuit, respectively. The two input terminals of the first LC circuit are coupled to a sixth power supply, and the two output terminals of the first LC circuit are coupled to the third terminals of the sixth and seventh MOSFETs, respectively. The two output terminals of the first LC circuit are the output terminals of the load circuit.

[0102] Optionally, when the sixth and seventh MOSFETs are N-type MOSFETs, the first terminal of the sixth MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the first terminal of the seventh MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the sources of both the sixth and seventh MOSFETs are grounded. When the sixth and seventh MOSFETs are P-type MOSFETs, the first terminal of the sixth MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the first terminal of the seventh MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the sources of both the sixth and seventh MOSFETs are connected to a fifth power supply. Optionally, the sixth and seventh MOSFETs can also be of different types. The following embodiments use NMOS transistors as an example.

[0103] For example, Figure 8 A schematic diagram of another circuit structure of a second frequency multiplier provided in an embodiment of this application is shown below. Figure 8 As shown, the structures of the first receiving circuit and the second receiving circuit are similar. Figure 6 and Figure 7 The difference between the structure of the first receiving circuit and the second receiving circuit in the second frequency multiplier shown is that... Figure 6 and Figure 7 In the second frequency multiplier shown, the output signals of the first and second receiving circuits are single-ended signals, while... Figure 8In the second frequency multiplier shown, the output signals of the first and second receiving circuits are differential signals. For example... Figure 8 The differential signal output by the first receiving circuit is coupled to the gate of M7 and the gate of M6, respectively, and the differential signal output by the second receiving circuit is coupled to the gate of M7 and the gate of M6, respectively.

[0104] like Figure 8 As shown, the load circuit includes a sixth MOSFET M6, a seventh MOSFET M7, and a first LC circuit. The first LC circuit includes inductors L1 and L2, and a variable capacitor C1. The gate of the sixth MOSFET M6 is coupled to the drain of the seventh MOSFET M7. The sources of the sixth MOSFET M6 and the seventh MOSFET M7 are grounded. The drain of the sixth MOSFET M6 is coupled to the gate of the seventh MOSFET M7. The gates of the sixth MOSFET M6 and the seventh MOSFET M7 are the two input terminals of the load circuit. One end m of L1 and one end n of L2 are the input terminals of the first LC circuit. One end m of L1 and one end n of L2 are coupled to the sixth power supply V6. The other end o of L1 and the other end p of L2 are coupled to the drains of the sixth MOSFET M6 and the seventh MOSFET M7, respectively. The other end o of L1 is coupled to the other end p of L2 through the variable capacitor C1. The other ends o of L1 and p of L2 are the two output terminals of the first LC circuit, which are the output terminals of the load circuit.

[0105] like Figure 8 As shown, when the local oscillator signal of the second chip is the first local oscillator signal, M3 and M4 in the second receiving circuit are in the off state. The first transformer T1 converts the first local oscillator signal into a differential signal, which is input to the gates of M1 and M2 respectively. The high-order odd-order differential current signal generated by the nonlinearity of M1 and M2 is injected into the negative resistance resonant cavity composed of M6, M7, L1, L2, and C1. The resonant cavity resonates and amplifies this high-order odd-order signal to achieve frequency multiplication output. For example, if a second frequency multiplier is used to achieve a 3x frequency multiplication output, the nonlinearity of M1 and M2 generates a 3rd harmonic. This 3rd harmonic is injected into the negative resistance resonant cavity composed of M6, M7, L1, L2, and C1. The resonant frequency of this resonant cavity is three times the frequency of the first local oscillator signal. The resonant cavity can resonate and amplify this weaker 3rd harmonic to achieve a 3x frequency multiplication output. Similarly, when the local oscillator signal of the second chip is the second local oscillator signal, M1 and M2 in the first receiving circuit are in the off state, and the second local oscillator signal is input to the gates of M3 and M4. The high-order odd differential current signal generated by the nonlinearity of M3 and M4 is injected into the negative resistance resonant cavity composed of M6, M7, L1, L2 and C1. The resonant cavity resonates and amplifies the high-order odd signal to achieve frequency doubling output.

[0106] Optionally, the first LC circuit described above can be a transformer, or it can consist of only one inductor, or only one inductor and one capacitor. It should be noted that the embodiments of this application do not limit the specific circuit structure of the first LC circuit. Figure 8 The following description uses only the first LC circuit, which includes two inductors L1 and L2, and a variable capacitor C1, as an example.

[0107] In the fourth implementation, the load circuit includes an eighth MOSFET, a ninth MOSFET, and a second LC circuit. The first terminal of the eighth MOSFET is coupled to the third terminal of the ninth MOSFET, and the third terminal of the eighth MOSFET is coupled to the first terminal of the ninth MOSFET. The second terminals of the eighth and ninth MOSFETs are the two input terminals of the load circuit, respectively. The two input terminals of the second LC circuit are coupled to a seventh power supply, and the two output terminals of the second LC circuit are coupled to the third terminals of the eighth and ninth MOSFETs, respectively. The two output terminals of the second LC circuit are the output terminals of the load circuit.

[0108] Optionally, when the eighth and ninth MOSFETs are N-type MOSFETs, the first terminal of the eighth MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the first terminal of the ninth MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the sources of both the eighth and ninth MOSFETs are grounded. When the eighth and ninth MOSFETs are P-type MOSFETs, the first terminal of the eighth MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the first terminal of the ninth MOSFET is the gate, the second terminal is the source, and the third terminal is the drain; the sources of both the eighth and ninth MOSFETs are connected to a seventh power supply. Optionally, the eighth and ninth MOSFETs can also be of different types. The following embodiments use NMOS transistors as an example.

[0109] For example, Figure 9 A schematic diagram of another circuit structure of a second frequency multiplier provided in an embodiment of this application is shown below. Figure 9 As shown, the structures of the first receiving circuit and the second receiving circuit are similar. Figure 6 and Figure 7 The difference between the first and second receiving circuits in the second frequency multiplier shown is that... Figure 6 and Figure 7 In the second frequency multiplier shown, the output signals of the first and second receiving circuits are single-ended signals, while... Figure 9 In the second frequency multiplier shown, the output signals of the first and second receiving circuits are differential signals. For example... Figure 9The differential signals output by the first receiving circuit are coupled to the sources of M8 and M9, respectively, and the differential signals output by the second receiving circuit are coupled to the sources of M8 and M9, respectively.

[0110] like Figure 9 As shown, the load circuit includes an eighth MOSFET M8, a ninth MOSFET M9, and a second LC circuit. The second LC circuit includes a variable capacitor C2 and a pair of differential inductors composed of inductors L3 and L4. The gate of the eighth MOSFET M8 is coupled to the drain of the ninth MOSFET M9, and the drain of the eighth MOSFET M8 is coupled to the gate of the ninth MOSFET M9. The sources of the eighth MOSFET M8 and the ninth MOSFET M9 are the two input terminals of the load circuit. One end q of L3 and one end r of L4 are the input terminals of the second LC circuit. One end q of L3 and one end r of L4 are coupled to the seventh power supply V7. The other end s of L3 and the other end t of L4 are coupled to the drains of the eighth MOSFET M8 and the ninth MOSFET M9, respectively. The other end s of L3 is coupled to the other end t of L4 through the variable capacitor C2. The other end s of L3 and the other end t of L4 are the two output terminals of the second LC circuit, which are the output terminals of the load circuit.

[0111] like Figure 9 As shown, when the local oscillator signal of the second chip is the first local oscillator signal, M3 and M4 in the second receiving circuit are in the off state. The first transformer T1 converts the first local oscillator signal into a differential signal, which is input to the gates of M1 and M2 respectively. The high-order odd-order differential current signal generated by the nonlinearity of M1 and M2 is injected into the negative resistance resonant cavity composed of M8, M9, L3, L4, and C2. The resonant cavity resonates and amplifies this high-order odd-order signal to achieve frequency multiplication output. For example, if a second frequency multiplier is used to achieve a 3x frequency multiplication output, the nonlinearity of M1 and M2 generates a 3rd harmonic. This 3rd harmonic is injected into the negative resistance resonant cavity composed of M8, M9, L3, L4, and C2. The resonant frequency of this resonant cavity is three times the frequency of the first local oscillator signal. The resonant cavity can resonate and amplify this weaker 3rd harmonic to achieve a 3x frequency multiplication output. Similarly, when the local oscillator signal of the second chip is the second local oscillator signal, M1 and M2 in the first receiving circuit are in the off state, and the second local oscillator signal is input to the gates of M3 and M4. The high-order odd-order differential current signal generated by the nonlinearity of M3 and M4 is injected into the negative-resistance resonant cavity composed of M8, M9, L3, L4, and C2. The resonant cavity resonates and amplifies this high-order odd-order signal, achieving frequency doubling output. It should be noted that... Figure 9 The second frequency multiplier shown is Figure 8 The difference in the second frequency multiplier shown is that the injection point of the differential current is different. Figure 8 The injection points for the differential current of the second frequency multiplier shown are the gates of M6 and M7, while Figure 9The injection points of the differential current of the second frequency multiplier shown are the sources of M8 and M9.

[0112] Optionally, the second LC circuit described above can be a transformer. The second LC circuit may also include only one inductor, or only one inductor and one capacitor, or it may include multiple inductors or capacitors. It should be noted that the embodiments of this application do not limit the specific circuit structure of the second LC circuit. Figure 9 The following explanation uses the second LC circuit, which includes two inductors L3 and L4 and a variable capacitor C2, as an example.

[0113] It should be noted that the above Figure 8 and Figure 9 The frequency multiplication structure of the second frequency multiplier shown employs an injection locking structure. A high-order odd-order differential current signal generated by the nonlinearity of the differential pair transistors is injected into the negative resistance resonant cavity. The resonant cavity resonates and amplifies this high-order odd-order signal to achieve frequency multiplication output. This application does not limit the specific circuit structure of the load circuit in the second frequency multiplier when using an injection locking structure for frequency multiplication; only the load circuit is described here. Figure 8 or Figure 9 The following explanation uses the oscillating circuit as an example.

[0114] The above Figures 6 to 9 The second frequency multiplier shown has both the function of selecting built-in signal input or external signal input and the function of frequency multiplication. Therefore, when using this frequency multiplier, the chip area can be reduced and the power consumption can be reduced.

[0115] Optionally, when the second frequency multiplier only has a frequency multiplication function and no selection function, the second chip may also include a selector. The second built-in signal generator is coupled to the second frequency multiplier through the selector, and the second frequency multiplier selects to receive the first local oscillator signal and the second local oscillator signal through the selector.

[0116] For example, such as Figure 10 As shown, the input of the selector is coupled to the first built-in signal generator and the second built-in signal generator, and the second frequency multiplier selects to receive the first local oscillator signal and the second local oscillator signal through the selector.

[0117] For example, Figure 11 This is a schematic diagram of the circuit structure of a multiplexer (MUX), as shown below. Figure 11As shown, one input port of the selector is a built-in signal input port used to receive the first local oscillator signal. The other input port of the selector is an external signal input port used to receive the second local oscillator signal. The first local oscillator signal is converted into a differential signal by a transformer, driving a set of differential common-source transistors M10 / M11. The second local oscillator signal can drive another set of differential common-source transistors M12 / M13. The two sets of common-source amplifier transistors are connected to differential common-source cascode amplifier transistors M14 / M15, and the output is driven to the subsequent frequency multiplier circuit through a transformer.

[0118] like Figure 11 As shown, this selector supports two operating modes: built-in signal input and external signal input. In the first operating mode, the input is the first local oscillator signal (external signal input). M12 and M13 are off, and M10 / M11 are on. The first local oscillator signal acts as the signal source to drive the differential common-source transistors M10 / M11, and the output is sent to the next stage frequency multiplier. In the second operating mode, the input is the second local oscillator signal (built-in signal input). M10 and M11 are off, and M12 / M13 are on. The second local oscillator signal acts as the signal source to drive the differential common-source transistors M12 / M13, and the output is sent to the next stage frequency multiplier.

[0119] For example, Figure 12 This is a schematic diagram of the circuit structure of a frequency multiplier, such as... Figure 12 As shown, the two output terminals of the selector are coupled to the two input terminals P and N of the frequency multiplier, respectively. The differential signal is input to the gates of M14 and M15, and the drains of M14 and M15 are output to the single-ended cascode transistor M16. The transformer converts the single-ended signal into a differential output, generating a double frequency signal.

[0120] For example, Figure 13 Here is a schematic diagram of the circuit structure of another frequency multiplier, such as... Figure 13 As shown, the two output terminals of the selector are coupled to the two input terminals P and N of the frequency multiplier, respectively. The input signal is input to the gates of M17 and M18. Due to the nonlinearity of M17 and M18, the high-order odd differential current signal is injected into the negative resistance resonant cavity composed of M19 and M20, i.e., the LC circuit. The resonant cavity resonates and amplifies the high-order odd signal to achieve frequency multiplication output.

[0121] This application does not limit the specific circuit structure of the selector and frequency multiplier; here, only the selector is used as an example. Figure 11 The circuit structure shown has a frequency multiplier. Figure 12 or Figure 13 The circuit structure shown is illustrated as an example.

[0122] It should be noted that, Figure 5A or Figure 5B The second chip structure shown is similar to Figure 10 The difference in the second chip structure shown is that, Figure 5A or Figure 5B The second frequency multiplier shown includes a first receiving circuit and a second receiving circuit. Through these first and second receiving circuits, the second frequency multiplier can selectively receive a first local oscillator signal (externally injected signal) and a second local oscillator signal (internal signal). Therefore, Figure 5A or Figure 5B The second frequency multiplier shown has both selection and multiplication functions, therefore no additional selector is needed. Figure 10 The second frequency multiplier shown does not have a selection function, so a selector needs to be set up. The second frequency multiplier selects the input built-in signal or the external signal through the selector.

[0123] For example, the above Figures 6 to 9 The second frequency multiplier shown includes a first receiving circuit and a second receiving circuit. These two receiving circuits allow the second frequency multiplier to selectively receive the first local oscillator signal and the second local oscillator signal. Figures 12 to 13 The second frequency multiplier shown does not have a selection function and needs to be selected via... Figure 11 The selector shown selects to receive the first local oscillator signal and the second local oscillator signal. It is understandable that this is achieved using... Figures 12 to 13 The second frequency multiplier shown includes both a second frequency multiplier and a selector in the second chip. This means the second chip requires two stages of circuitry to support both external and internal signal input operating modes and achieve frequency multiplication. This implementation results in a larger chip area and higher power consumption. However, using... Figures 6 to 9 The second frequency multiplier shown only requires one stage of circuitry to support both operating modes and achieve frequency multiplication, thus reducing chip area and power consumption. Furthermore, compared to... Figure 11 The selector shown and Figure 12 or Figure 13 The second frequency multiplier shown, Figures 6 to 9 The second frequency multiplier shown in either case, by combining the selection function and the frequency multiplication function, no longer requires an additional transformer, saving the coil area of ​​the first-stage transformer.

[0124] Optionally, the circuit structure of the first frequency multiplier described above can refer to the circuit structure of the second frequency multiplier described above, and will not be repeated here. When the circuit structure of the first frequency multiplier is... Figures 6 to 9 In any of the circuit structures shown, the first chip has a smaller area and lower power consumption.

[0125] Optionally, the multi-chip device may further include a power divider, which includes a first output terminal and a second output terminal. The input terminal of the power divider is coupled to the output terminal of a first built-in signal generator, and the first and second output terminals of the power divider are respectively coupled to a first frequency multiplier and a second frequency multiplier. The first built-in signal generator can output a first local oscillator signal to the first chip and the second chip respectively through the power divider.

[0126] For example, such as Figure 14 As shown, taking an N-way power divider as an example, a multi-chip device includes an N-way power divider, a first chip, and N-1 second chips. The N-way power divider has N output terminals. One output terminal of the N-way power divider is coupled to the external input port of the first chip. The other N-1 output terminals of the N-way power divider are coupled to the second frequency multiplier 1 to the second frequency multiplier N-1 through the external input ports of the N-1 second chips, respectively.

[0127] Understandable, because Figures 3 to 5A In the multi-chip device shown, the signal paths of the first local oscillator signal input to the first frequency multiplier and the first local oscillator signal input to the second frequency multiplier are different. For example, the first local oscillator signal input to the second chip is generated by the first built-in signal generator, driven by the output of the first chip, and then input to the second frequency multiplier through the external input port of the second chip. However, the first local oscillator signal input to the first frequency multiplier is directly input to the first frequency multiplier after being generated by the first built-in signal generator. Therefore, this may result in the first local oscillator signal input to the first frequency multiplier not being completely phased with the second local oscillator signal input to the second frequency multiplier. Additional circuitry is needed to correct the phase of the local oscillator signals to align the phases of the local oscillator signals of the first chip and the second chip. Figure 14 In the multi-chip device shown, by setting a power divider, the first local oscillator signal generated by the first built-in signal generator is output to the external input terminals of the first chip and the second chip through the power divider. This makes the signal paths of the local oscillator signal input by the first frequency multiplier and the local oscillator signal input by the second frequency multiplier completely identical. Therefore, the phase, amplitude and frequency of the local oscillator signal of the first chip and the local oscillator signal of the second chip are the same. No additional correction circuit is required to ensure the phase alignment of the first chip and the second chip.

[0128] Optionally, the above Figures 3 to 5A ,as well as Figure 14 In the multi-chip device shown, the circuit structures of the first chip and the second chip can be identical. For example, the second chip can also output the second frequency-multiplied signal generated by its second built-in signal generator to other chips via an output driver.

[0129] In the multi-chip device provided in this application embodiment, since the local oscillator signal of the first chip and the local oscillator signal of the second chip both come from the first built-in signal generator, the local oscillator signals of the first chip and the second chip are synchronized. Therefore, when the first chip and the second chip are used to perform phased array splicing, the signals of the first chip and the second chip can be superimposed to improve the phased array gain and reduce the signal transmission loss.

[0130] Optionally, the first chip may further include multiple first phased array channels and a first mixer, wherein the multiple first phased array channels are coupled to the first frequency multiplier through the first mixer. The second chip may further include multiple second phased array channels and a second mixer, wherein the multiple second phased array channels are coupled to the second frequency multiplier through the second mixer.

[0131] This application also provides a frequency multiplier, which includes a first receiving circuit, a second receiving circuit, and a load circuit. The input terminal of the first receiving circuit is used to receive a first local oscillator signal, and the input terminal of the second receiving circuit is used to receive a second local oscillator signal. The output terminals of the first and second receiving circuits are coupled to the input terminal of the load circuit. The specific circuit structures of the first receiving circuit, the second receiving circuit, and the load circuit can be referred to the above embodiments, and will not be repeated here. Since the frequency multiplier provided in this application can receive the first local oscillator signal and the second local oscillator signal through the first receiving circuit and the second receiving circuit respectively, a separate selector is not required to achieve selection and frequency multiplication functions, thereby reducing the chip area and power consumption.

[0132] This application also provides a communication device, which includes a first chip in any of the above embodiments, a second chip in any of the above embodiments, a plurality of first antenna units, and a plurality of second antenna units. The plurality of first antenna units are coupled to the plurality of first phased array channels one by one, and the plurality of second antenna units are coupled to the plurality of second phased array channels one by one.

[0133] This application also provides an electronic device, which includes a baseband chip and a multi-chip device. The structure of the multi-chip device can be referred to the above embodiments, and will not be repeated here.

[0134] The steps of the methods or algorithms described in this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Alternatively, the ASIC can reside in a core network interface device. Of course, the processor and storage medium can also exist as discrete components in the core network interface device.

[0135] Those skilled in the art will recognize that, in one or more of the examples above, the functions described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0136] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-chip device, comprising: The multi-chip device includes a first chip and a second chip. The first chip includes a first built-in signal generator and a first frequency multiplier coupled to the first built-in signal generator. The second chip includes a second built-in signal generator and a second frequency multiplier coupled to the second built-in signal generator. The second frequency multiplier includes a first receiving circuit, a second receiving circuit, and a load circuit. The input terminal of the first receiving circuit is coupled to the output terminal of the first built-in signal generator through input / output pins between the first chip and the second chip. The input terminal of the second receiving circuit is coupled to the output terminal of the second built-in signal generator. The output terminals of the first and second receiving circuits are coupled to the input terminal of the load circuit. The first built-in signal generator is used to generate the first local oscillator signal; The first frequency multiplier is used to receive the first local oscillator signal and to multiply the frequency of the first local oscillator signal; The second built-in signal generator is used to generate the second local oscillator signal; The second frequency multiplier is used to selectively receive the first local oscillator signal through the first receiving circuit and the second local oscillator signal through the second receiving circuit; The second frequency multiplier is also used to multiply the received first local oscillator signal or the second local oscillator signal. The first receiving circuit includes a conversion circuit and a first differential circuit. The input terminal of the conversion circuit is the input terminal of the first receiving circuit, and the two output terminals of the conversion circuit are respectively coupled to the input terminal of the first differential circuit. The output terminal of the first differential circuit is the output terminal of the first receiving circuit. The conversion circuit is used to convert the input first local oscillator signal into a differential signal; The differential circuit is used to receive the differential signal and output the differential signal to the load circuit.

2. The multi-chip device of claim 1, wherein, The multi-chip device further includes a power divider, which has a first output terminal and a second output terminal. The input terminal of the power divider is coupled to the output terminal of the first built-in signal generator, and the first output terminal and the second output terminal of the power divider are respectively coupled to the first frequency multiplier and the second frequency multiplier.

3. The multi-chip device according to claim 1 or 2, characterized in that, The first chip also includes an output driver, which is coupled to the output of the first built-in signal generator and is used to amplify the first local oscillator signal.

4. The multi-chip device according to claim 1 or 2, characterized in that, The first differential circuit includes a first metal-oxide-semiconductor MOSFET and a second MOSFET. The first terminal of the first MOSFET and the first terminal of the second MOSFET are the input terminals of the first differential circuit. The second terminals of the first MOSFET and the second terminals of the second MOSFET are grounded or powered by a first power supply. The third terminals of the first MOSFET and the third terminals of the second MOSFET are the output terminals of the first receiving circuit.

5. The multi-chip device according to claim 4, characterized in that, The first MOSFET and the second MOSFET are N-type MOSFETs. The first terminal of the first MOSFET is the gate, the second terminal of the first MOSFET is the source, and the third terminal of the first MOSFET is the drain. The first terminal of the second MOSFET is the gate, the second terminal of the second MOSFET is the source, and the third terminal of the second MOSFET is the drain. The sources of the first MOSFET and the second MOSFET are grounded.

6. The multi-chip device according to claim 1 or 2, characterized in that, The conversion circuit includes a first transformer, one end of the primary coil of the first transformer is the input terminal of the first receiving circuit, the second end of the primary coil of the first transformer is grounded, and the two ends of the secondary coil of the first transformer are the two output terminals of the conversion circuit.

7. The multi-chip device according to claim 1 or 2, characterized in that, The second receiving circuit includes a second differential circuit, which is used to receive the second local oscillator signal and output the second local oscillator signal to the load circuit.

8. The multi-chip device according to claim 7, characterized in that, The second differential circuit includes a third MOSFET and a fourth MOSFET. The first terminals of the third MOSFET and the fourth MOSFET are the two input terminals of the second receiving circuit. The second terminals of the third MOSFET and the fourth MOSFET are grounded or connected to a second power supply. The third terminals of the third MOSFET and the fourth MOSFET are the output terminals of the second receiving circuit.

9. The multi-chip device according to claim 8, characterized in that, The third and fourth MOS transistors are N-type MOS transistors. The first terminal of the third MOS transistor is the gate, the second terminal is the source, and the third terminal is the drain. The first terminal of the fourth MOS transistor is the gate, the second terminal is the source, and the third terminal is the drain. The sources of the third and fourth MOS transistors are grounded.

10. The multi-chip device according to claim 1 or 2, characterized in that, The load circuit includes a second transformer, one end of the primary coil of the second transformer is connected to a third power source, the other end of the primary coil of the second transformer is the input terminal of the load circuit, and the two ends of the secondary coil of the second transformer are the output terminals of the load circuit.

11. The multi-chip device according to claim 1 or 2, characterized in that, The load circuit includes a third transformer and a fifth MOSFET. One end of the primary coil of the third transformer is coupled to a fourth power supply and the first end of the fifth MOSFET, respectively. The other end of the primary coil of the third transformer is coupled to the third end of the fifth MOSFET. The second end of the fifth MOSFET is the input terminal of the load circuit, and the two ends of the secondary coil of the third transformer are the output terminals of the load circuit.

12. The multi-chip device according to claim 11, characterized in that, The fifth MOS transistor is an N-type MOS transistor. The first terminal of the fifth MOS transistor is the gate, the second terminal is the source, the third terminal is the drain, and the source is grounded.

13. The multi-chip device according to claim 1 or 2, characterized in that, The load circuit includes a sixth MOSFET, a seventh MOSFET, and a first LC circuit. The first terminal of the sixth MOSFET is coupled to the third terminal of the seventh MOSFET. The second terminal of the sixth MOSFET is grounded or connected to a fifth power supply. The third terminal of the sixth MOSFET is coupled to the first terminal of the seventh MOSFET. The first terminals of the sixth and seventh MOSFETs are the two input terminals of the load circuit, respectively. The two input terminals of the first LC circuit are coupled to a sixth power supply. The two output terminals of the first LC circuit are coupled to the third terminals of the sixth and seventh MOSFETs, respectively. The two output terminals of the first LC circuit are the output terminals of the load circuit.

14. The multi-chip device according to claim 13, characterized in that, The sixth and seventh MOS transistors are N-type MOS transistors. The first terminal of the sixth MOS transistor is the gate, the second terminal is the source, and the third terminal is the drain. The first terminal of the seventh MOS transistor is the gate, the second terminal is the source, and the third terminal is the drain. The sources of the sixth and seventh MOS transistors are grounded.

15. The multi-chip device according to claim 1 or 2, characterized in that, The load circuit includes an eighth MOSFET, a ninth MOSFET, and a second LC circuit. The first terminal of the eighth MOSFET is coupled to the third terminal of the ninth MOSFET, and the third terminal of the eighth MOSFET is coupled to the first terminal of the ninth MOSFET. The second terminals of the eighth MOSFET and the ninth MOSFET are respectively the two input terminals of the load circuit. The two input terminals of the second LC circuit are coupled to a seventh power supply, and the two output terminals of the second LC circuit are respectively coupled to the third terminals of the eighth MOSFET and the ninth MOSFET. The two output terminals of the second LC circuit are the output terminals of the load circuit.

16. The multi-chip device according to claim 15, characterized in that, The eighth and ninth MOS transistors are N-type MOS transistors. The first terminal of the eighth MOS transistor is the gate, the second terminal is the source, and the third terminal is the drain. The first terminal of the ninth MOS transistor is the gate, the second terminal is the source, and the third terminal is the drain. The sources of the eighth and ninth MOS transistors are grounded.

17. The multi-chip device according to claim 1 or 2, characterized in that, The first chip further includes multiple first phased array channels and a first mixer, wherein the multiple first phased array channels are coupled to the first frequency multiplier through the first mixer; the second chip further includes multiple second phased array channels and a second mixer, wherein the multiple second phased array channels are coupled to the second frequency multiplier through the second mixer.

18. A communication device, characterized in that, The communication device includes a multi-chip device as described in any one of claims 1-17; Multiple first antenna elements and multiple second antenna elements; the multiple first antenna elements are coupled one-to-one with multiple first phased array channels of the multi-chip device, and the multiple second antenna elements are coupled one-to-one with multiple second phased array channels of the multi-chip device.

19. An electronic device, characterized in that, The electronic device includes a baseband chip and a multi-chip device as claimed in any one of claims 1-17.

Images