Voltage-controlled oscillator and electronic device

Abstract

The application discloses a voltage-controlled oscillator and electronic equipment, comprising bias circuit, core circuit and buffer stage circuit connected in sequence, wherein the core circuit comprises PMOS cross-coupled pair, NMOS cross-coupled pair and LC resonant loop connected in parallel. Compared with the prior voltage-controlled oscillator, the core circuit of the voltage-controlled oscillator utilizes PMOS cross-coupled pair and NMOS cross-coupled pair to provide negative resistance, reduces the number and stack number of active devices in the core circuit, and is beneficial to optimization of noise performance of the voltage-controlled oscillator and low-voltage implementation. Meanwhile, the voltage-controlled oscillator adjusts the substrate voltage of the PMOS cross-coupled pair and the NMOS cross-coupled pair in the core circuit through the bias circuit, so that the voltage-controlled oscillator can work at low voltage and low power consumption, the current of the core circuit and the amplitude of the MOS tube transconductance changing with environmental factors such as temperature can be reduced, and the circuit robustness is improved.

Description

Technical Field

[0001] This application relates to the field of radio frequency integrated circuit technology, and in particular to a voltage-controlled oscillator and electronic device. Background Technology

[0002] In recent years, with the rapid development of wireless communication technology, the demands for information data transmission and processing from all walks of life have increased. Fourth-generation (4G) wireless communication technology is gradually failing to meet these demands, and there is an urgent need for higher data transmission rates and larger data volumes. Therefore, fifth-generation (5G) wireless communication systems have emerged. However, with the gradual application and popularization of 5G wireless communication systems, frequency resources have become extremely valuable. Currently, the spectrum below 6GHz is already very congested and heavily occupied. To obtain higher frequencies and wider bandwidths, millimeter-wave bands are playing an increasingly important role in radio frequency (RF) communication systems.

[0003] Transceiver circuits are indispensable for transmitting and receiving information in the millimeter-wave band. Phase-locked loop (PLL) circuits, capable of generating highly accurate clock signals in both frequency and phase, are a crucial module within these transceiver circuits. Voltage-controlled oscillators (VCOs) are one of the core modules of PLL circuits, and their performance directly determines the overall loop performance. Therefore, designing VCOs with superior noise performance and wider applicability has always been a challenge for RF designers. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a voltage-controlled oscillator and electronic device to optimize the noise performance of the voltage-controlled oscillator, enabling it to operate in low-noise, low-voltage scenarios.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0006] A voltage-controlled oscillator includes: a bias circuit, a core circuit, and a buffer stage circuit connected in sequence, wherein the core circuit includes a PMOS cross-coupled pair, an NMOS cross-coupled pair, and an LC resonant circuit connected in parallel;

[0007] The bias circuit provides a first substrate voltage to the substrate terminals of the two PMOS transistors in the PMOS cross-coupled pair and a second substrate voltage to the substrate terminals of the two NMOS transistors in the NMOS cross-coupled pair.

[0008] In the core circuit, the PMOS cross-coupled pair and the NMOS cross-coupled pair are used to provide negative resistance to compensate for the power loss of the LC resonant circuit. The LC resonant circuit is used to generate a first resonant signal and a second resonant signal with the same amplitude but opposite phase, which are output to the buffer stage circuit.

[0009] The buffer stage circuit converts the first resonant signal and the second resonant signal into single-ended signals and then outputs them.

[0010] Optionally, the PMOS cross-coupled pair includes a first PMOS transistor and a second PMOS transistor, and the NMOS cross-coupled pair includes a first NMOS transistor and a second NMOS transistor;

[0011] In the core circuit, the source terminals of the first PMOS transistor and the second PMOS transistor are both connected to the power supply voltage input terminal. The power supply voltage is input, the gate terminal of the first PMOS transistor is connected to the drain terminal of the second PMOS transistor, and the gate terminal of the second PMOS transistor is connected to the drain terminal of the first PMOS transistor.

[0012] The source terminals of the first NMOS transistor and the second NMOS transistor are both grounded. The gate terminal of the first NMOS transistor is connected to the drain terminal of the second NMOS transistor, and the gate terminal of the second NMOS transistor is connected to the drain terminal of the first NMOS transistor.

[0013] The drain terminals of the first PMOS transistor, the first NMOS transistor, and the first output terminal of the LC resonant circuit are all connected to the first node, and the drain terminals of the second PMOS transistor, the second NMOS transistor, and the second output terminal of the LC resonant circuit are all connected to the second node.

[0014] The first node and the second node serve as two output terminals of the core circuit, respectively outputting the first resonant signal and the second resonant signal generated by the LC resonant circuit.

[0015] Optionally, the bias circuit includes:

[0016] A first current mirror structure is composed of a third PMOS transistor and a fourth PMOS transistor, wherein the source terminals of the third PMOS transistor and the fourth PMOS transistor are both connected to the power supply voltage input terminal, the power supply voltage is input, the gate terminal of the third PMOS transistor is connected to its drain terminal, and the gate terminal of the fourth PMOS transistor is connected to the gate terminal of the third PMOS transistor.

[0017] A first feedback loop is formed by a fifth PMOS transistor and a first operational amplifier, wherein the source terminal of the fifth PMOS transistor is connected to the power supply voltage input terminal to receive the power supply voltage, the drain terminal of the fifth PMOS transistor is connected to the positive input terminal of the first operational amplifier, the gate terminal of the fifth PMOS transistor is connected to the reference voltage input terminal to receive the reference voltage, and the gate terminal of the fifth PMOS transistor is also connected to the negative input terminal of the first operational amplifier, and the substrate terminal of the fifth PMOS transistor is connected to the output terminal of the first operational amplifier.

[0018] A second feedback loop is formed by a third NMOS transistor and a second operational amplifier. The source terminal of the third NMOS transistor is grounded, the drain terminal of the third NMOS transistor is connected to the drain terminal of the fourth PMOS transistor, and the drain terminal of the third NMOS transistor is also connected to the positive input terminal of the second operational amplifier. The gate terminal of the third NMOS transistor is connected to the reference voltage input terminal to input the reference voltage, and the gate terminal of the third NMOS transistor is also connected to the negative input terminal of the second operational amplifier. The substrate terminal of the third NMOS transistor is connected to the output terminal of the second operational amplifier.

[0019] A second current mirror structure is composed of a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The drain of the fourth NMOS transistor is connected to the bias current input terminal, and a bias current is input. The gates of the fourth, fifth, and sixth NMOS transistors are all connected to the drain of the fourth NMOS transistor. The sources of the fourth, fifth, and sixth NMOS transistors are all grounded. The drain of the fifth NMOS transistor is connected to the drain of the third PMOS transistor, and the drain of the sixth NMOS transistor is connected to the drain of the fifth PMOS transistor.

[0020] The substrate of the fifth PMOS transistor is connected to the first output terminal of the bias circuit to output the first substrate voltage, and the substrate of the third NMOS transistor is connected to the second output terminal of the bias circuit to output the second substrate voltage.

[0021] Optionally, the bias circuit further includes:

[0022] A first low-pass filter consisting of a first resistor and a first capacitor, wherein the first end of the first resistor is connected to the substrate of the fifth PMOS transistor, and the second end is grounded through the first capacitor;

[0023] A second low-pass filter is composed of a second resistor and a second capacitor, wherein the first end of the second resistor is connected to the substrate end of the third NMOS transistor, and the second end is grounded through the second capacitor;

[0024] Wherein, the second end of the first resistor is the first output terminal of the bias circuit, and the second end of the second resistor is the second output terminal of the bias circuit.

[0025] Optionally, the first operational amplifier and the second operational amplifier are the same operational amplifier, the operational amplifier comprising:

[0026] A third current mirror structure is composed of a sixth PMOS transistor and a seventh PMOS transistor. The source terminals of both the sixth and seventh PMOS transistors are connected to the power supply voltage input terminal. The drain terminal of the sixth PMOS transistor is grounded through a seventh NMOS transistor, and the gate terminal of the sixth PMOS transistor is connected to the gate terminal of the seventh PMOS transistor. The gate terminal of the seventh PMOS transistor is connected to its drain terminal, and the drain terminal of the seventh PMOS transistor is connected to a third node. The gate terminal of the seventh NMOS transistor (N7) is connected to its drain terminal.

[0027] A fourth current mirror structure is composed of an eighth PMOS transistor and a ninth PMOS transistor. The source terminals of both the eighth and ninth PMOS transistors are connected to the power supply voltage input terminal. The drain terminal of the ninth PMOS transistor is grounded through an eighth NMOS transistor, and its gate terminal is connected to the gate terminal of the eighth PMOS transistor. The gate terminal of the eighth PMOS transistor is connected to its drain terminal, and its drain terminal is connected to a fourth node. The gate terminal of the eighth NMOS transistor is connected to the gate terminal of the seventh NMOS transistor.

[0028] A cross-coupled tenth PMOS transistor and an eleventh PMOS transistor, the source terminals of the tenth PMOS transistor and the eleventh PMOS transistor are both connected to the power supply voltage input terminal, the gate terminal of the tenth PMOS transistor is connected to the drain terminal of the eleventh PMOS transistor, and the drain terminal of the tenth PMOS transistor is connected to the third node; the gate terminal of the eleventh PMOS transistor is connected to the drain terminal of the tenth PMOS transistor, and the drain terminal of the eleventh PMOS transistor is connected to the fourth node.

[0029] The ninth NMOS transistor has its drain connected to the third node, its gate connected to the positive input terminal of the operational amplifier, and its source connected to the fifth node.

[0030] The tenth NMOS transistor has its drain connected to the fourth node, its gate connected to the negative input of the operational amplifier, and its source connected to the fifth node.

[0031] A fifth current mirror structure is composed of an eleventh NMOS transistor and a twelfth NMOS transistor. The source terminals of the eleventh and twelfth NMOS transistors are both grounded. The drain terminal of the eleventh NMOS transistor is connected to the bias current input terminal to receive the bias current. The gate terminal of the eleventh NMOS transistor is connected to its drain terminal. The gate terminal of the twelfth NMOS transistor is connected to the gate terminal of the eleventh NMOS transistor, and the drain terminal of the twelfth NMOS transistor is connected to the fifth node.

[0032] The drain terminal of the ninth PMOS transistor is the output terminal of the operational amplifier.

[0033] Optionally, the core circuit further includes a second harmonic cancellation circuit, which includes:

[0034] A first inductor and a third capacitor are connected in series, with the first end of the first inductor connected to the first node and the second end of the first inductor grounded through the third capacitor.

[0035] A second inductor and a fourth capacitor are connected in series, with the first end of the second inductor connected to the second node and the second end of the second inductor grounded through the fourth capacitor.

[0036] The resonant frequency of the first inductor and the third capacitor connected in series is the second harmonic frequency of the first resonant signal, and the resonant frequency of the second inductor and the fourth capacitor connected in series is the second harmonic frequency of the second resonant signal.

[0037] Optionally, the LC resonant circuit includes a third inductor, a switched capacitor array, and a variable capacitor branch connected in parallel; wherein,

[0038] The first end of the third inductor is connected to the first node, and the second end is connected to the second node;

[0039] The first end of the switched capacitor array is connected to the first node, the second end is connected to the second node, and the control terminal inputs a frequency band control word. The switched capacitor array provides capacitors of different sizes based on the frequency band control word.

[0040] The first end of the variable capacitor branch is connected to the first node, the second end is connected to the second node, and the control terminal is input with a tuning voltage. The variable capacitor branch provides capacitors of different sizes based on the tuning voltage.

[0041] Optionally, the variable capacitor branch includes: a fifth capacitor, a first varactor, a second varactor, and a sixth capacitor connected in series.

[0042] Wherein, the end of the fifth capacitor that is away from the first varactor tube is the first end of the variable capacitor branch and is connected to the first node;

[0043] The end of the sixth capacitor that is away from the second varactor tube is the second end of the variable capacitor branch and is connected to the second node;

[0044] The common terminal of the fifth capacitor and the first varactor is the sixth node. The sixth node is connected to the power supply voltage input terminal through the third resistor, and the sixth node is also grounded through the fourth resistor.

[0045] The common terminal of the sixth capacitor and the second varactor is the seventh node. The seventh node is connected to the power supply voltage input terminal through the fifth resistor, and the seventh node is also grounded through the sixth resistor.

[0046] The common terminal of the first varactor and the second varactor is the control terminal of the variable capacitor branch, and the tuning voltage is input therein.

[0047] Optionally, the switched capacitor array includes N switched capacitor branches connected in parallel, where N is a positive integer greater than 1, and each switched capacitor branch includes a control switching circuit and a weighting capacitor.

[0048] The frequency band control word input to the control terminal of the switched capacitor array is N bits, and each frequency band control word controls the closing and closing of the control switch circuit in one of the switched capacitor branches;

[0049] As the number of bits in the frequency band control word increases, the capacitance value of the weight capacitor in the switched capacitor branch controlled by the frequency band control word becomes larger.

[0050] Optionally, the control switch circuit includes: a thirteenth NMOS transistor, a fourteenth NMOS transistor, and a fifteenth NMOS transistor;

[0051] The gate terminal of the thirteenth NMOS transistor is input with a one-bit frequency band control word, the first terminal is grounded through the fourteenth NMOS transistor, and the second terminal is grounded through the fifteenth NMOS transistor.

[0052] The gate terminal of the fourteenth NMOS transistor is connected to the gate terminal of the fifteenth NMOS transistor. The common terminal of the gate terminals of the fourteenth NMOS transistor and the fifteenth NMOS transistor is also input with a one-bit frequency band control word. The frequency band control word input to the common terminal of the gate terminals of the fourteenth NMOS transistor and the fifteenth NMOS transistor is the same one-bit frequency band control word as the frequency band control word input to the gate terminal of the thirteenth NMOS transistor.

[0053] The source and drain terminals of the thirteenth NMOS transistor are the two ends of the control switch circuit, respectively.

[0054] Optionally, the buffer stage circuit includes:

[0055] A sixth current mirror structure is composed of a twelfth PMOS transistor and a thirteenth PMOS transistor, wherein the source terminals of the twelfth PMOS transistor and the thirteenth PMOS transistor are both connected to the power supply voltage input terminal, and the gate terminal of the twelfth PMOS transistor is connected to its drain terminal, and the gate terminal of the thirteenth PMOS transistor is connected to the gate terminal of the twelfth PMOS transistor.

[0056] The sixteenth NMOS transistor has its drain connected to the drain of the twelfth PMOS transistor, its gate is the first input terminal of the buffer stage circuit, which receives the first resonant signal, and its source is connected to the eighth node.

[0057] The seventeenth NMOS transistor has its drain connected to the drain of the thirteenth PMOS transistor, its gate is the second input terminal of the buffer stage circuit, which receives the second resonant signal, and its source is connected to the eighth node.

[0058] A seventh current mirror structure is composed of an eighteenth NMOS transistor and a nineteenth NMOS transistor. The source terminals of the eighteenth and nineteenth NMOS transistors are both grounded. The drain terminal of the eighteenth NMOS transistor is connected to the bias current input terminal to receive the bias current. The gate terminal of the eighteenth NMOS transistor is connected to its drain terminal. The drain terminal of the nineteenth NMOS transistor is connected to the eighth node, and the gate terminal of the nineteenth NMOS transistor is connected to the gate terminal of the eighteenth NMOS transistor.

[0059] The drain terminal of the thirteenth PMOS transistor is the output terminal of the buffer stage circuit.

[0060] An electronic device comprising the voltage-controlled oscillator described in any of the preceding claims.

[0061] Compared with existing technologies, the above technical solution has the following advantages:

[0062] The voltage-controlled oscillator (VCO) provided in this application includes a bias circuit, a core circuit, and a buffer stage circuit connected in sequence. The core circuit includes a PMOS cross-coupled pair, an NMOS cross-coupled pair, and an LC resonant circuit connected in parallel. Compared to existing VCOs that use a current mirror structure to provide negative resistance to compensate for the power loss of the LC resonant circuit, the VCO provided in this application abandons the current mirror structure in its core circuit. It uses a parallel PMOS cross-coupled pair and an NMOS cross-coupled pair to provide negative resistance to compensate for the power loss of the LC resonant circuit, reducing the number of active devices and stacking layers in the VCO core circuit. This is beneficial for optimizing the noise performance of the VCO and achieving low voltage. Furthermore, the VCO provided in this application uses the bias circuit to provide negative resistance to the two PMOS transistors and the NMOS cross-coupled pair in the core circuit. The two NMOS transistors of the coupling pair provide the substrate voltage. Therefore, the substrate voltages of the two PMOS transistors of the PMOS cross-coupled pair and the two NMOS transistors of the NMOS cross-coupled pair in the core circuit can be adjusted by the bias circuit, thereby adjusting the threshold voltages of the two PMOS transistors of the PMOS cross-coupled pair and the two NMOS transistors of the NMOS cross-coupled pair in the core circuit, and thus determining the current of the core circuit. This allows the voltage-controlled oscillator to operate under low voltage and low power consumption conditions. It is evident that the voltage-controlled oscillator provided in this application embodiment has better noise performance than existing voltage-controlled oscillators and can operate in low-noise and low-voltage scenarios, such as wearable portable devices.

[0063] Furthermore, in existing voltage-controlled oscillators (VCOs), the current in the core circuit is easily affected by the channel length modulation effect of the MOSFET when using a current mirror structure to determine the current of the core circuit. As the drain voltage of the MOSFET changes, the current of the core circuit and the transconductance of the MOSFET also change. Especially when environmental factors such as temperature change, the current of the core circuit and the transconductance of the MOSFET are more significantly affected by the channel length modulation effect of the MOSFET, resulting in poor circuit robustness. However, in the VCO provided in this application embodiment, the substrate voltage of the two PMOS transistors of the PMOS cross-coupled pair and the two NMOS transistors of the NMOS cross-coupled pair in the core circuit can be determined by the bias circuit. This allows the voltage at each terminal of the two PMOS transistors of the PMOS cross-coupled pair and the two NMOS transistors of the NMOS cross-coupled pair in the core circuit to be determined, thereby reducing the magnitude of the change in the current of the core circuit and the transconductance of the MOSFET with environmental factors such as temperature, which is beneficial to improving the robustness of the VCO core circuit.

[0064] As can be seen, the voltage-controlled oscillator provided in this application embodiment has better noise performance than existing voltage-controlled oscillators, can work in low-noise and low-voltage scenarios, such as wearable portable devices, and has good circuit robustness. Attached Figure Description

[0065] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0066] Figure 1 This is a system block diagram of the voltage-controlled oscillator provided in the embodiments of this application;

[0067] Figure 2 This is a schematic diagram of the core circuit in a voltage-controlled oscillator provided in one embodiment of this application;

[0068] Figure 3 A schematic diagram of the bias circuit in a voltage-controlled oscillator provided in another embodiment of this application;

[0069] Figure 4 A schematic diagram of the bias circuit in a voltage-controlled oscillator provided in yet another embodiment of this application;

[0070] Figure 5 This is a schematic diagram of the operational amplifier structure of the bias circuit in a voltage-controlled oscillator provided in another embodiment of this application;

[0071] Figure 6 A schematic diagram of the core circuit in a voltage-controlled oscillator provided in yet another embodiment of this application;

[0072] Figure 7 A schematic diagram of the core circuit in a voltage-controlled oscillator provided in another embodiment of this application;

[0073] Figure 8 A schematic diagram of the core circuit in a voltage-controlled oscillator provided in yet another embodiment of this application;

[0074] Figure 9 This is a schematic diagram of the structure of a switched capacitor branch in the LC resonant circuit of the core circuit of the voltage-controlled oscillator provided in another embodiment of this application.

[0075] Figure 10 A schematic diagram of the control switching circuit in the switched capacitor branch of the switched capacitor array in the LC resonant circuit of the core circuit of the voltage-controlled oscillator provided in another embodiment of this application.

[0076] Figure 11 A schematic diagram of the buffer stage circuit in a voltage-controlled oscillator provided in another embodiment of this application;

[0077] Figure 12 This is a schematic diagram of the simulation results showing how the oscillation frequency of the output signal of the voltage-controlled oscillator provided in the embodiments of this application changes with the tuning voltage under each frequency band control word.

[0078] Figure 13 and Figure 14 This is a schematic diagram of the simulation results of the phase noise before and after introducing the second harmonic cancellation circuit into the voltage-controlled oscillator provided in the embodiments of this application. Detailed Implementation

[0079] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0080] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0081] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0082] As described in the background section, designing voltage-controlled oscillators with better noise performance and wider applicability has always been a problem and challenge for RF designers.

[0083] In view of this, embodiments of this application provide a voltage-controlled oscillator, such as... Figure 1 As shown, the voltage-controlled oscillator includes: a bias circuit 100, a core circuit 200, and a buffer stage circuit 300 connected in sequence, wherein, as... Figure 2 As shown, the core circuit 200 includes a PMOS cross-coupled pair 210, an NMOS cross-coupled pair 220 and an LC resonant circuit 230 connected in parallel;

[0084] Combination Figure 1 and Figure 2As shown, the bias circuit 100 provides a first substrate voltage Vbulkp to the substrate terminals of the two PMOS transistors in the PMOS cross-coupled pair 210, and a second substrate voltage Vbulkn to the substrate terminals of the two NMOS transistors in the NMOS cross-coupled pair 220.

[0085] In the core circuit 200, the PMOS cross-coupled pair 210 and the NMOS cross-coupled pair 220 are used to provide negative resistance to compensate for the power loss of the LC resonant circuit 230. The LC resonant circuit 230 is used to generate a first resonant signal Vop and a second resonant signal Von with the same amplitude but opposite phase, which are output to the buffer stage circuit 300.

[0086] The buffer stage circuit 300 converts the first resonant signal Vop and the second resonant signal Von into a single-ended signal Vout and then outputs it.

[0087] Therefore, compared with the existing voltage-controlled oscillator core circuit which uses a current mirror structure to provide negative resistance to compensate for the power loss of the LC resonant circuit, the voltage-controlled oscillator provided in this application embodiment abandons the current mirror structure in its core circuit 200 and uses parallel PMOS cross-coupled pair 210 and NMOS cross-coupled pair 220 to provide negative resistance to compensate for the power loss of the LC resonant circuit. This reduces the number of active devices and stacking layers in the core circuit of the voltage-controlled oscillator, which is beneficial to the optimization of the noise performance of the voltage-controlled oscillator and the realization of low voltage.

[0088] It should be noted that the two PMOS transistors in the PMOS cross-coupled pair 210 and the two NMOS transistors in the NMOS cross-coupled pair 220 are both four-terminal MOS transistors based on the fully-depleted silicon-on-insulator (FDSOI) process. MOS transistors based on the FDSOI process have back-gate adjustable performance, that is, the voltage difference between the gate terminal and the substrate terminal of the MOS transistor based on the FDSOI process can adjust its threshold voltage, thereby adjusting the operating state of the MOS transistor. MOS transistors based on the FDSOI process also have the advantages of small parasitic capacitance, low noise, and relatively small quiescent current and operating current, making them suitable for low-voltage and low-power scenarios. Therefore, in this embodiment, the bias circuit 100 provides substrate voltages for the two PMOS transistors of the PMOS cross-coupled pair 210 and the two NMOS transistors of the NMOS cross-coupled pair 220 in the core circuit 200. This allows the bias circuit 100 to adjust the substrate voltages of the two PMOS transistors of the PMOS cross-coupled pair 210 and the two NMOS transistors of the NMOS cross-coupled pair 220, thereby adjusting the threshold voltages of the two PMOS transistors of the PMOS cross-coupled pair 210 and the two NMOS transistors of the NMOS cross-coupled pair 220, further determining the current of the core circuit, and enabling the core circuit 200 of the voltage-controlled oscillator to operate under low voltage and low power consumption conditions.

[0089] Furthermore, in existing voltage-controlled oscillators (VCOs), the current in the core circuit is easily affected by the channel length modulation effect of the MOSFET when using a current mirror structure to determine the core circuit current. As the drain voltage of the MOSFET changes, the current in the core circuit and the transconductance of the MOSFET also change. Especially when environmental factors such as temperature change, the current in the core circuit and the transconductance of the MOSFET are more significantly affected by the channel length modulation effect, resulting in poor circuit robustness. However, in the VCO provided in this application embodiment, the substrate voltages of the two PMOS transistors in the PMOS cross-coupled pair 210 and the two NMOS transistors in the NMOS cross-coupled pair 220 in the core circuit can be determined by the bias circuit. This allows the voltages at each terminal of the two PMOS transistors in the PMOS cross-coupled pair 210 and the two NMOS transistors in the NMOS cross-coupled pair 220 in the core circuit to be determined, thereby reducing the magnitude of changes in the current in the core circuit and the transconductance of the MOSFETs with environmental factors such as temperature, which is beneficial to improving the robustness of the VCO core circuit.

[0090] As can be seen, the voltage-controlled oscillator provided in this application embodiment has better noise performance than existing voltage-controlled oscillators, can work in low-noise and low-voltage scenarios, such as wearable portable devices, and has good circuit robustness.

[0091] Based on the above embodiments, optionally, in one embodiment of this application, such as Figure 2 As shown, the PMOS cross-coupled pair 210 includes a first PMOS transistor P1 and a second PMOS transistor P2, and the NMOS cross-coupled pair includes a first NMOS transistor N1 and a second NMOS transistor N2;

[0092] In the core circuit, the source terminals of the first PMOS transistor P1 and the second PMOS transistor P2 are both connected to the power supply voltage input terminal, which is VDD. The gate terminal of the first PMOS transistor P1 is connected to the drain terminal of the second PMOS transistor P2, and the gate terminal of the second PMOS transistor P2 is connected to the drain terminal of the first PMOS transistor P1.

[0093] The source terminals of the first NMOS transistor N1 and the second NMOS transistor N2 are both grounded. The gate terminal of the first NMOS transistor N1 is connected to the drain terminal of the second NMOS transistor N2, and the gate terminal of the second NMOS transistor N2 is connected to the drain terminal of the first NMOS transistor N1.

[0094] The drain terminals of the first PMOS transistor P1, the first NMOS transistor N1, and the first output terminal of the LC resonant circuit 230 are all connected to the first node A, and the drain terminals of the second PMOS transistor P2, the second NMOS transistor N2, and the second output terminal of the LC resonant circuit 230 are all connected to the second node B.

[0095] The first node A and the second node B serve as the two output terminals of the core circuit 200, respectively outputting the first resonant signal Vop and the second resonant signal Von generated by the LC resonant circuit 230.

[0096] It should be noted that, compared with the existing voltage-controlled oscillator core circuit which uses a current mirror structure to provide negative resistance to compensate for the power loss of the LC resonant circuit, the voltage-controlled oscillator provided in this application embodiment abandons the current mirror structure in its core circuit. Instead, it uses parallel-connected PMOS cross-coupled pairs and NMOS cross-coupled pairs to provide negative resistance to compensate for the power loss of the LC resonant circuit. The advantage of the PMOS cross-coupled pair 210 and the NMOS cross-coupled pair 220 is that they are current-multiplexed, which allows them to provide a larger negative resistance value under the same DC bias. This compensates for the power loss caused by the parasitic resistance on the inductor and capacitor in the LC resonant circuit 230, i.e., the energy consumed by the positive resistance of the LC resonant circuit 230, and maintains the oscillation of the LC resonant circuit.

[0097] Specifically, the negative conductance generated by the PMOS cross-coupling pair 210 for the first PMOS transistor P1 and the second PMOS transistor P2 is -g.mp The equivalent resistance generated by the PMOS cross-coupling pair 210 is -2 / g. mp The negative conductance generated by the NMOS cross-coupling pair in the 220 for the first NMOS transistor N1 and the second NMOS transistor N2 is -g. mn The equivalent negative resistance generated by the NMOS cross-coupling pair 220 is -2 / g. mn Therefore, the total negative resistance R generated by the PMOS cross-coupled pair 210 and the NMOS cross-coupled pair 220 is... n for:

[0098] (1)

[0099] The total negative resistance R generated by the PMOS cross-coupled pair 210 and the NMOS cross-coupled pair 220 is [missing information]. n This is used to compensate for the power loss caused by the parasitic resistance on the inductor and capacitor in the LC resonant circuit 230.

[0100] It should also be noted that the PMOS cross-coupled pair 210 contains four negative resistance transistors: the first PMOS transistor P1 and the second PMOS transistor P2, and the NMOS cross-coupled pair 220 contains the first NMOS transistor N1 and the second NMOS transistor N2. Compared with existing voltage-controlled oscillators, this voltage-controlled oscillator reduces the number of active devices and stacking layers in its core circuit, which is beneficial for optimizing the noise performance of the voltage-controlled oscillator and achieving low voltage.

[0101] Optionally, in one embodiment of this application, such as Figure 3 As shown, the bias circuit 100 includes:

[0102] A first current mirror structure 110 is composed of a third PMOS transistor P3 and a fourth PMOS transistor P4, wherein the source terminals of the third PMOS transistor P3 and the fourth PMOS transistor P4 are both connected to the power supply voltage input terminal, the input power supply voltage is VDD, the gate terminal of the third PMOS transistor P3 is connected to its drain terminal, and the gate terminal of the fourth PMOS transistor P4 is connected to the gate terminal of the third PMOS transistor.

[0103] A first feedback loop 120 is composed of a fifth PMOS transistor P5 and a first operational amplifier PA1. The source terminal of the fifth PMOS transistor P5 is connected to the power supply voltage input terminal, receiving the power supply voltage VDD. The drain terminal of the fifth PMOS transistor P5 is connected to the positive input terminal of the first operational amplifier PA1. The gate terminal of the fifth PMOS transistor P5 is connected to the reference voltage input terminal, receiving the reference voltage Vref. The gate terminal of the fifth PMOS transistor P5 is also connected to the negative input terminal of the first operational amplifier PA1. The substrate terminal of the fifth PMOS transistor P5 is connected to the output terminal of the first operational amplifier PA1.

[0104] A second feedback loop 130 is formed by a third NMOS transistor N3 and a second operational amplifier PA2. The source terminal of the third NMOS transistor N3 is grounded, the drain terminal of the third NMOS transistor N3 is connected to the drain terminal of the fourth PMOS transistor P4, and the drain terminal of the third NMOS transistor N3 is also connected to the positive input terminal of the second operational amplifier PA2. The gate terminal of the third NMOS transistor N3 is connected to the reference voltage input terminal, the input reference voltage Vref, and the gate terminal of the third NMOS transistor N3 is also connected to the negative input terminal of the second operational amplifier PA2. The substrate terminal of the third NMOS transistor N3 is connected to the output terminal of the second operational amplifier PA2.

[0105] A second current mirror structure 140 is composed of a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6. The drain of the fourth NMOS transistor N4 is connected to the bias current input terminal, which receives a bias current I. The gates of the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6 are all connected to the drain of the fourth NMOS transistor N4. The sources of the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6 are all grounded. The drain of the fifth NMOS transistor N5 is connected to the drain of the third PMOS transistor P3, and the drain of the sixth NMOS transistor N6 is connected to the drain of the fifth PMOS transistor P5.

[0106] The substrate of the fifth PMOS transistor P5 is connected to the first output terminal of the bias circuit 100, outputting the first substrate voltage Vbulkp. The substrate of the third NMOS transistor N3 is connected to the second output terminal of the bias circuit 100, outputting the second substrate voltage Vbulkn.

[0107] It should be noted that in the bias circuit 100, the reference Figure 3As shown, the branch formed by the fourth NMOS transistor N4 is designated as the first branch, and the current in the first branch is the first current I1; the branch formed by the third PMOS transistor P3 and the fifth NMOS transistor N5 connected in series is designated as the second branch, and the current in the second branch is the second current I2; the branch formed by the fifth PMOS transistor P5 and the sixth NMOS transistor N6 connected in series is designated as the third branch, and the current in the third branch is the third current I3; the branch formed by the fourth PMOS transistor P4 and the third NMOS transistor N3 is designated as the fourth branch, and the current in the fourth branch is the fourth current I4. Since the third PMOS transistor P3 and the fourth PMOS transistor P4 form a current mirror structure, and the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6 also form a current mirror structure, the current I3 in the third branch proportionally replicates the current I1 in the first branch, and the current I4 in the fourth branch proportionally replicates the current I2 in the second branch.

[0108] It should also be noted that the fifth PMOS transistor P5 and the third NMOS transistor N3 are both four-terminal MOS transistors based on FDSOI technology. The operation of the first feedback loop 120 utilizes the back gate adjustable performance of the fifth PMOS transistor P5 as an FDSOI device. Similarly, the operation of the second feedback loop 130 utilizes the back gate adjustable performance of the third NMOS transistor N3 as an FDSOI device.

[0109] The specific working process of the first feedback loop 120 will be explained below. For details, please refer to... Figure 3 As shown, the source terminal of the fifth PMOS transistor P5 is input to the power supply voltage VDD, and the gate terminal is input to the reference voltage Vref. Simultaneously, the negative input terminal of the first operational amplifier PA1 is also input to the reference voltage Vref. When the drain voltage of the fifth PMOS transistor P5 changes (for example, if the drain voltage of the fifth PMOS transistor P5 increases), the positive input terminal voltage of the first operational amplifier PA1 also increases, causing the output voltage of the first operational amplifier PA1 to increase, thereby increasing the substrate voltage V of the fifth PMOS transistor. B Increase, while the gate voltage V of the fifth PMOS transistor increases. S Since Vref remains constant, the voltage difference V between the gate and substrate of the fifth PMOS transistor remains constant. SB =V S -V B To decrease it, according to the threshold voltage formula of a MOSFET:

[0110] (2)

[0111] Among them, VTH0 γ is the threshold voltage of the MOSFET at zero bias, γ is the body effect coefficient, and φ is the threshold voltage of the MOSFET at zero bias. F It is the potential of the inversion layer of the MOSFET, V SB It is the voltage difference between the gate and substrate of the MOS transistor.

[0112] From formula (2), it can be seen that when the voltage difference V between the gate terminal and the substrate terminal of the fifth PMOS transistor is... SB When the threshold voltage V of the fifth PMOS transistor decreases, TH The current decreases, and since the current I3 flowing through the fifth PMOS transistor P5 proportionally replicates the current I1 of the first branch, the current I3 flowing through the fifth PMOS transistor P5 remains unchanged. Furthermore, the gate voltage (i.e., reference voltage Vref) and source voltage (i.e., power supply voltage VDD) of the fifth PMOS transistor P5 remain unchanged. In other words, the voltage difference V between the gate and source of the fifth PMOS transistor P5 remains constant. GS The voltage remains unchanged, therefore, the drain voltage of the fifth PMOS transistor will decrease again, thereby keeping the drain voltage of the fifth PMOS transistor stable, and consequently keeping the substrate voltage of the fifth PMOS transistor stable, that is, keeping the first substrate voltage Vbulkp output by the first output terminal of the bias circuit 100 stable.

[0113] Therefore, in the first feedback loop 120, the gate voltage of the fifth PMOS transistor P5 is determined by the reference voltage Vref, which means the negative input voltage of the first operational amplifier PA1 is determined by the reference voltage Vref. The drain voltage of the fifth PMOS transistor P5 is clamped by the first operational amplifier PA1, making the drain voltage of the fifth PMOS transistor P5 approximately equal to the reference voltage Vref. The substrate voltage of the fifth PMOS transistor P5 is determined by the output voltage of the first operational amplifier PA1. When the first operational amplifier PA1 stabilizes, the substrate voltage of the fifth PMOS transistor P5 stabilizes, thereby stabilizing the first substrate voltage Vbulkp output by the first output terminal of the bias circuit 100, which is then output to the core circuit 200.

[0114] Similarly, in the second feedback loop 130, the gate voltage of the third NMOS transistor N3 is determined by the reference voltage Vref, that is, the negative input voltage of the second operational amplifier PA2 is determined by the reference voltage Vref. The drain voltage of the third NMOS transistor N3 is clamped by the second operational amplifier PA2, making the drain voltage of the third NMOS transistor N3 approximately equal to the reference voltage Vref. The substrate voltage of the third NMOS transistor N3 is determined by the output voltage of the second operational amplifier PA2. When the second operational amplifier PA2 stabilizes, the substrate voltage of the third NMOS transistor N3 stabilizes, thereby stabilizing the second substrate voltage Vbulkn output by the second output terminal of the bias circuit 100, which is then output to the core circuit 200.

[0115] It should also be noted that, in this embodiment, the bias circuit 100 outputs a stable first substrate voltage Vbulkp and a second substrate voltage Vbulkn to the core circuit 200 through the first feedback loop 120 and the second feedback loop 130; and, compared with the first PMOS transistor P1 and the second PMOS transistor P2 in the core circuit 200, the fifth PMOS transistor P5 in the bias circuit 100 has the same substrate voltage Vbulkp, the same source voltage VDD, and the same gate voltage and drain voltage. That is, the voltages at each terminal of the first PMOS transistor P1 and the second PMOS transistor P2 in the core circuit 200 are matched one-to-one with the voltages at each terminal of the fifth PMOS transistor P5 in the bias circuit 100.

[0116] Similarly, compared with the first NMOS transistor N1 and the second NMOS transistor N2 in the core circuit 200, the substrate voltage of the third NMOS transistor N3 in the bias circuit 100 is the second substrate voltage Vbulkn. Their source terminals are all grounded, and their gate terminal voltage and drain terminal voltage are equal. That is, the voltages of each terminal of the first NMOS transistor N1 and the second NMOS transistor N2 in the core circuit 200 are matched one by one with the voltages of each terminal of the third NMOS transistor N3 in the bias circuit 100 to determine the value.

[0117] Therefore, by matching the voltages of the fifth PMOS transistor P5 in the bias circuit 100 with the voltages of the first PMOS transistor P1 and the second PMOS transistor P2 in the core circuit, and by matching the voltages of the third NMOS transistor N3 in the bias circuit 100 with the voltages of the first NMOS transistor N1 and the second NMOS transistor N2 in the core circuit, the current in each branch of the core circuit 200 can be determined. This reduces the variation of the branch current and the transconductance of the MOS transistors in the core circuit 200 with environmental factors such as temperature, which is beneficial to improving the robustness of the voltage-controlled oscillator core circuit.

[0118] In order to filter out high-frequency components in the first substrate voltage signal and the second substrate voltage signal output by the bias circuit 100, based on the above embodiments, in one embodiment of this application, such as... Figure 4 As shown, the bias circuit 100 further includes:

[0119] A first low-pass filter 150 is composed of a first resistor R1 and a first capacitor C1, wherein the first end of the first resistor R1 is connected to the substrate end of the fifth PMOS transistor P5, and the second end is grounded through the first capacitor C1.

[0120] A second low-pass filter 160 is composed of a second resistor R2 and a second capacitor C2, wherein the first end of the second resistor R2 is connected to the substrate end of the third NMOS transistor N3, and the second end is grounded through the second capacitor C2.

[0121] Wherein, the second end of the first resistor R1 is the first output terminal of the bias circuit 100, and the second end of the second resistor R2 is the second output terminal of the bias circuit 100.

[0122] Therefore, in this embodiment, the first substrate voltage Vbulkp output by the bias circuit 100 is filtered out of its high-frequency components by the first low-pass filter 150 and then output to the core circuit 200. The second substrate voltage Vbulkn output by the bias circuit 100 is filtered out of its high-frequency components by the second low-pass filter 160 and then output to the core circuit 200, making the first substrate voltage Vbulkp and the second substrate voltage Vbulkn input to the core circuit 200 more stable.

[0123] Optionally, in one embodiment of this application, the first operational amplifier PA1 and the second operational amplifier PA2 are the same operational amplifier, such as... Figure 5 As shown, the operational amplifier includes:

[0124] A third current mirror structure 170 is composed of a sixth PMOS transistor P6 and a seventh PMOS transistor P7. The source terminals of both the sixth PMOS transistor P6 and the seventh PMOS transistor P7 are connected to the power supply voltage input terminal, which is VDD. The drain terminal of the sixth PMOS transistor P6 is grounded through a seventh NMOS transistor N7. The gate terminal of the sixth PMOS transistor P6 is connected to the gate terminal of the seventh PMOS transistor P7. The gate terminal of the seventh PMOS transistor P7 is connected to its drain terminal, and the drain terminal of the seventh PMOS transistor P7 is connected to a third node. The gate terminal of the seventh NMOS transistor is connected to its drain terminal.

[0125] A fourth current mirror structure 180 is composed of an eighth PMOS transistor P8 and a ninth PMOS transistor P9. The source terminals of both the eighth PMOS transistor P8 and the ninth PMOS transistor P9 are connected to the power supply voltage input terminal, which is VDD. The drain terminal of the ninth PMOS transistor P9 is grounded through an eighth NMOS transistor N8, and the gate terminal of the ninth PMOS transistor P9 is connected to the gate terminal of the eighth PMOS transistor P8. The gate terminal of the eighth PMOS transistor P8 is connected to its drain terminal, and the drain terminal of the eighth PMOS transistor P8 is connected to a fourth node D. The gate terminal of the eighth NMOS transistor N8 is connected to the gate terminal of the seventh NMOS transistor N7.

[0126] The tenth PMOS transistor P10 and the eleventh PMOS transistor P11 are cross-coupled. The source terminals of both the tenth PMOS transistor P10 and the eleventh PMOS transistor P11 are connected to the power supply voltage input terminal, which is VDD. The gate terminal of the tenth PMOS transistor P10 is connected to the drain terminal of the eleventh PMOS transistor P11, and the drain terminal of the tenth PMOS transistor P10 is connected to the third node C. The gate terminal of the eleventh PMOS transistor P11 is connected to the drain terminal of the tenth PMOS transistor P10, and the drain terminal of the eleventh PMOS transistor P11 is connected to the fourth node D.

[0127] The ninth NMOS transistor N9 has its drain connected to the third node C, its gate connected to the positive input terminal of the operational amplifier, and its source connected to the fifth node E.

[0128] The tenth NMOS transistor N10 has its drain connected to the fourth node D, its gate connected to the negative input terminal of the operational amplifier, and its source connected to the fifth node E.

[0129] A fifth current mirror structure 190 is composed of an eleventh NMOS transistor N11 and a twelfth NMOS transistor N12. The source terminals of both the eleventh NMOS transistor N11 and the twelfth NMOS transistor N12 are grounded. The drain terminal of the eleventh NMOS transistor N11 is connected to the bias current input terminal, which receives a bias current I. The gate terminal of the eleventh NMOS transistor N11 is connected to its drain terminal. The gate terminal of the twelfth NMOS transistor N12 is connected to the gate terminal of the eleventh NMOS transistor N11, and the drain terminal of the twelfth NMOS transistor N12 is connected to the fifth node E.

[0130] The drain terminal of the ninth PMOS transistor P9 is the output terminal of the operational amplifier.

[0131] It should be noted that the voltage signal Vo output by the operational amplifier is determined based on the magnitudes of the voltage V+ input to its positive input terminal and the voltage V- input to its negative input terminal. Specifically, when the voltage V+ input to the positive input terminal of the operational amplifier is greater than the voltage V- input to its negative input terminal, the voltage Vo output increases; conversely, when the voltage V+ input to the positive input terminal of the operational amplifier is less than the voltage V- input to its negative input terminal, the voltage Vo output decreases. Therefore, in the bias circuit 100, when the drain voltage of the fifth PMOS transistor P5 or the third NMOS transistor N3 changes, the voltage V+ input to the positive input terminal of the operational amplifier changes in the same direction, causing the voltage Vo output by the operational amplifier (i.e., the substrate voltage V of the fifth PMOS transistor P5 or the third NMOS transistor N3) to increase. B The voltage difference V between the gate terminal and the substrate terminal of the fifth PMOS transistor P5 or the third NMOS transistor N3 also changes in the same direction, thereby causing the voltage difference V between the gate terminal and the substrate terminal of the fifth PMOS transistor P5 or the third NMOS transistor N3 to change. SB The reverse change causes the drain voltage of the fourth PMOS transistor P4 or the third NMOS transistor N3 to change in the opposite direction. That is, the first feedback loop 120 and the second feedback loop 130 are both stable, and the substrate voltage of the fifth PMOS transistor P5 or the third NMOS transistor N3 is also stable. That is, the first substrate voltage Vbulkp and the second substrate voltage Vbulkn output by the bias circuit are also stable.

[0132] Specifically, such as Figure 5As shown, in the operational amplifier circuit structure, when the voltage V+ input to its positive input terminal is greater than the voltage V- input to its negative input terminal, the drain current of the ninth NMOS transistor N9 increases, causing the voltage at the third node (point C) to decrease, i.e., the gate voltage of the eleventh PMOS transistor P11 decreases, thereby increasing the drain current of the eleventh PMOS transistor P11, which in turn causes the drain current of the eighth PMOS transistor P8 to change in the opposite direction. Because the eighth PMOS transistor P8 and the ninth PMOS transistor P9 form the fourth current mirror structure 180, the decrease in the drain current of the eighth PMOS transistor P8 causes a decrease in the current flowing through the ninth PMOS transistor P9. Therefore, the drain voltage of the ninth PMOS transistor P9 increases, i.e., the output voltage Vo of the operational amplifier increases. Similarly, when the voltage V+ input to the positive input terminal of the operational amplifier is less than the voltage V- input to its negative input terminal, its output voltage Vo decreases.

[0133] It should also be noted that the operational amplifier is a single-stage operational amplifier of the bias circuit 100, such as... Figure 5 As shown, the tenth PMOS transistor P10 and the eleventh PMOS transistor P11 form a cross-coupled negative resistance pair circuit, thereby increasing the gain of the operational amplifier. Meanwhile, for a traditional single-stage common-source amplifier, the output voltage can be considered as directly outputting from the fourth node (point D). In this case, the amplifier's output voltage swing is limited by the drain-source voltage Vds of the tenth NMOS transistor N10, the drain-source voltage Vds of the twelfth NMOS transistor N12, and the gate-source voltage Vgs of the input pair, the ninth NMOS transistor N9 and the tenth NMOS transistor N10. However, in the operational amplifier circuit structure provided in this embodiment, its lower limit of output swing is only limited by the drain-source voltage Vds of the eighth NMOS transistor N8, thus retaining the single-stage op-amp structure while having a larger output swing.

[0134] Furthermore, the operational amplifier is a single-stage amplifier. After being connected to the negative feedback loop of the bias circuit (i.e., the first feedback loop 120 and the second feedback loop 130), it forms a two-stage system, enabling the entire bias circuit 100 to reach a stable state.

[0135] Therefore, it can be seen that the operational amplifier circuit can effectively ensure the stability of the first feedback loop, the second feedback loop, and the entire bias circuit while meeting a large output voltage range.

[0136] Optionally, in one embodiment of this application, such as Figure 6 As shown, the core circuit 200 further includes a second harmonic cancellation circuit 240, which includes:

[0137] A first inductor L1 and a third capacitor C3 are connected in series. The first end of the first inductor L1 is connected to the first node A, and the second end of the first inductor L1 is grounded through the third capacitor C3.

[0138] A second inductor L2 and a fourth capacitor C4 are connected in series. The first end of the second inductor L2 is connected to the second node B, and the second end of the second inductor L2 is grounded through the fourth capacitor C4.

[0139] The resonant frequency of the first inductor L1 and the third capacitor C3 connected in series is the second harmonic frequency of the first resonant signal, and the resonant frequency of the second inductor L2 and the fourth capacitor C4 connected in series is the second harmonic frequency of the second resonant signal.

[0140] It should be noted that, in this embodiment, by adjusting the inductance value of the first inductor L1 and / or the capacitance value of the third capacitor C3, the resonant frequency of the series-connected first inductor L1 and the third capacitor C3 is made to be the second harmonic frequency of the first resonant signal. This results in the series-connected first inductor L1 and the third capacitor C3 forming a low-impedance loop at the second harmonic frequency of the first resonant signal, i.e., a low-impedance point relative to the second harmonic frequency of the first resonant signal. This guides the second harmonic frequency of the first resonant signal to ground, thereby eliminating the second harmonic frequency of the first resonant signal and further improving the noise performance of the voltage-controlled oscillator.

[0141] Similarly, by adjusting the inductance value of the second inductor L2 and / or the capacitance value of the fourth capacitor C4, the resonant frequency of the series-connected second inductor L2 and fourth capacitor C4 is made to be the second harmonic frequency of the second resonant signal. This allows the series-connected second inductor L2 and fourth capacitor C4 to form a low-impedance loop at the second harmonic frequency of the second resonant signal, i.e., a low-impedance point relative to the second harmonic frequency of the second resonant signal. This guides the second harmonic frequency of the second resonant signal to ground, thereby eliminating the second harmonic frequency of the second resonant signal and further improving the noise performance of the voltage-controlled oscillator.

[0142] Optionally, in one embodiment of this application, such as Figure 7 As shown, the LC resonant circuit 230 includes a third inductor L3, a switched capacitor array 231, and a variable capacitor branch 232 connected in parallel; wherein,

[0143] The first end of the third inductor L3 is connected to the first node A, and the second end is connected to the second node B;

[0144] The first terminal of the switched capacitor array 231 is connected to the first node A, the second terminal is connected to the second node B, and the control terminal inputs the frequency band control word S. VCO The switched capacitor array 231 is based on the frequency band control word S VCO Capacitors of different sizes are available;

[0145] The first terminal of the variable capacitor branch 232 is connected to the first node A, the second terminal is connected to the second node B, and the control terminal is input with a tuning voltage V. tune The variable capacitor branch 232 is based on the tuning voltage V tune Capacitors of different sizes are available.

[0146] It should be noted that in the LC resonant circuit, the inductance value of the third inductor L3 is fixed, and the switched capacitor array 231 is based on the frequency band control word S. VCO Capacitors of different sizes are provided, and the variable capacitor branch 232 is based on the tuning voltage V. tune Provide capacitors of different sizes, based on the oscillation frequency f0 generated when the LC resonant circuit resonates:

[0147] (3)

[0148] Wherein, L is the inductance value of the third inductor L3, and C is the equivalent capacitance of the switched capacitor array 231 and the variable capacitor branch 232 combined.

[0149] As can be seen from formula (3), based on the frequency band control word S VCO The variation and / or the tuning voltage V tune The change in capacitance, which is equivalent to the change in capacitance of the switched capacitor array 231 and the variable capacitor branch 232, can adjust the oscillation frequency of the resonant signal output by the LC resonant circuit.

[0150] It should also be noted that the frequency band control word S VCO The binary code controls the switched capacitor array 231 to provide discrete capacitance values, thereby making the oscillation frequency f0 of the resonant signal output by the LC resonant circuit a discrete and independent frequency point. The variable capacitor branch 232, under the tuning voltage V... tune Under the control of [the system], a continuously varying capacitance value is provided, thereby causing the oscillation frequency f0 of the resonant signal output by the LC resonant circuit to continuously change based on a certain frequency point.

[0151] Therefore, it can be seen that by adjusting the frequency band control word S VCOThis allows the switched capacitor array 231 to provide discrete capacitance values ​​to roughly adjust the oscillation frequency of the resonant signal output by the LC resonant circuit, and through the tuning voltage V tune This allows the variable capacitor branch 232 to provide a continuous capacitance value to precisely adjust the oscillation frequency of the resonant signal output by the LC resonant circuit.

[0152] Specifically, in one embodiment of this application, such as Figure 8 As shown, the variable capacitor branch 232 includes: a fifth capacitor C5, a first varactor Cvar1, a second varactor Cvar2, and a sixth capacitor C6 connected in series.

[0153] Wherein, the end of the fifth capacitor C5 that is away from the first varactor tube Cvar1 is the first end of the variable capacitor branch 232, and is connected to the first node A;

[0154] The end of the sixth capacitor C6 that is away from the second varactor Cvar2 is the second end of the variable capacitor branch 232 and is connected to the second node B.

[0155] The common terminal of the fifth capacitor C5 and the first varactor Cvar1 is the sixth node F. The sixth node F is connected to the power supply voltage input terminal through the third resistor R3. The sixth node F is also grounded through the fourth resistor R4.

[0156] The common terminal of the sixth capacitor C6 and the second varactor Cvar2 is the seventh node G. The seventh node G is connected to the power supply voltage input terminal through the fifth resistor R5. The seventh node G is also grounded through the sixth resistor R6.

[0157] The common terminal of the first varactor Cvar1 and the second varactor Cvar2 is the control terminal of the variable capacitor branch 232, and the tuning voltage V is input. tune .

[0158] It should be noted that since a MOS device is always a capacitor under voltage conditions that do not cause the insulating layer to break down, and capacitance adjustment can be achieved within a relatively small control voltage range, both the first varactor Cvar1 and the second varactor Cvar2 can be MOS devices.

[0159] Since the capacitance of a MOS device as a varactor changes with the voltage difference between its gate and source terminals, typically when the voltage difference between the gate and source terminals varies within the range of -1V to 1V, the capacitance changes linearly with this voltage difference. Therefore, in this embodiment, the voltage at one end of the first varactor Cvar1 (i.e., the voltage at the sixth node F) is determined by a voltage divider formed by the third resistor R3 and the fourth resistor R4 connected in series. The voltage at the other end of the first varactor Cvar1 varies with the tuning voltage V. tune The capacitance of the first varactor Cvar1 changes with the tuning voltage V, thus causing the capacitance of the first varactor Cvar1 to change with the tuning voltage V. tune The voltage changes linearly with respect to the change in resistance. Specifically, the series voltage divider configuration of the third resistor R3 and the fourth resistor R4 means that once the resistances of the third resistor R3 and the fourth resistor R4 are determined, since one end of the branch formed by the third resistor R3 and the fourth resistor R4 is connected to the power supply voltage VDD and the other end is grounded, the voltage divisions across the third resistor R3 and the fourth resistor R4 are determined. Therefore, the voltage at the sixth node F is also determined, that is, the voltage at the end of the first varactor Cvar1 connected to the sixth node F is also determined.

[0160] Similarly, the voltage at one end of the second varactor Cvar2 (i.e., the voltage at the seventh node G) is determined by a voltage divider formed by the series connection of the fifth resistor R5 and the sixth resistor R6. The voltage at the other end of the second varactor Cvar2 varies with the tuning voltage V. tune The capacitance of the second varactor Cvar2 changes with the tuning voltage V, thus causing the capacitance of the second varactor Cvar2 to change with the tuning voltage V. tune The change is linear.

[0161] Therefore, it can be seen that by adjusting the tuning voltage V tune The capacitances of the first varactor Cvar1 and the second varactor Cvar2 are linearly adjusted so that the total capacitance of the variable capacitor branch 232 also changes with the tuning voltage V. tune It changes linearly with the change of the tuning voltage V, that is, it changes linearly with the change of the tuning voltage V. tune This allows the variable capacitor branch 232 to provide a continuous capacitance value, thereby precisely adjusting the oscillation frequency of the resonant signal output by the LC resonant circuit and improving the linearity of the tuning curve of the voltage-controlled oscillator.

[0162] It should also be noted that the resistance values ​​of the third resistor R3 and the fourth resistor R4 should be large enough to form a high-pass filter with the fifth capacitor C5, ensuring that the signal passes through normally; similarly, the resistance values ​​of the fifth resistor R5 and the sixth resistor R6 should also be large enough to form a high-pass filter with the sixth capacitor C6, ensuring that the signal passes through normally.

[0163] Optionally, in one embodiment of this application, the switched capacitor array includes N switched capacitor branches connected in parallel, where N is a positive integer greater than 1, such as... Figure 9 As shown, each switched capacitor branch includes a control switch circuit 2311 and a weighted capacitor;

[0164] The frequency band control word input to the control terminal of the switched capacitor array is N bits, and each frequency band control word controls the closing and closing of the control switch circuit in one of the switched capacitor branches;

[0165] As the number of bits in the frequency band control word increases, the capacitance value of the weight capacitor in the switched capacitor branch controlled by the frequency band control word becomes larger.

[0166] Specifically, the weight capacitor in each of the switched capacitor branches may include multiple unit capacitors, each of which may be substantially the same. The number of unit capacitors included in the weight capacitor in each of the switched capacitor branches increases with the increase of the number of bits of the frequency band control word controlling that switched capacitor branch, thereby making the capacitance value of the weight capacitor in the switched capacitor branch controlled by the frequency band control word larger as the number of bits of the frequency band control word increases.

[0167] For example, the frequency band control word S VCO The frequency band control word is a 5-bit binary code, ranging from 00000 to 11111. Each bit controls the closing and closing of the control switch circuit in one of the switched capacitor branches. Therefore, there are 5 switched capacitor branches, and these 5 switched capacitor branches can be combined to form 2^... 5 In this case, 2^ 5 There are 32 types of capacitance values.

[0168] Optionally, in one embodiment of this application, such as Figure 10 As shown, the control switch circuit 2311 includes: a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, and a fifteenth NMOS transistor N15;

[0169] The gate terminal of the thirteenth NMOS transistor N13 is input with a one-bit frequency band control word. The first terminal is grounded through the fourteenth NMOS transistor N14, and the second terminal is grounded through the fifteenth NMOS transistor N15.

[0170] The gate of the fourteenth NMOS transistor N14 is connected to the gate of the fifteenth NMOS transistor N15. The common terminal of the gate of the fourteenth NMOS transistor and the gate of the fifteenth NMOS transistor is also input with a one-bit frequency band control word. The frequency band control word input to the common terminal of the gate of the fourteenth NMOS transistor and the gate of the fifteenth NMOS transistor is the same one-bit frequency band control word as the frequency band control word input to the gate of the thirteenth NMOS transistor.

[0171] The source and drain terminals of the thirteenth NMOS transistor N13 are the two ends of the control switch circuit 2311, respectively.

[0172] It should be noted that, in this embodiment, when the frequency band control word SW at the gate terminals of the thirteenth NMOS transistor N13, the fourteenth NMOS transistor N14, and the fifteenth NMOS transistor N15 is high, all three transistors are turned on, and the control switch circuit 2311 is closed; when the frequency band control word SW at the gate terminals of the thirteenth NMOS transistor N13, the fourteenth NMOS transistor N14, and the fifteenth NMOS transistor N15 is low, all three transistors are turned off, and the control switch circuit 2311 is turned off.

[0173] It should also be noted that the control switch circuit 2311 uses three NMOS transistors to form a switching circuit in order to obtain smaller parasitic capacitance and higher adjustment accuracy. Among them, the thirteenth NMOS transistor N13, the fourteenth NMOS transistor N14, and the fifteenth NMOS transistor N15 can all be designed as weighted transistors, and their aspect ratio can be increased as the number of bits of the frequency band control word at their gate input increases.

[0174] Optionally, in one embodiment of this application, such as Figure 11 As shown, the buffer stage circuit 300 includes:

[0175] A sixth current mirror structure 310 is composed of a twelfth PMOS transistor P12 and a thirteenth PMOS transistor P13. The source terminals of the twelfth PMOS transistor P12 and the thirteenth PMOS transistor P13 are both connected to the power supply voltage input terminal, which is VDD. The gate terminal of the twelfth PMOS transistor P12 is connected to its drain terminal, and the gate terminal of the thirteenth PMOS transistor P13 is connected to the gate terminal of the twelfth PMOS transistor P12.

[0176] The sixteenth NMOS transistor N16 has its drain connected to the drain of the twelfth PMOS transistor P12, its gate is the first input terminal of the buffer stage circuit 300, and it receives the first resonant signal Vop. Its source terminal is connected to the eighth node H.

[0177] The seventeenth NMOS transistor N17 has its drain connected to the drain of the thirteenth PMOS transistor P13, its gate is the second input terminal of the buffer stage circuit 300, and it inputs the second resonant signal Von. Its source terminal is connected to the eighth node H.

[0178] A seventh current mirror structure 320 is composed of an eighteenth NMOS transistor N18 and a nineteenth NMOS transistor N19. The source terminals of both the eighteenth NMOS transistor N18 and the nineteenth NMOS transistor N19 are grounded. The drain terminal of the eighteenth NMOS transistor N18 is connected to a bias current input terminal, receiving a bias current I. The gate terminal of the eighteenth NMOS transistor N18 is connected to its drain terminal. The drain terminal of the nineteenth NMOS transistor N19 is connected to the eighth node H, and the gate terminal of the nineteenth NMOS transistor N19 is connected to the gate terminal of the eighteenth NMOS transistor N18.

[0179] The drain terminal of the thirteenth PMOS transistor P13 is the output terminal of the buffer stage circuit 300.

[0180] Therefore, the buffer stage circuit 300 adopts a common-source amplifier structure with a current mirror as the load, which converts the differential signal output by the core circuit 200 (i.e., the first resonant signal Vop and the second resonant signal Von with the same amplitude but opposite phase) into a single-ended output signal Vout.

[0181] Furthermore, the output impedance of the buffer stage circuit is relatively large, which has the function of isolating external loads. When the external load environment changes, adding this output buffer stage circuit can reduce the probability that the core circuit will change with the change of the external load environment, and ensure the stability of the oscillation frequency of the voltage-controlled oscillator output signal Vout.

[0182] In summary, the voltage-controlled oscillator provided in this application includes: a bias circuit, a core circuit, and a buffer stage circuit connected in sequence. The core circuit includes a PMOS cross-coupled pair, an NMOS cross-coupled pair, and an LC resonant circuit connected in parallel. It abandons the current mirror structure in the core circuit of existing voltage-controlled oscillators, and uses the PMOS cross-coupled pair and NMOS cross-coupled pair to provide negative resistance to compensate for the power loss of the LC resonant circuit. This reduces the number of active devices and stacking layers in the core circuit of the voltage-controlled oscillator, which is beneficial to the optimization of the noise performance of the voltage-controlled oscillator and the realization of low voltage.

[0183] Meanwhile, the voltage-controlled oscillator provided in this application adjusts the substrate voltage of the two PMOS transistors in the PMOS cross-coupled pair and the two NMOS transistors in the NMOS cross-coupled pair through the bias circuit, thereby adjusting the threshold voltage of the two PMOS transistors in the PMOS cross-coupled pair and the two NMOS transistors in the NMOS cross-coupled pair, and thus determining the current of the core circuit, so that the core circuit of the voltage-controlled oscillator can operate under low voltage and low power consumption.

[0184] Furthermore, in the voltage-controlled oscillator provided in this application embodiment, the substrate voltages of the two PMOS transistors in the PMOS cross-coupled pair and the two NMOS transistors in the NMOS cross-coupled pair in the core circuit can be determined by the bias circuit. This allows the voltages at each terminal of the two PMOS transistors in the PMOS cross-coupled pair and the two NMOS transistors in the NMOS cross-coupled pair in the core circuit to be determined, thereby reducing the variation of the current in the core circuit and the transconductance of the MOS transistors with environmental factors such as temperature, which is beneficial to improving the robustness of the voltage-controlled oscillator core circuit.

[0185] Furthermore, the bias circuit employs a first feedback loop composed of a first operational amplifier and a PMOS transistor, and a second feedback loop composed of a second operational amplifier and an NMOS transistor, to ensure the stability of the substrate voltages of the two PMOS transistors in the PMOS cross-coupled pair and the two NMOS transistors in the NMOS cross-coupled pair in the core circuit. Moreover, the terminal voltages of the two PMOS transistors in the PMOS cross-coupled pair and the two NMOS transistors in the NMOS cross-coupled pair in the core circuit are also determined through matching technology, so that the current of the core circuit is also determined through this matching technology, thereby improving the robustness of the voltage-controlled oscillator core circuit.

[0186] Furthermore, a second harmonic cancellation circuit consisting of an inductor and a capacitor connected in series is introduced into the core circuit to eliminate the second harmonic of the first resonant signal and the second resonant signal generated by the LC resonant circuit, thereby further optimizing the noise performance of the voltage-controlled oscillator.

[0187] Finally, the buffer stage circuit employs a common-source amplifier structure with a current mirror as the load to convert the differential signal output from the core circuit into a single-ended output signal. Furthermore, the buffer stage circuit also isolates the external load, reducing the probability of changes in the core circuit due to variations in the external load environment and ensuring the stability of the voltage-controlled oscillator's output signal oscillation frequency.

[0188] Specifically, with the power supply voltage VDD=0.8V, the reference voltage Vref=0.4V, the bias circuit I=20μA, and the tuning voltage V... tune =0.2V-0.6V, the frequency band control word S VCO Taking the change from 00000 to 11111 as an example, we get Figure 12 The voltage-controlled oscillator provided in the embodiment of this application, as shown, outputs an oscillation frequency that varies with the tuning voltage V under each frequency band control word. tune A schematic diagram showing the simulation results changing with the changes. From... Figure 12 It can be seen that the frequency range of the output signal of the voltage-controlled oscillator is between 23.1 GHz and 25.9 GHz, and there is partial frequency overlap between the output signals of the voltage-controlled oscillator between adjacent frequency band control words, indicating that the tuning voltage V tune The frequency of the output signal of the voltage-controlled oscillator can be continuously adjusted.

[0189] Table 1 compares the simulation results of the current and transconductance of the core circuit in the traditional voltage-controlled oscillator and the voltage-controlled oscillator provided in the embodiments of this application as a function of temperature. The temperature range of the simulation is from 0℃ to 90℃. As can be seen from Table 1, by matching the bias circuit to determine the substrate voltage of the two PMOS transistors in the PMOS cross-coupled pair and the two NMOS transistors in the NMOS cross-coupled pair, the terminal voltages of the two PMOS transistors in the PMOS cross-coupled pair and the two NMOS transistors in the NMOS cross-coupled pair can be determined, thereby determining the current of the core circuit. This can effectively reduce the influence of temperature on the current and transconductance of the core circuit, which is beneficial to improving the robustness of the core circuit.

[0190] Table 1. Simulation results of core circuit current and MOSFET transconductance as a function of temperature in conventional voltage-controlled oscillators and the voltage-controlled oscillator of this application.

[0191]

[0192] Figure 13 and Figure 14 Furthermore, a comparative schematic diagram of simulation results of phase noise before and after applying the second harmonic cancellation circuit to the voltage-controlled oscillator provided in the embodiments of this application is given, showing the comparison. Figure 13 and Figure 14 It can be seen that before the second harmonic cancellation circuit was introduced into the voltage-controlled oscillator of this application, the phase noise at a frequency offset of 5MHz was -88.2446 dBc / Hz. After the second harmonic cancellation circuit was introduced into the core circuit of the voltage-controlled oscillator of this application, the phase noise at a frequency offset of 5MHz was -101.985dBc / Hz. It can be seen that by introducing the second harmonic cancellation circuit into the core circuit of the voltage-controlled oscillator of this application, the phase noise at a frequency offset of 5MHz was improved by 13.7dBc / Hz.

[0193] This application also provides an electronic device, including the voltage-controlled oscillator provided in any of the foregoing embodiments. Since the voltage-controlled oscillator has been described in detail in the foregoing embodiments, it will not be repeated here.

[0194] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0195] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A voltage-controlled oscillator, characterized in that, include: The bias circuit, core circuit, and buffer stage circuit are connected in sequence, wherein the core circuit includes a PMOS cross-coupled pair, an NMOS cross-coupled pair, and an LC resonant circuit connected in parallel. The bias circuit provides a first substrate voltage to the substrate terminals of the two PMOS transistors in the PMOS cross-coupled pair and a second substrate voltage to the substrate terminals of the two NMOS transistors in the NMOS cross-coupled pair. In the core circuit, the PMOS cross-coupled pair and the NMOS cross-coupled pair are used to provide negative resistance to compensate for the power loss of the LC resonant circuit. The LC resonant circuit is used to generate a first resonant signal and a second resonant signal with the same amplitude but opposite phase, which are output to the buffer stage circuit. The buffer stage circuit converts the first resonant signal and the second resonant signal into single-ended signals and then outputs them. The bias circuit includes: A first current mirror structure is composed of a third PMOS transistor and a fourth PMOS transistor, wherein the source terminals of the third PMOS transistor and the fourth PMOS transistor are both connected to the power supply voltage input terminal, the power supply voltage is input, the gate terminal of the third PMOS transistor is connected to its drain terminal, and the gate terminal of the fourth PMOS transistor is connected to the gate terminal of the third PMOS transistor. A first feedback loop is formed by a fifth PMOS transistor and a first operational amplifier, wherein the source terminal of the fifth PMOS transistor is connected to the power supply voltage input terminal to receive the power supply voltage, the drain terminal of the fifth PMOS transistor is connected to the positive input terminal of the first operational amplifier, the gate terminal of the fifth PMOS transistor is connected to the reference voltage input terminal to receive the reference voltage, and the gate terminal of the fifth PMOS transistor is also connected to the negative input terminal of the first operational amplifier, and the substrate terminal of the fifth PMOS transistor is connected to the output terminal of the first operational amplifier. A second feedback loop is formed by a third NMOS transistor and a second operational amplifier. The source terminal of the third NMOS transistor is grounded, the drain terminal of the third NMOS transistor is connected to the drain terminal of the fourth PMOS transistor, and the drain terminal of the third NMOS transistor is also connected to the positive input terminal of the second operational amplifier. The gate terminal of the third NMOS transistor is connected to the reference voltage input terminal to input the reference voltage, and the gate terminal of the third NMOS transistor is also connected to the negative input terminal of the second operational amplifier. The substrate terminal of the third NMOS transistor is connected to the output terminal of the second operational amplifier. A second current mirror structure is composed of a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The drain of the fourth NMOS transistor is connected to the bias current input terminal, and a bias current is input. The gates of the fourth, fifth, and sixth NMOS transistors are all connected to the drain of the fourth NMOS transistor. The sources of the fourth, fifth, and sixth NMOS transistors are all grounded. The drain of the fifth NMOS transistor is connected to the drain of the third PMOS transistor, and the drain of the sixth NMOS transistor is connected to the drain of the fifth PMOS transistor. The substrate of the fifth PMOS transistor is connected to the first output terminal of the bias circuit to output the first substrate voltage, and the substrate of the third NMOS transistor is connected to the second output terminal of the bias circuit to output the second substrate voltage.

2. The voltage-controlled oscillator according to claim 1, characterized in that, The PMOS cross-coupled pair includes a first PMOS transistor and a second PMOS transistor, and the NMOS cross-coupled pair includes a first NMOS transistor and a second NMOS transistor; In the core circuit, the source terminals of the first PMOS transistor and the second PMOS transistor are both connected to the power supply voltage input terminal. The power supply voltage is input, the gate terminal of the first PMOS transistor is connected to the drain terminal of the second PMOS transistor, and the gate terminal of the second PMOS transistor is connected to the drain terminal of the first PMOS transistor. The source terminals of the first NMOS transistor and the second NMOS transistor are both grounded. The gate terminal of the first NMOS transistor is connected to the drain terminal of the second NMOS transistor, and the gate terminal of the second NMOS transistor is connected to the drain terminal of the first NMOS transistor. The drain terminals of the first PMOS transistor, the first NMOS transistor, and the first output terminal of the LC resonant circuit are all connected to the first node, and the drain terminals of the second PMOS transistor, the second NMOS transistor, and the second output terminal of the LC resonant circuit are all connected to the second node. The first node and the second node serve as two output terminals of the core circuit, respectively outputting the first resonant signal and the second resonant signal generated by the LC resonant circuit.

3. The voltage-controlled oscillator according to claim 1, characterized in that, The bias circuit further includes: A first low-pass filter consisting of a first resistor and a first capacitor, wherein the first end of the first resistor is connected to the substrate of the fifth PMOS transistor, and the second end is grounded through the first capacitor; A second low-pass filter is composed of a second resistor and a second capacitor, wherein the first end of the second resistor is connected to the substrate end of the third NMOS transistor, and the second end is grounded through the second capacitor; Wherein, the second end of the first resistor is the first output terminal of the bias circuit, and the second end of the second resistor is the second output terminal of the bias circuit.

4. The voltage-controlled oscillator according to claim 1, characterized in that, The first operational amplifier and the second operational amplifier are the same operational amplifier, and the operational amplifier includes: A third current mirror structure is composed of a sixth PMOS transistor and a seventh PMOS transistor. The source terminals of both the sixth and seventh PMOS transistors are connected to the power supply voltage input terminal. The drain terminal of the sixth PMOS transistor is grounded through a seventh NMOS transistor, and the gate terminal of the sixth PMOS transistor is connected to the gate terminal of the seventh PMOS transistor. The gate terminal of the seventh PMOS transistor is connected to its drain terminal, and the drain terminal of the seventh PMOS transistor is connected to a third node. The gate terminal of the seventh NMOS transistor (N7) is connected to its drain terminal. A fourth current mirror structure is composed of an eighth PMOS transistor and a ninth PMOS transistor. The source terminals of both the eighth and ninth PMOS transistors are connected to the power supply voltage input terminal. The drain terminal of the ninth PMOS transistor is grounded through an eighth NMOS transistor, and its gate terminal is connected to the gate terminal of the eighth PMOS transistor. The gate terminal of the eighth PMOS transistor is connected to its drain terminal, and its drain terminal is connected to a fourth node. The gate terminal of the eighth NMOS transistor is connected to the gate terminal of the seventh NMOS transistor. A cross-coupled tenth PMOS transistor and an eleventh PMOS transistor, the source terminals of the tenth PMOS transistor and the eleventh PMOS transistor are both connected to the power supply voltage input terminal, the gate terminal of the tenth PMOS transistor is connected to the drain terminal of the eleventh PMOS transistor, and the drain terminal of the tenth PMOS transistor is connected to the third node; the gate terminal of the eleventh PMOS transistor is connected to the drain terminal of the tenth PMOS transistor, and the drain terminal of the eleventh PMOS transistor is connected to the fourth node. The ninth NMOS transistor has its drain connected to the third node, its gate connected to the positive input terminal of the operational amplifier, and its source connected to the fifth node. The tenth NMOS transistor has its drain connected to the fourth node, its gate connected to the negative input of the operational amplifier, and its source connected to the fifth node. A fifth current mirror structure is composed of an eleventh NMOS transistor and a twelfth NMOS transistor. The source terminals of the eleventh and twelfth NMOS transistors are both grounded. The drain terminal of the eleventh NMOS transistor is connected to the bias current input terminal to receive the bias current. The gate terminal of the eleventh NMOS transistor is connected to its drain terminal. The gate terminal of the twelfth NMOS transistor is connected to the gate terminal of the eleventh NMOS transistor, and the drain terminal of the twelfth NMOS transistor is connected to the fifth node. The drain terminal of the ninth PMOS transistor is the output terminal of the operational amplifier.

5. The voltage-controlled oscillator according to claim 2, characterized in that, The core circuit also includes a second harmonic cancellation circuit, which comprises: A first inductor and a third capacitor are connected in series, with the first end of the first inductor connected to the first node and the second end of the first inductor grounded through the third capacitor. A second inductor and a fourth capacitor are connected in series, with the first end of the second inductor connected to the second node and the second end of the second inductor grounded through the fourth capacitor. The resonant frequency of the first inductor and the third capacitor connected in series is the second harmonic frequency of the first resonant signal, and the resonant frequency of the second inductor and the fourth capacitor connected in series is the second harmonic frequency of the second resonant signal.

6. The voltage-controlled oscillator according to claim 2, characterized in that, The LC resonant circuit includes a third inductor, a switched capacitor array, and a variable capacitor branch connected in parallel; wherein... The first end of the third inductor is connected to the first node, and the second end is connected to the second node; The first end of the switched capacitor array is connected to the first node, the second end is connected to the second node, and the control terminal inputs a frequency band control word. The switched capacitor array provides capacitors of different sizes based on the frequency band control word. The first end of the variable capacitor branch is connected to the first node, the second end is connected to the second node, and the control terminal is input with a tuning voltage. The variable capacitor branch provides capacitors of different sizes based on the tuning voltage.

7. The voltage-controlled oscillator according to claim 6, characterized in that, The variable capacitor branch includes: a fifth capacitor, a first varactor, a second varactor, and a sixth capacitor connected in series. Wherein, the end of the fifth capacitor that is away from the first varactor tube is the first end of the variable capacitor branch and is connected to the first node; The end of the sixth capacitor that is away from the second varactor tube is the second end of the variable capacitor branch and is connected to the second node; The common terminal of the fifth capacitor and the first varactor is the sixth node. The sixth node is connected to the power supply voltage input terminal through the third resistor, and the sixth node is also grounded through the fourth resistor. The common terminal of the sixth capacitor and the second varactor is the seventh node. The seventh node is connected to the power supply voltage input terminal through the fifth resistor, and the seventh node is also grounded through the sixth resistor. The common terminal of the first varactor and the second varactor is the control terminal of the variable capacitor branch, and the tuning voltage is input therein.

8. The voltage-controlled oscillator according to claim 6, characterized in that, The switched capacitor array includes N switched capacitor branches connected in parallel, where N is a positive integer greater than 1. Each switched capacitor branch includes a control switching circuit and a weight capacitor. The frequency band control word input to the control terminal of the switched capacitor array is N bits, and each frequency band control word controls the closing and closing of the control switch circuit in one of the switched capacitor branches; As the number of bits in the frequency band control word increases, the capacitance value of the weight capacitor in the switched capacitor branch controlled by the frequency band control word becomes larger.

9. The voltage-controlled oscillator according to claim 8, characterized in that, The control switch circuit includes: a thirteenth NMOS transistor, a fourteenth NMOS transistor, and a fifteenth NMOS transistor; The gate terminal of the thirteenth NMOS transistor is input with a one-bit frequency band control word, the first terminal is grounded through the fourteenth NMOS transistor, and the second terminal is grounded through the fifteenth NMOS transistor. The gate terminal of the fourteenth NMOS transistor is connected to the gate terminal of the fifteenth NMOS transistor. The common terminal of the gate terminals of the fourteenth NMOS transistor and the fifteenth NMOS transistor is also input with a one-bit frequency band control word. The frequency band control word input to the common terminal of the gate terminals of the fourteenth NMOS transistor and the fifteenth NMOS transistor is the same one-bit frequency band control word as the frequency band control word input to the gate terminal of the thirteenth NMOS transistor. The source and drain terminals of the thirteenth NMOS transistor are the two ends of the control switch circuit, respectively.

10. The voltage-controlled oscillator according to claim 1, characterized in that, The buffer stage circuit includes: A sixth current mirror structure is composed of a twelfth PMOS transistor and a thirteenth PMOS transistor, wherein the source terminals of the twelfth PMOS transistor and the thirteenth PMOS transistor are both connected to the power supply voltage input terminal, and the gate terminal of the twelfth PMOS transistor is connected to its drain terminal, and the gate terminal of the thirteenth PMOS transistor is connected to the gate terminal of the twelfth PMOS transistor. The sixteenth NMOS transistor has its drain connected to the drain of the twelfth PMOS transistor, its gate is the first input terminal of the buffer stage circuit, which receives the first resonant signal, and its source is connected to the eighth node. The seventeenth NMOS transistor has its drain connected to the drain of the thirteenth PMOS transistor, its gate is the second input terminal of the buffer stage circuit, which receives the second resonant signal, and its source is connected to the eighth node. A seventh current mirror structure is composed of an eighteenth NMOS transistor and a nineteenth NMOS transistor. The source terminals of the eighteenth and nineteenth NMOS transistors are both grounded. The drain terminal of the eighteenth NMOS transistor is connected to the bias current input terminal to receive the bias current. The gate terminal of the eighteenth NMOS transistor is connected to its drain terminal. The drain terminal of the nineteenth NMOS transistor is connected to the eighth node, and the gate terminal of the nineteenth NMOS transistor is connected to the gate terminal of the eighteenth NMOS transistor. The drain terminal of the thirteenth PMOS transistor is the output terminal of the buffer stage circuit.

11. An electronic device, characterized in that, Includes the voltage-controlled oscillator according to any one of claims 1-10.

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