A low power frequency detection circuit for assisting in the trimming of an oscillator

Abstract

The application provides a low-power frequency detection circuit for auxiliary oscillator trimming, which comprises a frequency-voltage conversion circuit and a comparator circuit. The frequency-voltage conversion circuit comprises a logic circuit, an inverter circuit, a switched-capacitor network, a reference current source and a replication circuit. The logic circuit receives a clock signal and a frequency detection enable signal, shapes the clock signal into a same-frequency square wave only when the enable signal is valid, and cuts off the signal path otherwise. The inverter circuit inverts the square wave into a complementary square wave. The replication circuit replicates the current of the reference current source to the switched-capacitor network and a fixed resistor, and forms a first voltage at the fixed resistor. The switched-capacitor network switches the charging and discharging of the capacitor under the triggering of the two complementary square waves, and forms a second voltage with an equivalent resistor. The comparator circuit receives a comparison enable signal and the two voltages, compares the two voltages only when the enable signal is valid, and cuts off the internal current path otherwise. The application has the advantages of simple structure, low power consumption and flexible control, and is suitable for wafer-level trimming scenarios with low power consumption and intermittent operation.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing and tuning technology, and in particular to a low-power frequency detection circuit for auxiliary oscillator tuning. Background Technology

[0002] In semiconductor manufacturing, due to the inherent limitations of processes such as photolithography and etching, the actual physical dimensions and electrical parameters (such as threshold voltage, channel length, interconnect resistance, etc.) of components such as transistors, resistors, and capacitors inside the chip will inevitably deviate from the design values ​​(up to ±20%). This process variation is particularly significant at the nanometer level and is a key factor that causes circuit performance (such as speed, power consumption, frequency) to deviate from the design target and reduce the yield.

[0003] To compensate for the impact of process variations on circuit performance and improve chip yield and performance consistency, the industry widely adopts wafer-level trimming technology. This technology involves powering the bare chip with a probe station before wafer dicing and packaging, and precisely measuring its key performance parameters (such as the input offset voltage of operational amplifiers and the output frequency of oscillators). Based on the measurement results, adjustable components inside the chip (such as fuses, thin-film resistor arrays, or capacitor arrays) are adjusted through methods such as laser fusing and electrical programming to calibrate the circuit performance to the target range, thereby reducing manufacturing process errors. For example, for high-precision operational amplifiers, mismatch can be compensated by adjusting the resistor network near the input pair transistors, thus significantly reducing the input offset voltage.

[0004] Relaxation oscillators, commonly used signal sources in low-power analog systems, have their output frequency determined by the RC time constants of on-chip resistors and capacitors. This frequency is extremely sensitive to process variations; therefore, frequency tuning is essential to ensure system clock accuracy. The core of the tuning process is a closed-loop judgment: the system needs to quickly and accurately determine whether the oscillator's current output frequency is higher or lower than a preset target threshold, and based on the judgment result, decide whether to increase or decrease the tuning code value (e.g., close or open more tuning switches) until the frequency reaches the target.

[0005] However, as Figure 1As shown, a single wafer contains tens of thousands of bare chips, and the process of testing and adjusting each one is extremely time-consuming. Therefore, the frequency detection circuit, as the "eye" of the adjustment system, must minimize power consumption while ensuring accuracy. An ideal detection circuit should be able to use the characteristics of the input signal (oscillator clock) itself to determine the frequency level and support on-demand start / stop. When no detection is needed, the circuit should be completely shut down, entering a zero static power state, thereby significantly reducing the energy consumption of the entire adjustment system and improving the overall efficiency of the adjustment process.

[0006] Existing frequency detection circuits mainly include counting methods, phase-locked loop (PLL) methods, resonant methods, and detection methods based on switched-capacitor-resistor networks. Among these, the counting method relies on a precise reference clock, typically calculated by a microcontroller or FPGA-based digital system counting the number of input pulses within a fixed time window. While simple in principle, this method requires a high-precision clock source and incurs significant hardware overhead. The PLL method achieves frequency comparison through a feedback loop, offering high detection accuracy, but its complex structure, difficult debugging, and high power consumption make it challenging. The resonant method detects frequencies based on the resonant characteristics of inductors and capacitors; although it can achieve judgment within a certain frequency range, its output characteristics are non-monotonic, hindering subsequent circuit processing. Schemes based on switched-capacitor-resistor networks can reduce clock dependence to some extent, but because the frequency-dependent network and comparator must remain continuously conducting during detection, flexible start-stop control is difficult, resulting in high static power consumption even during idle periods. Overall, existing frequency detection schemes generally suffer from complex structures, high power consumption, and inflexible control, failing to achieve intermittent sampling and comparison based on system energy states. This makes them unsuitable for low-power, intermittent wafer-level trimming scenarios. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides a low-power frequency detection circuit for auxiliary oscillator tuning. It solves the problems of existing frequency detection schemes having complex structures, high power consumption, and inflexible control, which make it difficult to meet the requirements of wafer-level tuning scenarios with low power consumption and intermittent operation.

[0008] According to an embodiment of the present invention, a low-power frequency detection circuit for assisting oscillator tuning includes a frequency-to-voltage conversion circuit and a comparator circuit. The frequency-to-voltage conversion circuit includes a logic circuit, an inverting circuit, a switched capacitor network, a reference current source, and a replication circuit, wherein:

[0009] The logic circuit receives the clock signal to be tested and the frequency detection enable signal. It only shapes the clock signal to be tested into a square wave signal of the same frequency when the frequency detection enable signal is valid. Otherwise, it cuts off the signal path and outputs a fixed level.

[0010] The inverting circuit inverts the received square wave signal of the same frequency after being shaped by the logic circuit into another square wave signal of the same frequency that is complementary to it and outputs it.

[0011] The replication circuit replicates the current of the reference current source and flows through the switched capacitor network and the fixed resistor respectively, forming a first voltage at the fixed resistor; the switched capacitor network performs capacitor charging and discharging switching under the drive of two complementary square wave signals output by the received logic circuit and the inverting circuit, forming a second voltage with equivalent resistance under the current of the reference current source.

[0012] The comparator circuit receives a comparison enable signal, a first voltage, and a second voltage. It compares the first voltage and the second voltage only when the comparison enable signal is valid; otherwise, it cuts off the internal current path and outputs a fixed level.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] The input clock signal under test is directly converted into two sets of complementary square wave signals with the same frequency to drive the switched capacitor network through the logic circuit and the inverting circuit. The switched capacitor network switches between charging and discharging under the drive of the two square wave signals. This process is equivalent to a frequency-controlled resistor. The current of the reference current source is then copied through the replication circuit and flows through the equivalent resistor and the fixed resistor respectively. This generates voltages across the equivalent resistor and the fixed resistor respectively. By comparing the voltage between the equivalent resistor and the fixed resistor, the frequency of the input signal can be determined. Compared with traditional frequency detection schemes, this method has a simpler structure and is easier to implement and integrate in standard CMOS processes.

[0015] By employing a two-stage enable control system consisting of a frequency detection enable signal and a comparison enable signal, the subsequent circuitry can be directly shut down and a fixed level output can be generated when the frequency detection enable signal is invalid, thereby eliminating most of the static and dynamic power consumption. When the comparison enable signal is invalid, the comparator circuit will cut off the current path and output a fixed level, achieving module-level power management and further saving energy. Compared with the traditional continuously conducting frequency detection scheme, this system enables on-demand activation and instantaneous operation, adapting to the intermittent "test-adjust-retest" workflow of wafer-level trimming scenarios, greatly reducing power consumption. At the same time, since the two enable signals can be controlled independently, it provides flexibility in timing configuration, allowing the circuit to flexibly adapt to different detection requirements. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the oscillator adjustment process.

[0017] Figure 2This is a control principle diagram of a low-power frequency detection circuit for auxiliary oscillator tuning according to an embodiment of the present invention.

[0018] Figure 3 This is a detailed circuit diagram of the frequency-to-voltage conversion circuit according to an embodiment of the present invention.

[0019] Figure 4 This is a detailed circuit diagram of the comparator circuit according to an embodiment of the present invention.

[0020] In the above figures: 1. Frequency-to-voltage conversion circuit; 2. Comparator circuit; 11. Switched capacitor network; 12. AND gate logic circuit; 13. Inverting circuit; 14. Reference current source; 15. Replication circuit; 21. Differential input stage; 22. Positive feedback circuit; 23. Latch output stage; 24. Enable control circuit. Detailed Implementation

[0021] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0022] Example 1

[0023] like Figure 2 As shown, this embodiment of the invention proposes a low-power frequency detection circuit for auxiliary oscillator tuning, including a frequency-to-voltage conversion circuit 1 and a comparator circuit 2. The frequency-to-voltage conversion circuit 1 includes a switched capacitor network 11, a logic circuit, an inverting circuit 13, a reference current source 14, and a replication circuit 15, wherein:

[0024] The logic circuit receives the clock signal to be tested and the frequency detection enable signal. It only shapes the clock signal to be tested into a square wave signal of the same frequency when the frequency detection enable signal is valid. Otherwise, it cuts off the signal path and outputs a fixed level.

[0025] The inverting circuit 13 inverts the received square wave signal of the same frequency after it has been shaped by the logic circuit into another square wave signal of the same frequency that is complementary to it and outputs it.

[0026] The replication circuit 15 replicates the current of the reference current source 14 and flows through the switched capacitor network 11 and the fixed resistor respectively, forming a first voltage at the fixed resistor; the switched capacitor network 11 performs capacitor charging and discharging switching under the drive of the two complementary square wave signals output by the received logic circuit and the inverter circuit 13, forming a second voltage with equivalent resistance under the current of the reference current source 14.

[0027] The comparator circuit 2 receives a comparison enable signal, a first voltage, and a second voltage. It compares the first voltage and the second voltage only when the comparison enable signal is valid; otherwise, it cuts off the internal current path and outputs a fixed level.

[0028] In this embodiment, the input clock signal under test is directly converted into two sets of complementary square wave signals with the same frequency to drive the switched capacitor network 11 through the logic circuit and the inverting circuit 13. This allows the switched capacitor network 11 to switch between charging and discharging under the drive of the two square wave signals. This process is equivalent to a frequency-controlled resistor. The current from the reference current source 14 is then replicated by the replication circuit 15 and flows through the equivalent resistor and the fixed resistor respectively, thereby generating voltages across the equivalent resistor and the fixed resistor. By comparing the voltage relationship between the equivalent resistor and the fixed resistor, the frequency of the input signal can be determined. Compared with traditional frequency detection schemes, this method has a simpler structure and is easier to implement in standard CMOS processes. The system integrates two-stage enable control via a frequency detection enable signal and a comparison enable signal. This allows for direct shutdown of the subsequent circuitry and output of a fixed level when the frequency detection enable signal is invalid, thereby eliminating most of the static and dynamic power consumption. When the comparison enable signal is invalid, the comparator circuit 2 internally cuts off the current path and outputs a fixed level, achieving module-level power management and further saving energy. Compared with traditional continuously conducting frequency detection schemes, this system enables on-demand activation and instantaneous operation, adapting to the intermittent "test-adjust-retest" workflow of wafer-level trimming scenarios, greatly reducing power consumption. At the same time, since the two enable signals can be controlled independently, it provides flexibility in timing configuration, allowing the circuit to flexibly adapt to different detection requirements.

[0029] Example 2

[0030] like Figure 3 As shown, based on Embodiment 1, the logic circuit is an AND gate logic circuit 12. When the frequency detection enable signal is high, the signal path of the AND gate logic circuit 12 is turned on, and the clock signal is shaped into a square wave signal of the same frequency for output. When the frequency detection enable signal is low, the signal path of the AND gate logic circuit 12 is turned off, and the output remains low.

[0031] Preferably, the AND gate logic circuit 12 includes PMOS transistors MP1, MP2, MP3 and NMOS transistors MN1, MN2 and MN3, wherein:

[0032] The clock signal to be tested is connected to the gates of the PMOS transistor MP1 and the NMOS transistor MN2, and the frequency detection enable signal is connected to the gates of the PMOS transistor MP2 and the NMOS transistor MN1.

[0033] The gates of the PMOS transistor MP3 and the NMOS transistor MN3 are interconnected; the drains of the PMOS transistor MP3 and the NMOS transistor MN3 are interconnected and output to the inverting circuit 13 and the switched capacitor network 11, respectively.

[0034] The sources of PMOS transistors MP1, MP2, and MP3 are connected together, and the drains of PMOS transistors MP1 and MP2 are both connected to the gate of PMOS transistor MP3.

[0035] The source of NMOS transistor MN1 is interconnected with the drain of NMOS transistor MN2, the drain of NMOS transistor MN1 is connected to the gate of PMOS transistor MP3, and the source of NMOS transistor MN2 is connected to the source of NMOS transistor MN3.

[0036] Specifically, when the frequency detection enable signal Func_EN is set to a high level, the clock signal Vin under test enters the AND gate logic circuit, making the outputs of MP3 and MN3 the same frequency square wave after the clock signal Vin under test is shaped; when the frequency detection enable signal Func_EN is set to a low level, the outputs of MP3 and MN3 remain at a low level.

[0037] Since the power consumption of the AND gate logic circuit is not high when the input is high or low, but the power consumption is relatively high when the input switches from high to low or from low to high, it can be seen that the power consumption of the AND gate logic circuit is the greatest during the state switching process. Therefore, when the frequency detection enable signal Func_EN is low (i.e., no detection is required), keeping the output of the AND gate logic circuit low can avoid repeated state switching of the AND gate logic circuit, thereby effectively reducing power consumption.

[0038] Furthermore, PMOS transistor MP4 and NMOS transistor MN4 form an inverting circuit 13 to invert the same-frequency square waves output by MP3 and MN3 (i.e., if MP3 and MN3 output a high level, then MP4 and MN4 output a low level; conversely, if MP3 and MN3 output a low level, then MP4 and MN4 output a high level), and output another same-frequency square wave signal that is complementary to the same-frequency square waves output by MP3 and MN3, so as to control the subsequent switching capacitor network 11 to turn on and off.

[0039] Furthermore, the switched capacitor network 11 includes a switching branch, one end of which is connected to the output terminal of the replication circuit 15, and the other end of which is grounded.

[0040] The switching branch includes two switching units connected in series, and the connection terminals of the two switching units are grounded through a capacitor; each switching unit includes an NMOS transistor and a PMOS transistor connected in parallel, the sources of the NMOS transistor and the PMOS transistor are interconnected, and the drains of the NMOS transistor and the PMOS transistor are interconnected.

[0041] The two switching units are controlled to conduct alternately by two complementary square wave signals of the same frequency, driving the capacitor to charge or discharge periodically within two complementary clock phases, so as to generate an equivalent resistance whose resistance value is inversely proportional to the capacitance value of the capacitor and the clock frequency.

[0042] Specifically, NMOS transistors MN5 and MP5, and NMOS transistors MN6 and MP6 each constitute two switching units. When the switching unit composed of MN5 and MP5 is off, and the switching unit composed of MN6 and MP6 is on, the charge on capacitor C_total is approximately:

[0043] (1)

[0044] When the switching unit consisting of MN5 and MP5 is turned on, and the switching unit consisting of MN6 and MP6 is turned off, the charge on capacitor C_total is approximately:

[0045] (2)

[0046] Therefore, the average current is:

[0047] (3)

[0048] Among them, T osc f represents the period of the oscillator. osc This represents the frequency of the oscillator. Transforming (3) yields:

[0049] (4)

[0050] As can be seen from (4), when the capacitance C_total is determined, the switched capacitor circuit can be equivalent to a circuit controlled by frequency f. osc The controlled resistor, this equivalent resistance is:

[0051] (5)

[0052] Figure 3 The value of the resistor R is:

[0053] (6)

[0054] in The threshold frequency is represented by (6). Once C_total is determined, the value of the resistance R can be calculated using (6).

[0055] When the oscillator frequency is higher than the threshold frequency, the equivalent resistance R eq The value is less than the fixed resistor R; the opposite is true when the oscillator frequency is below the threshold frequency.

[0056] Preferably, the equivalent resistance R eq A first filter capacitor CF1 is connected in parallel at the fixed resistor R, and a second filter capacitor CF2 is connected in parallel at the fixed resistor R. The first filter capacitor CF1 and the second filter capacitor CF2 respectively filter the equivalent resistance R. eq The DC voltage is filtered by the fixed resistor R to make it more stable.

[0057] Furthermore, in order to compare two resistors (equivalent resistance R) eq The reference current source 14 is designed to generate a reference current, and the reference current is copied to the two resistors through the replication circuit 15. When the same current flows through the two resistors, different voltages will be formed at the two resistors. The frequency can be determined by comparing the magnitudes of the two voltages.

[0058] Specifically, PMOS transistors MP7 and MP8 constitute the replication circuit 15, which replicates the reference current generated by the reference current source 14 to the equivalent resistance R. eq And at the fixed resistor R.

[0059] Preferably, the reference current source 14 includes a reference resistor, NMOS transistors MN7 and MN8, and PMOS transistors MP9 and MP10, wherein:

[0060] The source of NMOS transistor MN7 is grounded, the source of NMOS transistor MN8 is grounded through the reference resistor, the gates of NMOS transistors MN7 and MN8 are interconnected, and the gate and drain of NMOS transistor MN7 are interconnected.

[0061] The PMOS transistors MP9 and MP10 form a current mirror. The sources of the PMOS transistors MP9 and MP10 receive external power input. The gates of the PMOS transistors MP9 and MP10 are interconnected, and the gate and drain of the PMOS transistor MP10 are interconnected. The drains of the PMOS transistors MP9 and MP10 are connected to the drains of the NMOS transistors MN7 and MN8, respectively.

[0062] More preferably, the NMOS transistors MN7 and MN8 and the PMOS transistors MP9 and MP10 all operate in the subthreshold region, the PMOS transistors MP9 and MP10 have the same width-to-length ratio, and the NMOS transistor MN8 has a width-to-length ratio twice that of the NMOS transistor MN7.

[0063] Specifically, the voltage-current relationship of an NMOS transistor in the subthreshold region is as follows:

[0064] (7)

[0065] Where ξ is the non-ideal factor. It is thermal voltage, in Figure 3 According to Kirchhoff's voltage law, we can obtain:

[0066] (8)

[0067] Substituting (7) into (8) yields:

[0068] (9)

[0069] Therefore, the reference current provided by the reference current source 14 is:

[0070] (10)

[0071] In this embodiment, when detection is not required, the frequency detection enable signal Func_EN is set to a low level, the output of the frequency-to-voltage conversion circuit 1 remains low, cutting off the signal path and directly shutting off the subsequent circuits (the switched capacitor network 11 and the comparator circuit 2), eliminating most of the static and dynamic power consumption. When detection is required, the frequency detection enable signal Func_EN is set to a high level, the clock signal Vin to be tested enters the AND gate logic circuit 12, outputting a set of square waves of the same frequency after the clock signal Vin to be tested is shaped, and another set of square waves of the same frequency complementary to it is output through the inverting circuit 13. A square wave drives the two switching branches of the switched capacitor network 11 to conduct alternately, causing the capacitors of the switched capacitor network 11 to charge or discharge periodically within two complementary clock phases. This generates an equivalent resistance whose resistance is inversely proportional to the capacitance and the clock frequency. A reference current is then generated through the reference current source 14, and the reference current is replicated to the equivalent resistance and the fixed resistance through the replication circuit 15. When the same current flows through the two resistors, different voltages are generated across them. By comparing the voltage relationship between the equivalent resistance and the fixed resistance, the frequency of the input signal is determined. Compared with traditional continuously conducting frequency detection schemes, this invention achieves on-demand start / stop while maintaining a simple structure, effectively reducing power consumption during non-detection phases.

[0072] Example 3

[0073] like Figure 4 As shown, based on Embodiment 1, the comparator circuit 2 includes a differential input stage 21, a positive feedback circuit 22, a latch output stage 23, and an enable control circuit 24, wherein:

[0074] The differential input stage 21 includes two input terminals and two output terminals. The two input terminals of the differential input stage 21 receive a first voltage and a second voltage, respectively, and the two output terminals of the differential input stage 21 output an initial voltage difference.

[0075] The positive feedback circuit 22 includes two input terminals and two output terminals. The two input terminals of the positive feedback circuit 22 are respectively connected to the two output terminals of the differential input stage 21, and the two output terminals of the positive feedback circuit 22 are respectively connected to the two input terminals of the latch output stage 23, so as to feed back the voltage difference output by the differential input stage 21 to the latch output stage 23.

[0076] The latch output stage 23 receives and latches the voltage difference fed back by the positive feedback circuit 22, and outputs the final comparison result;

[0077] The enable control circuit 24 receives a comparison enable signal and provides bias current to the differential input stage 21 only when the comparison enable signal is valid; otherwise, it cuts off the bias current of the differential input stage 21.

[0078] Specifically, NMOS transistors MN9 and MN10 form a differential input stage 21 with a capacitive load, where the capacitor is a parasitic capacitance formed by nodes P and Q (the voltages of nodes P and Q are initially at the power supply voltage VDD), which receives differential voltages from the equivalent resistance and the fixed resistance, respectively, and transmits them to the positive feedback circuit 22.

[0079] Preferably, the positive feedback circuit 22 includes a first inverter and a second inverter. The first inverter includes a PMOS transistor MP11 and an NMOS transistor MN11, and the second inverter includes a PMOS transistor MP12 and an NMOS transistor MN12. The inputs and outputs of the NMOS transistors MN11 and MN12 are interconnected, and the inputs and outputs of the PMOS transistors MP11 and MP12 are interconnected.

[0080] Specifically, after the comparison begins, the voltages of both nodes P and Q gradually decrease. If the gate voltage of MN9 is higher than the gate voltage of MN10, the discharge rate of point P is faster than that of point Q, and the voltage decreases more rapidly. When the voltage of node P drops to approximately VDD – Vth (the threshold voltage of MN11), MN11 begins to conduct and continues to discharge (the situation for nodes Q and MN12 is similar to that for nodes P and MN11). Since MN11 conducts earlier than MN12, the voltage of node X will decrease before that of node Y, thus triggering the conduction of MP12. At this time, node X discharges earlier than node Y and charges node Y after MP12 conducts. Conversely, if the gate voltage of MN9 is lower than that of MN10, the discharge rate of point Q is faster than that of point P, causing MN12 to conduct earlier than MN11. The voltage of node Y will decrease before that of node X, thus triggering the conduction of MP11. At this time, node Y discharges earlier than node X and charges node X after MP11 conducts. Through the above process, the voltage difference between nodes P and Q can be amplified, and two completely opposite logic states can be output at nodes X and Y (such as node X being low and node Y being high, or node X being high and node Y being low), in order to accelerate the comparison process of the voltage difference.

[0081] Preferably, the latch output stage 23 includes a third inverter, a fourth inverter, and a latch, wherein:

[0082] The input terminals of the third inverter and the fourth inverter are respectively connected to the output terminals of the first inverter and the second inverter, and the third inverter and the fourth inverter are used to invert the amplified differential input signal respectively;

[0083] The two input terminals of the latch are respectively connected to the output terminals of the third inverter and the fourth inverter. The latch is used to capture and latch the final comparison result transmitted by the third inverter and the fourth inverter within the effective window of the comparison enable signal. After latching, its output terminal is stably maintained at a fixed level state so as to determine the level state of the oscillator frequency relative to the set threshold frequency.

[0084] Specifically, PMOS transistors MP13 and MN13, and PMOS transistors MP16 and MN16 respectively constitute the third inverter and the fourth inverter. The input terminal of the third inverter is connected to node X, and the input terminal of the fourth inverter is connected to node Y, so that the third inverter and the fourth inverter invert the differential signals at nodes X and Y respectively. NMOS transistors MN14 and MN15, and PMOS transistors MP14 and MP15 constitute the latch. After the third inverter and the fourth inverter invert the differential signals at nodes X and Y respectively, the latch captures and latches the final comparison result transmitted from the third inverter and the fourth inverter. After latching, its output terminal maintains a stable fixed level state to determine whether the oscillator frequency is high or low relative to the set threshold frequency, thus completing the comparison process.

[0085] Specifically: When the gate voltage of MN9 is higher than the gate voltage of MN10, node X eventually drops to a low level, while node Y rises to a high level. At this time, the third inverter composed of MP13 and MN13 outputs a high level, turning on MN14. The drain voltage of MN14 gradually decreases and charges the output Vop to VDD after MP15 turns on. At the same time, the fourth inverter composed of MP16 and MN16 outputs a low level, and there is no current in the branches of MP15 and MN15, thus keeping Vop at a high level (Von is at a low level at this time). Thus, the comparison of the two input voltages is completed. Conversely, when the gate voltage of MN9 is lower than the gate voltage of MN10, the Y node eventually drops to a low level, while the X node rises to a high level. At this time, the fourth inverter composed of MP16 and MN16 outputs a high level, turning on MN15. The drain voltage of MN15 gradually decreases and charges the output Von to VDD after MP14 turns on. At the same time, the third inverter composed of MP13 and MN13 outputs a low level, and there is no current in the MP14 and MN14 branches, thus keeping Von at a high level (at this time, Vop is at a low level). Thus, the comparison of the two input voltages is completed.

[0086] After the comparison is completed, for the differential input stage 21, MN11 and MN12 have cut off the current path between VDD and GND; for the third inverter composed of MP13 and MN13 and the fourth inverter composed of MP16 and MN16, the current flowing through them is almost zero when the input is held high or low; for the latch composed of MN14, MN15, MP14 and MP15, its static current is also negligible after the comparison is completed. Therefore, after the comparison is completed, the static power consumption of the comparator circuit 2 is almost zero, and the system power consumption is extremely low.

[0087] Preferably, the enable control circuit 24 includes a fifth enable switch, which is connected in series in the tail current source path of the differential input stage 21 and is controlled by the comparison enable signal.

[0088] When the comparison enable signal is low, the fifth enable switch is turned off to cut off the bias current of the differential input stage 21; when the comparison enable signal is high, the fifth enable switch is turned on to provide bias current to the differential input stage 21.

[0089] Specifically, the input terminal of the fifth enable switch S5 receives the comparison enable signal Com_EN. When the comparison enable signal Com_EN is high, the fifth enable switch S5 is turned on, providing bias current to the differential input stage 21 (MN9 and MN10). When the comparison enable signal Com_EN is low, the fifth enable switch S5 is turned off, cutting off the current of the differential input stage 21. At the same time, the low level Com_EN will pull up the voltage of the X and Y nodes, causing the third inverter composed of MP13 and MN13 and the fourth inverter composed of MP16 and MN16 to output a low level, thereby shutting off the current path of MN14 and MN15. Thus, when Com_EN is low, the entire circuit is in a closed state, and its static power consumption is negligible, further reducing power consumption.

[0090] More preferably, the enable control circuit 24 further includes a first enable switch, a second enable switch, a third enable switch, and a fourth enable switch. The first enable switch, the second enable switch, the third enable switch, and the fourth enable switch are all controlled by a comparison enable signal. The first enable switch and the fourth enable switch are respectively connected to the two output terminals of the differential input stage 21, and the second enable switch and the third enable switch are respectively connected to the two output terminals of the positive feedback circuit 22.

[0091] Specifically, the first enable switch S1, the second enable switch S2, the third enable switch S3, and the fourth enable switch S4 are all controlled by the comparison enable signal Com_EN. The output terminals of the first enable switch S1, the second enable switch S2, the third enable switch S3, and the fourth enable switch S4 are respectively connected to nodes P, X, Y, and Q. When the comparison enable signal Com_EN is low, nodes P, Q, X, and Y are all charged to the power supply voltage VDD to clear the interference left by the previous comparison process.

[0092] In this embodiment, when it is not necessary to compare the voltages of the two resistors, the comparison enable signal Com_EN is set to low, the fifth enable switch S5 is turned off, cutting off the bias current of the differential input stage 21. Simultaneously, the voltages of the X and Y nodes are pulled high, causing both the third and fourth inverters to output low levels, thereby closing the current path of the latch and further reducing power consumption. When it is necessary to compare the voltages of the two resistors, the comparison enable signal Com_EN switches from low to high. At this time, the fifth enable switch S5 is turned on, and the first enable switch S1, the second enable switch S2, the third enable switch S3, and the fourth enable switch S4 are turned off. The differential input stage 21 receives differential input signals from the equivalent resistance and the fixed resistance. The positive feedback path formed by the first inverter and the second inverter accelerates the comparison process of the differential input signals. Then, the third inverter and the fourth inverter invert the differential signals at the X node and the Y node, respectively. After inversion, the latch captures and latches the final comparison result transmitted from the third inverter and the fourth inverter. After latching, the output of the latch will stably maintain a fixed level state to determine whether the oscillator frequency is high or low relative to the set threshold frequency, thus completing the comparison process.

[0093] Because the entire comparator circuit 2 adopts a dynamic comparison structure, compared with the traditional dynamic comparator driven by the clock cycle, the comparator circuit 2 is equipped with a comparison signal issued by the tuning control system according to the rhythm or step state of the tuning process. The comparison action is only started when frequency determination is required. After the comparison is completed, the comparator circuit 2 will immediately return to the static state. At this time, the static bias current is very low, thereby further reducing the overall power consumption. At the same time, since the comparison enable signal is provided by the tuning control system, different signal intervals can be set according to different application scenarios, thus providing greater flexibility for system design.

[0094] Finally, it should be noted that both the frequency-voltage conversion circuit 1 and the comparator circuit 2 of this invention are controlled by external circuits to start and stop. When the circuit is turned on again after being turned off for a long time, the frequency-voltage conversion circuit 1 should be started first, and then the comparator circuit 2 should be started.

[0095] The low-power frequency detection circuit of the present invention can be applied not only to oscillator tuning systems, but also to various low-power scenarios that require frequency threshold determination. For example, in a clock monitoring circuit, when the input signal frequency is lower than a set threshold, the system can automatically switch to a backup clock source to maintain normal system operation. In a sensor interface or control node, the level of the input signal frequency can reflect changes in external physical quantities (such as pressure, vibration, or temperature), and the detection results can be used to trigger different working modes.

[0096] Furthermore, this invention is particularly applicable to energy-constrained or self-sufficient systems, where the frequency detection function typically operates intermittently. The system only briefly activates the detection circuit at specific times or when an event triggers it, and immediately shuts down the relevant modules after determining the frequency, thereby significantly reducing average power consumption. For example, in battery-powered wireless sensor nodes, the system can periodically activate the frequency detection circuit of this invention to determine whether the sensor output exceeds a threshold.

[0097] This invention is implemented using CMOS technology. By employing this structure, the frequency detection circuit can be started and stopped on demand according to system control signals, briefly turning on during the detection phase and turning off during the idle phase. This design not only meets the requirements for frequency threshold determination but also significantly reduces power consumption, making it suitable for various low-power, low-cost electronic systems.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A low-power frequency detection circuit for auxiliary oscillator tuning, characterized in that: It includes a frequency-to-voltage conversion circuit and a comparator circuit. The frequency-to-voltage conversion circuit includes a logic circuit, an inverting circuit, a switched capacitor network, a reference current source, and a replication circuit, wherein: The logic circuit receives the clock signal to be tested and the frequency detection enable signal. It only shapes the clock signal to be tested into a square wave signal of the same frequency when the frequency detection enable signal is valid. Otherwise, it cuts off the signal path and outputs a fixed level. The inverting circuit inverts the received square wave signal of the same frequency after being shaped by the logic circuit into another square wave signal of the same frequency that is complementary to it and outputs it. The replication circuit replicates the current of the reference current source and flows through the switched capacitor network and the fixed resistor respectively, forming a first voltage at the fixed resistor; the switched capacitor network performs capacitor charging and discharging switching under the drive of two complementary square wave signals output by the received logic circuit and the inverting circuit, forming a second voltage with equivalent resistance under the current of the reference current source. The comparator circuit receives a comparison enable signal, a first voltage, and a second voltage. It compares the first voltage and the second voltage only when the comparison enable signal is valid; otherwise, it cuts off the internal current path and outputs a fixed level.

2. The low-power frequency detection circuit for auxiliary oscillator tuning as described in claim 1, characterized in that: The logic circuit is an AND gate logic circuit. When the frequency detection enable signal is set to a high level, the signal path of the AND gate logic circuit is turned on, and the clock signal is shaped into a square wave signal of the same frequency for output. When the frequency detection enable signal is set to a low level, the signal path of the AND gate logic circuit is turned off, and the output remains at a low level.

3. The low-power frequency detection circuit for auxiliary oscillator tuning as described in claim 2, characterized in that: The AND gate logic circuit includes PMOS transistors MP1, MP2, and MP3, and NMOS transistors MN1, MN2, and MN3, wherein: The clock signal to be tested is connected to the gates of the PMOS transistor MP1 and the NMOS transistor MN2, and the frequency detection enable signal is connected to the gates of the PMOS transistor MP2 and the NMOS transistor MN1. The gates of the PMOS transistor MP3 and the NMOS transistor MN3 are interconnected; the drains of the PMOS transistor MP3 and the NMOS transistor MN3 are interconnected and output to the inverting circuit and the switched capacitor network, respectively. The sources of PMOS transistors MP1, MP2, and MP3 are connected together, and the drains of PMOS transistors MP1 and MP2 are both connected to the gate of PMOS transistor MP3. The source of NMOS transistor MN1 is interconnected with the drain of NMOS transistor MN2, the drain of NMOS transistor MN1 is connected to the gate of PMOS transistor MP3, and the source of NMOS transistor MN2 is connected to the source of NMOS transistor MN3.

4. The low-power frequency detection circuit for auxiliary oscillator tuning as described in claim 1, characterized in that: The switched capacitor network includes a switching branch, one end of which is connected to the output terminal of the replication circuit, and the other end of which is grounded. The switching branch includes two switching units connected in series, and the connection terminals of the two switching units are grounded through a capacitor; each switching unit includes an NMOS transistor and a PMOS transistor connected in parallel, the sources of the NMOS transistor and the PMOS transistor are interconnected, and the drains of the NMOS transistor and the PMOS transistor are interconnected. The two switching units are controlled to conduct alternately by two complementary square wave signals of the same frequency, driving the capacitor to charge or discharge periodically within two complementary clock phases, so as to generate an equivalent resistance whose resistance value is inversely proportional to the capacitance value of the capacitor and the clock frequency.

5. The low-power frequency detection circuit for auxiliary oscillator tuning as described in claim 1, characterized in that: The reference current source includes a reference resistor, NMOS transistors MN7 and MN8, and PMOS transistors MP9 and MP10, wherein: The source of NMOS transistor MN7 is grounded, the source of NMOS transistor MN8 is grounded through the reference resistor, the gates of NMOS transistors MN7 and MN8 are interconnected, and the gate and drain of NMOS transistor MN7 are interconnected. The PMOS transistors MP9 and MP10 form a current mirror. The sources of the PMOS transistors MP9 and MP10 receive external power input. The gates of the PMOS transistors MP9 and MP10 are interconnected, and the gate and drain of the PMOS transistor MP10 are interconnected. The drains of the PMOS transistors MP9 and MP10 are connected to the drains of the NMOS transistors MN7 and MN8, respectively.

6. The low-power frequency detection circuit for auxiliary oscillator tuning as described in claim 5, characterized in that: The NMOS transistors MN7 and MN8 and the PMOS transistors MP9 and MP10 all operate in the subthreshold region. The PMOS transistors MP9 and MP10 have the same width-to-length ratio, and the NMOS transistor MN8 has a width-to-length ratio twice that of the NMOS transistor MN7.

7. The low-power frequency detection circuit for auxiliary oscillator tuning as described in claim 1, characterized in that: The comparator circuit includes a differential input stage, a positive feedback circuit, a latch output stage, and an enable control circuit, wherein: The differential input stage includes two input terminals and two output terminals. The two input terminals of the differential input stage receive a first voltage and a second voltage, respectively, and the two output terminals of the differential input stage output an initial voltage difference. The positive feedback circuit includes two input terminals and two output terminals. The two input terminals of the positive feedback circuit are respectively connected to the two output terminals of the differential input stage, and the two output terminals of the positive feedback circuit are respectively connected to the two input terminals of the latch output stage, so as to feed back the voltage difference output by the differential input stage to the latch output stage. The latch output stage receives and latches the voltage difference fed back by the positive feedback circuit, and outputs the final comparison result. The enable control circuit receives a comparison enable signal and provides bias current to the differential input stage only when the comparison enable signal is valid; otherwise, it cuts off the bias current of the differential input stage.

8. The low-power frequency detection circuit for auxiliary oscillator tuning as described in claim 7, characterized in that: The positive feedback circuit includes a first inverter and a second inverter. The first inverter includes a PMOS transistor MP11 and an NMOS transistor MN11, and the second inverter includes a PMOS transistor MP12 and an NMOS transistor MN12. The inputs and outputs of the NMOS transistors MN11 and MN12 are interconnected, and the inputs and outputs of the PMOS transistors MP11 and MP12 are interconnected.

9. The low-power frequency detection circuit for auxiliary oscillator tuning as described in claim 7, characterized in that: The enable control circuit includes a fifth enable switch, which is connected in series in the tail current source path of the differential input stage and is controlled by a comparison enable signal. When the comparison enable signal is low, the fifth enable switch is turned off to cut off the bias current of the differential input stage; When the comparison enable signal is high, the fifth enable switch is turned on, providing bias current to the differential input stage.

10. The low-power frequency detection circuit for auxiliary oscillator tuning as described in claim 9, characterized in that: The enable control circuit further includes a first enable switch, a second enable switch, a third enable switch, and a fourth enable switch, all of which are controlled by a comparison enable signal. The first enable switch and the fourth enable switch are respectively connected to the two output terminals of the differential input stage, and the second enable switch and the third enable switch are respectively connected to the two output terminals of the positive feedback circuit.

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