Series resonant oscillator

Abstract

This disclosure relates to an oscillator, such as a series resonant oscillator, comprising: an inverter; a non-inverting buffer circuit system including a first transistor having a first gate terminal and a first source terminal and a second transistor having a second gate terminal and a second source terminal; a first inductor-capacitor (LC) tank circuit coupled between the inverter and the output of the non-inverting buffer circuit system; and a second LC tank circuit coupled between the inverter and the input of the non-inverting buffer circuit system, wherein the first gate terminal and the second gate terminal are coupled to the input of the non-inverting buffer circuit system, the first source terminal and the second source terminal are coupled to the output of the non-inverting buffer circuit system, the first source terminal and the second source terminal are individually DC biased, and the first gate terminal and the second gate terminal are individually DC biased.

Description

Technical Field

[0001] The embodiments of the subject matter described herein generally relate to oscillator circuits, including series resonant oscillator circuits. Background Technology

[0002] Modern applications for wireless signal transmission / reception, such as mobile telecommunications, radio, or radar, typically require low phase noise in clock or local oscillator (LO) signal generation to achieve better signal-to-noise ratio specifications. Radio frequency (RF) oscillators are commonly used in phase-locked loops (PLLs), which are frequently used for both clock and LO signal generation in these applications. Series resonant oscillators typically offer a low phase noise figure at the expense of high current consumption. Summary of the Invention

[0003] Various exemplary embodiments are presented below. Some simplifications and omissions may have been made in the following examples to highlight and illustrate some aspects of the various exemplary embodiments, rather than to limit the scope.

[0004] In an example embodiment, an oscillator includes: an inverter having a first input and a first output; a non-inverting buffer circuit system having: a second input; a second output; a first transistor having a first gate and a first source; a second transistor having a second gate and a second source; a first inductor-capacitor (LC) tank coupled between the first input of the inverter and the second output of the non-inverting buffer circuit system; and a second LC tank coupled between the first output of the inverter and the second input of the non-inverting buffer circuit system, wherein the first gate of the first transistor is coupled to the second input of the non-inverting buffer circuit system, the second gate of the second transistor is coupled to the second input of the non-inverting buffer circuit system, the first source of the first transistor is coupled to the second output of the non-inverting buffer circuit system, the second source of the second transistor is coupled to the second output of the non-inverting buffer circuit system, the first source and the second source are individually DC biased, and the first gate and the second gate are individually DC biased.

[0005] In one or more embodiments, the first transistor is an n-type metal-oxide-semiconductor (NMOS) transistor, and the second transistor is a p-type metal-oxide-semiconductor (PMOS) transistor.

[0006] In one or more embodiments, the non-inverting buffer circuit system further includes: a first resistor coupled between a reference node and the first source terminal of the first transistor, wherein the first source terminal is DC biased via the first resistor; and a second resistor coupled between a voltage source and the second source terminal of the second transistor, wherein the second source terminal is DC biased via the second resistor.

[0007] In one or more embodiments, the non-inverting buffer circuit system further includes: a first resistor coupled between a voltage source and a first gate terminal of the first transistor, wherein the first gate terminal is DC biased via the first resistor; and a second resistor coupled between a reference node and a second gate terminal of the second transistor, wherein the second gate terminal is DC biased via the second resistor.

[0008] In one or more embodiments, the non-inverting buffer circuit system further includes: a first inductor coupled between a voltage source and a first gate terminal of the first transistor, wherein the first gate terminal is DC biased via the first inductor; and a second inductor coupled between a reference node and a second gate terminal of the second transistor, wherein the second gate terminal is DC biased via the second inductor.

[0009] In one or more embodiments, the second LC tank circuit includes the first inductor and the second inductor.

[0010] In one or more embodiments, the non-inverting buffer circuit system further includes: a first capacitor coupled between the second input of the non-inverting buffer circuit system and the first gate terminal of the first transistor; a second capacitor coupled between the second input of the non-inverting buffer circuit system and the second gate terminal of the second transistor; a third capacitor coupled between the second output of the non-inverting buffer circuit system and the first source terminal of the first transistor; and a fourth capacitor coupled between the second output of the non-inverting buffer circuit system and the second source terminal of the second transistor.

[0011] In one or more embodiments, the second LC tank circuit further includes the first capacitor and the second capacitor, and the first LC tank circuit includes the third capacitor and the fourth capacitor.

[0012] In one or more embodiments, the oscillator further includes: a first inductor ring corresponding to the first inductor; a second inductor ring corresponding to the second inductor; and a third inductor ring electromagnetically coupled to the first inductor ring and the second inductor ring.

[0013] In one or more embodiments, the oscillator further includes an output buffer coupled to the third inductor ring and configured to provide a differential output signal to the oscillator based on a signal received from the third inductor ring.

[0014] In an example embodiment, a series resonant oscillator includes: an inverter; a non-inverting buffer circuit system including a first transistor having a first control terminal and a first current-carrying terminal and a second transistor having a second control terminal and a second current-carrying terminal, wherein the first control terminal and the second control terminal are individually DC biased, and the first current-carrying terminal and the second current-carrying terminal are individually DC biased; a first inductor-capacitor (LC) tank circuit coupled between the inverter and the non-inverting buffer circuit system; and a second LC tank circuit coupled between the inverter and the non-inverting buffer circuit system.

[0015] In one or more embodiments, the first transistor is an n-type metal-oxide-semiconductor (NMOS) transistor, and the second transistor is a p-type metal-oxide-semiconductor (PMOS) transistor.

[0016] In one or more embodiments, the non-inverting buffer circuit system further includes: a first resistor coupled between a reference node and a first current-carrying terminal of the first transistor, wherein the first current-carrying terminal is DC biased via the first resistor; and a second resistor coupled between a voltage source and a second current-carrying terminal of the second transistor, wherein the second current-carrying terminal is DC biased via the second resistor.

[0017] In one or more embodiments, the non-inverting buffer circuit system further includes: a third resistor coupled between the voltage source and the first control terminal of the first transistor, wherein the first control terminal is DC biased via the third resistor; and a fourth resistor coupled between the reference node and the second control terminal of the second transistor, wherein the second control terminal is DC biased via the fourth resistor.

[0018] In one or more embodiments, the non-inverting buffer circuit system further includes: a first inductor coupled between the voltage source and the first control terminal of the first transistor, wherein the first control terminal is DC biased via the first inductor; and a second inductor coupled between the reference node and the second control terminal of the second transistor, wherein the second control terminal is DC biased via the second inductor.

[0019] In one or more embodiments, the second LC tank circuit includes the first inductor and the second inductor.

[0020] In one or more embodiments, the non-inverting buffer circuit system further includes: a first capacitor coupled between the input of the non-inverting buffer circuit system and the first control terminal of the first transistor; a second capacitor coupled between the input of the non-inverting buffer circuit system and the second control terminal of the second transistor; a third capacitor coupled between the output of the non-inverting buffer circuit system and the first current-carrying terminal of the first transistor; and a fourth capacitor coupled between the output of the non-inverting buffer circuit system and the second current-carrying terminal of the second transistor.

[0021] In one or more embodiments, the second LC tank circuit further includes the first capacitor and the second capacitor, and the first LC tank circuit includes the third capacitor and the fourth capacitor.

[0022] In one or more embodiments, the series resonant oscillator further includes: a first inductor ring corresponding to the first inductor; a second inductor ring corresponding to the second inductor; and a third inductor ring electromagnetically coupled to the first inductor ring and the second inductor ring.

[0023] In one or more embodiments, the series resonant oscillator further includes an output buffer coupled to the third inductor ring and configured to provide a differential output signal to the series resonant oscillator based on a signal received from the third inductor ring. Attached Figure Description

[0024] A more complete understanding of the subject matter can be obtained by referring to the specific embodiments and claims considered in conjunction with the following figures, in which similar reference numerals refer to similar elements in each figure. For simplicity and clarity, the elements in the figures are shown, and these elements are not necessarily drawn to scale. The figures, together with the specific embodiments, are incorporated in and form part of this specification, and are used to further illustrate examples, embodiments, etc., and to explain various principles and advantages according to this disclosure. In the figures:

[0025] Figure 1 Illustrative circuit diagrams according to various embodiments are shown, illustrating a series resonant oscillator including two inductor-capacitor (LC) tank circuits, an inverter, and a non-inverting buffer;

[0026] Figure 2 Illustrative circuit diagrams are shown according to various embodiments, illustrating that... Figure 1 The non-inverting buffer used in a series resonant oscillator;

[0027] Figure 3An illustrative circuit diagram is shown according to various embodiments, illustrating a series resonant oscillator including two LC tank circuits, an inverter, and a non-inverting buffer.

[0028] Figure 4 An illustrative circuit diagram according to various embodiments is shown, illustrating a series resonant oscillator including two LC tank paths, an inverter, and a non-inverting buffer, wherein a portion of the LC tank path is split between parallel paths at the input and output of the non-inverting buffer.

[0029] Figure 5 Illustrative circuit diagrams are shown according to various embodiments, illustrating that... Figure 3 or Figure 4 The non-inverting buffer circuit system used in the series resonant oscillator; and

[0030] Figure 6 Schematic diagrams are shown according to various embodiments, illustrating implementation options. Figure 4 or Figure 5 The LC tank circuit inductance of the series resonant oscillator and the nested inductor ring of the output. Detailed Implementation

[0031] The following detailed description is illustrative in nature only and is not intended to limit the use of the embodiments described herein and such embodiments. Furthermore, it is not intended to be bound by any explicit or implicit theory presented in the foregoing technical field, background art, or the following detailed description.

[0032] For the sake of simplicity and clarity, the figures illustrate general construction methods. Descriptions and details of well-known features and techniques may be omitted from the following detailed descriptions to avoid unnecessarily obscuring this disclosure. For example, the dimensions of some elements or regions in the figures may be enlarged relative to other elements or regions to aid in understanding the embodiments described herein.

[0033] The terms “first,” “second,” “third,” “fourth,” etc. (if present) used in the description and claims are used to distinguish similar elements and are not necessarily used to describe a particular sequence or chronological order. It should be understood that the terms thus used are interchangeable where appropriate, such that the embodiments described herein can be operated, for example, in a different order than that shown or described herein. Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. As used herein, the terms “approximately,” “about,” “substantially,” and “basically” mean sufficient to achieve the stated purpose in a practical manner, and minor defects (if present) are not important to the stated purpose.

[0034] In accordance with these principles, when references are made to measurable quantities, including but not limited to dimensions, these terms mean that the quantity is equal to the stated value, subject to acceptable tolerances of any method or apparatus chosen for manufacturing the described structure or measuring the described quantity or dimension. Unless otherwise stated, directional references, such as “top,” “bottom,” “left,” “right,” “above,” “below,” etc., are not intended to require any preferred orientation, but are illustrative of the orientation of one or more corresponding figures for illustrative purposes. As used herein, the terms “exemplary” or “example” mean “serving as an example, instance, or illustration.” Any embodiment described herein as exemplary or illustrative should not necessarily be construed as preferred or advantageous over other embodiments. Furthermore, certain terms may be used herein for reference only and are therefore not intended to be restrictive.

[0035] In this document, elements, nodes, or features are sometimes referred to as “connected” or “coupled” together. As used herein, unless explicitly stated otherwise, “connected” means that one element is directly engaged to (or directly connected to) another element in an electrical or non-electrical manner, and not necessarily mechanically. Similarly, unless explicitly stated otherwise, “coupled” means that one element is directly or indirectly engaged to (or directly or indirectly connected to) another element in an electrical or non-electrical manner, and not necessarily mechanically. Therefore, although the schematic diagrams shown depict exemplary arrangements of elements, additional intervening elements, devices, features, or components may be present in one or more embodiments of the depicted subject matter.

[0036] The various embodiments described herein relate to series resonant oscillators implemented using two stages. Conventional series resonant oscillators typically include four resonant circuits and four driver stages. Each of the four driver stages in such a conventional series resonant oscillator typically requires a differential input signal, which increases routing complexity and sensitivity to layout parasitics at high frequencies. It may be necessary for each driver stage to present a low output impedance to enable driving low-impedance resonant circuits in series resonant mode. Additionally, using four driver stages in such conventional embodiments results in relatively high current consumption and a relatively large layout size (e.g., area footprint). In this document, unless otherwise specified, “flow” refers to current.

[0037] The embodiments described herein address these challenges by implementing a two-stage series resonant oscillator comprising a non-inverting buffer as a first driver stage and an inverter as a second driver stage. The first resonant circuitry (e.g., an inductor-capacitor (LC) tank circuit) is coupled between the output of the first driver stage and the input of the second driver stage, and the second resonant circuitry is coupled between the output of the second driver stage and the input of the first driver stage. By using fewer driver stages than a conventional four-stage series resonant oscillator, the embodiments of the two-stage series resonant oscillator described herein advantageously have reduced current consumption and a reduced footprint. In one or more embodiments, the driver stages of the two-stage series resonant oscillator may not require differential input signals, which advantageously reduces routing complexity and sensitivity to high-frequency layout parasitic effects compared to conventional series resonant oscillators with driver stages requiring differential input signals.

[0038] In one or more embodiments, the series resonant oscillator may include a non-inverting buffer as a first driver stage and an inverter as a second driver stage. The series resonant oscillator may include a first LC tank circuit system coupled between the output of the non-inverting buffer and the input of the inverter. The series resonant oscillator may include a second LC tank circuit system coupled between the output of the inverter and the input of the non-inverting buffer. The non-inverting buffer may include a first source follower transistor and a second source follower transistor. In one or more embodiments, the first and second source follower transistors may be metal-oxide-semiconductor field-effect transistors (MOSFETs). The first source follower transistor may be a p-channel MOSFET (PMOS) transistor, and the second source follower transistor may be an n-channel MOSFET (NMOS) transistor. The first and second source follower transistors may include a gate or control terminal, each coupled to the same input of the non-inverting buffer. The first and second source follower transistors may include a source terminal or a current-carrying terminal, each source terminal or current-carrying terminal coupled to the same output of the non-inverting buffer. In one or more embodiments, the source and drain terminals of each of the first and second source follower transistors may be individually biased.

[0039] In one or more embodiments, each LC tank path of the two-stage series resonant oscillator may include a capacitor series-coupled between the first driver stage and the second driver stage, and an inductor (e.g., a shunt inductor) coupled to a reference node. In this document, the term "shunt" is sometimes used to refer to a component or group of components coupled or connected between a signal path and a reference (e.g., ground or common) voltage or a supply voltage (e.g., VDD).

[0040] In one or more other embodiments, each LC tank path of the two-stage series resonant oscillator may include an inductor series-coupled between the first driver stage and the second driver stage, and a capacitor (e.g., a shunt capacitor) coupled to a reference node. In one or more such embodiments, the gates or control terminals of the first and second source follower transistors of the non-inverting buffer may be biased via an inductor of the LC tank path disposed at the input of the non-inverting buffer. In one or more such embodiments, the inductors used to bias the gates of the first and second source follower transistors may be arranged as first and second nested inductor rings, further nested and electromagnetically coupled to a third inductor ring, wherein the output of the oscillator is provided via the third inductor ring through an output buffer.

[0041] Figure 1An illustrative circuit diagram is shown, representing a series resonant oscillator 100 (sometimes referred to herein as "oscillator 100") including a non-inverting buffer 102, an inverter 110, and inductor-capacitor (LC) tank circuits 103 and 105. Herein, the term "LC tank circuit" refers to a resonant circuit comprising an inductor and a capacitor, arranged to act as an electrical resonator, thereby exhibiting resonant behavior at one or more resonant frequencies. In one or more embodiments, the inverter 110 may be implemented as a self-biased AC-coupled inverter, a non-limiting example of which is represented by circuit system 111. In one or more other embodiments, the inverter 110 may be implemented as a conventional inverter, and the LC tank circuit 103 may be supplied with a bias voltage instead of ground or a reference voltage. The series resonant oscillator 100 may be voltage-driven. The series resonant oscillator 100 may include two driver stages, a non-inverting buffer 102 and an inverter 110, which advantageously reduces current consumption and layout size (e.g., area occupation) compared to a conventional series resonant oscillator that requires four driver stages.

[0042] LC tank circuit 103 may include inductor 104 and capacitor 108. LC tank circuit 105 may include inductor 112 and capacitor 116. Capacitors 108 and 116 may be implemented using a single capacitor or a network of two or more capacitors connected in series, in parallel, or a combination of series and parallel capacitors. Inductors 104 and 112 may be implemented using a single inductor or a network of two or more inductors connected in series, in parallel, or a combination of series and parallel inductors.

[0043] In one or more embodiments, inductor 104 is coupled between the output of non-inverting buffer 102 and node 106. Capacitor 108 is coupled between node 106 and reference node 118. That is, capacitor 108 may be a shunt capacitor. A ground or reference voltage may be provided via reference node 118. Node 106 is coupled to the input of inverter 110. Inductor 112 is coupled between the output of inverter 110 and node 114. Capacitor 116 is coupled between node 114 and reference node 118. That is, capacitor 116 may be a shunt capacitor. Node 114 is coupled to the input of non-inverting buffer 102. Each of inverter 110 and non-inverting buffer 102 may have a single-ended input and a single-ended output.

[0044] Oscillator 100 can be configured to oscillate at the series resonant frequency of LC tank circuits 103 and 105. The series resonant frequency of LC tank circuits 103 and 105 can be determined by the capacitance values ​​of capacitors 108 and 116 and the inductance values ​​of inductors 104 and 112. For example, the fundamental series resonant frequency for a given LC tank circuit. It can be given as:

[0045]

[0046] Where L is the inductance and C is the capacitance.

[0047] The phase relationship between LC tank paths 103 and 105 and the driver stage (non-inverting buffer 102 and inverter 110) allows for operation at the resonant frequency. The signal continues to oscillate. In the current example, the phase of the signal at the input of the non-inverting buffer 102 (e.g., at node 114) is given to 0°. Due to the -90° phase shift applied by the LC slot path 103, the signal phase at the input of the inverter 110 (e.g., at node 106) is 270° relative to the signal phase at node 114. Due to the 180° phase shift applied by the inverter 110, the signal phase at the output of the inverter 110 before the LC slot path 105 is 90° relative to the signal phase at node 114. The LC slot path 105 applies a -90° phase shift to the signal output by the inverter 110 so that the relative signal phase returns to 0° at node 114.

[0048] Depending on the Q factor of LC tank 103, non-inverting buffer 102 can have a sufficiently low output impedance, which allows non-inverting buffer 102 to drive LC tank 103 when the impedance of LC tank 103 is low (e.g., for signals at or near the series resonant frequency f0). In one or more embodiments, the output impedance can be sufficiently low when the output impedance of a non-inverting buffer, such as non-inverting buffer 102, is less than or equal to the equivalent resistance of an LC tank, such as LC tank 103, at the output of the non-inverting buffer, which allows the non-inverting buffer to deliver sufficient energy to the LC tank. For example, the equivalent resistance of LC tank 103 can be equal to (2πf0*L) / Q, where f0 is the resonant frequency, L is the inductance value of inductor 104, and Q is the Q factor of LC tank 103. For example, the value of 2πf0 of LC tank 103 can be equal to 1 / sqrt(LC), where C is the capacitance value of capacitor 108 and L is the inductance value of inductor 104. In one or more embodiments, the Q factor of the LC tank path 103 may be 10 or greater to achieve relatively low phase noise. As a non-limiting example, given L = 500 pH, C = 500 fF, and Q = 10, the equivalent resistance of the LC tank path 103 is approximately 3 ohms (e.g., approximately 3.333 ohms), and the output impedance of the non-inverting buffer 102 may be less than or equal to approximately 3 ohms. In one or more embodiments, the non-inverting buffer 102 may be implemented using one or more source follower transistor arrangements to achieve a suitable low output impedance. In one or more embodiments, the non-inverting buffer may include both a PMOS source follower transistor and an NMOS source follower transistor, each coupled between the input and output of the non-inverting buffer 102, such that the output impedance of the non-inverting buffer 102 is suitably low for both rising and falling signal directions. In one or more embodiments, the PMOS and NMOS source follower transistors can be individually biased while each receiving the same high-frequency (e.g., RF) signal at its respective gate terminal (e.g., each receiving a separate DC bias voltage at its respective gate terminal and a separate DC bias voltage at its respective source and drain terminals). Figure 2 An example of a non-inverting buffer that can be used to implement non-inverting buffer 102 is shown.

[0049] Figure 2 An illustrative circuit diagram is shown, illustrating a non-inverting buffer 200 comprising an arrangement of two source follower transistors, each having a gate, drain, and source terminal individually DC biased. As a non-limiting example, the non-inverting buffer 200 may correspond to... Figure 1 An embodiment of the non-inverting buffer 102. In the current example, refer to... Figure 1The oscillator 100 describes the non-inverting buffer 200. The same reference numerals are used to denote the same elements, and for the sake of brevity, such identical elements are not necessarily described again here. It should be understood that, according to one or more other embodiments, in Figure 1 The use of a non-inverting buffer 200 in the oscillator 100 is intended to be illustrative and not limiting, such that the non-inverting buffer 200 can be implemented as part of other suitable oscillators (e.g., as part of...). Figure 3 The non-inverting buffer 302 in the oscillator 300.

[0050] As shown, the non-inverting buffer 200 may include capacitors 204, 206, 228, and 230, resistors 208, 210, 224, and 226, transistors 216 and 218, an input node 232, and an output node 234. Capacitors 204 and 228, resistors 208 and 224, and transistor 216 may be included in or connected to a first path connecting the input node 232 and the output node 234. Capacitors 206 and 230, resistors 210 and 226, and transistor 218 may be connected to or included in a second path connecting the input node 232 and the output node 234. As shown, the first and second paths may be connected in parallel between the input node 232 and the output node 234.

[0051] In the first path, capacitor 204 may be coupled between input node 232 and node 212. Node 212 may correspond to or be coupled to the gate terminal of transistor 216. Resistor 208 may be coupled between voltage source 202 (e.g., voltage source 202 may provide a supply voltage VDD) and node 212. The drain terminal of transistor 216 may be coupled to voltage source 202. Resistor 224 may be coupled between node 220 and reference node 118 (e.g., reference node 118 may provide ground or a reference voltage). Node 220 may correspond to or be coupled to the source terminal of transistor 216. Capacitor 228 may be coupled between node 220 and output node 234.

[0052] In the second path, capacitor 206 may be coupled between input node 232 and node 214. Node 214 may correspond to or be coupled to the gate terminal of transistor 218. Resistor 210 may be coupled between node 214 and reference node 118. The drain terminal of transistor 218 may be coupled to reference node 118. Resistor 226 may be coupled between voltage source 202 and node 222. Node 222 may correspond to or be coupled to the source terminal of transistor 218. Capacitor 230 may be coupled between node 222 and output node 234. Although the terms “gate terminal,” “drain terminal,” and “source terminal” are sometimes used when describing transistors herein, it should be understood that the “gate terminal” of a transistor is an example of a “control terminal,” and the “drain terminal” and “source terminal” of a transistor are examples of “current-carrying terminals.”

[0053] Capacitors 204 and 206 provide DC and low-frequency signal blocking between input node 232 and the gate terminals of transistors 216 and 218. Capacitors 228 and 230 provide DC and low-frequency signal blocking between output node 234 and the source terminals of transistors 216 and 218, thereby enabling independent DC voltages at source node 220 of transistor 216 and source node 222 of transistor 218.

[0054] The DC bias voltage supplied to the gate of transistor 216 via resistor 208 can be set based on the DC voltage VDD. The DC bias voltage supplied to the drain of transistor 216 can also be the DC voltage VDD. The DC bias voltage supplied to the gate of transistor 218 can be determined based on the reference voltage supplied from reference node 118 via resistor 210. The DC bias voltage supplied at the source of transistor 218 can also be the reference voltage supplied via reference node 118. In this way, the gates of transistors 216 and 218 are individually DC biased, and the corresponding source and drain terminals of transistors 216 and 218 are individually DC biased. Although the same reference voltage and supply voltage (VDD) are shown supplied at nodes 118 and 202 respectively in the present example, it should be understood that such arrangement is intended to be illustrative and not limiting. For example, in one or more other embodiments, one or more of nodes 202 may be supplied with a power supply voltage different from one or more other power supply voltages supplied to other nodes 202, and one or more of nodes 118 may be supplied with a reference voltage different from one or more other reference voltages supplied to other nodes 118.

[0055] In one or more embodiments, transistor 216 may be an NMOS transistor, and transistor 218 may be a PMOS transistor. In one or more embodiments, transistor 216 may be arranged as an NMOS source follower, and transistor 218 may be arranged as a PMOS source follower. For example, a source follower transistor may have a source voltage that follows its gate voltage to some extent. Typically, a source follower transistor can decouple a load from the gate of the source follower transistor, and the source terminal can provide load current. By implementing transistors 216 and 218 as source follower NMOS and PMOS transistors in the illustrated arrangement, the non-inverting buffer 200 can maintain low output impedance both when the magnitude of the input signal (e.g., an RF input signal) received at input node 232 rises and when the magnitude of the input signal falls. For example, in one or more such embodiments, transistor 216 may provide low output impedance during the period when the input signal rises, and transistor 218 may provide low output impedance during the period when the input signal falls. In this manner, transistors 216 and 218 can provide appropriately low output impedance for the non-inverting buffer 200 for both rising and falling signal directions (e.g., suitable for a series resonant oscillator). While one or more embodiments of this example implement transistors 216 and 218 as PMOS and NMOS transistors, this is intended to be illustrative and not limiting. In one or more other embodiments, transistors 216 and 218 may alternatively be implemented as two bipolar junction transistors (BJTs), or as a BJT and a MOSFET (e.g., as a non-limiting example, where transistor 216 is implemented as an NPN bipolar emitter follower and transistor 218 is implemented as a PMOS source follower).

[0056] In one or more embodiments, the placement of the capacitor and inductor in the LC tank path of the series resonant oscillator is interchangeable (e.g., relative to...). Figure 1 The arrangement shown allows at least one LC tank circuit inductor to be used for the DC bias of the oscillator's non-inverting buffer. For example, Figure 3 An illustrative circuit diagram is shown representing a series resonant oscillator 300 (sometimes referred to herein as "oscillator 300") including a non-inverting buffer 302, inductor-capacitor (LC) tank circuits 303 and 305, and an inverter 110. One or more components of the oscillator 300 may be similar to... Figure 1The corresponding elements of oscillator 100 (e.g., reference node 118 and inverter 110), and in this example, the same reference numerals are used to denote the same elements. Series resonant oscillator 300 may be voltage-driven. Series resonant oscillator 300 may include two driver stages: a non-inverting buffer 302 and an inverter 110, which advantageously reduces current consumption and layout size (e.g., area occupied) compared to conventional series resonant oscillators that require four driver stages.

[0057] LC tank circuit 303 may include inductor 304 and capacitor 308. LC tank circuit 305 may include inductor 312 and capacitor 316. Capacitors 308 and 316 may be implemented using a single capacitor or a network of two or more capacitors connected in series, in parallel, or a combination of series and parallel capacitors. Inductors 304 and 312 may be implemented using a single inductor or a network of two or more inductors connected in series, in parallel, or a combination of series and parallel inductors.

[0058] In one or more embodiments, capacitor 308 is coupled between the output of non-inverting buffer 302 and node 306. Inductor 304 is coupled between node 306 and reference node 118. That is, inductor 304 may be a shunt inductor. A ground or reference voltage may be provided via reference node 118. Node 306 is coupled to the input of inverter 110. Capacitor 316 is coupled between the output of inverter 110 and node 314. Inductor 312 is coupled between node 314 and reference node 118. That is, inductor 312 may be a shunt inductor. Node 314 is coupled to the input of non-inverting buffer 302.

[0059] Oscillator 300 can be configured to achieve the series resonant frequency of LC tank circuits 303 and 305. The oscillation occurs at the series resonant frequency of LC tank circuits 303 and 305. It can be determined by the capacitance values ​​of capacitors 308 and 316 and the inductance values ​​of inductors 304 and 312 (for example, according to Equation 1 above).

[0060] The phase relationship between LC tank circuits 303 and 305 and the driver stage (non-inverting buffer 302 and inverter 110) allows for operation at the resonant frequency. The signal continues to oscillate. In the current example, the phase of the signal at the input of the non-inverting buffer 302 (e.g., at node 314) is given to 0°. Due to the +90° phase shift applied by the LC slot path 303, the signal phase at the input of the inverter 110 (e.g., at node 306) is 90° relative to the signal phase at node 314. Due to the 180° phase shift applied by the inverter 110, the signal phase at the output of the inverter 110 before the LC slot path 305 is 270° relative to the signal phase at node 314. The LC slot path 305 applies a +90° phase shift to the signal output by the inverter 110 so that the relative signal phase returns to 0° at node 314.

[0061] Depending on the Q factor of the LC tank circuit 303, the non-inverting buffer 302 can have a sufficiently low output impedance, which allows the non-inverting buffer 302 to drive the LC tank circuit 303 when its impedance is low (e.g., for signals at or near the series resonant frequency f0). For example, a sufficiently low output impedance of the non-inverting buffer 302 can be an output impedance less than or equal to the Q factor-related equivalent resistance of the LC tank circuit 303, similar to the above combination. Figure 1 Examples described. In one or more embodiments, the non-inverting buffer 302 may be implemented using one or more source follower transistor arrangements to achieve a suitable low output impedance. In one or more embodiments, the non-inverting buffer may include both a PMOS source follower transistor and an NMOS source follower transistor, each coupled between the input and output of the non-inverting buffer 302, such that the output impedance of the non-inverting buffer 302 is suitably low for both rising and falling signal directions. In one or more embodiments, the PMOS and NMOS source follower transistors may be individually biased (e.g., each receiving a separate DC bias voltage at its respective gate and a separate DC bias voltage at its respective source and drain terminals) while receiving the same high-frequency (e.g., RF) signal at their respective gate terminals. As a non-limiting example, the non-inverting buffer 302 may use... Figure 2 Non-inverting buffer 200 or Figure 5 It can be implemented using any of the non-inverting buffers 500.

[0062] Figure 4 An illustrative circuit diagram is shown, representing a series resonant oscillator 400 (sometimes referred to herein as "oscillator 400") comprising a non-inverting buffer 402, an inverter 110, and inductor-capacitor (LC) tank circuits 403 and 405. One or more components of the oscillator 400 may resemble... Figure 1The corresponding elements of oscillator 100 (e.g., reference node 118 and inverter 110), and in this example, the same reference numerals are used to denote the same elements. Series resonant oscillator 400 may be voltage-driven. Series resonant oscillator 400 may include two driver stages: a non-inverting buffer 402 and an inverter 110, which advantageously reduces current consumption and layout size (e.g., area occupation) compared to conventional series resonant oscillators that require four driver stages.

[0063] LC tank circuit 403 may include inductor 404 and capacitors 408-1 and 408-2. LC tank circuit 405 may include inductors 412-1 and 412-2 and capacitors 416-1 and 416-2. Capacitors 408-1, 408-2, 416-1, and 416-2 may be implemented using a single capacitor or a network of two or more capacitors connected in series, in parallel, or a combination of series and parallel capacitors, respectively. Inductors 404, 412-1, and 412-2 may be implemented using a single inductor or a network of two or more inductors connected in series, in parallel, or a combination of series and parallel inductors, respectively.

[0064] In one or more embodiments, capacitors 408-1 and 408-2 are coupled between the respective outputs of the non-inverting buffer 402 and node 406. Inductor 404 is coupled between node 406 and reference node 118. That is, inductor 404 may be a shunt inductor. A ground or reference voltage may be provided via reference node 118. Node 406 is coupled to the input of inverter 110. Capacitor 416-1 is coupled between the output of inverter 110 (i.e., node 414) and node 420. Capacitor 416-2 is coupled between the output of inverter 110 (i.e., node 414) and node 422. Inductor 412-1 is coupled between voltage source 401 (e.g., voltage source 401 may provide supply voltage VDD) and node 420. Inductor 412-2 is coupled between node 422 and reference node 118. That is, inductors 412-2 and 412-1 may be shunt inductors. Node 420 is coupled to the first input of the non-inverting buffer 402. Node 422 is coupled to the second input of the non-inverting buffer 402.

[0065] In one or more embodiments, node 414 may correspond to the input of non-inverting buffer 402 (e.g., in one or more such embodiments, LC tank path 405 is considered part of non-inverting buffer 402), and node 406 may correspond to the output of non-inverting buffer 402 (e.g., in one or more such embodiments, capacitors 408-1 and 408-2 are considered part of both non-inverting buffer 402 and LC tank path 403). In one or more embodiments, the gate terminals of the transistors of non-inverting buffer 402 may be DC biased via inductors 412-1 and 412-2 when inductors 412-1 and 412-2 are also used as inductor elements of LC tank path 405. When capacitors 408-1, 408-2, 416-1, and 416-2 are also used as capacitive elements of LC tank paths 403 and 405, capacitors 408-1, 408-2, 416-1, and 416-2 may provide DC blocking for non-inverting buffer 402.

[0066] Oscillator 400 can be configured at the series resonant frequency of LC tank circuits 403 and 405. The oscillation occurs at the series resonant frequency of LC tank circuits 403 and 405. It can be determined by the capacitance values ​​of capacitors 408-1, 408-2, 416-1 and 416-2 and the inductance values ​​of inductors 404, 412-1 and 412-2.

[0067] The phase relationship between LC tank circuits 403 and 405 and the driver stage (non-inverting buffer 402 and inverter 110) allows for operation at the resonant frequency. The oscillation continues. These phase relationships can be similar to those described above. Figure 3 The phase relationships described are (e.g., 0° at the input of the non-inverting buffer 402, 90° at the input of the inverter 110, and 270° at the output of the inverter 110), and for the sake of brevity, such descriptions of phase relationships will not be repeated here.

[0068] Depending on the Q factor of the LC tank circuit 403, the non-inverting buffer 402 can have a sufficiently low output impedance, which allows the non-inverting buffer 402 to drive the LC tank circuit 403 when its impedance is low (e.g., for signals at or near the series resonant frequency f0). For example, a sufficiently low output impedance of the non-inverting buffer 402 can be an output impedance less than or equal to the Q factor-related equivalent resistance of the LC tank circuit 403, similar to the above combination. Figure 1Examples described. In one or more embodiments, one or more source follower transistor arrangements may be used to implement the non-inverting buffer 402 to achieve a suitable low output impedance. In one or more embodiments, the non-inverting buffer may include both a PMOS source follower transistor and an NMOS source follower transistor, each coupled between the input and output of the non-inverting buffer 402, such that the output impedance of the non-inverting buffer 402 is suitably low for both rising and falling signal directions. In one or more embodiments, the PMOS and NMOS source follower transistors may be individually biased (e.g., each receiving a separate DC bias voltage at its respective gate and a separate DC bias voltage at its respective source and drain terminals) while receiving the same high-frequency (e.g., RF) signal at their respective gate terminals. As a non-limiting example, various embodiments may be used... Figure 5 The non-inverting buffer circuit system 500 is used to implement the non-inverting buffer 402.

[0069] Figure 5 An illustrative circuit diagram is shown, illustrating a non-inverting buffer circuit system 500 comprising two source follower transistors arranged individually DC biased. As a non-limiting example, the non-inverting buffer circuit system 500 may include... Figure 4 An embodiment of the non-inverting buffer 402. In the current example, refer to... Figure 4 The oscillator 400 describes a non-inverting buffer circuit system 500. The same reference numerals are used to denote the same elements, and for the sake of brevity, such identical elements are not necessarily described again here. It should be understood that, according to one or more other embodiments, in... Figure 4 The use of a non-inverting buffer circuit system 500 in the oscillator 400 is intended to be illustrative and not limiting, so that the non-inverting buffer circuit system 500 can be implemented as part of other suitable oscillators.

[0070] As shown, the non-inverting buffer circuit system 500 may include capacitors 416-1, 416-2, 408-1 and 408-2, resistors 524 and 526, inductors 412-1 and 412-2, transistors 516 and 518, an input node 414, and an output node 406. Capacitors 416-1 and 408-1, resistor 524, inductor 412-1, and transistor 516 may be included in or connected to a first path connecting the input node 414 and the output node 406. Capacitors 416-2 and 408-2, resistor 526, inductor 412-2, and transistor 518 may be connected to or included in a second path connecting the input node 414 and the output node 406. As shown, the first and second paths may be connected in parallel between the input node 414 and the output node 406.

[0071] In the first path, capacitor 416-1 may be coupled between input node 414 and node 420. Node 420 may correspond to or be coupled to the gate terminal of transistor 516. Inductor 412-1 may be coupled between voltage source 401 (e.g., voltage source 401 provides a supply voltage VDD) and node 420. The drain terminal of transistor 516 may be coupled to voltage source 401. Resistor 524 may be coupled between node 520 and reference node 118 (e.g., reference node 118 provides ground or a reference voltage). Node 520 may correspond to or be coupled to the source terminal of transistor 516. Capacitor 408-1 may be coupled between node 520 and output node 406.

[0072] In the second path, capacitor 416-2 may be coupled between input node 414 and node 422. Node 422 may correspond to or be coupled to the gate terminal of transistor 518. Inductor 412-2 may be coupled between node 422 and reference node 118. The drain terminal of transistor 518 may be coupled to reference node 118. Resistor 526 may be coupled between voltage source 401 and node 522. Node 522 may correspond to or be coupled to the source terminal of transistor 518. Capacitor 408-2 may be coupled between node 522 and output node 406.

[0073] Capacitors 416-1 and 416-2 provide DC and low-frequency signal blocking between input node 414 and the gate terminals of transistors 516 and 518. In one or more embodiments, capacitors 416-1 and 416-2 may additionally serve as capacitive elements of LC tank circuit 405. Capacitors 408-1 and 408-2 provide DC and low-frequency signal blocking between output node 406 and the source terminals of transistors 516 and 518, and capacitors 408-1 and 408-2 allow for independent DC voltages at the source nodes 520 and 522 of transistors 516 and 518. In one or more embodiments, capacitors 408-1 and 408-2 may additionally serve as LC tank circuits (e.g., Figure 4 The capacitor element of LC channel 403.

[0074] The DC bias voltage supplied to the gate of transistor 516 via inductor 412-1 can be set based on the DC voltage VDD. The DC bias voltage supplied to the drain of transistor 516 can also be the DC voltage VDD. The DC bias voltage supplied to the gate of transistor 518 via inductor 412-2 can be determined based on a reference voltage provided via reference node 118. The DC bias voltage supplied at the drain of transistor 518 can also be the reference voltage provided via reference node 118. In this way, the gates of transistors 516 and 518 are individually DC biased, the source terminals of transistors 516 and 518 are individually DC biased, and the drain terminals of transistors 516 and 518 are individually DC biased. Compared to resistor-based DC biasing, providing DC bias to the gates of transistors 516 and 518 in the non-inverting buffer circuit system 500 using inductors further reduces phase noise. In one or more embodiments, inductors 412-1 and 412-2 may additionally be used as inductor elements of the LC tank circuit 405. While the present example shows the same reference voltage and supply voltage (VDD) supplied at nodes 118 and 401 respectively, it should be understood that such arrangement is intended to be illustrative and not limiting. For example, in one or more other embodiments, one or more of nodes 401 may be supplied with a supply voltage different from one or more other supply voltages supplied to the other nodes 401, and one or more of nodes 118 may be supplied with a reference voltage different from one or more other reference voltages supplied to the other nodes 118.

[0075] In one or more embodiments of the non-inverting buffer 402, transistor 516 may be an NMOS transistor, and transistor 518 may be a PMOS transistor. In one or more embodiments, transistor 516 may be arranged as an NMOS source follower, and transistor 518 may be arranged as a PMOS source follower. By implementing transistors 516 and 518 as source follower NMOS and PMOS transistors in the illustrated arrangement, the non-inverting buffer 500 can maintain low output impedance both when the input signal (e.g., an RF input signal) received at input node 414 rises and when the input signal falls. For example, in one or more such embodiments, transistor 516 may provide low output impedance during the rising period of the input signal, and transistor 518 may provide low output impedance during the falling period of the input signal. In this way, transistors 516 and 518 can provide appropriately low output impedance for the non-inverting buffer 402 for both the rising and falling signal directions (e.g., suitable for a series resonant oscillator). While one or more embodiments of this example implement transistors 516 and 518 as PMOS and NMOS transistors, this is intended to be illustrative and not limiting. In one or more other embodiments, transistors 516 and 518 may alternatively be implemented as two bipolar junction transistors (BJTs), or as a BJT and a MOSFET (e.g., as a non-limiting example, where transistor 516 is implemented as an NPN bipolar emitter follower and transistor 518 is implemented as a PMOS source follower).

[0076] Figure 6 A schematic diagram of a circuit system 600 is shown, comprising nested inductor rings 606, 608, and 610 arranged to provide one or more outputs of a series resonant oscillator. (Reference) Figure 4 The series resonant oscillator 400 describes the circuit system 600, wherein the same reference numerals denote the same elements.

[0077] In one or more embodiments, for example, the nested inductor ring of circuit system 600 includes Figure 4 Examples of inductors 412-1 and 412-2 in a series resonant oscillator 400. For example, inductor 412-1 may be implemented as a first inductor ring 606, inductor 412-2 may be implemented as a second inductor ring 608, and a third inductor ring 610 may be electromagnetically (e.g., inductively) coupled to the first inductor ring 608 and the second inductor ring 610.

[0078] A first inductor ring 606 may be coupled between node 420 and voltage source 401. A second inductor ring 608 may be coupled between node 422 and reference node 118. A third inductor ring may be coupled between the first and second inputs of output buffer 604. Output buffer 604 provides differential output signals VOUT_P and VOUT_N, which may correspond to a series resonant oscillator including inductor rings 606, 608, and 610 (e.g., Figure 4 The output of the series resonant oscillator 400. Voltage source 602 may (e.g., via a center tap) be coupled to the center point of the third inductor ring 610 and may provide a bias voltage VBIAS to the third inductor ring 610. In one or more embodiments, VBIAS may be approximately half (e.g., within + / - 10%) of the supply voltage VDD provided by voltage source 401. In one or more embodiments, the bias voltage VBIAS may define a common-mode bias.

[0079] In one or more embodiments, as a non-limiting example, inductor rings 606, 608, and 610 may be formed from different metal layers of a circuit board or die. In one or more embodiments, the inductance and resistance of the third inductor ring 610 may differ from those of the first inductor ring 606 and the second inductor ring 608, at least because the third inductor ring 610 may have a lower quality factor (“Q factor”) than the first inductor ring 606 and the second inductor ring 608.

[0080] Return to reference Figure 4 In one or more embodiments, during operation of oscillator 400, due to non-idealities and variations in buffer 402 or inverter 110, such as delays or signal amplitude or clipping, the signal phases at nodes 406 and 414 may not be perfectly aligned by 90° and 270°, respectively. At least in part due to these non-idealities, the differential output signals obtained directly from nodes 406 and 414 may be difficult to align. Return to Figure 6 To address this challenge, differential output signals VOUT_P and VOUT_N can alternatively be provided via output buffer 604 and nested inductor rings 606, 608, and 610 to improve alignment. For example, the oscillation signal at the output of inverter 110 can be driven by inductor rings 606 and 608 (e.g., inductors 414-1 and 414-2), which can cause an oscillation in the third inductor ring 610, based on which output buffer 604 can generate differential output signals VOUT_P and VOUT_N.

[0081] As used herein, the terms “circuit” and “circuit system,” including the term “processing circuit system” and related terms, refer to any suitable combination of analog or digital circuit elements, hardware, firmware, software, etc.; including but not limited to application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), microcontrollers, and microprocessors. It should be understood that the term “circuit system” encompasses both non-volatile and volatile memory devices, including but not limited to random access memory (RAM), read-only memory (ROM), etc., which may be implemented using any suitable means, such as SRAM, DRAM, or magnetic storage devices as examples of non-limiting examples.

[0082] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the foregoing detailed description will provide a convenient guide for those skilled in the art to implement the described embodiments or embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which includes known and foreseeable equivalents at the time of filing of this patent application.

Claims

1. An oscillator characterized by, include: An inverter, which includes a first input and a first output; A non-inverting buffer circuit system, comprising: Second input; Second output; A first transistor having a first gate terminal and a first source terminal; and The second transistor has a second gate terminal and a second source terminal; A first inductor-capacitor (LC) tank circuit is coupled between the first input of the inverter and the second output of the non-inverting buffer circuit system; and A second LC slot path is coupled between the first output of the inverter and the second input of the non-inverting buffer circuit system, wherein... The first gate terminal of the first transistor is coupled to the second input of the non-inverting buffer circuit system. The second gate terminal of the second transistor is coupled to the second input of the non-inverting buffer circuit system. The first source terminal of the first transistor is coupled to the second output of the non-inverting buffer circuit system. The second source terminal of the second transistor is coupled to the second output of the non-inverting buffer circuit system. The first source terminal and the second source terminal are individually DC biased, and The first gate terminal and the second gate terminal are individually DC biased.

2. The oscillator of claim 1, wherein The non-inverting buffer circuit system further includes: A first inductor, coupled between a voltage source and the first gate terminal of the first transistor, wherein the first gate terminal is DC biased via the first inductor; and A second inductor is coupled between the reference node and the second gate terminal of the second transistor, wherein the second gate terminal is DC biased via the second inductor.

3. The oscillator of claim 2, wherein The second LC tank circuit includes the first inductor and the second inductor.

4. The oscillator of claim 3, wherein The non-inverting buffer circuit system further includes: A first capacitor is coupled between the second input of the non-inverting buffer circuit system and the first gate terminal of the first transistor. A second capacitor is coupled between the second input of the non-inverting buffer circuit system and the second gate terminal of the second transistor. A third capacitor is coupled between the second output of the non-inverting buffer circuit system and the first source terminal of the first transistor; and A fourth capacitor is coupled between the second output of the non-inverting buffer circuit system and the second source terminal of the second transistor.

5. A series resonant oscillator characterized by, include: Inverter; A non-inverting buffer circuit system, comprising: A first transistor having a first control terminal and a first current-carrying terminal; and The second transistor has a second control terminal and a second current-carrying terminal, wherein the first control terminal and the second control terminal are individually DC biased, and the first current-carrying terminal and the second current-carrying terminal are individually DC biased. A first inductor-capacitor (LC) tank circuit is coupled between the inverter and the non-inverting buffer circuit system; and The second LC slot is coupled between the inverter and the non-inverting buffer circuit system.

6. The series resonant oscillator of claim 5, wherein, The non-inverting buffer circuit system further includes: A first resistor, coupled between a reference node and the first current-carrying terminal of the first transistor, wherein the first current-carrying terminal is DC biased via the first resistor; and A second resistor is coupled between a voltage source and the second current-carrying terminal of the second transistor, wherein the second current-carrying terminal is DC biased via the second resistor.

7. The series resonant oscillator of claim 6, wherein, The non-inverting buffer circuit system further includes: A third resistor is coupled between the voltage source and the first control terminal of the first transistor, wherein the first control terminal is DC biased via the third resistor; and A fourth resistor is coupled between the reference node and the second control terminal of the second transistor, wherein the second control terminal is DC biased via the fourth resistor.

8. The series resonant oscillator of claim 6, wherein, The non-inverting buffer circuit system further includes: A first inductor, coupled between the voltage source and the first control terminal of the first transistor, wherein the first control terminal is DC biased via the first inductor; and A second inductor is coupled between the reference node and the second control terminal of the second transistor, wherein the second control terminal is DC biased via the second inductor.

9. The series resonant oscillator of claim 8, wherein, The second LC tank circuit includes the first inductor and the second inductor.

10. The series resonant oscillator of claim 9, wherein, The non-inverting buffer circuit system further includes: A first capacitor is coupled between the input of the non-inverting buffer circuit system and the first control terminal of the first transistor. A second capacitor is coupled between the input of the non-inverting buffer circuit system and the second control terminal of the second transistor; A third capacitor is coupled between the output of the non-inverting buffer circuit system and the first current-carrying terminal of the first transistor; and A fourth capacitor is coupled between the output of the non-inverting buffer circuit system and the second current-carrying terminal of the second transistor.

Images