A power amplifier circuit integrating gain adjustment and bias adjustment and an adjustable power amplifier
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING FUHUXI TECHNOLOGY CO LTD
- Filing Date
- 2026-03-26
- Publication Date
- 2026-06-19
Smart Images
Figure CN122247352A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power amplifier circuit technology, and particularly relates to a power amplifier circuit with integrated gain adjustment and bias adjustment, and an adjustable power amplifier. Background Technology
[0002] As the core signal amplification unit in analog electronic systems, power amplifiers directly determine the operational stability and signal control accuracy of downstream equipment through their output drive capability, gain adjustment accuracy, and signal fidelity. They are widely used in key technology areas such as semiconductor device driving, display imaging, communication measurement and control, medical and industrial testing. In semiconductor driving scenarios, they can serve as driving units for PIN diodes and power MOSFETs, providing precise control signals and sufficient drive current. In display imaging, they are used for signal driving of OLED and CCD panels, ensuring pixel output uniformity. In communication and measurement and control, they can provide dynamic power support for base station envelope tracking modules and can also be integrated into automated testing equipment to achieve high-precision signal excitation. In the medical and industrial fields, they are commonly used in ultrasonic electric drives and waveform generation equipment to meet the requirements of high-power signal amplification and stable output.
[0003] Traditional power amplifiers currently have significant technical shortcomings in practical engineering applications, making them difficult to adapt to diverse and demanding usage requirements. These shortcomings are specifically reflected in the following three aspects: 1. Insufficient power output under high load driving scenarios: Traditional power amplifiers mostly adopt a single power operational amplifier architecture. Limited by the maximum output current and power density of a single chip, in high load driving scenarios such as ultrasonic electric drive and base station envelope tracking, the output power is prone to saturation and insufficient load driving capability, which in turn leads to increased signal distortion and equipment failure. Simply upgrading the specifications of a single chip will significantly increase hardware costs and heat dissipation pressure, and the power increase is limited, which cannot meet the requirements for long-term stable operation under high load.
[0004] 2. Poor gain adjustment flexibility and high risk of signal distortion: Most traditional power amplifiers are designed with fixed gain, which can only adapt to input signals of a specific amplitude. In scenarios such as automatic testing and waveform generation that require multi-amplitude signal output, an external gain adjustment module must be added, which not only increases the complexity and cost of the system, but also easily introduces additional noise. The few solutions with adjustable gain function mostly achieve gain adjustment by directly changing the value of the feedback resistor. This method is prone to disrupting the phase balance of the amplifier, resulting in poor signal linearity and increased distortion. In scenarios such as OLED driving and CCD driving, which have strict requirements for signal fidelity, it will seriously affect the working performance of the equipment.
[0005] 3. Lack of integrated DC offset adjustment capability and strong dependence on signal source: Traditional power amplifiers generally do not have DC offset adjustment function. They can only amplify the DC component of the input signal. When in use, they need to rely on special equipment such as function signal generators to generate a signal with preset DC bias in order to meet the working requirements of scenarios such as PIN diode driving and ultrasonic electric driving. If the input signal has no DC bias, an external bias circuit needs to be built, which not only increases the system size, but also easily leads to the instability of the overall system due to poor compatibility between the bias signal and the amplified signal.
[0006] In summary, existing power amplifiers cannot simultaneously meet the three core requirements of high load power output, low distortion adjustable gain, and integrated DC offset adjustment, making it difficult to meet the diverse application needs of multiple fields such as semiconductor driving, display imaging, and communication measurement and control. Therefore, there is an urgent need for an integrated, high-performance, and highly adaptable power amplifier solution. Summary of the Invention
[0007] The purpose of this invention is to address the aforementioned technical problems by providing a power amplifier circuit and an adjustable power amplifier that integrates gain and bias adjustment.
[0008] In view of this, the present invention provides a power amplifier circuit integrating gain adjustment and bias adjustment, comprising: The core amplification module uses a parallel architecture of two power operational amplifiers for signal amplification and current balancing under high load. The power supply module is used to supply power to each module; The gain adjustment module, whose output is connected to the signal input of the core amplifier module, is used to achieve adjustable gain; The bias adjustment module, whose output is connected to the bias signal input of the core amplification module, is used to achieve adjustable DC offset. Input / output modules are used to adapt signal inputs and outputs to load impedance.
[0009] Furthermore, the core amplification module includes a first power operational amplifier, a second power operational amplifier, a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; One end of the first resistor is connected to the non-inverting input of the first power operational amplifier and the non-inverting input of the second power operational amplifier, and the other end serves as the signal input of the core amplification module. The sixth resistor connects the inverting input of the first power operational amplifier to ground, and the seventh resistor connects the inverting input of the second power operational amplifier to ground. The resistance values of the sixth and seventh resistors are equal. The fourth resistor and the first capacitor are connected in parallel between the inverting input and the output of the first power operational amplifier, and the fifth resistor and the second capacitor are connected in parallel between the inverting input and the output of the second power operational amplifier. The resistance values of the fourth and fifth resistors are equal, and the capacitance values of the first and second capacitors are equal. One end of the second and third resistors are connected to each other to form a common connection point as the output of the core amplification module. The other end of the second resistor is electrically connected to the output of the first power operational amplifier, and the other end of the third resistor is electrically connected to the output of the second power operational amplifier.
[0010] Furthermore, the gain adjustment module includes a non-inverting adder circuit, the output of which is electrically connected to the input of the adjustable attenuation network, for superimposing and conditioning the input signal and the reference voltage signal before sending it to the adjustable attenuation network.
[0011] Furthermore, the gain adjustment module also includes an adjustable attenuation network, the output of which is electrically connected to the signal input of the core amplification module.
[0012] Furthermore, the adjustable attenuation network adopts a multi-level adjustable voltage divider structure, including a first rotary encoder, N level resistors and a twelfth resistor; the N level resistors are respectively connected to the level pins of the first rotary encoder; one end of the twelfth resistor is electrically connected to the common pin of the first rotary encoder, and the other end serves as the output terminal of the adjustable attenuation network and is electrically connected to the first resistor of the core amplification module.
[0013] Furthermore, the bias adjustment module includes a non-inverting adder circuit, which includes a third operational amplifier, a fourth operational amplifier, a linear potentiometer, a first single-pole double-throw switch, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, and a third capacitor. The linear potentiometer is connected to a positive power supply at one end and a negative power supply at the other end, with its sliding end electrically connected to the non-inverting input of the third operational amplifier; the thirteenth resistor is connected in parallel between the inverting input and output of the third operational amplifier; the moving end of the first single-pole double-throw switch is electrically connected to one end of the fourteenth resistor, the first stationary end is electrically connected to the output of the third operational amplifier, and the second stationary end is grounded; the other end of the fourteenth resistor is electrically connected to the non-inverting input of the fourth operational amplifier; one end of the fifteenth resistor is connected to an external input signal, and the other end is electrically connected to the non-inverting input of the fourth operational amplifier; the sixteenth resistor and the third capacitor are connected in parallel between the inverting input and output of the fourth operational amplifier; the seventeenth resistor connects the inverting input of the fourth operational amplifier to ground.
[0014] Furthermore, the first single-pole double-throw switch is used to control the input and output of the bias signal. When the switch is switched to the output of the third operational amplifier, the bias is input, and when it is switched to ground, the bias is canceled.
[0015] Furthermore, the input / output module includes an input interface, an output interface, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a fourth capacitor, and a second single-pole double-throw switch; The input interface is electrically connected to the moving end of the second single-pole double-throw switch. The first stationary end of the second single-pole double-throw switch is grounded through the eighteenth resistor, and the second stationary end is grounded through the nineteenth resistor, which is used to switch the input impedance matching mode. The output end of the core amplification module is electrically connected to the output interface after being connected in series with the twentieth and twenty-first resistors. The fourth capacitor and the twenty-second resistor are connected in parallel between the common node of the twentieth and twenty-first resistors and ground.
[0016] Furthermore, the input interface is an SMA interface, which can be switched between 50Ω impedance matching and 1MΩ impedance matching via a second single-pole double-throw switch.
[0017] Secondly, the present invention also proposes an adjustable power amplifier, which employs a power amplifier circuit with integrated gain adjustment and bias adjustment.
[0018] The beneficial effects of this invention are: This invention achieves high load drive capability, adjustable gain, and DC offset adjustment by adopting a dual-power operational amplifier parallel architecture, integrating gain adjustment, bias adjustment, input-output matching, and unified power supply. It solves the problems of insufficient power, gain distortion, and lack of bias adjustment in traditional power amplifiers, and improves the versatility and stability of the system. Attached Figure Description
[0019] Figure 1 A schematic diagram of a power amplifier circuit with integrated gain and bias adjustment provided in an embodiment of the present invention; Figure 2 This is a top-view interface diagram provided in an embodiment of the present invention; Figure 3 This is a graph showing the test results of small-signal low-load frequency response provided in an embodiment of the present invention; Figure 4 This is a graph showing the test results of small-signal high-load frequency response provided in an embodiment of the present invention; Figure 5 The graph shows the test results of the large signal low load frequency response provided in the embodiment of the present invention. Figure 6 The graph shows the test results of the high-signal, high-load frequency response provided in the embodiments of the present invention. Figure 7 This is a graph showing the test results of low-load frequency response after small-signal superposition and DC offset provided in an embodiment of the present invention. Figure 8 The graph shows the test results of high load frequency response after small signal superposition and DC offset provided in the embodiments of the present invention. Detailed Implementation
[0020] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.
[0021] In the description of this application, it should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. For ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.
[0022] It should be noted that the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0023] It should be noted that in the description of this application, the directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application. The directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.
[0024] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
[0025] Reference Figure 1 , Figures 3-8 A power amplifier circuit integrating gain and bias adjustment, comprising: The core amplification module uses a parallel architecture of two power operational amplifiers for signal amplification and current balancing under high load. The power supply module is used to supply power to each module; The gain adjustment module, whose output is connected to the signal input of the core amplifier module, is used to achieve adjustable gain; The bias adjustment module, whose output is connected to the bias signal input of the core amplification module, is used to achieve adjustable DC offset. Input / output modules are used to adapt signal inputs and outputs to load impedance.
[0026] This application achieves high load drive capability, adjustable gain, and DC offset adjustment by adopting a dual-power operational amplifier parallel architecture, integrating gain adjustment, bias adjustment, input-output matching, and unified power supply. This solves the problems of insufficient power, gain distortion, and lack of bias adjustment in traditional power amplifiers, and improves the system's versatility and stability.
[0027] In the example of this application, the core amplification module includes a first power operational amplifier, a second power operational amplifier, a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; One end of the first resistor is connected to the non-inverting input of the first power operational amplifier and the non-inverting input of the second power operational amplifier, and the other end serves as the signal input of the core amplification module. The sixth resistor connects the inverting input of the first power operational amplifier to ground, and the seventh resistor connects the inverting input of the second power operational amplifier to ground. The resistance values of the sixth and seventh resistors are equal. The fourth resistor and the first capacitor are connected in parallel between the inverting input and the output of the first power operational amplifier, and the fifth resistor and the second capacitor are connected in parallel between the inverting input and the output of the second power operational amplifier. The resistance values of the fourth and fifth resistors are equal, and the capacitance values of the first and second capacitors are equal. One end of the second and third resistors are connected to each other to form a common connection point as the output of the core amplification module. The other end of the second resistor is electrically connected to the output of the first power operational amplifier, and the other end of the third resistor is electrically connected to the output of the second power operational amplifier.
[0028] Both the first and second power operational amplifiers use ADA4870; the first resistor is 560Ω, the second and third resistors are both 0.2Ω, the fourth and fifth resistors are both 1kΩ, and the first and second capacitors are both 1.5pF; the core amplification module has a fixed gain of 5 times, and the overall circuit bandwidth covers 30MHz.
[0029] As a preferred example of the present invention, by combining in-phase addition with adjustable attenuation, low noise, low distortion, and stable adjustable gain are achieved, avoiding phase imbalance and waveform distortion caused by traditional changes in feedback resistor.
[0030] In the example of this application, the gain adjustment module includes a non-inverting adder circuit, the output of which is electrically connected to the input of an adjustable attenuation network, for superimposing and conditioning the input signal and a reference voltage signal before sending it to the adjustable attenuation network; the gain adjustment module also includes an adjustable attenuation network, the output of which is electrically connected to the signal input of the core amplification module.
[0031] As a preferred example of the present invention, by combining in-phase addition with adjustable attenuation, low noise, low distortion, and stable adjustable gain are achieved, avoiding phase imbalance and waveform distortion caused by traditional changes in feedback resistor.
[0032] In the example of this application, the adjustable attenuation network adopts a multi-level adjustable voltage divider structure, including a first rotary encoder, N level resistors and a twelfth resistor; the N level resistors are respectively connected to the level pins of the first rotary encoder; one end of the twelfth resistor is electrically connected to the common pin of the first rotary encoder, and the other end is used as the output terminal of the adjustable attenuation network and electrically connected to the first resistor of the core amplification module.
[0033] The adjustable attenuation network is preferably configured with 2-6 levels. The level resistors include the eighth resistor (normally off), the ninth resistor (4kΩ), the tenth resistor (2kΩ), the eleventh resistor (1kΩ), and the twelfth resistor (1kΩ). The attenuation factor is calculated using the formula: R12 / (R_selected resistor + R12). This, in conjunction with the core amplification module, enables the system to achieve an adjustable gain of 1 to 5 times.
[0034] As a preferred example of the present invention, the multi-level rotary encoder voltage divider achieves precise level gain adjustment, convenient operation, good attenuation linearity, low signal distortion, and adaptability to input signals of different amplitudes.
[0035] In the example of this application, the bias adjustment module includes a non-inverting adder circuit, which includes a third operational amplifier, a fourth operational amplifier, a linear potentiometer, a first single-pole double-throw switch, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, and a third capacitor. The linear potentiometer is connected to a positive power supply at one end and a negative power supply at the other end, with its sliding end electrically connected to the non-inverting input of the third operational amplifier; the thirteenth resistor is connected in parallel between the inverting input and output of the third operational amplifier; the moving end of the first single-pole double-throw switch is electrically connected to one end of the fourteenth resistor, the first stationary end is electrically connected to the output of the third operational amplifier, and the second stationary end is grounded; the other end of the fourteenth resistor is electrically connected to the non-inverting input of the fourth operational amplifier; one end of the fifteenth resistor is connected to an external input signal, and the other end is electrically connected to the non-inverting input of the fourth operational amplifier; the sixteenth resistor and the third capacitor are connected in parallel between the inverting input and output of the fourth operational amplifier; the seventeenth resistor connects the inverting input of the fourth operational amplifier to ground.
[0036] The third and fourth operational amplifiers both use THS4631; the linear potentiometer is 10kΩ, the thirteenth resistor is 10kΩ, the fourteenth, fifteenth, sixteenth, and seventeenth resistors are all 1kΩ, and the third capacitor is 0.5pF; the fourth operational amplifier is configured as a single-gain non-inverting adder, which can achieve precise superposition of the bias signal and the input signal.
[0037] As a preferred example of the present invention, by using dual operational amplifiers in-phase addition, linear potentiometers and switch control, a wide range of continuously adjustable DC bias, precise superposition of bias and AC signal, and stable output baseline are achieved, reducing the dependence on the DC component of the signal source.
[0038] In the example of this application, the first single-pole double-throw switch is used to control the input and output of the bias signal. When the switch is switched to the output of the third operational amplifier, the bias is input, and when it is switched to ground, the bias is canceled.
[0039] As a preferred example of the present invention, the bias is quickly connected / disconnected via a switch, which satisfies the need for flexible switching of DC offset in different scenarios and makes it more convenient to use.
[0040] In the example of this application, the input / output module includes an input interface, an output interface, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a fourth capacitor, and a second single-pole double-throw switch; The input interface is electrically connected to the moving end of the second single-pole double-throw switch. The first stationary end of the second single-pole double-throw switch is grounded through the eighteenth resistor, and the second stationary end is grounded through the nineteenth resistor, which is used to switch the input impedance matching mode. The output end of the core amplification module is electrically connected to the output interface after being connected in series with the twentieth and twenty-first resistors. The fourth capacitor and the twenty-second resistor are connected in parallel between the common node of the twentieth and twenty-first resistors and ground.
[0041] The eighteenth resistor is 50Ω, the nineteenth resistor is 1MΩ, the twentieth and twenty-first resistors are both 0.5Ω, and the fourth capacitor and the twenty-second resistor are normally open; both the input and output interfaces use SMA interfaces, and the output interface is also compatible with BNC interfaces.
[0042] As a preferred example of the present invention, multi-load impedance adaptation, reduced signal reflection, purer output waveform, and more stable performance with capacitive loads are achieved through input impedance switching, output series matching, and parallel RC network.
[0043] In the example of this application, the input interface is an SMA interface, which can be switched between 50Ω impedance matching and 1MΩ impedance matching via a second single-pole double-throw switch.
[0044] As a preferred example of the present invention, it supports one-click switching of standard impedances such as 50Ω / 1MΩ, is compatible with signal sources and test equipment, and improves scene adaptability.
[0045] like Figure 2 As shown, the present invention also proposes an adjustable power amplifier, which employs a power amplifier circuit with integrated gain adjustment and bias adjustment.
[0046] The adjustable power amplifier also includes a housing and a heat sink. The housing surface is equipped with a gain adjustment knob, a bias adjustment knob, a bias adjustment switch, a power switch, and a status indicator light. The power supply voltage is 10-15V. After testing, the circuit can support stable output under various scenarios such as small signal / large signal, low load / high load, and biased / unbiased conditions, with a frequency response covering 30MHz.
[0047] This application integrates the aforementioned power amplifier circuit into the entire amplifier system, achieving high power, low distortion, adjustable gain, and adjustable bias, directly forming a marketable product.
[0048] The embodiments of this application have been described above with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. This application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.
Claims
1. A power amplification circuit integrating gain adjustment and bias adjustment, characterized by, include: The core amplification module uses a parallel architecture of two power operational amplifiers for signal amplification and current balancing under high load. The power supply module is used to supply power to each module; The gain adjustment module, whose output is connected to the signal input of the core amplifier module, is used to achieve adjustable gain; The bias adjustment module, whose output is connected to the bias signal input of the core amplification module, is used to achieve adjustable DC offset. Input / output modules are used to adapt signal inputs and outputs to load impedance.
2. The power amplifier circuit according to claim 1, characterized in that, The core amplification module includes a first power operational amplifier, a second power operational amplifier, a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; One end of the first resistor is connected to the non-inverting input of the first power operational amplifier and the non-inverting input of the second power operational amplifier, and the other end serves as the signal input of the core amplification module. The sixth resistor connects the inverting input of the first power operational amplifier to ground, and the seventh resistor connects the inverting input of the second power operational amplifier to ground. The resistance values of the sixth and seventh resistors are equal. The fourth resistor and the first capacitor are connected in parallel between the inverting input and the output of the first power operational amplifier, and the fifth resistor and the second capacitor are connected in parallel between the inverting input and the output of the second power operational amplifier. The resistance values of the fourth and fifth resistors are equal, and the capacitance values of the first and second capacitors are equal. One end of the second and third resistors are connected to each other to form a common connection point as the output of the core amplification module. The other end of the second resistor is electrically connected to the output of the first power operational amplifier, and the other end of the third resistor is electrically connected to the output of the second power operational amplifier.
3. The power amplifier circuit according to claim 1, characterized in that, The gain adjustment module includes a non-inverting adder circuit, the output of which is electrically connected to the input of an adjustable attenuation network, and is used to superimpose and condition the input signal and the reference voltage signal before sending it to the adjustable attenuation network.
4. The power amplifier circuit according to claim 3, characterized in that, The gain adjustment module also includes an adjustable attenuation network, the output of which is electrically connected to the signal input of the core amplification module.
5. The power amplifier circuit according to claim 4, characterized in that, The adjustable attenuation network adopts a multi-level adjustable voltage divider structure, including a first rotary encoder, N level resistors and a twelfth resistor; the N level resistors are respectively connected to the level pins of the first rotary encoder; one end of the twelfth resistor is electrically connected to the common pin of the first rotary encoder, and the other end serves as the output terminal of the adjustable attenuation network and is electrically connected to the first resistor of the core amplification module.
6. The power amplifier circuit according to claim 1, characterized in that, The bias adjustment module includes a non-inverting adder circuit, which includes a third operational amplifier, a fourth operational amplifier, a linear potentiometer, a first single-pole double-throw switch, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, and a third capacitor. The linear potentiometer is connected to a positive power supply at one end and a negative power supply at the other end, with its sliding end electrically connected to the non-inverting input of the third operational amplifier; the thirteenth resistor is connected in parallel between the inverting input and output of the third operational amplifier; the moving end of the first single-pole double-throw switch is electrically connected to one end of the fourteenth resistor, the first stationary end is electrically connected to the output of the third operational amplifier, and the second stationary end is grounded; the other end of the fourteenth resistor is electrically connected to the non-inverting input of the fourth operational amplifier; one end of the fifteenth resistor is connected to an external input signal, and the other end is electrically connected to the non-inverting input of the fourth operational amplifier; the sixteenth resistor and the third capacitor are connected in parallel between the inverting input and output of the fourth operational amplifier; the seventeenth resistor connects the inverting input of the fourth operational amplifier to ground.
7. The power amplifier circuit according to claim 6, characterized in that, The first single-pole double-throw switch is used to control the input and output of the bias signal. When the switch is switched to the output of the third operational amplifier, the bias is input, and when it is switched to ground, the bias is canceled.
8. The power amplifier circuit according to claim 1, characterized in that, The input / output module includes an input interface, an output interface, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a fourth capacitor, and a second single-pole double-throw switch; The input interface is electrically connected to the moving end of the second single-pole double-throw switch. The first stationary end of the second single-pole double-throw switch is grounded through the eighteenth resistor, and the second stationary end is grounded through the nineteenth resistor, which is used to switch the input impedance matching mode. The output end of the core amplification module is electrically connected to the output interface after being connected in series with the twentieth and twenty-first resistors. The fourth capacitor and the twenty-second resistor are connected in parallel between the common node of the twentieth and twenty-first resistors and ground.
9. The power amplifier circuit according to claim 8, characterized in that, The input interface is an SMA interface, which can be switched between 50Ω impedance matching and 1MΩ impedance matching via a second single-pole double-throw switch.
10. An adjustable power amplifier, characterized in that, The power amplifier circuit employs the integrated gain adjustment and bias adjustment as described in any one of claims 1-9.