A power amplifier gate voltage control circuit
By combining processing and control modules, and utilizing level and voltage dividers as well as the control of NMOS and PMOS transistors, the accuracy and stability issues of gate voltage control in power amplifiers are resolved, achieving stable gate voltage control and gain performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING LEADING INNOVATION MEDICAL VALLEY CO LTD
- Filing Date
- 2023-03-09
- Publication Date
- 2026-06-19
Smart Images
Figure CN116208105B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of power amplifiers, and more particularly to a power amplifier gate voltage control circuit. Background Technology
[0002] Power amplifiers are mainly used in radio frequency communication systems to drive and amplify weak electrical signals from a signal source to achieve the required power level, which is then fed to the antenna for radiation or used for other purposes.
[0003] It is understood that when using a power amplifier, in addition to controlling the gate voltage to turn the power amplifier on or off to achieve certain functions, it is also necessary to control the gate voltage so that the power amplifier output is amplified by a specified gain coefficient to achieve the desired gain effect.
[0004] However, it is currently difficult to achieve precise and stable control of the gate voltage. Summary of the Invention
[0005] In order to accurately and stably control the gate voltage, this application provides a power amplifier gate voltage control circuit.
[0006] This application provides a power amplifier gate voltage control circuit, which adopts the following technical solution:
[0007] A power amplifier gate voltage control circuit includes a processing module and a control module;
[0008] The processing module has a level output terminal and a voltage output terminal. The level output terminal is used to output a level signal, and the voltage output terminal is used to output a high-precision voltage signal. The control module includes a first resistor, a second resistor, a third resistor, a fourth resistor, an NMOS transistor, and a PMOS transistor.
[0009] One end of the first resistor is connected to the level output terminal, and the other end is connected to the second resistor. The end of the second resistor away from the first resistor is grounded. The common terminal of the first resistor and the second resistor serves as the first enable signal output terminal. The first enable signal is used to drive the driver stage power amplifier.
[0010] The gate of the NMOS transistor is connected to the common terminal of the first and second resistors, the source is grounded, the drain is connected to one end of the third resistor, the other end of the third resistor is connected to the fourth resistor, and the free end of the fourth resistor is connected to the voltage output terminal; the gate of the PMOS transistor is connected to the common terminal of the third and fourth resistors, the source is connected to the voltage output terminal, and the drain serves as the output terminal of the second enable signal, which is used to drive the final stage power amplifier.
[0011] By adopting the above technical solution, the processing module outputs a level through the level output terminal, which is then precisely divided by the first and second resistors to provide a stable enable signal for the driver stage power amplifier. When the NMOS transistor is turned on, the precise voltage output from the voltage output terminal is divided by the third and fourth resistors and output together with the precise voltage output from the voltage output terminal to drive the final stage power amplifier, thereby accurately and stably controlling the gate voltage directly.
[0012] Optionally, the accuracy of the voltage signal is one ten-thousandth.
[0013] By adopting the above technical solution, the accuracy of the gate voltage can be improved.
[0014] Optionally, the processing module includes a first processing unit and a second processing unit. The first processing unit has a level output terminal and is an MCU or FPGA. The second processing unit has a voltage output terminal and is an MCU or a digital-to-analog converter.
[0015] Optionally, both the first resistor and the second resistor are selected as resistors with a resistance value in the KΩ range.
[0016] By adopting the above technical solution, the voltage division is accurate, and a stable voltage and low current are provided for the NMOS transistor and the first enable signal output terminal.
[0017] Optionally, both the third and fourth resistors are selected as resistors with a resistance value in the KΩ range.
[0018] By adopting the above technical solution, the voltage division is accurate, and a stable voltage and low current are provided for the PMOS transistor.
[0019] Optionally, a fifth resistor is also included, one end of which is connected to the drain of the PMOS transistor, and the other end serves as the output terminal of the second enable signal.
[0020] By adopting the above technical solution, the gate of the logic circuit and the power amplifier can be isolated to provide a stable gate voltage value with low current.
[0021] Optionally, a sixth resistor is also included, one end of which is connected to the drain of the PMOS transistor, and the other end is grounded.
[0022] By adopting the above technical solution, the influence of the leakage current of the PMOS transistor on the output terminal of the second enable signal can be eliminated.
[0023] Optionally, it also includes a first capacitor and a second capacitor; the first capacitor is connected in parallel with the second resistor, and the second capacitor is connected in parallel with the sixth resistor.
[0024] By adopting the above technical solution, interference of radio frequency signals on logic levels can be prevented.
[0025] Optionally, a third capacitor may also be included, with one end connected to the voltage output terminal and the other end grounded.
[0026] By adopting the above technical solution, the third capacitor can store energy, so that when the voltage at the voltage output terminal changes, no glitches will be generated on the rising and falling edges, thereby protecting the power amplifier.
[0027] In summary, this application includes at least one of the following beneficial technical effects:
[0028] The processing module outputs a voltage level through a level output terminal, which is then precisely divided by the first and second resistors to provide a stable enable signal for the driver-stage power amplifier. When the NMOS transistor is turned on, the precise voltage output from the voltage output terminal is divided by the third and fourth resistors and output together with the precise voltage output from the voltage output terminal to drive the final-stage power amplifier, thereby accurately and stably controlling the gate voltage directly. Attached Figure Description
[0029] Figure 1 This is a circuit diagram of the power amplifier gate voltage control circuit according to an embodiment of this application.
[0030] Explanation of reference numerals in the attached diagram: 1. Processing module; 2. First processing unit; 3. Second processing unit; 4. Level output terminal; 5. Voltage output terminal; 6. First enable signal output terminal; 7. Second enable signal output terminal; 8. Control module. Detailed Implementation
[0031] To make the purpose, technical solution, and advantages of this application clearer, the following description is provided in conjunction with the appendix. Figure 1 The present application will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the application.
[0032] This application discloses a power amplifier gate voltage control circuit, mainly used to stably output a precise enable signal to control the gate voltage of the power amplifier. Furthermore, the power amplifier gate voltage control circuit of this application can be adjusted according to actual needs to achieve control of the gate voltage of multi-stage power amplifiers.
[0033] Reference Figure 1The power amplifier gate voltage control circuit includes a processing module 1 and a control module 8. The processing module 1 has a level output terminal 4 and a voltage output terminal 5. The processing module 1 outputs a level signal and a voltage signal with an accuracy of one ten-thousandth through the voltage output terminal 5. The control module 8 is connected to the processing module 1 through the level output terminal 4 and the voltage output terminal 5, and can stably output a precise voltage enable signal under the combined control of the level and voltage signals to drive the power amplifier.
[0034] The processing module 1 includes a first processing unit 2 and a second processing unit 3.
[0035] The first processing unit 2 has a level output terminal 4, which can output a level signal through the level output terminal 4. Preferably, the first processing unit 2 can be an MCU chip or an FPGA chip.
[0036] The second processing unit 3 has a voltage output terminal 5, which can output a voltage signal with an accuracy of one ten-thousandth, providing a high-precision input voltage for controlling the gate voltage of the power amplifier. Preferably, the second processing unit 3 can be an MCU chip or an analog-to-digital converter chip. The voltage value output by the voltage output terminal 5 is 0.7V~3.3V.
[0037] It is understood that in other embodiments, the processing module 1 may also use an MCU chip to achieve the function of simultaneously outputting level signals and high-precision voltage signals.
[0038] The control module 8 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a second capacitor C2, a third capacitor C3, an NMOS transistor T1, and a PMOS transistor T2.
[0039] Specifically, one end of the first resistor R1 is connected to the level output terminal 4, and the other end is connected to the second resistor R2. The end of the second resistor R2 furthest from the first resistor R1 is grounded. The first capacitor C1 is connected in parallel with the second resistor R2. The common terminal of the first resistor R1 and the second resistor R2 serves as the first enable signal output terminal 6, used to output a first enable signal capable of driving the driver stage power amplifier.
[0040] It is understood that the first processing unit 2 can control the level of the signal, i.e., to achieve pulse width modulation to control the duty cycle. Since the first resistor R1 and the second resistor R2 are connected in series and form a voltage divider, the voltage at the common terminal of the first resistor R1 and the second resistor R2 changes with the signal level. That is, when the signal level is high, the common terminal of the first resistor R1 and the second resistor R2 is at a high potential. When the signal level is low, the common terminal of the first resistor R1 and the second resistor R2 is at a low level, thus enabling the driver-stage power amplifier connected to the first enable signal output terminal 6 to receive either a low-level signal or a high-level signal, providing a switching function to the driver-stage power amplifier. The switching speed is determined by the first processing unit 2, preferably in the nanosecond range. Both the first resistor R1 and the second resistor R2 are selected with resistance values in the kΩ range, enabling precise voltage division and low current. Furthermore, the second resistor R2 also acts as a pull-down resistor to keep the potential of the common terminal of the first resistor R1 and the second resistor R2 at a low level when the level signal state is uncertain, thus providing a definite level state for the NMOS transistor T1 and the driver stage power amplifier. Simultaneously, the first capacitor C1 is an RF filter capacitor, which can prevent RF signals from interfering with the logic level. Preferably, the voltage of the level signal is between 2.7V and 3.3V.
[0041] The gate of NMOS transistor T1 is connected to the common terminal of the first resistor R1 and the second resistor R2, the source is grounded, the drain is connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to the fourth resistor R4, and the free end of the fourth resistor R4 is connected to the voltage output terminal 5. One end of the third capacitor C3 is connected to the voltage output terminal 5, and the other end is grounded.
[0042] It can be understood that since the third resistor R3 and the fourth resistor R4 are connected in series and form a voltage divider, the voltage at the common terminal of the third resistor R3 and the fourth resistor R4 changes due to the on / off state of the NMOS transistor T1 and the voltage signal. Specifically, when the gate of the NMOS transistor T1 is connected to a high level, the NMOS transistor is in the on state, causing the end of the third resistor R3 connected to the drain of the NMOS transistor T1 to be grounded. At this time, the voltage across the third resistor R3 and the fourth resistor R4 is the voltage value reflected by the negative voltage signal, causing the voltage at the common terminal of the third resistor R3 and the fourth resistor R4 to change with the voltage signal. That is, when the voltage signal is at a high level, the potential value at the common terminal of the third resistor R3 and the fourth resistor R4 is higher. When the voltage signal is at a low level, the potential value at the common terminal of the third resistor R3 and the fourth resistor R4 is lower. Both the third resistor R3 and the fourth resistor R4 are chosen with resistance values in the kΩ range, enabling precise voltage division and low current. The third capacitor C3 is mainly used for energy storage, ensuring that no glitches or abrupt changes occur on the rising and falling edges of the voltage output terminal 5, thus protecting the power amplifier. Preferably, the third capacitor C3 is a uF-level capacitor.
[0043] The gate of PMOS transistor T2 is connected to the common terminal of the third resistor R3 and the fourth resistor R4, and its source is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the voltage output terminal 5, and its drain serves as the second enable signal output terminal 7, used to output a second enable signal capable of driving the final stage power amplifier. One end of the sixth resistor R6 is connected to the drain of PMOS transistor T2, and the other end is grounded. The second capacitor C2 is connected in parallel with the sixth resistor R6. When the gate of PMOS transistor T2 is connected to a low level, PMOS transistor T2 is in the on state, making the second enable signal output terminal 7 connected to the voltage output terminal 5. Conversely, when the gate of PMOS transistor T2 is connected to a high level, PMOS transistor T2 is in the off state. Thus, the first processing unit 2 and the second processing unit 3 control the switching state of the final stage power amplifier by controlling the output levels of the level output terminal 4 and the voltage output terminal 5. The turn-on and turn-off speed of the final stage power amplifier is jointly determined by the first processing unit 2 and the second processing unit 3, preferably in the nanosecond range to -5µs. The fifth resistor, R5, is primarily used to isolate the logic circuit from the gate of the power amplifier, providing a stable gate voltage value for low current operation. Simultaneously, the sixth resistor, R6, acts as a pull-down resistor, eliminating the influence of PMOS transistor leakage current on the second enable signal, thus making the second enable signal more stable. Preferably, the second capacitor, C2, is an RF filter capacitor to prevent RF signals from interfering with the logic level.
[0044] Furthermore, the power amplifier's start-up and shutdown process is as follows: When the level output terminal 4 is high, the first enable signal output terminal 6 outputs a high level to control the start-up of the driver stage power amplifier. When the gate potential of NMOS transistor T1 is greater than 0.45V, NMOS transistor T1 is turned on, the third resistor R3 and the fourth resistor R4 divide the voltage, and the common terminal potential of the third resistor R3 and the fourth resistor R4 reaches an inverted level. When the gate potential of PMOS transistor T2 is less than -0.45V, PMOS transistor T2 is turned on, the second enable signal output terminal 7 is at a precise high level, and the final stage amplifier starts under a precise gate voltage. When the level output terminal 4 is low, the first enable signal output terminal 6 outputs a low level to control the start-up of the driver stage power amplifier. When the gate potential of NMOS transistor T1 is less than 0.45V, NMOS transistor T1 is turned off, the third resistor R3 and the fourth resistor R4 do not divide the voltage, and the common terminal potential of the third resistor R3 and the fourth resistor R4 is the same as the potential of the voltage output terminal 5. When the gate potential of PMOS transistor T2 is 0V, PMOS transistor T2 is turned off. Under the action of the sixth resistor R6, the potential of the second enable signal output terminal 7 is also 0V. At this time, the final stage power amplifier is turned off.
[0045] It is understood that the level signal can be configured into a PWM waveform through the first processing unit 2. The pulse and frequency of this PWM waveform can be arbitrarily set. When the level signal is a PWM waveform, the first enable signal output terminal 6 can output a PWM modulation signal with a certain duty cycle. If the voltage signal is also always in a high-level state, the second enable signal output terminal 7 can output a PWM modulation signal with a certain duty cycle. The pulse width and frequency threshold of the PWM waveform depend on the processor performance, the PWM waveform state depends on the performance of the NMOD transistor T1 and the PMOS transistor T2 and the performance of the I / O pins of the first processing unit 2, and the rising and falling edges are also related to the above performance, preferably below 5µs.
[0046] It is worth noting that in this application, the NMOS transistor T1 and PMOS transistor T2 should be selected with low leakage current, preferably SI2301 and SI2302.
[0047] Of course, in order to control multi-stage power amplifiers, this application can also make adaptive adjustments based on the number of power amplifiers to be controlled as needed. Specifically, the enable signal driving each driver stage power amplifier is connected to the common terminal of the first resistor R1 and the second resistor R2.
[0048] The implementation principle of a power amplifier gate voltage control circuit according to an embodiment of this application is as follows: The level output by the processing module 1 through the level output terminal 4 is precisely divided by the first resistor and the second resistor and then output, which can provide a stable enable signal for the driver stage power amplifier. When the NMOS transistor is turned on, the precise voltage output by the voltage output terminal 5 is divided by the third resistor and the fourth resistor and then output, which together with the precise voltage output by the voltage output terminal 5 drives the final stage power amplifier, so as to directly control the gate voltage accurately and stably.
[0049] The above are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any feature disclosed in this specification (including the abstract and drawings) may be replaced by other equivalent or similar features unless specifically stated otherwise. That is, unless specifically stated otherwise, each feature is only one example of a series of equivalent or similar features.
Claims
1. A power amplifier gate voltage control circuit, characterized by: It includes a processing module (1) and a control module (8); The processing module (1) has a level output terminal (4) and a voltage output terminal (5). The level output terminal (4) is used to output a level signal, and the voltage output terminal (5) is used to output a voltage signal. The control module (8) includes a first resistor, a second resistor, a third resistor, a fourth resistor, an NMOS transistor, and a PMOS transistor. One end of the first resistor is connected to the level output terminal (4), and the other end is connected to the second resistor. The end of the second resistor away from the first resistor is grounded. The common terminal of the first resistor and the second resistor serves as the first enable signal output terminal (6). The first enable signal is used to drive the driver stage power amplifier. The gate of the NMOS transistor is connected to the common terminal of the first resistor and the second resistor. The source of the NMOS transistor is grounded. The drain of the NMOS transistor is connected to one end of the third resistor. The other end of the third resistor is connected to one end of the fourth resistor. The other end of the fourth resistor is connected to the voltage output terminal (5). The gate of the PMOS transistor is connected to the common terminal of the third resistor and the fourth resistor. The source of the PMOS transistor is connected to the voltage output terminal (5). The drain of the PMOS transistor serves as the second enable signal output terminal (7). The second enable signal is used to drive the final stage power amplifier. The accuracy of the voltage signal is one ten-thousandth.
2. The power amplifier gate voltage control circuit according to claim 1, characterized in that: The processing module (1) includes a first processing unit (2) and a second processing unit (3). The first processing unit (2) has a level output terminal (4) and is an MCU or FPGA. The second processing unit (3) has a voltage output terminal (5) and is an MCU or a digital-to-analog converter.
3. The power amplifier gate voltage control circuit according to claim 1, characterized in that: Both the first resistor and the second resistor are selected as resistors with a resistance value of KΩ or higher.
4. The power amplifier gate voltage control circuit according to claim 1, characterized in that: The third and fourth resistors are both selected from resistors with a resistance value of KΩ or higher.
5. The power amplifier gate voltage control circuit according to claim 1, characterized in that: It also includes a fifth resistor, one end of which is connected to the drain of the PMOS transistor, and the other end serves as the second enable signal output terminal (7).
6. The power amplifier gate voltage control circuit according to claim 5, characterized in that: It also includes a sixth resistor, one end of which is connected to the drain of the PMOS transistor, and the other end is grounded.
7. The power amplifier gate voltage control circuit according to claim 6, characterized in that: It also includes a first capacitor and a second capacitor; the first capacitor is connected in parallel with a second resistor, and the second capacitor is connected in parallel with a sixth resistor.
8. The power amplifier gate voltage control circuit according to claim 7, characterized in that: It also includes a third capacitor, one end of which is connected to the voltage output terminal (5), and the other end is grounded.