A fast response current limiting protection circuit applied to RS485 driver

Abstract

This invention discloses a fast-response current-limiting protection circuit for an RS485 driver, comprising a current sampling unit and a fast-response hysteresis comparator. The current sampling unit receives signals, and its output is connected to the fast-response hysteresis comparator. The fast-response hysteresis comparator receives the output voltage of the current sampling unit, amplifies and compares the received voltage, and outputs a control signal based on the comparison result. This invention, by setting the current sampling unit to sample the current of the power transistor, and connecting the output signal of the current sampling unit to the voltage conversion unit of the fast-response hysteresis comparator, can quickly and effectively respond to changes in the gate voltage signal of the power transistor, enabling the output control signal to quickly control the current flowing through the protected power transistor. This overcomes the problem in existing RS485 driver circuits where, in high-speed applications, the overcurrent protection response is untimely when a short circuit occurs on the A / B bus, causing excessive current and chip burnout during short circuits.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more specifically to a fast-response current-limiting protection circuit for RS485 drivers. Background Technology

[0002] RS485 is a low-cost and reliable communication standard widely used in industrial control, communication equipment, smart meters, inverters, security monitoring, and other fields. Typically, the RS485 interface A / B transmission bus is exposed outdoors, thus the A / B bus cable is susceptible to short circuits (A / B bus short-circuited to power supply, A / B bus short-circuited to ground, or A / B bus short-circuited itself). The RS485 interface defines corresponding electrical characteristics to prevent damage to the chip during short circuits. This necessitates limiting the current during A / B short circuits to avoid excessive current burning out the chip. Summary of the Invention

[0003] The purpose of this invention is to provide a fast-response current limiting protection circuit for RS485 drivers, overcoming the problem in the prior art where the overcurrent protection of RS485 driver circuits fails to respond in time when a short circuit occurs on the A / B bus in high-speed applications, resulting in excessive current and chip burnout when the chip is short-circuited.

[0004] This invention is achieved through the following technical solution:

[0005] A fast-response current-limiting protection circuit for RS485 drivers includes:

[0006] Current sampling unit and fast-response hysteresis comparator;

[0007] The current sampling unit is used to receive signals. Its input terminals are used to receive the first signal voltage, the second signal voltage, and the third signal voltage, respectively. Its output terminal is connected to a fast response hysteresis comparator.

[0008] The fast-response hysteresis comparator includes a bias unit, a voltage conversion unit, a hysteresis control unit, and a comparison output unit. The fast-response hysteresis comparator is used to receive the output voltage of the current sampling unit, amplify and compare the received voltage, and output a control signal based on the comparison result.

[0009] As an optional approach, the input terminals of the current sampling unit include an S port, a D port, and a PG port, which are used to receive the first signal voltage, the second signal voltage, and the third signal voltage, respectively; the output terminal of the current sampling unit is the CS_H port.

[0010] As an optional approach, the current sampling unit includes a sampling power transistor (PMS) and a resistor (R1). The gate of the sampling power transistor (PMS) is connected to the PG port, the drain is connected to the D port, and its source and one end of the resistor (R1) are connected to the CS_H port. The other end of the resistor (R1) is connected to the S port.

[0011] As an optional approach, the bias unit consists of a current source IB1 and a NOMS NM1. One end of the current source IB1 is connected to the power supply, and the other end of the current source IB1 is connected to the drain and gate of the NMOS transistor NM1. The source of NM1 is grounded.

[0012] As an optional configuration, the voltage conversion unit includes PMOS transistors PM1 and PM2, NMOS transistor NM2, resistors R2, R3, and R4; the source of PMOS transistor PM1 is connected to the CS_H port; the gate and drain of PM1 are connected to the drain of NMOS transistor NM2, and also to the gate of PM2; the source of NM2 is grounded; the drain of PM2 is connected to one end of resistor R2, and the other end of resistor R2 is grounded; the source of PM2 is connected to one end of resistor R3, and the other end of resistor R3 is connected to one end of resistor R4; it is also connected to the drain of PM3 in the hysteresis control unit, and the other end of resistor R4 is connected to the power supply.

[0013] As an optional configuration, the hysteresis control unit includes NMOS transistors NM3 and NM4, PMOS transistors PM3, PM4, and PM5, a Schmitt trigger SMT1, and an inverter INV1. The gate of NM3 is connected to the gate and drain of NM1 in the bias unit, and the drain of NM3 is connected to the gate and drain of PM4, as well as the gate of PM5. The source of PM4 is connected to the power supply, and the source of PM5 is also connected to the power supply. The gate of NM4 is connected to the drain of the output transistor PM2 in the voltage conversion unit. The drain of NM4 is connected to the drain of PM5, as well as the input of the Schmitt trigger SMT1. The output of the Schmitt trigger SMT1 is connected to the input of the inverter INV1, and the output of the inverter INV1 is connected to the gate of PM3.

[0014] As an optional configuration, the comparator output unit includes an NMOS transistor NM5, a PMOS transistor PM6, PM7, a resistor R5, and a capacitor C1. The gate of NM5 is connected to the drain of the voltage conversion unit output transistor PM2. The drain of NM5 is connected to both the gate and drain of PM6, and is also connected to one end of resistor R5 and the gate of PM7. The other end of resistor R5 is connected to one end of capacitor C1, and the other end of capacitor C1 is connected to the power supply. The source of PM6 is connected to the power supply, the source of PM7 is connected to the power supply, and the drain of PM7 outputs the control signal PG.

[0015] As an optional approach, a fast-response current protection circuit is also included. The fast-response current protection circuit is used to protect the output power transistor PMM of the RS485. The S port of the fast-response current protection circuit is connected to the source of the power transistor PMM, the D port of the fast-response current protection circuit is connected to the drain of the power transistor PMM, and the PG port of the fast-response current protection circuit is connected to the gate of the power transistor PMM.

[0016] As an alternative, the current sampling unit is connected to the power transistor PMM to sample the current of the power transistor PMM.

[0017] As an alternative, the output signal PG of the fast-response current protection circuit is used to control the gate voltage of the power transistor PMM, thereby limiting the output current of the power transistor PMM.

[0018] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0019] This invention samples the current of the power transistor by setting a current sampling unit. The output signal of the current sampling unit is connected to the voltage conversion unit of the fast response hysteresis comparator, which can quickly and effectively respond to changes in the gate voltage signal of the power transistor, so that the output control signal can quickly control the current flowing through the protected power transistor. Attached Figure Description

[0020] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0021] Figure 1 This is a schematic diagram of the fast response current limiting protection circuit structure provided in an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of the fast response current limiting protection circuit provided in an embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of the current sampling unit structure provided in an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of a fast-response hysteresis comparator structure provided in an embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of a fast-response current protection circuit provided in an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0027] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0028] In the description of this invention, it should be noted that the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0029] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0030] Example

[0031] Please see Figures 1-5 This embodiment provides a fast-response current-limiting protection circuit for an RS485 driver, including a current sampling unit and a fast-response hysteresis comparator. The current sampling unit receives signals, with its input terminals receiving a first signal voltage, a second signal voltage, and a third signal voltage, respectively. Its output terminal is connected to the fast-response hysteresis comparator. The fast-response hysteresis comparator includes a bias unit, a voltage conversion unit, a hysteresis control unit, and a comparison output unit. The fast-response hysteresis comparator receives the output voltage of the current sampling unit, amplifies and compares the received voltage, and outputs a control signal based on the comparison result. This circuit overcomes the problem in existing RS485 driver circuits where the overcurrent protection response is untimely when a short circuit occurs on the A / B bus in high-speed applications, causing excessive current and chip burnout during short circuits.

[0032] To achieve the aforementioned technical effects, the input terminals of the current sampling unit include an S port, a D port, and a PG port, used to receive the first signal voltage, the second signal voltage, and the third signal voltage, respectively; the output terminal of the current sampling unit is the CS_H port. The current sampling unit is connected to the protected power transistor and is used to sample the current of the protected power transistor. The magnitude of the sampled current is set by the ratio of the sampling transistor to the protected power transistor. In this embodiment, the current sampling unit includes a sampling power transistor PMS and a resistor R1. The gate of the sampling power transistor PMS is connected to the PG port, the drain is connected to the D port, and its source and one end of the resistor R1 are connected to the CS_H port; the other end of the resistor R1 is connected to the S port.

[0033] Please refer to this again. Figure 4 In this embodiment, the bias unit consists of a current source IB1 and a NOMS NM1. One end of the current source IB1 is connected to the power supply, and the other end of the current source IB1 is connected to the drain and gate of the NMOS transistor NM1. The source of NM1 is grounded.

[0034] The voltage conversion unit includes PMOS transistors PM1 and PM2, NMOS transistor NM2, resistors R2, R3, and R4. The source of PMOS transistor PM1 is connected to the CS_H port. The gate and drain of PM1 are connected to the drain of NMOS transistor NM2, and also to the gate of PM2. The source of NM2 is grounded. The drain of PM2 is connected to one end of resistor R2, and the other end of resistor R2 is grounded. The source of PM2 is connected to one end of resistor R3, and the other end of resistor R3 is connected to one end of resistor R4. It is also connected to the drain of PM3 in the hysteresis control unit. The other end of resistor R4 is connected to the power supply.

[0035] The hysteresis control unit includes NMOS transistors NM3 and NM4, PMOS transistors PM3, PM4, and PM5, a Schmitt trigger SMT1, and an inverter INV1. The gate of NM3 is connected to the gate and drain of NM1 in the bias unit, and the drain of NM3 is connected to the gate and drain of PM4 and also to the gate of PM5. The source of PM4 and PM5 are connected to the power supply. The gate of NM4 is connected to the drain of the output transistor PM2 in the voltage conversion unit. The drain of NM4 is connected to the drain of PM5 and also to the input of Schmitt trigger SMT1. The output of Schmitt trigger SMT1 is connected to the input of inverter INV1, and the output of inverter INV1 is connected to the gate of PM3.

[0036] The comparator output unit includes NMOS transistor NM5, PMOS transistors PM6 and PM7, resistor R5, and capacitor C1. The gate of NM5 is connected to the drain of the voltage conversion unit output transistor PM2. The drain of NM5 is connected to the gate and drain of PM6, and also to one end of resistor R5 and the gate of PM7. The other end of resistor R5 is connected to one end of capacitor C1, and the other end of capacitor C1 is connected to the power supply. The source of PM6 is connected to the power supply, the source of PM7 is connected to the power supply, and the drain of PM7 outputs the control signal PG.

[0037] Please refer to this again. Figure 5 This embodiment also provides a fast-response current protection circuit for current limiting protection of the RS485 output power transistor PMM. The circuit protects the PMM by connecting its S-port to the source of the PMM, its D-port to the drain, and its PG-port to the gate. The output signal PG of the fast-response current protection circuit controls the gate voltage of the PMM, thus limiting the output current of the PMM.

[0038] The current sampling unit is connected to the protected power transistor (PMM) to sample its current. The sampling unit has a small resistance value, and the current sampling accuracy is determined by the ratio of the power transistor to the sampling transistor, resulting in high accuracy. The output signal CS_H of the current sampling unit is connected to a fast-response hysteresis comparator voltage conversion unit. The input of the voltage conversion unit is the source of the PMOS transistor, a low-impedance node. The output resistor of the voltage conversion unit is also small, making it a low-impedance node. This allows the voltage conversion unit to respond quickly and effectively to changes in the power transistor's gate voltage signal, and the output control signal PG can quickly control the current flowing through the protected power transistor.

[0039] Furthermore, in some optional implementation scenarios, for the current limiting protection circuit of the RS485 output power transistor NMM transistor, the above-mentioned fast response hysteresis comparator can be mirrored to obtain another current limiting protection circuit.

[0040] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A fast-response current-limiting protection circuit for RS485 drivers, characterized in that, include: Current sampling unit and fast-response hysteresis comparator; The current sampling unit is used to receive signals. Its input terminals are used to receive the first signal voltage, the second signal voltage, and the third signal voltage, respectively. Its output terminal is connected to the fast response hysteresis comparator. The fast response hysteresis comparator includes a bias unit, a voltage conversion unit, a hysteresis control unit, and a comparison output unit; the fast response hysteresis comparator is used to receive the output voltage of the current sampling unit, amplify and compare the received voltage, and output a control signal based on the comparison result. The bias unit consists of a current source IB1 and an NMOS transistor NM1. One end of the current source IB1 is connected to the power supply, and the other end of the current source IB1 is connected to the drain and gate of the NMOS transistor NM1. The source of NM1 is grounded. The voltage conversion unit includes PMOS transistors PM1 and PM2, NMOS transistor NM2, resistors R2, R3, and R4. The source of PMOS transistor PM1 is connected to the CS_H port. The gate and drain of PM1 are connected to the drain of NMOS transistor NM2, and also to the gate of PM2. The source of NM2 is grounded. The drain of PM2 is connected to one end of resistor R2, and the other end of resistor R2 is grounded. The source of PM2 is connected to one end of resistor R3, and the other end of resistor R3 is connected to one end of resistor R4. It is also connected to the drain of PM3 in the hysteresis control unit. The other end of resistor R4 is connected to the power supply. The hysteresis control unit includes NMOS transistors NM3 and NM4, PMOS transistors PM3, PM4, and PM5, a Schmitt trigger SMT1, and an inverter INV1. The gate of NM3 is connected to the gate and drain of NM1 in the bias unit, and the drain of NM3 is connected to the gate and drain of PM4 and also to the gate of PM5. The source of PM4 is connected to the power supply, and the source of PM5 is connected to the power supply. The gate of NM4 is connected to the drain of the output transistor PM2 in the voltage conversion unit. The drain of NM4 is connected to the drain of PM5 and also to the input of Schmitt trigger SMT1. The output of Schmitt trigger SMT1 is connected to the input of inverter INV1, and the output of inverter INV1 is connected to the gate of PM3. The comparison output unit includes an NMOS transistor NM5, a PMOS transistor PM6, PM7, a resistor R5, and a capacitor C1. The gate of NM5 is connected to the drain of the voltage conversion unit output transistor PM2. The drain of NM5 is connected to both the gate and drain of PM6, and is also connected to one end of the resistor R5 and the gate of PM7. The other end of the resistor R5 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the power supply. The source of PM6 is connected to the power supply, the source of PM7 is connected to the power supply, and the drain of PM7 outputs the control signal PG.

2. The fast-response current-limiting protection circuit for an RS485 driver according to claim 1, characterized in that, The input terminals of the current sampling unit include an S port, a D port, and a PG port, which are used to receive the first signal voltage, the second signal voltage, and the third signal voltage, respectively; the output terminal of the current sampling unit is the CS_H port.

3. The fast-response current-limiting protection circuit for an RS485 driver according to claim 2, characterized in that, The current sampling unit includes a sampling power transistor PMS and a resistor R1. The gate of the sampling power transistor PMS is connected to the PG port, the drain is connected to the D port, and its source and one end of the resistor R1 are connected to the CS_H port. The other end of the resistor R1 is connected to the S port.

4. The fast-response current-limiting protection circuit for an RS485 driver according to claim 1, characterized in that, It also includes a fast-response current protection circuit, which is used to protect the output power transistor PMM of RS485. The S port of the fast-response current protection circuit is connected to the source of the power transistor PMM, the D port of the fast-response current protection circuit is connected to the drain of the power transistor PMM, and the PG port of the fast-response current protection circuit is connected to the gate of the power transistor PMM.

5. A fast-response current-limiting protection circuit for an RS485 driver according to claim 4, characterized in that, The current sampling unit is connected to the power transistor PMM and is used to sample the current of the power transistor PMM.

6. A fast-response current-limiting protection circuit for an RS485 driver according to claim 5, characterized in that, The output signal PG of the fast-response current protection circuit is used to control the gate voltage of the power transistor PMM and limit the output current of the power transistor PMM.

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