Multi-value rram read-write circuit and read-write method thereof

Abstract

This invention belongs to the field of analog integrated circuits and memory technology, and relates to a multi-value RRAM read / write circuit and its method. The multi-value RRAM read / write circuit includes an RRAM control unit, a low-dropout linear regulator, a standard resistor unit, a leakage current sampling unit, a read / write conversion unit, a CMOS switch, and an operational amplifier. The low-dropout linear regulator provides a stable gate voltage for the RRAM control unit and the standard resistor unit. The standard resistor unit adjusts the resistance value of the RRAM. The leakage current sampling unit samples and compensates for leakage current. The read / write conversion unit receives a read / write conversion signal and controls the CMOS switch based on the signal to switch between read and write modes of the multi-value RRAM read / write circuit. The operational amplifier is connected in write mode to maintain voltage stability across the RRAM. This invention can sample and compensate for leakage current, greatly reducing the impact of leakage current on RRAM read / write operations.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuits and memory technology, and in particular to a multi-value RRAM read / write circuit and its read / write method. Background Technology

[0002] Resistive Random Access Memory (RRAM) is an emerging type of memory where information is stored in the resistance of memory cells, typically composed of a very thin, nanoscale dielectric layer, usually made of an insulator. By forcing a current through the dielectric layer, tiny conductive filaments composed of ion vacancies (and positive charges) are formed in the dielectric material, causing a change in resistance. By applying a current in the opposite direction, these filaments may break, resulting in an increase in resistance. The difference in resistance between the formed and broken filaments can be interpreted as different cell states and used as memory; the stored data is non-volatile and is not lost after power failure. Multi-value read / write operations in RRAM refer to storing more than one bit of information in a single memory cell, achieved by precisely controlling the resistance state of the resistive switching layer.

[0003] Multi-value read / write RRAM can improve data storage density, reduce the energy consumption per bit of data operation, and is naturally adapted to neural network simulation calculations (such as weight mapping), making it a key technology for improving RRAM storage density and reducing costs. Existing multi-value RRAM read / write circuits suffer from leakage current in the RRAM array, which has the following impacts on RRAM read / write: First, it can lead to false reads. When the target cell is in a high-resistance state while surrounding unselected cells are in a low-resistance state, the leakage current will be shunt through these low-resistance paths, causing the actual read current to be much greater than the true current of the target cell. This can lead to several issues: First, it can cause the system to incorrectly identify a high-resistance state as a low-resistance state. Second, it can lead to write errors. When writing to a row or column, if an unselected cell experiences a voltage exceeding its threshold, it may be accidentally set or reset, resulting in unintended data modification. Third, it can reduce read / write margins. Leakage current can interfere with the current signal of the target cell, narrowing the current difference between high-resistance and low-resistance states (i.e., read margin), reducing the signal-to-noise ratio, and making it difficult for the sense amplifier to accurately determine the state. Fourth, it can increase power consumption. Leakage current continues to flow in unselected paths, causing additional static power consumption, especially in large-scale arrays where the cumulative effect is significant. Fifth, it can lead to write failures or the need for multiple verifications. In analog in-memory computing applications, leakage current can disrupt programming accuracy, causing the written value to deviate from the target, requiring repeated "write-verify" operations, increasing latency and reducing energy efficiency.

[0004] Therefore, there is an urgent need to propose a multi-valued RRAM read / write circuit and method that can reduce the impact of leakage current on RRAM read / write. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of existing technologies by proposing a multi-value RRAM read / write circuit and its method. It employs a leakage current sampling unit for leakage current sampling and compensation, significantly reducing the impact of leakage current on RRAM read / write operations. Furthermore, the entire circuit uses only one operational amplifier and a low-dropout linear regulator. Read and write modes are switched by adjusting a CMOS switch, providing both read and write functionality without requiring a large area. The low-dropout linear regulator provides a stable voltage for the entire circuit, effectively suppressing the impact of voltage fluctuations. In addition, this invention adjusts the RRAM resistance by setting a reference resistor and a mirror current, avoiding the feedback adjustment process and improving write speed.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a multi-value RRAM read / write circuit, comprising: an RRAM control unit, a low-dropout linear regulator, a standard resistor unit, a leakage current sampling unit, a read / write conversion unit, a CMOS switch, and an operational amplifier;

[0008] Among them, the low dropout linear regulator is connected to the RRAM control unit and the standard resistor unit to provide a stable gate voltage for the RRAM control unit and the standard resistor unit;

[0009] The RRAM control unit includes the RRAM and control circuitry, and a standard resistor unit is used to adjust the resistance value of the RRAM.

[0010] The leakage current sampling unit is connected to the RRAM control unit and the standard resistor unit to sample and compensate for leakage current. The leakage current sampling unit receives the status control signal and the current mirror control signal, and has a sampling state and a compensation state. When the status control signal is at a high potential and the current mirror control signal is at a low potential, the leakage current sampling unit is in the sampling state and performs leakage current sampling. When both the status control signal and the current mirror control signal are at a low potential, the leakage current sampling unit is in the compensation state and generates a compensation current to offset the leakage current.

[0011] The read / write conversion unit is connected to the CMOS switch and is used to receive the read / write conversion signal. Based on the read / write conversion signal, it controls the CMOS switch to open or close, so as to switch the read mode or write mode of the multi-value RRAM read / write circuit.

[0012] The operational amplifier is connected to the RRAM control unit in write mode to maintain the voltage stability across the RRAM.

[0013] As one possible implementation, the leakage current sampling unit includes a CMOS switch group, a state transition circuit, a current mirror, and a current mirror state control circuit.

[0014] The state transition circuit is connected to the CMOS switch group and is used to control the opening or closing of the switches in the CMOS switch group. The CMOS switch group includes four switches, two of which are used to change the operating state of the transistor in the current mirror, and the other two switches are used to change the feedback path of the low dropout linear regulator. The current mirror state control circuit is connected to the current mirror and is used to control the current mirror to be in diode state or current mirror state. When the current mirror is in diode state, the leakage current sampling unit enters the sampling state. When the current mirror is in current mirror state, the leakage current sampling unit enters the compensation state.

[0015] As one possible implementation, the feedback path of the low-dropout linear regulator is changed. Specifically, in the sampling state, the voltage across the RRAM is fed back to the low-dropout linear regulator to maintain the voltage across the RRAM stable, so as to sample the current of the RRAM at a certain voltage. In the compensation state, the voltage across the standard resistor unit is fed back to the low-dropout linear regulator to maintain the voltage across the standard resistor unit stable, so that the current through the RRAM is completely controlled.

[0016] As one possible implementation, the multi-value RRAM read / write circuit also includes a write verification unit; when the leakage current sampling unit is in the compensation state, the multi-value RRAM read / write circuit enters read / write mode, switching between read and write modes based on the read / write conversion signal, specifically including:

[0017] When the read / write conversion signal is high, the multi-value RRAM read / write circuit enters write mode. The read / write conversion unit controls the CMOS switch to turn on, and the operational amplifier and write verification unit are simultaneously connected to the multi-value RRAM read / write circuit to maintain the voltage across the RRAM and monitor the write status. After the write is completed, the status control signal is pulled to a high level.

[0018] When the read / write conversion signal is low, the multi-value RRAM read / write circuit enters read mode. The read / write conversion unit controls the CMOS switch to turn off, and the operational amplifier and write verification unit are disconnected from the multi-value RRAM read / write circuit. The voltage across the RRAM is read directly, and after the read is completed, the status control signal is pulled to a high level.

[0019] As one possible implementation, the standard resistor cell includes multiple standard resistors connected in parallel. The current in the RRAM is a mirror image of the current in the standard resistor cell, so that the resistance of the RRAM is the total resistance of the parallel standard resistors. The number of parallel standard resistors is equal to the data width to be written to the RRAM. Each parallel standard resistor has two states: connected and disconnected. By controlling the connection or disconnection of each standard resistor, the total resistance of the parallel standard resistors is changed, thereby adjusting the resistance of the RRAM and realizing multi-value writing.

[0020] In a second aspect, the present invention provides a read / write method for a multi-value RRAM read / write circuit, implemented based on the multi-value RRAM read / write circuit provided in the first aspect, comprising:

[0021] S1. Initialize the multi-value RRAM read / write circuit to provide a stable gate voltage for the RRAM control unit and standard resistor unit;

[0022] S2. Set the status control signal to a high potential and the current mirror control signal to a low potential to put the leakage current sampling unit into the sampling state and perform leakage current sampling.

[0023] S3. Set both the status control signal and the current mirror control signal to a low potential to put the leakage current sampling unit in a compensation state and generate a compensation current to offset the leakage current.

[0024] S4. Adjust the potential of the read / write conversion signal to control the multi-value RRAM read / write circuit to enter write mode or read mode;

[0025] S5. After a write or read operation is completed, pull the status control signal back to a high level.

[0026] As one possible implementation, the compensation current is generated using the following method:

[0027] When the leakage current sampling unit is in the sampling state, it records the gate voltage. When the leakage current sampling unit is in the compensation state, it drives the current mirror included in the leakage current sampling unit based on the recorded gate voltage to generate a compensation current.

[0028] As one possible implementation, S4 specifically includes:

[0029] When the read / write conversion signal is adjusted to a high potential, the multi-value RRAM read / write circuit enters the write mode. The voltage across the RRAM is kept stable based on the operational amplifier, and the write status is monitored based on the write verification unit.

[0030] When the read / write conversion signal is adjusted to a low potential, the multi-value RRAM read / write circuit enters read mode and directly reads the voltage across the RRAM.

[0031] As one possible implementation, after entering write mode, the connection or disconnection of each standard resistor is controlled to change the total resistance value of the parallel standard resistors in the standard resistor unit, thereby adjusting the resistance value of the RRAM and realizing multi-value writing.

[0032] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0033] 1. The multi-value RRAM read / write circuit proposed in this invention, by setting up a dedicated leakage current sampling unit and utilizing the switching between sampling and compensation states, can first accurately sample the leakage current in the circuit, and then generate a matching compensation current in the compensation state to cancel it out. This dynamic compensation mechanism effectively eliminates the interference of leakage current on the RRAM cell current, ensuring the accuracy of data judgment during read operations and the precision of resistance adjustment during write operations.

[0034] 2. The multi-value RRAM read / write circuit proposed in this invention achieves clear separation between read and write modes through a read / write conversion unit and a CMOS switch: In write mode, an operational amplifier is connected to form a feedback loop, forcibly stabilizing the voltage across the RRAM and preventing voltage drift due to leakage current or circuit parameter changes, thus ensuring a high write success rate. In read mode, the operational amplifier is disconnected, and the voltage is read directly, avoiding noise and offset introduced by active devices. Simultaneously, leakage current compensation is implemented in both modes, and the circuit is reset after operation, significantly improving the overall reliability and anti-interference capability of the circuit.

[0035] 3. The multi-value RRAM read / write circuit proposed in this invention can precisely adjust the total resistance value by controlling the on / off state of multiple parallel resistors in a standard resistor unit, thereby setting the RRAM resistance value to the corresponding multi-value state. In write mode, the operational amplifier maintains the absolute stability of the voltage across the RRAM. Combined with the monitoring of the write verification unit, it ensures that the writing process with different resistance values ​​is unaffected by voltage fluctuations and leakage current, thus reliably achieving multi-value storage.

[0036] 4. This invention proposes a multi-value RRAM read / write circuit and its read / write method. The read / write circuit can be switched, eliminating the need for separate read or write circuits and saving the total area of ​​the read / write circuit. Attached Figure Description

[0037] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0038] Figure 1 A schematic diagram of a multi-value RRAM read / write circuit structure provided in an embodiment of the present invention;

[0039] Figure 2 A schematic diagram of a multi-value RRAM read / write circuit provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the leakage current sampling unit structure in the multi-value RRAM read / write circuit provided in an embodiment of the present invention;

[0041] Figure 4A circuit block diagram of a multi-value RRAM read / write circuit provided in an embodiment of the present invention;

[0042] Figure 5 A flowchart of a multi-value RRAM read / write circuit read / write method provided in an embodiment of the present invention;

[0043] Figure 6 This is a circuit block diagram of the leakage current sampling unit in the sampling state in an embodiment of the present invention;

[0044] Figure 7 This is a circuit block diagram of the leakage current sampling unit in the compensation state in an embodiment of the present invention;

[0045] Figure 8 This is a circuit block diagram of the multi-value RRAM read / write circuit in write mode in an embodiment of the present invention;

[0046] Figure 9 This is a circuit block diagram of the multi-value RRAM read / write circuit in read mode in an embodiment of the present invention;

[0047] Figure 10 This is a schematic diagram of a prior art read circuit in an embodiment of the present invention;

[0048] Figure 11 This is a schematic diagram of a prior art write circuit in an embodiment of the present invention.

[0049] Figure Labels

[0050] 1- RRAM control unit, 2- Low dropout linear regulator, 3- Standard resistor unit, 4- Leakage current sampling unit, 40- CMOS switch group, 41- State transition circuit, 42- Current mirror, 43- Current mirror state control circuit, 5- Read / write conversion unit, 6- CMOS switch, 7- Operational amplifier, 8- Write verification unit. Detailed Implementation

[0051] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0052] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0053] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one" or similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, "at least one of a, b, or c" can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0054] This invention aims to provide a multi-value RRAM read / write circuit and its method. By setting a reference resistor and a mirror current, the resistance value of the RRAM is adjusted, avoiding the feedback adjustment process and improving the write speed. This invention also employs a leakage current sampling unit for leakage current sampling and compensation, significantly reducing the impact of leakage current on RRAM read / write operations. Furthermore, the entire circuit uses only one operational amplifier and a low-dropout linear regulator, switching between read and write modes by adjusting a CMOS switch, providing both read and write functionality without occupying a large area. The low-dropout linear regulator provides a stable voltage for the entire circuit, effectively suppressing the effects of voltage fluctuations.

[0055] In a first aspect, embodiments of the present invention provide a multi-value RRAM read / write circuit, see [link to relevant documentation]. Figure 1 It includes: RRAM control unit 1, low dropout linear regulator 2, standard resistor unit 3, leakage current sampling unit 4, read / write conversion unit 5, CMOS switch 6, and operational amplifier 7;

[0056] See Figure 1 The low-dropout linear regulator 2 is connected to the RRAM control unit 1 and the standard resistor unit 3 to provide a stable gate voltage for the RRAM control unit 1 and the standard resistor unit 3.

[0057] As an example, see Figure 1 and Figure 2The low-dropout linear regulator 2 includes five NMOS transistors: NMOS transistor 1, NMOS transistor 2, NMOS transistor 3, NMOS transistor 4, and NMOS transistor 5, and five PMOS transistors: PMOS transistor 1, PMOS transistor 2, PMOS transistor 3, PMOS transistor 4, and PMOS transistor 5. The connection is as follows: the drain and gate of NMOS transistor 1 are connected to the gates of NMOS transistors 2 and 5, respectively; the source of NMOS transistor 3 is connected to the source of NMOS transistor 4 and the drain of NMOS transistor 5; the drain of NMOS transistor 2 is connected to the drain of PMOS transistor 1; the gate of PMOS transistor 1 is connected to its drain; the gate of PMOS transistor 2 is connected to its drain and the gate of PMOS transistor 3; the source of PMOS transistor 4 is connected to the drain of PMOS transistor 2; and the source of PMOS transistor 5 is connected to the drain of PMOS transistor 3.

[0058] RRAM control unit 1 includes RRAM and control circuit, and standard resistor unit 3 is used to adjust the resistance value of RRAM;

[0059] As an example, see Figure 1 and Figure 2 The control circuit includes three PMOS transistors: PMOS transistor 6, PMOS transistor 7, and PMOS transistor 8. The connection is as follows: the drain of PMOS transistor 6 is connected to the source of PMOS transistor 7, the drain of PMOS transistor 7 is connected to the source of PMOS transistor 8, the drain of PMOS transistor 8 is connected to the first terminal of the RRAM, the source of PMOS transistor 6 is connected to the power supply VCC, and the second terminal of the RRAM is grounded.

[0060] As one possible implementation, the standard resistor cell includes multiple standard resistors connected in parallel. The current in the RRAM is a mirror image of the current in the standard resistor cell, so that the resistance of the RRAM is the total resistance of the parallel standard resistors. The number of parallel standard resistors is equal to the data width to be written to the RRAM. Each parallel standard resistor has two states: connected and disconnected. By controlling the connection or disconnection of each standard resistor, the total resistance of the parallel standard resistors is changed, thereby adjusting the resistance of the RRAM and realizing multi-value writing.

[0061] As an example, standard resistor unit 3 includes 3 PMOS transistors, n NMOS transistors, and n standard resistors. In this embodiment, n can be any integer between 1 and 5. For example, if n is 4, see [link to documentation]. Figure 2The standard resistor unit includes three PMOS transistors: PMOS transistor 9, PMOS transistor 10 and PMOS transistor 11; four NMOS transistors: NMOS transistor 6, NMOS transistor 7, NMOS transistor 8 and NMOS transistor 9; and four standard resistors: resistors R1, R2, R3 and R4. The connection method is as follows: the drain of PMOS transistor 9 is connected to the source of PMOS transistor 10, the drain of PMOS transistor 10 is connected to the source of PMOS transistor 11, the drain of PMOS transistor 11 is connected to the first terminal of resistors R1, R2, R3, and R4, the second terminal of resistors R1, R2, R3, and R4 is connected to the drains of NMOS transistors 6, 7, 8, and 9 respectively, the gates of NMOS transistors 6, 7, 8, and 9 are connected to control voltages rs0, rs1, rs2, and rs3 respectively, the sources of NMOS transistors 6, 7, 8, and 9 are grounded, and the source of PMOS transistor 9 is connected to the power supply VCC.

[0062] See Figures 1 to 2 As an example, the low dropout linear regulator 2 is connected to the RRAM control unit 1 and the standard resistor unit 3 as follows: the source of PMOS transistor 5 is connected to the drain of PMOS transistor 3, and then to the gates of PMOS transistors 6 and 9; the drain of PMOS transistor 5 is connected to the drain of NMOS transistor 4, and then to the gates of PMOS transistors 7 and 10; the gate of NMOS transistor 3 is connected to the source of PMOS transistor 11; the sources of PMOS transistors 1, 2, and 3 are all connected to the power supply VCC; the sources of NMOS transistors 1, 2, and 5 are all grounded; the drain of NMOS transistor 1 is connected to the current source ib; and the gate of NMOS transistor 4 is connected to the write voltage vwr.

[0063] See Figure 1 The leakage current sampling unit 4 is connected to the RRAM control unit 1 and the standard resistor unit 3, and is used to sample and compensate for leakage current.

[0064] See Figure 1 As one possible implementation, the leakage current sampling unit 4 receives the state control signal and the current mirror control signal, and has a sampling state and a compensation state. When the state control signal is at a high potential and the current mirror control signal is at a low potential, the leakage current sampling unit is in the sampling state and performs leakage current sampling. When both the state control signal and the current mirror control signal are at a low potential, the leakage current sampling unit is in the compensation state and generates a compensation current to offset the leakage current.

[0065] See Figure 3As one possible implementation, the leakage current sampling unit 4 includes a CMOS switch group 40, a state transition circuit 41, a current mirror 42, and a current mirror state control circuit 43.

[0066] The state transition circuit is connected to the CMOS switch group and is used to control the opening or closing of the switches in the CMOS switch group. The CMOS switch group includes four switches, two of which are used to change the operating state of the transistor in the current mirror, and the other two switches are used to change the feedback path of the low dropout linear regulator 2. The current mirror state control circuit is connected to the current mirror and is used to control the current mirror to be in diode state or current mirror state. When the current mirror is in diode state, the leakage current sampling unit enters the sampling state. When the current mirror is in current mirror state, the leakage current sampling unit enters the compensation state.

[0067] As an example, see Figures 2 to 3The CMOS switch group 40 includes four switches: CMOS Switch1, CMOS Switch2, CMOS Switch3, and CMOS Switch4. CMOS Switch1 includes NMOS transistor 19 and PMOS transistor 21; CMOS Switch2 includes NMOS transistor 20 and PMOS transistor 22; CMOS Switch3 includes NMOS transistor 23 and PMOS transistor 23; and CMOS Switch4 includes NMOS transistor 24 and PMOS transistor 24. The state transition circuit 41 includes PMOS transistor 25, PMOS transistor 26, NMOS transistor 27, and NMOS transistor 28. The current mirror 42 includes NMOS transistors 21 and 22. The current mirror state control circuit 43 includes NMOS transistors 25 and 26. The connection method is as follows: the source of NMOS transistor 19 is connected to the source of PMOS transistor 21, and then to the drain of PMOS transistor 10 in standard resistor unit 3; the gate of NMOS transistor 19 is connected to the gate of PMOS transistor 22, and then to the gate of PMOS transistor 23; the drain of NMOS transistor 19 is connected to the drain of PMOS transistor 21, and then to the gate of NMOS transistor 3 in low dropout linear regulator 2, and then to the sources of NMOS transistor 20 and PMOS transistor 22; the gate of NMOS transistor 20 is connected to the gate of PMOS transistor 21, and then to the gate of NMOS transistor 23; the drain of NMOS transistor 20 is connected to the drain of PMOS transistor 22, and then to the source of PMOS transistor 8 in RRAM control unit 1. The gate of PMOS transistor 25 is connected to the gate of NMOS transistor 27. The drain of PMOS transistor 25 is connected to the drain of NMOS transistor 27, and then to the gates of PMOS transistor 26, NMOS transistor 28, PMOS transistor 23, and PMOS transistor 24. The drain of PMOS transistor 26 is connected to the drain of NMOS transistor 28, and then to the gates of PMOS transistor 21 and NMOS transistor 20. The gate of NMOS transistor 24 is connected to the gate of PMOS transistor 23. The drain of NMOS transistor 21 is connected to the source of NMOS transistor 23 and the source of PMOS transistor 23, and also to the drain of PMOS transistor 11 in standard resistor unit 3. The gate of NMOS transistor 21 is connected to the drain of NMOS transistor 23 and the drain of PMOS transistor 23, and also to the source of NMOS transistor 26. The source of NMOS transistor 21 is connected to the drain of NMOS transistor 22. The drain of NMOS transistor 22 is connected to the source of NMOS transistor 24 and the source of PMOS transistor 24. The gate of NMOS transistor 22 is connected to the drain of NMOS transistor 24 and the drain of PMOS transistor 24, and then to the source of NMOS transistor 25. The source of NMOS transistor 22 is connected to the drain of NMOS transistor 25, the drain of NMOS transistor 26, the source of NMOS transistor 27, and the source of NMOS transistor 28, and finally grounded.The gate connection status control signal of PMOS transistor 25, the gate connection current mirror control signal of NMOS transistor 25, the source of PMOS transistor 25 is connected to the source of PMOS transistor 26, and connected to power supply VCC.

[0068] This invention utilizes a dedicated leakage current sampling unit, switching between sampling and compensation states, to accurately sample the leakage current in the circuit before generating a matching compensation current in the compensation state to cancel it out. This dynamic compensation mechanism effectively eliminates the interference of leakage current on the RRAM cell current, ensuring the accuracy of data judgment during read operations and the precision of resistance adjustment during write operations.

[0069] As one possible implementation, the feedback path of the low-dropout linear regulator is changed. Specifically, in the sampling state, the voltage across the RRAM is fed back to the low-dropout linear regulator to maintain the voltage across the RRAM stable, so as to sample the current of the RRAM at a certain voltage. In the compensation state, the voltage across the standard resistor unit is fed back to the low-dropout linear regulator to maintain the voltage across the standard resistor unit stable, so that the current through the RRAM is completely controlled.

[0070] The read / write conversion unit 5 is connected to the CMOS switch 6 and is used to receive the read / write conversion signal. Based on the read / write conversion signal, it controls the CMOS switch 6 to open or close, so as to switch the read mode or write mode of the multi-value RRAM read / write circuit.

[0071] As an example, see Figures 1 to 2The CMOS switch 6 includes an NMOS transistor 10, a PMOS transistor 12, and an NMOS transistor 11. The source of PMOS transistor 12 is connected to the gate of PMOS transistor 11 in standard resistor unit 3. The source of NMOS transistor 10 is connected to the source of PMOS transistor 12. The drain of NMOS transistor 10 is connected to the drain of PMOS transistor 12, and then connected to the source of NMOS transistor 12 in operational amplifier 7. The source of PMOS transistor 12 is connected to the gate of PMOS transistor 11 in standard resistor unit 3. The gate of PMOS transistor 12 is connected to the gate of NMOS transistor 11. The drain of NMOS transistor 11 is connected to the gate of PMOS transistor 11 in standard resistor unit 3. The source of NMOS transistor 11 is grounded. The read / write conversion unit 5 includes two PMOS transistors: PMOS transistor 18 and PMOS transistor 19, and two NMOS transistors: NMOS transistor 16 and NMOS transistor 17. The drain of PMOS transistor 18 is connected to the drain of NMOS transistor 16, and then to the gate of PMOS transistor 19, NMOS transistor 17, and NMOS transistor 11 in CMOS switch 6. The drain of PMOS transistor 19 is connected to the drain of NMOS transistor 17, and then to the gate of NMOS transistor 10 in CMOS switch 6. The gate of PMOS transistor 18 is connected to the gate of NMOS transistor 16, and the read / write conversion signal whlr is connected. The gates of PMOS transistors 18 and 19 are connected to the power supply VCC, and the sources of NMOS transistors 16 and 17 are grounded.

[0072] Operational amplifier 7 is connected to RRAM control unit 1 in write mode to maintain stable voltage across RRAM.

[0073] As an example, see Figures 1 to 2Operational amplifier 7 includes 5 PMOS transistors: PMOS transistor 13, PMOS transistor 14, PMOS transistor 15, PMOS transistor 16, and PMOS transistor 17, 4 NMOS transistors: NMOS transistor 12, NMOS transistor 13, NMOS transistor 14, and NMOS transistor 15, and resistor R5. The connection method is as follows: the gate of PMOS transistor 13 is connected to the gate of PMOS transistor 14, and then connected to the gates of PMOS transistor 1 in low-dropout linear regulator 2 and PMOS transistor 20 in write verification unit 8. The drain of PMOS transistor 13 is connected to the source and drain of PMOS transistor 15. The drain of PMOS transistor 14 is connected to the source of PMOS transistors 16 and 17. The gate of PMOS transistor 15 is connected to the gate of NMOS transistor 12 and the first terminal of resistor R5. The source of PMOS transistor 15 is connected to the source and drain of NMOS transistor 12. The source of NMOS transistor 12 is connected to the drain of NMOS transistor 13. The second terminal of resistor R5 is connected to PMOS transistor 14. The drain of transistor 6 is connected. The gate of NMOS transistor 13 is connected to the drain of NMOS transistor 14. The drain of PMOS transistor 16 is connected to the drain of NMOS transistor 14. The gate of PMOS transistor 16 is connected to the drain of PMOS transistor 11 in standard resistor unit 3. The drain of PMOS transistor 17 is connected to the gate and drain of NMOS transistor 15. The gate of PMOS transistor 17 is connected to the drain of PMOS transistor 8 in RRAM control unit 1. The gate of NMOS transistor 14 is connected to the gate of NMOS transistor 16. The source of PMOS transistor 13 and the source of PMOS transistor 14 are both connected to the power supply VCC. The sources of NMOS transistors 13, 14, and 15 are grounded.

[0074] This invention achieves clear separation between read and write modes through a read / write conversion unit and a CMOS switch: In write mode, an operational amplifier is connected to form a feedback loop, forcibly stabilizing the voltage across the RRAM and preventing voltage drift due to leakage current or circuit parameter changes, thus ensuring a high write success rate. In read mode, the operational amplifier is disconnected, and the voltage is read directly, avoiding noise and offset introduced by active devices. Simultaneously, leakage current compensation is implemented in both modes, and the circuit is reset after operation, significantly improving overall circuit reliability and anti-interference capability.

[0075] The circuit block diagram of the multi-value RRAM read / write circuit provided in this embodiment is as follows: Figure 4 As shown, see one possible implementation method. Figure 1 The multi-value RRAM read / write circuit also includes a write verification unit 8; when the leakage current sampling unit is in the compensation state, the multi-value RRAM read / write circuit enters the read / write mode, switching between read and write modes based on the read / write conversion signal, specifically including:

[0076] When the read / write conversion signal is high, the multi-value RRAM read / write circuit enters write mode. The read / write conversion unit controls the CMOS switch to turn on, and the operational amplifier and write verification unit are simultaneously connected to the multi-value RRAM read / write circuit to maintain the voltage across the RRAM and monitor the write status. After the write is completed, the status control signal is pulled to a high level.

[0077] When the read / write conversion signal is low, the multi-value RRAM read / write circuit enters read mode. The read / write conversion unit controls the CMOS switch to turn off, and the operational amplifier and write verification unit are disconnected from the multi-value RRAM read / write circuit. The voltage across the RRAM is read directly, and after the read is completed, the status control signal is pulled to a high level.

[0078] As an example, see Figure 1 and Figure 2 The write verification unit 8 includes one PMOS transistor: PMOS transistor 20, and one NMOS transistor: NMOS transistor 18. The gate of PMOS transistor 20 is connected to the gate of PMOS transistor 14 in operational amplifier 7, the drain of PMOS transistor 20 is connected to the drain of NMOS transistor 18, the gate of NMOS transistor 18 is connected to the drain of NMOS transistor 11 in standard resistor unit 3, the source of NMOS transistor 18 is grounded, the source of PMOS transistor 20 is connected to power supply VCC, and the input write verification signal is connected to the drain of PMOS transistor 20.

[0079] This invention precisely adjusts the total resistance value by controlling the on / off state of multiple parallel resistors in a standard resistor unit, thereby setting the RRAM resistance value to the corresponding multi-value state. In write mode, the operational amplifier maintains the absolute stability of the voltage across the RRAM. Combined with the monitoring of the write verification unit, this ensures that the RRAM is unaffected by voltage fluctuations and leakage current during the writing process at different resistance values, thus reliably achieving multi-value storage.

[0080] Secondly, embodiments of the present invention provide a read / write method for a multi-value RRAM read / write circuit, implemented based on the multi-value RRAM read / write circuit provided in the first aspect, see [link to documentation]. Figure 5 ,include:

[0081] S1. Initialize the multi-value RRAM read / write circuit to provide a stable gate voltage for the RRAM control unit and standard resistor unit;

[0082] S2. Set the status control signal to a high potential and the current mirror control signal to a low potential to put the leakage current sampling unit into the sampling state and perform leakage current sampling.

[0083] S3. Set both the status control signal and the current mirror control signal to a low potential to put the leakage current sampling unit in a compensation state and generate a compensation current to offset the leakage current.

[0084] As one possible implementation, the compensation current is generated using the following method:

[0085] When the leakage current sampling unit is in the sampling state, it records the gate voltage. When the leakage current sampling unit is in the compensation state, it drives the current mirror included in the leakage current sampling unit based on the recorded gate voltage to generate a compensation current.

[0086] S4. Adjust the potential of the read / write conversion signal to control the multi-value RRAM read / write circuit to enter write mode or read mode;

[0087] As one possible implementation, S4 specifically includes:

[0088] When the read / write conversion signal is adjusted to a high potential, the multi-value RRAM read / write circuit enters the write mode. The voltage across the RRAM is kept stable based on the operational amplifier, and the write status is monitored based on the write verification unit.

[0089] As one possible implementation, after entering write mode, the connection or disconnection of each standard resistor is controlled to change the total resistance value of the parallel standard resistors in the standard resistor unit, thereby adjusting the resistance value of the RRAM and realizing multi-value writing.

[0090] When the read / write conversion signal is adjusted to a low potential, the multi-value RRAM read / write circuit enters read mode and directly reads the voltage across the RRAM.

[0091] S5. After a write or read operation is completed, pull the status control signal back to a high level.

[0092] As an example, the state control signal is input to CMOS Switch1 and CMOS Switch2 via state transition circuits. CMOS Switch1 and CMOS Switch2 are connected to the standard resistor unit and the RRAM control unit, respectively. The current mirror control signal is input to the current mirror control circuit, and its output is connected to the current mirror. When the current mirror control signal is low and the state control signal is high, the leakage current sampling unit is in sampling mode. When the current mirror control signal is low and the state control signal is low, the leakage current sampling unit is in compensation mode, and the multi-value RRAM read / write circuit is in read / write mode. At this time, the read / write conversion signal is input to the CMOS switch via the read / write conversion unit. The output of the CMOS switch is amplified by an operational amplifier and connected to the RRAM control unit and the standard resistor unit. When the read / write conversion signal is high, the CMOS switch is on, the multi-value RRAM read / write circuit is in write mode, and the signal output by the operational amplifier is used to ensure that the voltages of the RRAM control unit and the standard resistor unit are the same. When the read / write conversion signal is low, the CMOS switch is off, the multi-value RRAM read / write circuit is in read mode, the operational amplifier does not participate in the operation of the RRAM control unit and the standard resistor unit, and directly reads the voltage on the RRAM.

[0093] Specifically, when the multi-value RRAM read / write circuit is in sampling mode, the state transition circuit controls CMOS switch 1 to turn off and CMOS switch 2 to turn on, while the current mirror control circuit controls CMOS switch 3 and CMOS switch 4 to turn on. At this time, NMOS transistors 21 and 22 enter diode load mode, sampling leakage current and recording gate voltage. The circuit then behaves as follows: Figure 6 As shown.

[0094] When the multi-value RRAM read / write circuit is in read / write mode, the state transition circuit controls CMOS switch 1 to turn on and CMOS switch 2 to turn off, while the current mirror control circuit controls CMOS switch 3 and CMOS switch 4 to turn off. Since the gate voltage can still be maintained briefly, NMOS transistors 21 and 22 enter a brief current mirror state, inputting the sampled leakage current into the standard resistor unit to cancel out the leakage current's effect. At this time, the circuit behaves as follows: Figure 7 As shown.

[0095] When the multi-valued RRAM read / write circuit is in write mode, the state transition circuit controls the state of the transistor in the current mirror, switching it between sampling and read / write states. The current mirror control circuit controls whether the current mirror is connected to the circuit. The read / write conversion unit controls the CMOS switch to turn on, connecting the operational amplifier and write verification unit to the circuit. At this time, the circuit functions as follows: Figure 8As shown. The operational amplifier serves as a feedback path to ensure that the voltage across the RRAM is equal to the voltage across the reference resistor. The write verification unit outputs a write verification signal after the write operation is completed.

[0096] When the multi-value RRAM read / write circuit is in read mode, the read / write conversion unit controls the CMOS switch to turn off, disconnecting the operational amplifier and the write verification unit. At this time, the circuit behaves as follows: Figure 9 As shown, the voltage across the RRAM is read through the output port.

[0097] Figure 10 and Figure 11 These are the existing write circuit and read circuit, respectively. The write circuit of this invention is... Figure 10 The difference in the write circuit shown is that this invention uses a parallel resistor, and the resistance value of the RRAM is adjusted by controlling whether the resistor is connected to the circuit. Figure 10 The circuit shown uses feedback to ultimately correlate the resistance value of the RRAM with the input voltage. Furthermore, Figure 10 The circuit shown requires three operational amplifiers and has a complex feedback process. This invention uses only one operational amplifier, resulting in a simpler feedback process and saving circuit area. The read circuit proposed in this invention is only responsible for reading the voltage across the RRAM and does not include the design of a decoding circuit. Figure 11 The read circuit shown already includes the decoding circuit, which decodes by comparing with different resistance values, making it more complex.

[0098] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the description of the drawings, in carrying out the claimed invention. In this specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components. A single processor or other unit can implement several of the functions listed in the specification. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0099] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely illustrative of the invention and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications fall within the scope of the invention and its equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A multi-value RRAM read / write circuit, characterized in that, include: RRAM control unit, low dropout linear regulator, standard resistor unit, leakage current sampling unit, read / write conversion unit, CMOS switch and operational amplifier; Among them, the low dropout linear regulator is connected to the RRAM control unit and the standard resistor unit to provide a stable gate voltage for the RRAM control unit and the standard resistor unit; The RRAM control unit includes the RRAM and control circuitry, and a standard resistor unit is used to adjust the resistance value of the RRAM. The leakage current sampling unit is connected to the RRAM control unit and the standard resistor unit to sample and compensate for leakage current. The leakage current sampling unit receives the status control signal and the current mirror control signal, and has a sampling state and a compensation state. When the status control signal is at a high potential and the current mirror control signal is at a low potential, the leakage current sampling unit is in the sampling state and performs leakage current sampling. When both the status control signal and the current mirror control signal are at a low potential, the leakage current sampling unit is in the compensation state and generates a compensation current to offset the leakage current. The read / write conversion unit is connected to the CMOS switch and is used to receive the read / write conversion signal. Based on the read / write conversion signal, it controls the CMOS switch to open or close, so as to switch the read mode or write mode of the multi-value RRAM read / write circuit. The operational amplifier is connected to the RRAM control unit in write mode to maintain the voltage stability across the RRAM; the leakage current sampling unit includes a CMOS switch group, a state transition circuit, a current mirror, and a current mirror state control circuit. The state transition circuit is connected to the CMOS switch group and is used to control the opening or closing of the switches in the CMOS switch group. The CMOS switch group includes four switches, two of which are used to change the operating state of the transistor in the current mirror, and the other two switches are used to change the feedback path of the low dropout linear regulator. The current mirror state control circuit is connected to the current mirror and is used to control the current mirror to be in diode state or current mirror state. When the current mirror is in diode state, the leakage current sampling unit enters the sampling state. When the current mirror is in current mirror state, the leakage current sampling unit enters the compensation state.

2. The multi-value RRAM read / write circuit according to claim 1, characterized in that, The feedback path of the low-dropout linear regulator is changed as follows: In the sampling state, the voltage across the RRAM is fed back to the low-dropout linear regulator to maintain the voltage across the RRAM stable, so as to sample the current of the RRAM under a certain voltage; in the compensation state, the voltage across the standard resistor unit is fed back to the low-dropout linear regulator to maintain the voltage across the standard resistor unit stable, so that the current through the RRAM is completely controlled.

3. The multi-value RRAM read / write circuit according to claim 1, characterized in that, The multi-value RRAM read / write circuit also includes a write verification unit; when the leakage current sampling unit is in the compensation state, the multi-value RRAM read / write circuit enters read / write mode, switching between read and write modes based on the read / write conversion signal, specifically including: When the read / write conversion signal is high, the multi-value RRAM read / write circuit enters write mode. The read / write conversion unit controls the CMOS switch to turn on, and the operational amplifier and write verification unit are simultaneously connected to the multi-value RRAM read / write circuit to maintain the voltage across the RRAM and monitor the write status. After the write is completed, the status control signal is pulled to a high level. When the read / write conversion signal is low, the multi-value RRAM read / write circuit enters read mode. The read / write conversion unit controls the CMOS switch to turn off, and the operational amplifier and write verification unit are disconnected from the multi-value RRAM read / write circuit. The voltage across the RRAM is read directly, and after the read is completed, the status control signal is pulled to a high level.

4. The multi-value RRAM read / write circuit according to claim 1, characterized in that, The standard resistor unit includes multiple standard resistors connected in parallel. The current in the RRAM is a mirror image of the current in the standard resistor unit, so that the resistance of the RRAM is the total resistance of the parallel standard resistors. The number of parallel standard resistors is equal to the data width to be written to the RRAM. Each parallel standard resistor has two states: connected and disconnected. By controlling the connection or disconnection of each standard resistor, the total resistance of the parallel standard resistors is changed, thereby adjusting the resistance of the RRAM and realizing multi-value writing.

5. A read / write method for a multi-value RRAM read / write circuit, implemented based on the multi-value RRAM read / write circuit according to any one of claims 1 to 4, characterized in that, include: S1. Initialize the multi-value RRAM read / write circuit to provide a stable gate voltage for the RRAM control unit and standard resistor unit; S2. Set the status control signal to a high potential and the current mirror control signal to a low potential to put the leakage current sampling unit into the sampling state and perform leakage current sampling. S3. Set both the status control signal and the current mirror control signal to a low potential to put the leakage current sampling unit in a compensation state and generate a compensation current to offset the leakage current. S4. Adjust the potential of the read / write conversion signal to control the multi-value RRAM read / write circuit to enter write mode or read mode; S5. After a write or read operation is completed, pull the status control signal back to a high level.

6. The read / write method of the multi-value RRAM read / write circuit according to claim 5, characterized in that, The compensation current is generated using the following method: When the leakage current sampling unit is in the sampling state, it records the gate voltage. When the leakage current sampling unit is in the compensation state, it drives the current mirror included in the leakage current sampling unit based on the recorded gate voltage to generate a compensation current.

7. The read / write method for the multi-value RRAM read / write circuit according to claim 5, characterized in that, S4 specifically includes: When the read / write conversion signal is adjusted to a high potential, the multi-value RRAM read / write circuit enters the write mode. The voltage across the RRAM is kept stable based on the operational amplifier, and the write status is monitored based on the write verification unit. When the read / write conversion signal is adjusted to a low potential, the multi-value RRAM read / write circuit enters read mode and directly reads the voltage across the RRAM.

8. The read / write method of the multi-value RRAM read / write circuit according to claim 7, characterized in that, After entering write mode, the connection or disconnection of each standard resistor is controlled to change the total resistance value of the parallel standard resistors in the standard resistor unit, thereby adjusting the resistance value of the RRAM and realizing multi-value writing.

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