Asynchronous multi-facet independent scheme dynamic simulation resource sharing in three-dimensional memory devices

Abstract

A memory device including a plurality of memory planes is disclosed. The memory device further includes a first pump set coupled with the plurality of memory planes and configured to supply a first output voltage to a plurality of linear regulators during a steady phase, and a second pump set coupled with the plurality of memory planes and configured to supply a second output voltage to the plurality of linear regulators during a ramp phase. The plurality of linear regulators can include a first linear regulator set configured to regulate the first output voltage or the second output voltage to generate a first voltage bias for a first set of word lines of the plurality of memory planes, and a second linear regulator set configured to regulate the first output voltage or the second output voltage to generate a second voltage bias for a second set of word lines of the plurality of memory planes.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology, and more particularly to a method for performing asynchronous multifaceted independent read operations on a three-dimensional (3D) memory. Background Technology

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells. In 3D NAND memory, a single chip can include multiple dies capable of independently performing NAND operations (e.g., read, write, and erase). Each die can include multiple memory planes, and each memory plane can include multiple vertically stacked memory cells to increase storage capacity per unit area, where memory cells can be addressed from shared word lines.

[0003] Asynchronous Multi-Face Independent (AMPI) reads (meaning that multiple memory faces within a die can also perform asynchronous independent read operations) are a key feature on 3D NAND for accelerating random read performance. During an AMPI read process, 3D NAND devices can experience large capacitive loads as multiple charge pumps are ramped up to boost all unselected word lines. At the start of the ramp operation, the outputs of multiple charge pumps can be pulled down by sharing charge across the multiple memory faces within the 3D NAND device. To support AMPI, a common approach is to replicate analog resources so that each face can have its own drive circuitry (e.g., pumps and linear regulators) to supply word line bias. Summary of the Invention

[0004] This disclosure describes embodiments of a three-dimensional (3D) memory device and method for performing asynchronous multifaceted independent read operations thereon.

[0005] One aspect of this disclosure provides a memory device comprising: a plurality of memory planes; a first pump set coupled to the plurality of memory planes and configured to supply a first output voltage to a plurality of linear regulators during a stabilization phase; and a second pump set coupled to the plurality of memory planes and configured to supply a second output voltage to the plurality of linear regulators during a ramp phase; wherein the plurality of linear regulators includes: a first set of linear regulators configured to adjust the first output voltage or the second output voltage to generate a first voltage bias for a first set of word lines of the plurality of memory planes; and a second set of linear regulators configured to adjust the first output voltage or the second output voltage to generate a second voltage bias for a second set of word lines of the plurality of memory planes.

[0006] In some embodiments, each of the plurality of memory planes includes a plurality of memory strings correspondingly coupled to bit lines; and the first set of word lines has a higher impact on the string current of read operations of the memory device compared to the second set of word lines.

[0007] In some embodiments, the first group of word lines includes one or more selected word lines and one or more word lines directly adjacent to the selected word lines.

[0008] In some embodiments, the second set of word lines includes one or more dummy word lines or one or more dedicated word lines.

[0009] In some embodiments, the first linear regulator set includes a plurality of first linear regulator subsets, each of which corresponds to one of a plurality of memory planes.

[0010] In some embodiments, the second set of linear regulators includes: a second subset of linear regulators configured to regulate the first output voltage during a steady-state phase to generate a second voltage bias; and a third subset of linear regulators configured to regulate the second output voltage during a ramp-up phase to generate a second voltage bias.

[0011] In some embodiments, the memory device further includes a multiplexer circuit connected between the first pump set and the first linear regulator set, and connected between the second pump set and the first linear regulator set.

[0012] In some embodiments, the multiplexer circuit includes a plurality of bidirectional switches, each configured to alternately connect a corresponding subset of first linear regulators to a first pump set or a second pump set.

[0013] In some embodiments, the memory device further includes a controller configured to control one of a plurality of bidirectional switches to switch from a slewing power supply to a holding power supply after a word line slewing operation is completed.

[0014] In some embodiments, the memory device further includes a detector configured to automatically detect the state of a word line skewing operation.

[0015] In some embodiments, the memory device is a three-dimensional NAND memory device.

[0016] In some embodiments, the controller is further configured to: control a first pump set to supply a first output voltage to a plurality of linear regulators during a steady-state phase in an asynchronous multifaceted independent readout operation; and control a second pump set to supply a second output voltage to a plurality of linear regulators during a ramp phase in an asynchronous multifaceted independent readout operation.

[0017] In some embodiments, the controller is further configured to: in response to receiving a first read operation, control a first pump set and / or a second pump set to perform a first skewing operation on a first word line in a first memory plane; and after completing the first skewing operation on the first word line in the first memory plane, in response to receiving a second read operation, control the first pump set and / or the second pump set to perform a second skewing operation on a second word line in a second memory plane.

[0018] In some embodiments, the controller is further configured to: after completing a first swash operation on a first word line in a first memory plane, in response to receiving a second read operation and a third read operation, control a first pump set and / or a second pump set to simultaneously perform a second swash operation on a second word line in a second memory plane and a third swash operation on a third word line in a third memory plane.

[0019] In some embodiments, the controller is further configured to: after completing a second swash operation on a second word line in a second memory plane, in response to receiving a third read operation, control a first pump set and / or a second pump set to perform a third swash operation on a third word line in a third memory plane.

[0020] Another aspect of this disclosure provides a method for performing asynchronous multi-faceted independent read operations on a memory device comprising multiple memory faces, comprising: controlling a first pump set coupled to the multiple memory faces to supply a first output voltage to multiple linear regulators during a steady-state phase; controlling a second pump set coupled to the multiple memory faces to supply a second output voltage to the multiple linear regulators during a ramp phase; controlling a first set of linear regulators among the multiple linear regulators to adjust the first output voltage or the second output voltage to generate a first voltage bias for a first set of word lines of a memory face of the multiple memory faces of the memory device; and controlling a second set of linear regulators among the multiple linear regulators to adjust the first output voltage or the second output voltage to generate a second voltage bias for a second set of word lines of a memory face of the multiple memory faces of the memory device.

[0021] In some embodiments, the method further includes: controlling a second subset of linear regulators to adjust a first output voltage during a stabilization phase to generate a second voltage bias; and controlling a third subset of linear regulators to adjust a second output voltage during a ramp phase to generate a second voltage bias.

[0022] In some embodiments, the method further includes controlling a bidirectional switch to alternately connect a corresponding subset of the first linear regulator to a first pump set or a second pump set.

[0023] In some embodiments, the method further includes controlling a bidirectional switch to switch from a slewing power supply to a holding power supply after the word line slewing operation is completed.

[0024] In some embodiments, the method further includes: controlling a first pump set to supply a first output voltage to a plurality of linear regulators during a steady-state phase of an asynchronous multifaceted independent readout operation; and controlling a second pump set to supply a second output voltage to a plurality of linear regulators during a ramp phase of an asynchronous multifaceted independent readout operation.

[0025] In some embodiments, the method further includes: in response to receiving a first read operation, controlling a first pump set and / or a second pump set to perform a first skewing operation on a first word line in a first memory plane; and after completing the first skewing operation on the first word line in the first memory plane, in response to receiving a second read operation, controlling the first pump set and / or the second pump set to perform a second skewing operation on a second word line in a second memory plane.

[0026] In some embodiments, the method further includes: after completing a first swash operation on a first word line in a first memory plane, in response to receiving a second read operation and a third read operation, controlling a first pump set and / or a second pump set to simultaneously perform a second swash operation on a second word line in a second memory plane and a third swash operation on a third word line in a third memory plane.

[0027] In some embodiments, the method further includes: after completing a second swash operation on a second word line in a second memory plane, in response to receiving a third read operation, controlling a first pump set and / or a second pump set to perform a third swash operation on a third word line in a third memory plane.

[0028] Another aspect of this disclosure provides a memory system including: the memory device disclosed above and a memory controller, the memory controller being configured to control the memory device to perform asynchronous multi-faceted independent read operations.

[0029] Other aspects of this disclosure will be understood by those skilled in the art based on the specification, claims and drawings. Attached Figure Description

[0030] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0031] Figure 1A A block diagram of an exemplary system having a memory device according to some embodiments is shown.

[0032] Figure 1B A diagram of an exemplary memory card having a memory device according to some embodiments is shown.

[0033] Figure 1C A diagram of an exemplary solid-state drive (SSD) with memory is shown according to some embodiments.

[0034] Figure 2 A schematic block diagram of an exemplary hardware module construction of a memory system according to some embodiments is shown.

[0035] Figure 3 A schematic circuit diagram of an exemplary memory device including peripheral circuitry according to some aspects of this disclosure is shown.

[0036] Figure 4A A perspective view of a portion of an exemplary three-dimensional (3D) memory array structure according to some embodiments is shown.

[0037] Figure 4B A schematic diagram of an exemplary 3D memory device according to some embodiments is shown in plan view.

[0038] Figure 5 A schematic logic circuit diagram of an exemplary driving system for word lines of a 3D NAND device according to some embodiments is shown.

[0039] Figure 6 A schematic logic circuit diagram of another exemplary driving system for the word lines of a 3D NAND device according to some embodiments is shown.

[0040] Figures 7A-7D A schematic voltage-time evolution diagram of an exemplary driving system for word lines of a 3D NAND device under various implementations of memory operation according to some embodiments is shown.

[0041] The features and advantages of the invention will become more apparent from the specific embodiments set forth below when taken in conjunction with the accompanying drawings, in which similar reference numerals consistently identify corresponding elements. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The first appearance of an element in a drawing is indicated by the leftmost numeral(s) of the corresponding reference numeral(s).

[0042] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0043] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other constructions and arrangements can be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure can be used for a variety of other applications.

[0044] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in this specification indicate that the described embodiments include specific features, structures, or characteristics, but each embodiment may not necessarily include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge scope of those skilled in the art.

[0045] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a” or “described” can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0046] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on” something, but also includes “on” something with an intermediate feature or layer in between. Furthermore, “above” or “on top of” not only means “above” or “on top of” something, but can also include “above” or “on top of” something without an intermediate feature or layer in between (i.e., directly on) something.

[0047] Furthermore, spatial relative terms, such as “below,” “under,” “lower,” “above,” and “upper,” are used herein for ease of description to describe the relationship between one element or feature and another element(s) or feature as shown in the figures. Spatial relative terms are intended to cover different orientations in device use or process steps other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0048] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The front surface of the substrate is typically where semiconductor devices are formed, and therefore semiconductor devices are formed on the top side of the substrate, unless otherwise stated. The bottom surface is opposite to the front surface, and therefore the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or left unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0049] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer may extend over the entire upper or lower layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnects, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0050] In this disclosure, for ease of description, the term "layer" is used to refer to elements having substantially the same height along the vertical direction. For example, a word line and an underlying gate dielectric layer may be referred to as a "layer," a word line and an underlying insulating layer may be referred to together as a "layer," word lines having substantially the same height may be referred to as a "word line layer," or similar, and so on.

[0051] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter for a component or process step, set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may arise due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given quantity that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can indicate a value of a given quantity that varies, for example, within 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0052] In this disclosure, the terms "horizontal / horizontally / laterally" mean nominally parallel to the lateral surface of the substrate, and the terms "vertical" or "perpendicularly" mean nominally perpendicular to the lateral surface of the substrate.

[0053] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate.

[0054] Figure 1A A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1A As shown, system 100 may include a host 108 and a storage system 102, the storage system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0055] Memory device 104 can be any memory device disclosed herein, such as a NAND flash memory device. Consistent with the scope of this disclosure, memory controller 106 can control multiple programming passes of memory device 104 such that NGS operation is enabled on all memory cells (even those that have passed the corresponding verification operation) during a non-final programming pass of the multiple programming passes. Peripheral circuitry (e.g., word line drivers) can apply a low voltage (e.g., ground (GND) voltage) to the DSG of each memory string coupled to a selected word line, and can apply a low voltage or a negative voltage to the selected word line to enable NGS operation on all memory cells coupled to the selected word line during a non-final programming pass.

[0056] According to some embodiments, a memory controller 106 is coupled to a memory device 104 and a host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in high-duty-cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which serve as data storage for mobile devices such as smartphones, tablets, laptops, etc., and for enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as programming the memory device 104. The memory controller 106 may communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0057] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 1BIn one example shown, the memory controller 106 and a single memory device 104 can be integrated into a memory card 112. The memory card 112 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 112 may also include a connector for connecting the memory card 112 to a host computer (e.g., Figure 1A The host 108 is coupled to the memory card connector 114. In such a... Figure 1C In another example shown, the memory controller 106 and multiple memory devices 104 can be integrated into the SSD 116. The SSD 116 may also include a connection between the SSD 116 and a host (e.g., ...). Figure 1A The SSD connector 118 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 116 is greater than the storage capacity and / or operating speed of the memory card 112.

[0058] Figure 2 A diagram of an exemplary memory device 104 (e.g., NAND flash memory) with a memory cell array 202 and peripheral circuitry is shown. The peripheral circuitry includes a page buffer 204, a column decoder / bit line driver 206, a row decoder / word line driver 208, a voltage generator 210, control logic 212, a register 214, and an interface 216. Figure 3 A schematic circuit diagram of an exemplary memory device 104 is shown, including a memory cell array 202 and peripheral circuitry 302 coupled to the memory cell array 202. For ease of explanation, it is described together with other components. Figure 2 and Figure 3 Some components in it. Peripheral circuitry 302 may include... Figure 2 The components include page buffer 204, column decoder / bit line driver 206, row decoder / word line driver 208, voltage generator 210, control logic 212, register 214, and interface 216. It should be understood that in some examples, additional peripheral circuitry may also be included.

[0059] In some embodiments, the voltage generator 210 may include a plurality of charge pumps and a linear regulator. In some embodiments, the memory cell array may include a plurality of faces (i.e., face 0, face 1, face 2, and face 3). Although Figure 2Four faces (face 0, face 1, face 2, and face 3) are shown, but in some other embodiments, the NAND die may be divided into fewer or more faces (e.g., 1, 2, 6, 8, etc.). Faces include multiple memory cells, which may be grouped into memory blocks. A memory block is typically the smallest erasable entity in a NAND flash memory die. In one example, a memory block includes several cells coupled to the same bit line. A memory block includes one or more pages. The size of a page can vary depending on the implementation. In one example, a page has a size of 16kB. Page sizes less or more than 16kB are also possible (e.g., 512B, 2kB, 4kB, etc.).

[0060] It should be noted that NAND memory devices are capable of performing read operations on one face at a time. Such NAND memory devices have a single state machine for the entire die. If a read is being performed on one face, the other faces are idle. Therefore, such a read (called a single-face read) does not utilize all faces simultaneously. This lack of parallelism leads to high latency because, for example, the read becomes "blocked" after other reads.

[0061] Another type of operation is multi-sided operation (e.g., quad-sided read, which performs reads on all four sides at once). For multi-sided operations, there are several constraints on the command. For array commands, the array operations must be identical (e.g., programming, erasing, or reading, but not a combination), and the page types for those array operations must also be identical. The voltage biases used to access different page types (e.g., bottom page, top page, etc.) are different, and a single state machine on the die applies the same voltage bias to all sides. For random workloads, this requirement is difficult to meet for read commands. The probability of receiving reads of the same page type on all four sides is low for random workloads. Therefore, for random workloads, the improvement in read latency with quad-sided read is minimal. Thus, this characteristic is generally not used for random read workloads, which are typically considered the critical workload for SSDs (Solid State Drives).

[0062] Another solution attempted was to combine reads of different page types on different faces into a single command. However, all these reads are processed by the NAND as a single command, meaning there is a single start and finish for each read. Therefore, with this technique, the read duration is dominated by the worst (e.g., slowest) page type, and asynchronous reads are impossible. Thus, combining different page types on different faces into a single command also results in a minimal increase in performance and Quality of Service (QoS).

[0063] Unlike conventional NAND operations, independent multi-faceted operation enables independent and parallel operation of each face. A separate state machine for each face allows different bias voltages to be applied to each face to serve requests independently and simultaneously. This independent operation at the face level enables all NAND array commands, resulting in significant performance improvements. Array commands are those that trigger array operations, such as writing data to or from the array, erasing blocks, or other operations on the array.

[0064] In one example, each facet can receive and serve different array commands (e.g., read commands, programming commands, erase commands, etc.) and send and complete commands at different times. Non-array commands (e.g., reset commands, timing mode change commands, etc.) can remain as die-level commands. In an alternative example, read operations are allowed independently at the facet level. Other operations (e.g., programming and erase commands) are die-level operations. Furthermore, some support commands for reading (e.g., read status and read column enhancement commands) can also be facet-level commands.

[0065] like Figure 3 As shown, the memory cell array 202 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor. In one example, the memory cell 306 includes a transistor with a replacement gate. The memory cell 306 with a replacement gate typically has a low-resistance gate (e.g., a tungsten gate) and a charge-trapping layer between the gate and the channel, in which charge is trapped or stored to represent one or more bit values. In another example, the memory cell 306 may include a transistor with a floating gate (e.g., a high-resistance polysilicon gate) that stores charge indicating one or more bit values. Other architectures are also possible.

[0066] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0067] like Figure 3 As shown, each NAND memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. SSG 310 and DSG 312 are the respective gate electrodes of the SSG transistor and DSG transistor, which can be configured to activate the selected NAND memory string 308 (column of the array) during read and program operations. In some embodiments, the SSG 310 of the NAND memory strings 308 in the same block 304 is coupled to, for example, ground via the same source line (SL) 314 (e.g., a common SL). According to some embodiments, the DSG 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, from which data can be read via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0068] like Figure 3As shown, NAND memory strings 308 can be organized into multiple blocks 304, each of which may have a common source line 314. In some embodiments, each block 304 is the basic data unit for erase operations, i.e., all memory cells 306 on the same block 304 are erased simultaneously. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is the basic data unit for programming operations. The size of a page 320, in bits, may correspond to the number of NAND memory strings 308 coupled by word lines 318 in a block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, as well as gate lines coupling the control gates. In some cases, dummy word lines that do not contain user data can also be used in memory arrays adjacent to select-gate transistors. These dummy word lines can shield edge data word lines from certain edge effects.

[0069] Peripheral circuitry 302 can be coupled to memory cell array 202 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 can apply voltages to bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313 to perform multi-pass programming, including the proposed NGS scheme, in non-final programming passes. As described above, peripheral circuitry 302 can include any suitable circuitry for facilitating operation of memory cell array 202 by applying voltage and / or current signals via word line 318, source line 314, SSG line 315, and DSG line 313 to each target memory cell 306 via bit line 316 and sensing voltage and / or current signals from each target memory cell 306. Peripheral circuitry 302 can include various types of peripheral circuitry formed using MOS technology.

[0070] A programming sequence for a group of memory cells 306 may include programming all predetermined pages into the group of memory cells 306. The programming sequence may include one or more programming passes. A programming pass (which may include one or more programming cycles) may program one or more pages. A programming pass may include applying one or more valid programming voltages to the cells to be programmed, followed by applying one or more verification voltages to those cells to determine which cells have been programmed (subsequent programming passes generally do not apply valid programming voltages and / or verification voltages to cells that have been programmed). Applying valid programming voltages to a cell may include changing the voltage difference between the cell's control gate and channel to change the cell's threshold voltage. Thus, the voltage of the word line (coupled to the control gate of the target cell) and / or the cell's channel can be set to implement the application of valid programming voltages. Since programming voltage is typically used to refer to the voltage applied to the word line, valid programming voltage can be the voltage difference between the cell's control gate and channel (which can be synonymous with programming voltage if the channel is held at 0V).

[0071] Figure 4A A perspective view of a portion of an exemplary three-dimensional (3D) memory cell array structure 400 according to some embodiments is shown. The memory cell array structure 400 includes a substrate 430, an insulating film 431 over the substrate 430, a bottom select gate (BSG) layer 432 over the insulating film 431, and a plurality of control gate layers 433 (also referred to as “word lines (WL)”) stacked on top of the BSG 432 to form a film stack layer 435 of alternating conductive and dielectric layers. For clarity, in Figure 4A The dielectric layer adjacent to the control gate layer is not shown.

[0072] The control gate of each layer is separated by slot structures 416-1 and 416-2 through the film stack 435. The memory cell array structure 400 also includes a top selected gate layer (TSG) 434 above the stack of control gates 433. The stack of TSG 434, control gates 433, and BSG 432 is also referred to as a “gate electrode”. The memory cell array structure 400 also includes memory strings 412 and doped source line regions 444 in the portion of the substrate 430 between adjacent BSGs 432. Each memory string 412 includes a channel via 436 extending through the film stack 435 of insulating film 431 and alternating conductive and dielectric layers. The memory string 412 also includes a storage film 437 on the sidewall of the channel via 436, a channel layer 438 above the storage film 437, and a core fill film 439 surrounded by the channel layer 438. Memory cells 440 may be formed at the intersection of the control gate 433 and the memory string 412. The portion of the channel layer 438 beneath the control gate 433 is also referred to as the channel of the memory cell 440. The memory cell array structure 400 also includes multiple bit lines (BLs) 441 connected to the memory string 412 over the TSG 434. The memory cell array structure 400 also includes multiple metal interconnects 443 connected to the gate electrode via multiple contact structures 414. The edges of the film stack layer 435 are configured in a stepped shape to allow electrical connections to each gate electrode layer.

[0073] exist Figure 4A In this illustration, for illustrative purposes, three control gate layers 433-1, 433-2, and 433-3 are shown together with one layer of TSG 434 and one layer of BSG 432. In this example, each memory string 412 may include three memory cells 440-1, 440-2, and 440-3 corresponding to control gates 433-1, 433-2, and 433-3, respectively. The number of control gates and the number of memory cells may exceed three to increase storage capacity. The memory cell array structure 400 may also include other structures, such as TSG slicing structures, common source contacts, and dummy memory strings, etc. For simplicity, in Figure 4A These structures are not shown in the diagram.

[0074] Figure 4B A schematic diagram of an exemplary 3D memory device 450 according to some embodiments of the present disclosure is shown in plan view. The 3D memory device 450 may include multiple channel structure regions, such as memory planes, memory blocks, memory fingers, etc., and may form one or more through-array contact (TAC) structures between two adjacent channel structure regions. In some embodiments, such as Figure 4BAs shown, the 3D memory device 450 may include four or more memory surfaces 460, and each of the four or more memory surfaces 460 may include a plurality of memory blocks 465. It should be noted that... Figure 4B The arrangement of memory surfaces 460 in the 3D memory device 450 shown and the arrangement of memory blocks 465 in each memory surface 460 are merely examples and do not limit the scope of this disclosure.

[0075] The TAC structure may include one or more bit line (BL) TAC regions 471, one or more word line (WL) TAC regions 473, and one or more stepped structure (SS) TAC regions 480 at the edge of each memory surface 460. The one or more bit line (BL) TAC regions 471 are sandwiched by two adjacent memory blocks 465 in the bit line direction (labeled "BL" in the figure) of the 3D memory device and extend along the word line direction (labeled "WL" in the figure). The one or more word line (WL) TAC regions 473 are sandwiched by two adjacent memory blocks 465 in the word line direction (WL) and extend along the bit line direction (BL).

[0076] In some embodiments, the 3D memory device 450 may include a plurality of contact pads 490 arranged in a straight line at the edge of the 3D memory device 450. Interconnect contacts may be used to electrically interconnect the 3D memory device 450 to any suitable device and / or interface that provides drive power, receives control signals, transmits response signals, etc.

[0077] Figure 5 A schematic logic circuit diagram of an exemplary driving system for word lines of 3D NAND devices based on some existing systems is shown.

[0078] As described in the background section above, Asynchronous Multiface Independent (AMPI) reads allow multiple faces to perform asynchronous independent read operations, thus significantly accelerating the random read performance of 3D NAND. To support AMPI reads, a common approach is to design a drive system that replicates the analog resource, allowing each face to have its own drive circuitry, such as a pump and linear regulator, to supply word line bias. It should be noted that the pump, also known as a precharge driver, can be used to precharge the face before the read operation. The linear regulator can be a DC linear voltage regulator (e.g., a low-dropout regulator) that can adjust the pump's output voltage.

[0079] like Figure 5As shown, face 0 can be connected to pump 50 and multiple linear regulators 500, 501, ..., 50m; face 1 can be connected to pump 51 and multiple linear regulators 510, 511, ..., 51m; ...; face N can be connected to pump 5n and multiple linear regulators 5n0, 5n1, ..., 5nm. N is the number of faces, and m is the number of word lines in each face. That is, in a conventional scheme, each drive circuit is connected to a corresponding one of multiple faces without intermediate connections. In such a scheme, if the chip has four or more faces, the area and power costs of this arrangement may be relatively high.

[0080] Figure 6 A schematic logic circuit diagram of another exemplary driving system for the word lines of a 3D NAND device according to some embodiments is shown.

[0081] As shown in the figure, multiple pumps are separated into two groups: a first pump set 610 and a second pump set 620. The first pump set 610 can be used to supply a first output voltage to the linear regulator during the steady-state phase (pumps_hold state). The second pump set 620 can be used to supply a second output voltage to the linear regulator during the ramp phase (pumps_ramp state).

[0082] The linear regulators can also be separated into two groups: a first set of linear regulators 630 and a second set of linear regulators 650. The first set of linear regulators 630 can be used to regulate either a first output voltage or a second output voltage to supply a first word line voltage bias for the first set of word lines. In some embodiments, the first set of word lines can be of high importance to the performance of the NAND device. For example, compared to the second set of word lines, the first set of word lines can have a higher impact on the serial current of read operations of the memory device. The second set of linear regulators 640 can be used to regulate either the first output voltage or the second output voltage to supply a word line voltage bias for the second set of word lines. In some embodiments, the second set of word lines can be of lower importance to the performance of the NAND device compared to the first set of word lines. For example, compared to the first set of word lines, the second set of word lines can have a lower impact on the serial current of read operations of the memory device.

[0083] In some embodiments, the first linear regulator set 630 may include N first linear regulator subsets 640, each first linear regulator subset 640 corresponding to one of the N faces (e.g., face 0, face 1, ..., face N). Each first linear regulator subset 640 may include k first linear regulators 641. In some embodiments, each first linear regulator 641 may be used to drive one or more selected word lines that may be highly important to the performance of the NAND device. For example, each first linear regulator 641 may be used to drive a selected word line (e.g., WLn) and word lines directly adjacent to the selected word line (e.g., WLn+1 and WLn-1). In some embodiments, each first linear regulator 641 may be used to drive a first number of word lines, wherein the first number is greater than or equal to a predetermined number.

[0084] In some embodiments, the second linear regulator set 650 may include a second linear regulator subset 660 and a third linear regulator subset 670. Each second linear regulator 662 in the second linear regulator subset 660 may be used to adjust the first output voltage to generate a second word line voltage bias during a steady-state phase (pumps_hold state). Each third linear regulator 673 in the third linear regulator subset 670 may be used to adjust the second output voltage to generate a third word line voltage bias during a ramp phase (pumps_ramp state). The second linear regulators 662 and third linear regulators 673 may be used to drive one or more word lines that may have lower importance to the performance of the NAND device. For example, each second linear regulator 662 or third linear regulator 673 may be used to drive one or more dummy word lines or one or more dedicated word lines. In some embodiments, each second linear regulator 662 or third linear regulator 673 may be used to drive a second number of word lines, wherein the second number is less than a predetermined number.

[0085] With Figure 5 Compared to the construction of the pump and linear regulator shown, which replicates the number of surfaces, Figure 6 The configuration shown includes two pump sets and linear regulators shared across all surfaces. Each first linear regulator subset 640 may include k first linear regulators 641. The second linear regulator subset 660 may include (mk) second linear regulators 662, and the third linear regulator subset 670 may include (mk) third linear regulators 673. Thus, the total number of linear regulators can be significantly reduced from n×m to (n×k+2m-2k).

[0086] like Figure 6As shown, the ramp regulator output and the stabilizer output can be connected to multiplexer circuit 680 to interconnect to all surfaces (e.g., surface 0, surface 1, ..., surface N). Each first linear regulator subset can be alternately connected to the first pump set 610 and the second pump set 620 via bidirectional switch 688. In some embodiments, the controller (e.g., as shown) Figure 2 The control logic 212 shown can initiate a switch from the ramp power supply to the holding power supply after ramping is complete. A possible simple implementation can use a finely adjustable delay for this switch. Another improved implementation can be achieved through an automatic detection scheme for ramping completion.

[0087] It should be noted that most of the NAND x-path biases ramp up at the start of a read operation and remain at the same voltage level until they recover. Some biases may have a pulse at the start of a read operation. For example... Figure 6 The disclosed asynchronous multifaceted independent (AMPI) dynamic simulation resource sharing scheme shown can meet these requirements and can have better performance than... Figure 5 The area and power advantages of the scheme shown are illustrated.

[0088] In one example, the number of faces, n, is 4. To support 4-way AMPI, in the disclosed AMPI dynamic simulation resource-sharing scheme, only two pump sets can be used instead of four. As mentioned above, the total number of linear regulators is reduced from 4m to (2k+2m). Therefore, the disclosed AMPI dynamic simulation resource-sharing scheme has both area and power advantages by having a smaller number of pumps and linear regulators. In some embodiments, the trade-off is that there is sometimes additional latency depending on the time interval for AMPI to read command inputs.

[0089] like Figure 7A As shown, at time point t1, a first AMPI command for the first face (e.g., the AMPI read PI1 command as labeled) is entered, and the ramping resources, including the pump and linear regulator for the first face, can begin ramping at time point t11. After the ramping operation for the first face is completed at time point t2, a second AMPI command for the second face (e.g., the AMPI read PI2 command as labeled) is entered at time point t3, and the ramping resources, including the pump and linear regulator for the second face, can begin ramping at time point t33. Generally, the word line ramping time occupies a relatively small percentage of the read time. Figure 7A As shown, the delay time periods (t11-t1) and (t33-t3) are very small and negligible, and therefore can be considered as zero delay.

[0090] like Figure 7BAs shown, a first AMPI command for the first face is entered at time point t1 (e.g., AMPI read PI1 command as shown), and the swashplate resources, including the pump and linear regulator for the first face, can begin swashplate operation at time point t11. A second AMPI command for the second face is entered at time point t2 (e.g., AMPI read PI2 as labeled), while the first face is in the middle of word line swashplate operation. Because the swashplate resources, including the pump and linear regulator, are busy, there is an additional delay to wait until the first face completes swashplate operation at time point t3. Figure 7B As shown, the additional delay period for the second AMPI command is (t3-t2).

[0091] In one implementation, if multiple AMPI commands are input while a face is in the middle of a word line skewing, a possible implementation is that the controller can skew the word lines one face at a time. For example, automatic detection of the completion of a face's skewing can trigger the skewing operation for the next face. Such an implementation is simple, but one or more faces may have a relatively long delay. Figure 7C As shown, a first AMPI command for the first face is input at time point t1 (e.g., AMPI read PI1 command as shown), and the ramp resources, including the pump and linear regulator for the first face, can begin ramping at time point t11. A second AMPI command for the second face is input at time point t2 (e.g., AMPI read PI2 as labeled), and a third AMPI command for the third face is input at time point t3 (e.g., AMPI read PI0 as labeled), with the first face in the middle of the word line ramping. An additional delay period (t4-t2) exists for the second AMPI command to wait until the first face completes ramping at time point t4, and an additional delay period (t5-t3) exists for the third AMPI command to wait until the second face completes ramping at time point t5.

[0092] Another implementation is that the controller can simultaneously perform word line skewing on multiple faces. Assume that multiple AMPI commands are input while a face is in the middle of a WL skewing operation. After that face completes its skewing, all other waiting faces can simultaneously begin their word line skewing operations. Because multiple faces are skewing simultaneously, the skewing time can be longer than the time required to skew on a single face, but shorter than the time required to skew on multiple faces sequentially. Specifically, as... Figure 7DAs shown, a first AMPI command for the first face (e.g., AMPI read PI1 command as shown) is input at time t1, and the swashplate resources, including the pump and linear regulator for the first face, can begin swashplate operation at time t11. A second AMPI command for the second face (e.g., AMPI read PI2 as labeled) is input at time t2, and a third AMPI command for the third face (e.g., AMPI read PI0 as labeled) is input at time t3, with the first face in the middle of the word line swashplate operation. After the first face completes swashplate operation at time t4, both the first and second faces begin word line swashplate operation simultaneously at time t4. Therefore, the delay time period for the second AMPI command is (t4-t2), and the delay time period for the third AMPI command is (t4-t3).

[0093] In some practical implementations, the controller can set the data output time for each face to be naturally interleaved with the AMPI command inputs. This reduces the probability of encountering additional latency, thus mitigating the impact of low-level additional latency.

[0094] In addition, one potential concern is the noise introduced at the steady-state bias during power switching. (As mentioned above...) Figure 6 The linear regulators are divided into two groups for regulating either the first or second output voltage to generate a first priority voltage bias and a second priority voltage bias, respectively. The first set of linear regulators 630 for generating the first priority voltage bias is surface-dependent. The regulator pump power supply regulator can handle small pump power supply switching noise. The second set of linear regulators 640 for regulating either the first or second output voltage to generate the second priority voltage bias can have a small voltage drop at the output that does not cause a change in the array cell current. Therefore, the impact on sensing can be ignored.

[0095] In some embodiments, as described above Figure 2 The operation of the disclosed dynamic simulation resource sharing scheme can be directly executed by the control logic 212 of the NAND flash memory device, and can be combined with the corresponding software module. The software module can exist in any suitable storage / memory medium, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc.

[0096] Therefore, the disclosed dynamic simulation resource-sharing scheme can achieve AMPI with area and power advantages over conventional schemes. However, if the time interval for AMPI to read command inputs is very short, additional latency may exist. For practical use, the data output time for each face can be interleaved for AMPI command inputs, significantly reducing the negative impact of latency.

[0097] It should be noted that in NAND memory devices, the peripheral circuitry adjacent to and under the array architecture may have a larger circuit area than the array area, especially for products with an increased number of word line layers. Since the disclosed dynamic analog resource sharing scheme can save a large amount of circuit area, this saving directly translates to size and cost reduction.

[0098] One aspect of this disclosure provides a memory device comprising: a plurality of memory planes; a first pump set coupled to the plurality of memory planes and configured to supply a first output voltage to a plurality of linear regulators during a stabilization phase; and a second pump set coupled to the plurality of memory planes and configured to supply a second output voltage to the plurality of linear regulators during a ramp phase; wherein the plurality of linear regulators includes: a first set of linear regulators configured to adjust the first output voltage or the second output voltage to generate a first voltage bias for a first set of word lines of the plurality of memory planes; and a second set of linear regulators configured to adjust the first output voltage or the second output voltage to generate a second voltage bias for a second set of word lines of the plurality of memory planes.

[0099] In some embodiments, each of the plurality of memory planes includes a plurality of memory strings correspondingly coupled to bit lines; and the first set of word lines has a higher impact on the string current of read operations of the memory device compared to the second set of word lines.

[0100] In some embodiments, the first group of word lines includes one or more selected word lines and one or more word lines directly adjacent to the selected word lines.

[0101] In some embodiments, the second set of word lines includes one or more dummy word lines or one or more dedicated word lines.

[0102] In some embodiments, the first linear regulator set includes a plurality of first linear regulator subsets, each of which corresponds to one of a plurality of memory planes.

[0103] In some embodiments, the second set of linear regulators includes: a second subset of linear regulators configured to regulate the first output voltage during a steady-state phase to generate a second voltage bias; and a third subset of linear regulators configured to regulate the second output voltage during a ramp-up phase to generate a second voltage bias.

[0104] In some embodiments, the memory device further includes a multiplexer circuit connected between the first pump set and the first linear regulator set, and connected between the second pump set and the first linear regulator set.

[0105] In some embodiments, the multiplexer circuit includes a plurality of bidirectional switches, each configured to alternately connect a corresponding subset of first linear regulators to a first pump set or a second pump set.

[0106] In some embodiments, the memory device further includes a controller configured to control one of a plurality of bidirectional switches to switch from a slewing power supply to a holding power supply after a word line slewing operation is completed.

[0107] In some embodiments, the memory device further includes a detector configured to automatically detect the state of a word line skewing operation.

[0108] In some embodiments, the memory device is a three-dimensional NAND memory device.

[0109] In some embodiments, the controller is further configured to: control a first pump set to supply a first output voltage to a plurality of linear regulators during a steady-state phase in an asynchronous multifaceted independent readout operation; and control a second pump set to supply a second output voltage to a plurality of linear regulators during a ramp phase in an asynchronous multifaceted independent readout operation.

[0110] In some embodiments, the controller is further configured to: in response to receiving a first read operation, control a first pump set and / or a second pump set to perform a first skewing operation on a first word line in a first memory plane; and after completing the first skewing operation on the first word line in the first memory plane, in response to receiving a second read operation, control the first pump set and / or the second pump set to perform a second skewing operation on a second word line in a second memory plane.

[0111] In some embodiments, the controller is further configured to: after completing a first swash operation on a first word line in a first memory plane, in response to receiving a second read operation and a third read operation, control a first pump set and / or a second pump set to simultaneously perform a second swash operation on a second word line in a second memory plane and a third swash operation on a third word line in a third memory plane.

[0112] In some embodiments, the controller is further configured to: after completing a second swash operation on a second word line in a second memory plane, in response to receiving a third read operation, control a first pump set and / or a second pump set to perform a third swash operation on a third word line in a third memory plane.

[0113] Another aspect of this disclosure provides a method for performing asynchronous multi-faceted independent read operations on a memory device comprising multiple memory faces, comprising: controlling a first pump set coupled to the multiple memory faces to supply a first output voltage to multiple linear regulators during a steady-state phase; controlling a second pump set coupled to the multiple memory faces to supply a second output voltage to the multiple linear regulators during a ramp phase; controlling a first set of linear regulators among the multiple linear regulators to adjust the first output voltage or the second output voltage to generate a first voltage bias for a first set of word lines of a memory face of the multiple memory faces of the memory device; and controlling a second set of linear regulators among the multiple linear regulators to adjust the first output voltage or the second output voltage to generate a second voltage bias for a second set of word lines of a memory face of the multiple memory faces of the memory device.

[0114] In some embodiments, the method further includes: controlling a second subset of linear regulators to adjust a first output voltage during a stabilization phase to generate a second voltage bias; and controlling a third subset of linear regulators to adjust a second output voltage during a ramp phase to generate a second voltage bias.

[0115] In some embodiments, the method further includes controlling a bidirectional switch to alternately connect a corresponding subset of the first linear regulator to a first pump set or a second pump set.

[0116] In some embodiments, the method further includes controlling a bidirectional switch to switch from a slewing power supply to a holding power supply after the word line slewing operation is completed.

[0117] In some embodiments, the method further includes: controlling a first pump set to supply a first output voltage to a plurality of linear regulators during a steady-state phase of an asynchronous multifaceted independent readout operation; and controlling a second pump set to supply a second output voltage to a plurality of linear regulators during a ramp phase of an asynchronous multifaceted independent readout operation.

[0118] In some embodiments, the method further includes: in response to receiving a first read operation, controlling a first pump set and / or a second pump set to perform a first skewing operation on a first word line in a first memory plane; and after completing the first skewing operation on the first word line in the first memory plane, in response to receiving a second read operation, controlling the first pump set and / or the second pump set to perform a second skewing operation on a second word line in a second memory plane.

[0119] In some embodiments, the method further includes: after completing a first swash operation on a first word line in a first memory plane, in response to receiving a second read operation and a third read operation, controlling a first pump set and / or a second pump set to simultaneously perform a second swash operation on a second word line in a second memory plane and a third swash operation on a third word line in a third memory plane.

[0120] In some embodiments, the method further includes: after completing a second swash operation on a second word line in a second memory plane, in response to receiving a third read operation, controlling a first pump set and / or a second pump set to perform a third swash operation on a third word line in a third memory plane.

[0121] Another aspect of this disclosure provides a memory system including: the memory device disclosed above and a memory controller, the memory controller being configured to control the memory device to perform asynchronous multi-faceted independent read operations.

[0122] The foregoing description of the specific embodiments so fully reveals the general nature of this disclosure that others can readily modify and / or adapt these specific embodiments for various applications by applying knowledge of the art without excessive experimentation and without departing from the general concept of this disclosure. Therefore, based on the disclosure and guidance presented herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is for descriptive rather than limiting purposes, and that the terminology or terminology of this specification should be interpreted by those skilled in the art based on the disclosure and guidance.

[0123] The embodiments of this disclosure have been described above using functional building blocks that illustrate implementations of specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries can be defined as long as the specified functions and their relationships are properly performed.

[0124] The summary and abstract section may set forth one or more, but not all, exemplary embodiments of this disclosure as conceived by the inventors, and therefore is not intended to limit this disclosure and the appended claims in any way.

[0125] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A memory device, comprising: Multiple memory planes; A first pump set, coupled to the plurality of memory surfaces, is configured to supply a first output voltage to the plurality of linear regulators during a steady-state phase. as well as A second pump set, coupled to the plurality of memory surfaces, is configured to supply a second output voltage to the plurality of linear regulators during the ramp-up phase; The plurality of linear regulators include: A first set of linear regulators, configured to regulate either the first output voltage or the second output voltage to generate a first voltage bias for a first set of word lines for each of the plurality of memory planes, and A second set of linear regulators is configured to regulate either the first output voltage or the second output voltage to generate a second voltage bias for a second set of word lines for each of the plurality of memory planes.

2. The memory device according to claim 1, wherein: Each of the plurality of memory planes includes a plurality of memory strings correspondingly coupled to bit lines; and Compared to the second set of word lines, the first set of word lines has a higher impact on the serial current of the read operation of the memory device.

3. The memory device according to claim 1 or 2, wherein, The first group of character lines includes one or more selected character lines and the character lines directly adjacent to the one or more selected character lines.

4. The memory device according to claim 1 or 2, wherein, The second group of character lines includes one or more virtual character lines or one or more dedicated character lines.

5. The memory device according to claim 1, wherein, The first set of linear regulators includes multiple subsets of first linear regulators, each subset of first linear regulators corresponding to one of the multiple memory planes.

6. The memory device according to claim 1 or 5, wherein, The second set of linear regulators includes: A second subset of linear regulators, configured to regulate the first output voltage during the stabilization phase to generate the second voltage bias; and A third linear regulator subset is configured to regulate the second output voltage during the ramp-up phase to generate the second voltage bias.

7. The memory device of claim 1 further includes a multiplexer circuit, the multiplexer circuit being connected between the first pump set and the first linear regulator set and between the second pump set and the first linear regulator set.

8. The memory device according to claim 7, wherein, The multiplexer circuit includes multiple bidirectional switches, each configured to alternately connect a corresponding subset of the first linear regulator to either the first pump set or the second pump set.

9. The memory device according to claim 8, further comprising: A controller configured to control one of the plurality of bidirectional switches to switch from the swashplate power supply to the holding power supply after the word line swashplate operation is completed.

10. The memory device according to claim 9, further comprising: A detector configured to automatically detect the state of the word line slant operation.

11. The memory device according to claim 1, wherein, The memory device is a three-dimensional NAND memory device.

12. The memory device according to claim 9, wherein, The controller is also configured to: The first pump set is controlled to supply the first output voltage to the plurality of linear regulators during the stabilization phase of the asynchronous multifaceted independent readout operation; and The second pump set is controlled to supply the second output voltage to the plurality of linear regulators during the ramp phase of the asynchronous multifaceted independent readout operation.

13. The memory device according to claim 9, wherein, The controller is also configured to: In response to receiving a first read operation, control the first pump set and / or the second pump set to perform a first slant change operation on the first word line in the first memory plane; and After completing the first slant operation on the first word line in the first memory plane, in response to receiving a second read operation, the first pump set and / or the second pump set are controlled to perform a second slant operation on the second word line in the second memory plane.

14. The memory device according to claim 13, wherein, The controller is also configured to: After completing the first slant operation of the first word line in the first memory plane, in response to receiving the second read operation and the third read operation, the first pump set and / or the second pump set are controlled to simultaneously perform the second slant operation of the second word line in the second memory plane and the third slant operation of the third word line in the third memory plane.

15. The memory device according to claim 13, wherein, The controller is also configured to: After completing the second swash operation on the second word line in the second memory plane, in response to receiving a third read operation, the first pump set and / or the second pump set are controlled to perform a third swash operation on the third word line in the third memory plane.

16. A method for performing asynchronous multi-face independent read operations on a memory device comprising multiple memory faces, comprising: Control the first pump set coupled to the plurality of memory surfaces to supply a first output voltage to the plurality of linear regulators during the stabilization phase; Control the second pump set coupled to the plurality of memory surfaces to supply a second output voltage to the plurality of linear regulators during the ramp-up phase; Controlling a first set of linear regulators among the plurality of linear regulators to adjust the first output voltage or the second output voltage to generate a first voltage bias for a first set of word lines for each of the plurality of memory planes of the memory device, and A second set of linear regulators among the plurality of linear regulators is controlled to adjust the first output voltage or the second output voltage to generate a second voltage bias for a second set of word lines for each of the plurality of memory planes of the memory device.

17. The method according to claim 16, wherein, The plurality of memory planes include a plurality of memory strings correspondingly coupled to bit lines, and the first set of word lines has a higher influence on the string current of the read operation of the memory device compared to the second set of word lines.

18. The method according to claim 16, wherein, The first group of character lines includes one or more selected character lines and the character lines directly adjacent to the one or more selected character lines.

19. The method of claim 16, wherein, The second group of character lines includes one or more virtual character lines or one or more dedicated character lines.

20. The method of claim 16, further comprising: Control a second subset of linear regulators to adjust the first output voltage during the stabilization phase to generate the second voltage bias; as well as A third linear regulator subset is controlled to adjust the second output voltage during the ramp-up phase to generate the second voltage bias.

21. The method of claim 16, further comprising: Control the bidirectional switch to alternately connect the corresponding first linear regulator subset to the first pump set or the second pump set.

22. The method of claim 21, further comprising: Control the bidirectional switch to switch from the slewing power supply to the holding power supply after the word line slewing operation is completed.

23. The method of claim 16, further comprising: The first pump set is controlled to supply the first output voltage to the plurality of linear regulators during the stabilization phase of the asynchronous multifaceted independent readout operation; as well as The second pump set is controlled to supply the second output voltage to the plurality of linear regulators during the ramp phase of the asynchronous multifaceted independent readout operation.

24. The method of claim 16, further comprising: In response to receiving a first read operation, control the first pump set and / or the second pump set to perform a first slant change operation on the first word line in the first memory plane; and After completing the first slant operation on the first word line in the first memory plane, in response to receiving a second read operation, the first pump set and / or the second pump set are controlled to perform a second slant operation on the second word line in the second memory plane.

25. The method of claim 24, further comprising: After completing the first slant operation of the first word line in the first memory plane, in response to receiving the second read operation and the third read operation, the first pump set and / or the second pump set are controlled to simultaneously perform the second slant operation of the second word line in the second memory plane and the third slant operation of the third word line in the third memory plane.

26. The method of claim 24, further comprising: After completing the second swash operation on the second word line in the second memory plane, in response to receiving a third read operation, the first pump set and / or the second pump set are controlled to perform a third swash operation on the third word line in the third memory plane.

27. A memory system comprising: Memory device, the memory device comprising: Multiple memory planes; A first pump set, configured to supply a first output voltage to a plurality of linear regulators during a steady-state phase; and A second pump set is configured to supply a second output voltage to the plurality of linear regulators during the ramp-up phase. The plurality of linear regulators include: A first set of linear regulators, configured to regulate either the first output voltage or the second output voltage to generate a first voltage bias for a first set of word lines for each of the plurality of memory planes, and A second set of linear regulators, configured to regulate either the first or the second output voltage to generate a second voltage bias for a second set of word lines for each of the plurality of memory planes; and A memory controller configured to control the memory device to perform asynchronous multi-faceted independent read operations.

28. The memory system of claim 27, wherein: Each of the plurality of memory planes includes a plurality of memory strings correspondingly coupled to bit lines; and Compared to the second set of word lines, the first set of word lines has a higher impact on the serial current of the read operation of the memory device.

29. The memory system according to claim 27 or 28, wherein, The first group of character lines includes one or more selected character lines and the character lines directly adjacent to the one or more selected character lines.

30. The memory system according to claim 27 or 28, wherein, The second group of character lines includes one or more virtual character lines or one or more dedicated character lines.

31. The memory system according to claim 27, wherein, The first set of linear regulators includes multiple subsets of first linear regulators, each subset of first linear regulators corresponding to one of the multiple memory planes.

32. The memory system according to claim 27 or 31, wherein, The second set of linear regulators includes: A second subset of linear regulators, configured to regulate the first output voltage during the stabilization phase to generate the second voltage bias; and A third linear regulator subset is configured to regulate the second output voltage during the ramp-up phase to generate the second voltage bias.

33. The memory system according to claim 27, wherein, The memory device further includes a multiplexer circuit connected between the first pump set and the first linear regulator set, and connected between the second pump set and the first linear regulator set.

34. The memory system according to claim 33, wherein, The multiplexer circuit includes multiple bidirectional switches, each configured to alternately connect a corresponding subset of the first linear regulator to either the first pump set or the second pump set.

35. The memory system of claim 34, further comprising: A controller configured to control one of the plurality of bidirectional switches to switch from the swashplate power supply to the holding power supply after the word line swashplate operation is completed.

36. The memory system of claim 35, further comprising: A detector configured to automatically detect the state of the word line slant operation.

37. The memory system according to claim 27, wherein, The memory device is a three-dimensional NAND memory device.

38. The memory system according to claim 35, wherein, The controller is also configured to: The first pump set is controlled to supply the first output voltage to the plurality of linear regulators during the stabilization phase of the asynchronous multifaceted independent readout operation; and The second pump set is controlled to supply a second output voltage to the plurality of linear regulators during the ramp phase of the asynchronous multifaceted independent readout operation.

39. The memory system according to claim 35, wherein, The controller is also configured to: In response to receiving a first read operation, control the first pump set and / or the second pump set to perform a first slant change operation on the first word line in the first memory plane; and After completing the first slant operation on the first word line in the first memory plane, in response to receiving a second read operation, the first pump set and / or the second pump set are controlled to perform a second slant operation on the second word line in the second memory plane.

40. The memory system of claim 39, wherein, The controller is also configured to: After completing the first slant operation of the first word line in the first memory plane, in response to receiving the second read operation and the third read operation, the first pump set and / or the second pump set are controlled to simultaneously perform the second slant operation of the second word line in the second memory plane and the third slant operation of the third word line in the third memory plane.

41. The memory system according to claim 39, wherein, The controller is also configured to: After completing the second swash operation on the second word line in the second memory plane, in response to receiving a third read operation, the first pump set and / or the second pump set are controlled to perform a third swash operation on the third word line in the third memory plane.

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