Waveguide surface acoustic wave device and method of manufacturing the same

Abstract

This application provides a guided surface acoustic wave (SAW) device and its manufacturing method, which is optimized for high-frequency operation, atomic diffusion prevention, and wave confinement. The device includes a wafer substrate having a multilayer stacked structure bonded by hypersonic bonding layers. The multilayer stacked structure includes a piezoelectric thin film layer, a hypersonic diffusion-blocking layer, and a discrete hypersonic bonding layer. The manufacturing process includes depositing a trap-rich layer, oxidation / planarization, hydrogen / helium ion implantation for smart lift-off transfer, applying the blocking layer / bonding layer, room-temperature surface activated bonding (SAB), piezoelectric thin film transfer, annealing, chemical mechanical polishing (CMP), and formation of interdigital transducers. The device enhances wave confinement, reduces losses, improves the filter quality factor (Q), and ensures performance consistency, making it suitable for 4G / 5G RF filters, sensors, and resonators.

Description

Technical Field

[0001] This application relates to the technical field of surface acoustic wave (SAW) devices and manufacturing methods thereof, and more specifically, to a waveguide-type surface acoustic wave device and manufacturing method thereof. Background Technology

[0002] Surface acoustic wave (SAW) devices, capable of converting electrical signals into mechanical acoustic waves propagating along the surface of a piezoelectric wafer substrate, have been widely used in communications, sensors, and filters. Traditional SAW devices typically use bulk piezoelectric materials such as lithium tantalate (LiTaO3) or lithium niobate (LiNbO3) as substrates, with interdigital transducers (IDTs) patterned on the surface to excite and receive acoustic waves.

[0003] During surface acoustic wave (SAW) propagation, the electrical signal applied to the interdigital transducer generates an alternating electric field. Through the piezoelectric effect, this alternating electric field induces mechanical strain in the substrate, thereby exciting sound waves propagating along the surface. These sound waves are typically Rayleigh waves, whose particles move elliptically in a plane perpendicular to the surface and parallel to the propagation direction, decaying exponentially towards the interior of the bulk material. In some orientations, a leaky surface acoustic wave (LSAW) mode is employed, which radiates energy into the bulk material but can be confined in multilayer structures. The wave velocity depends on the material; for piezoelectric materials, the wave velocity is typically around 3000-5000 m / s. The operating frequency is determined by the spacing of the interdigital transducers, where f = v / λ, where v is the SAW velocity of the substrate material and λ is the wavelength of the SAW. The spacing is the center-to-center distance between two adjacent identical electrodes in the interdigital transducer. When an electrical signal is applied, the interdigital transducer generates a periodic strain field on the substrate surface. To achieve the strongest excitation (resonance), the period of the strain field (determined by the interdigital transducer spacing) must match the desired acoustic wavelength. Therefore, the operating frequency is set by the physical dimensions of the interdigital transducers.

[0004] Recent technological advancements have explored the use of multilayer structures to enhance device performance, such as improving wave confinement, reducing losses, and achieving higher operating frequencies. For example, acoustic wave devices with multilayer piezoelectric wafer substrates have been proposed to optimize wave propagation characteristics. These structures typically involve bonding thin piezoelectric layers to a carrier substrate with higher sound velocities to guide acoustic waves and prevent leakage into the bulk material. For instance, some SAW devices incorporate piezoelectric layers on quartz or silicon carrier substrates to suppress acoustic radiation and improve device efficiency.

[0005] Similar multilayer structures are also used in commercial technologies. Murata Manufacturing's ultra-high performance (IHP) SAW devices combine thin piezoelectric layers with Bragg reflector stacks or multilayer substrates to concentrate leaky surface acoustic wave energy, achieving higher quality factors and coupling coefficients. For example, U.S. Patent No. 9,450,167B2 discloses a SAW device with an intermediate layer to improve performance. Qualcomm's Ultra-SAW technology uses Soitec's piezoelectric-on-insulator (POI) wafers, which place thin lithium tantalate or lithium niobate layers on silicon with buried oxide layers, providing high-performance RF filters for 4G / 5G applications with low loss at frequencies up to 2.7 GHz. Details of the manufacturing methods for such bonded wafers and SAW devices can be found in Soitec's U.S. Patent No. 10,381,998B2, which discloses ion implantation and bonding techniques for multilayer substrates.

[0006] However, the fabrication of such multilayer devices remains challenging. Bonding processes, especially those involving high temperatures, can cause atoms (such as lithium, tantalum, or niobium) in the piezoelectric layer to diffuse into adjacent layers, degrading material and device performance. In some cases, diffusion-blocking layers have been considered, but their integration with high-velocity acoustic bonding layers remains limited. Simulations and characterizations of multilayer SAW devices demonstrate the need for precise control of layer thickness and materials to achieve the desired acoustic velocities and minimize losses. Furthermore, in applications such as biosensing or chemical sensing, SAW devices require stable multilayer structures to maintain sensitivity and reliability.

[0007] Furthermore, layered SAW sensors have been developed, integrating additional thin films to enhance functionality. However, existing designs have not fully addressed the interface stability issues during annealing, nor the need for trap-rich layers in silicon-based substrates to mitigate parasitic effects. Recent advances in low-dimensional materials for SAW sensors highlight the importance of hypersonic layers, but anti-diffusion barrier layers are often overlooked. Overall, while existing technologies provide fundamental multilayer SAW structures, improved devices integrating anti-diffusion barrier layers in hypersonic bonding schemes are still needed to enable high-temperature processing without material degradation. Summary of the Invention

[0008] This application provides a guided surface acoustic wave (SAW) device with a multilayer stacked structure, designed to enhance acoustic wave confinement, prevent atomic diffusion during manufacturing, and support high operating frequencies.

[0009] In this device, one side of the piezoelectric thin film layer supports the interdigital transducer (IDT) metal structure, while the other side features a high-velocity diffusion barrier layer and a discrete high-velocity bonding layer, which is connected to the supporting wafer. This structure ensures that the support layer has a high velocity of sound to effectively guide sound waves, while the diffusion barrier layer prevents the migration of elements in the piezoelectric layer during annealing at temperatures up to 600°C.

[0010] Furthermore, the technical solution includes: selecting piezoelectric materials such as lithium tantalate (LiTaO3) or lithium niobate (LiNbO3) with a thickness between 0.1 and 1 micrometer; and selecting alumina (Al2O3) or silicon nitride (SiN2O3). x The diffusion barrier layer, such as alumina, has a thickness less than 1 / 20 of the sound wave wavelength. Amorphous silicon or similar materials are chosen as the bonding layer, and its total thickness is also less than 1 / 20 of the wavelength. The carrier wafer may include a silicon substrate with a buried silicon oxide (BOX) layer and a trap-rich polycrystalline silicon layer for improved electrical isolation. The sound velocity hierarchy is as follows: the diffusion barrier layer has the highest sound velocity (e.g., the longitudinal sound velocity of alumina is approximately 11,100 m / s), followed by the bonding layer (e.g., the sound velocity of amorphous silicon is approximately 8,300 m / s), and when a silicon carrier wafer is used, the buried silicon oxide layer has the lowest sound velocity (approximately 5,960 m / s). This sound velocity hierarchy ensures effective wave guidance and minimal leakage.

[0011] Room temperature surface activated bonding (SAB) technology minimizes the problem of coefficient of thermal expansion (CTE) mismatch, enabling the use of various material combinations for piezoelectric wafers and carrier wafers. The silicon-based bonding layer ensures reliable adhesion and prevents atomic diffusion under the protection of the barrier layer, resulting in filters with a higher quality factor (Q) while improving the performance consistency of devices on the same wafer and between wafers in the same batch.

[0012] This application also relates to a manufacturing method comprising the following steps: depositing a trap-rich polycrystalline silicon layer, oxidation and planarization, ion implantation to achieve smart lift-off transfer of the piezoelectric thin film, applying a barrier layer and a bonding layer, room-temperature surface-activated bonding, separation, high-temperature annealing to restore the lattice, chemical mechanical polishing (CMP), and formation of an interdigital transducer. This method enables robust integration of sensitive piezoelectric materials without diffusion-related degradation, thereby resulting in superior performance for filters, resonators, and sensors. Attached Figure Description

[0013] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0014] Figure 1The front view of the substrate 1 shows a first side 1 (a) and a second side 1 (b). Figure 2 This shows the state in which a polycrystalline silicon layer 2 is epitaxially grown on the first side of a silicon substrate 1; Figure 3 This shows the state of an oxide layer 3 epitaxially grown on the surface of the polycrystalline silicon layer 2; Figure 4 This shows the state of the multilayer substrate 101 formed after planar polishing of oxide layer 3; Figure 5 This is a front view of silicon support substrate 4; Figure 6 This is a front view of a piezoelectric material substrate 5, which has a first side 5 (a) and a second side 5 (b); Figure 7 This shows the bonding state between the piezoelectric material substrate 5 and the silicon support substrate 4; Figure 8 The image shows the state of thinning and polishing of the bond between the piezoelectric material substrate 5 and the silicon support substrate 4 from the first side of the piezoelectric material substrate 5. Figure 9 This illustrates the state in which the bond between the piezoelectric material substrate 5 and the silicon support substrate 4 is implanted from the first side of the piezoelectric material substrate 5 to form a damaged layer inside the piezoelectric material substrate 5. Figure 10 This shows the state in which an anti-diffusion barrier layer 6 is deposited on the surface of a piezoelectric material substrate 5 to form a bond 102; Figure 11A This shows the state of an intermediate bonding layer deposited on the surface of the anti-diffusion barrier layer 6 on the piezoelectric material substrate 5 of the bonding body 102; Figure 11B This shows the state of an intermediate bonding layer deposited on the surface of the oxide layer 3 of the multilayer substrate 101; Figure 12 This shows the state in which the multilayer substrate 101 and the bonding body 102 are bonded together to form the bonding body 103; Figure 13 This shows the state in which the piezoelectric material substrate 5 is separated from the damaged layer after the bonding body 103 is processed; Figure 14 This shows the state of processing the bond 103 and thinning the piezoelectric material substrate 5; Figure 15 The diagram shows the state in which electrodes 10 are fabricated on the surface of a piezoelectric material substrate 5 to form an acoustic wave device. Detailed Implementation

[0015] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present application can be combined with each other.

[0016] The guided surface acoustic wave (SAW) device of this application comprises a multilayer stacked structure bonded by a high-velocity acoustic layer, optimized for wave guidance and fabrication stability. During SAW propagation in this structure, interdigital transducers excite surface waves (Rayleigh waves or leakage waves) in the piezoelectric layer. Due to the velocity mismatch with the underlying high-velocity acoustic layer, the energy is confined near the surface. The acoustic waves propagate horizontally and decay exponentially into the substrate, minimizing bulk radiation losses and resulting in a higher quality factor (Q) and lower insertion loss.

[0017] In a preferred embodiment, the structure uses a carrier wafer as the base substrate. The material selection for the carrier wafer must meet mechanical strength and compatibility requirements to suit specific application scenarios. Silicon (Si) with a buried oxide (BOX) layer is chosen due to its high compatibility with standard wafer fabrication processes and packaging plants, enabling seamless integration into CMOS-compatible processes and cost-effective mass production. Silicon carbide (SiC) has excellent heat dissipation properties, with a thermal conductivity of approximately 490 W / m. Kelvin is suitable for high-power RF applications with demanding thermal management requirements. Sapphire (Al2O3) offers advantages in RF performance, including low dielectric loss, a stable dielectric constant, and high thermal conductivity (approximately 35 W / m). With its superior Kelvin, chemical stability, and thermal shock resistance, diamond can reliably operate in high-frequency, high-temperature environments. However, compared to silicon or silicon carbide, it is more expensive and its application in standard manufacturing processes is less widespread. Spinel (MgAl2O4) offers similar RF advantages, such as low dielectric loss and high mechanical strength, making it suitable for enhancing surface acoustic wave propagation and acousto-optic properties. Although its cost is higher and its manufacturing process compatibility is limited, it still has application value in dedicated high-performance RF devices. Diamond possesses excellent RF characteristics, including the highest thermal conductivity (approximately 2000 W / m). With its high Kelvin content and excellent mechanical properties, it supports ultra-high frequency operation with minimal loss. Although its high cost and difficulty in integrating into standard manufacturing processes are challenging, its unparalleled performance more than compensates for these shortcomings in demanding applications. When silicon is used as the carrier wafer, a trap-rich polysilicon layer is placed beneath the buried oxide layer to capture free carriers and reduce parasitic conductivity, thereby improving RF performance.

[0018] The high-velocity acoustic bonding layer consists of two parts: the first part is bonded to the piezoelectric wafer, and the second part is bonded to the carrier wafer. Both parts are preferably made of the same material, such as amorphous silicon (A-Si, with a sound velocity of approximately 8,300 m / s), polycrystalline silicon (with a sound velocity of approximately 8,400 m / s), monocrystalline silicon (with a sound velocity of approximately 8,433 m / s), or silicon nitride (with a sound velocity of approximately 11,000 m / s), or alumina (with a sound velocity of approximately 11,100 m / s). In one embodiment, both parts have the same thickness, and the total thickness is less than 1 / 20th of the wavelength of the acoustic wave at the device's operating frequency (for 5G applications, the operating frequency is typically in the gigahertz range, corresponding to a wavelength of approximately 1-5 micrometers). This thin bonding layer minimizes acoustic loss while providing a robust interface.

[0019] The first and second parts of the bonding layer are bonded using a room temperature surface activated bonding (SAB) process, which ensures low-stress integration and reduces the risk of thermal expansion coefficient mismatch (e.g., the thermal expansion coefficient of lithium tantalate is about 14-16 ppm / Kelvin, while that of silicon is about 2.6 ppm / Kelvin), allowing for a wider range of material choices and avoiding thermally induced defects.

[0020] A high-velocity diffusion-blocking layer is provided between the piezoelectric layer and the first bonding portion. The material of this barrier layer can be selected from alumina (Al2O3, with a sound velocity of approximately 11,100 m / s) and silicon nitride (SiN). x The sound velocity of the barrier layer is approximately 11,000 m / s, while that of the bonding layer is higher. The sound velocity of the bonding layer is higher than that of the low-velocity layers such as silicon dioxide in the stacked structure. The barrier layer is less than 1 / 20th of the wavelength of the sound wave and thinner than the total thickness of the bonding layer, effectively blocking diffusion without significantly affecting wave propagation. The sound velocity hierarchy (barrier layer > bonding layer > silicon dioxide buried layer (if present)) enhances the wave confinement effect by guiding the sound wave back to the piezoelectric surface.

[0021] The piezoelectric thin film layer, with a thickness of 0.1 to 1 micrometer, is supported on a diffusion-blocking layer. Suitable piezoelectric materials include lithium tantalate (LiTaO3, surface acoustic wave velocity approximately 4,100-4,200 m / s, bulk longitudinal acoustic velocity approximately 6,100 m / s), lithium niobate (LiNbO3, surface acoustic wave velocity approximately 3,800-4,000 m / s, bulk longitudinal acoustic velocity approximately 7,300 m / s), aluminum nitride (AlN, surface acoustic wave velocity approximately 5,600 m / s), and scandium-doped aluminum nitride (Sc). x Al 1-x N, where x < 0.5, with surface acoustic wave velocities up to approximately 5,000 m / s, zinc oxide (ZnO, with a surface acoustic wave velocity of approximately 2,700 m / s), or lead zirconate titanate (PZT, with a surface acoustic wave velocity of approximately 4,000 m / s). An interdigitated transducer metal structure, typically made of aluminum or copper alloy, is formed on the exposed side of the piezoelectric layer to excite and detect surface acoustic waves.

[0022] During operation, the high-velocity acoustic properties of the barrier layer and bonding layer confine sound waves to the piezoelectric surface, reducing bulk radiation losses. When lithium tantalate or lithium niobate are used as the piezoelectric material, the diffusion-blocking barrier layer is particularly crucial. It prevents lithium, tantalum, niobium, or oxygen atoms from migrating into the silicon-based bonding layer during high-temperature annealing at up to 600°C, thus protecting the piezoelectric performance. This structure not only enables filters with higher quality factors but also ensures performance consistency between devices on the same wafer and between wafers in the same batch, thanks to uniform layer transfer and minimal diffusion variability.

[0023] The manufacturing method of this device includes the following steps: (a) Depositing trap-rich polycrystalline silicon regions on a silicon carrier substrate to mitigate electroparasitic effects; (b) The surface rich in trap regions is oxidized to generate a silicon dioxide layer, and the silicon dioxide layer is planarized to obtain a smooth bonding surface; (c) Provide a piezoelectric wafer substrate and bond its first side to a temporary silicon wafer carrier for operation; (d) Thinning of the piezoelectric wafer substrate from the exposed second side in preparation for transfer; (e) By implanting hydrogen and helium ions, ion implantation is performed from the exposed side surface of the piezoelectric wafer substrate to form a damage layer at a predetermined depth inside the piezoelectric wafer substrate, thereby achieving a smart lift-off process. (f) Apply a diffusion-blocking layer to the piezoelectric layer after implantation to prevent subsequent diffusion; (g) Applying the first portion of the bonding layer onto the anti-proliferation barrier layer; (h) Applying a second portion of the bonding layer onto the planarized silicon dioxide layer obtained in step (b); (i) A room temperature surface activation bonding process is used to bond the piezoelectric wafer substrate portion to the silicon wafer substrate portion; (j) Separate the piezoelectric wafer substrate along the damaged layer, thereby transferring the piezoelectric thin film layer onto the silicon carrier substrate; (k) Perform high-temperature annealing up to 600°C to restore the piezoelectric lattice damage caused by the implantation process (step (e)); (l) A chemical mechanical polishing (CMP) process is used to polish the thin portion of the piezoelectric thin film layer to obtain a smooth surface; (m) An interdigitated transducer electrode structure is formed on the polished piezoelectric layer to complete the device fabrication.

[0024] This manufacturing method ensures precise film transfer and recovery, and the anti-diffusion barrier layer allows for rigorous annealing processes without compromising material integrity. Thickness or materials can be adjusted to meet specific frequency requirements, while the core structure retains its waveguide advantages.

[0025] The present application will now be described in further detail with reference to the accompanying drawings.

[0026] like Figure 1 and Figure 2 As shown, a high resistivity substrate 1 is prepared, having a first side surface 1(a) and a second side surface 1(b), and a polycrystalline silicon layer 2 is epitaxially grown on the first side surface 1(a). Then, as... Figure 3 As shown, an oxide layer 3 is formed on the polycrystalline silicon layer 2. The oxide layer 3 is planarized and polished to a predetermined thickness. Polishing reduces the roughness of the oxide layer surface 3(c), thereby improving bonding strength. Figure 4 As shown, a substrate 1, a polysilicon layer 2, and an oxide layer 3 form a multilayer stack 101. In this embodiment, the oxide layer 3 serves as a buried oxide (BOX) layer, and the polysilicon layer 2 is a trap-rich layer. Therefore, the stack 101 is a substrate structure comprising a silicon substrate, a trap-rich polysilicon layer, and a buried oxide layer.

[0027] At the same time, such as Figure 5 and Figure 6 As shown, a supporting silicon substrate 4 and a piezoelectric material substrate 5 are fabricated. An intermediate bonding layer is formed on the second side 5(b) of the piezoelectric material substrate 5 and the first side 4(a) of the supporting silicon substrate 4. Then, as shown... Figure 7 As shown, the bonding surface 5(b) of the piezoelectric material substrate 5 is bonded to the surface 4(a) of the supporting silicon substrate 4 to form a bonded body. The intermediate bonding layer helps to improve the bonding force.

[0028] Then, as Figure 8As shown, the first exposed side 5(a) of the piezoelectric material substrate 5 is processed and thinned to a predetermined thickness to reduce stress caused by thermal mismatch of dissimilar materials in subsequent processes. The thinned piezoelectric material substrate 5 has a smooth surface 5(c).

[0029] Then, as Figure 9 As shown, an implantation process is performed from the surface 5(c) of the piezoelectric material substrate 5 to form a damage layer at a predetermined depth 5(B).

[0030] In an exemplary embodiment, the damaged layer 5(B) is formed by ion implantation. Suitable implantation parameters include, for example, approximately 5 × 10¹ 6 A dose of atoms per square centimeter and an energy of approximately 100 kiloelectron volts are injected into hydrogen ions, which then move at approximately 1 × 10¹ 7 Helium ions are injected at a dose of atoms per square centimeter and an energy of approximately 30 kiloelectron volts. These parameters can be adjusted according to the desired depth of the damage layer and the specific piezoelectric material used.

[0031] Then, as Figure 10 As shown, a thin diffusion barrier layer 6 is deposited on the surface of the piezoelectric material substrate 5. The diffusion barrier layer 6 can prevent the diffusion of elements such as tantalum and lithium. The supporting silicon substrate 4, the piezoelectric material substrate 5 and the diffusion barrier layer 6 form a multilayer stack 102.

[0032] Then, as Figure 11A and Figure 11B As shown, an intermediate bonding layer 7 is deposited on the surface of the multilayer stack 101, and an intermediate bonding layer 8 is deposited on the surface of the multilayer stack 102. These first and second bonding layers (7, 8) together constitute the hypersonic bonding layer of this device. The intermediate bonding layer helps to improve the bonding force.

[0033] Then, as Figure 12 As shown, the bonding surface 7(a) of the intermediate bonding layer 7 on the multilayer stack 101 is directly bonded to the bonding surface 8(a) of the intermediate bonding layer 8 on the multilayer stack 102 to form a bonding body 103.

[0034] Then, as Figure 13 As shown, the bond 103 is processed and heated in an oven. The piezoelectric substrate 5 is separated into two parts 5(A) and 5(C) along the damaged layer 5(B). Part 5(C) with the supporting substrate 4 is reusable. Part 5(A) is transferred onto the multilayer stack 101. The piezoelectric layer 5(A) and the multilayer stack 101 form a new multilayer stack 104.

[0035] Then, as Figure 14As shown, the multilayer stack 104 is processed to planarize to a predetermined thickness. The piezoelectric material is annealed. Residual damaged piezoelectric layers can be removed by polishing, and lattice degradation can be restored by annealing. The initial room-temperature surface activation bonding process alleviates thermal stress during bonding. Subsequent high-temperature annealing is performed after a stable bond is formed. This annealing process is feasible because the bonding layer material (e.g., amorphous silicon) has thermal stability, and the diffusion barrier layer provides protection, preventing elemental diffusion and interface degradation during the heat treatment process.

[0036] Then, as Figure 15 As shown, a predetermined electrode 10 is fabricated on the surface 5(d) of a piezoelectric material substrate 5(A) to obtain an acoustic wave device 105. Furthermore, according to the above embodiment ( Figures 1 to 15 The acoustic wave device 105 includes an anti-diffusion barrier layer 6, an intermediate layer 7 on the side of the multilayer stack 101, and an intermediate layer 8 on the side of the piezoelectric material substrate 5(A). This application is not limited to this embodiment, and only one of the intermediate layers may be provided (only the intermediate layer 7 on the side of the multilayer stack 101 or only the intermediate layer 8 on the side of the piezoelectric material substrate).

[0037] The components of this application are described in detail below.

[0038] Known surface acoustic wave devices 104 include thin-film surface acoustic wave devices and Lamb wave type surface acoustic wave devices. For example, a thin-film surface acoustic wave device is fabricated by setting an input-side interdigital transducer (also called a comb electrode or interdigital electrode) for exciting surface acoustic waves and an output-side interdigital transducer for receiving surface acoustic waves on the surface of a piezoelectric single-crystal substrate. By applying a high-frequency signal to the input-side interdigital transducer, an electric field is generated between the electrodes, thereby exciting and propagating surface acoustic waves on the piezoelectric material substrate. Then, the output-side interdigital transducer, positioned along the propagation direction, converts the propagating surface acoustic waves into an electrical signal output.

[0039] The electrode pattern on the piezoelectric material substrate 5 is preferably formed by sputtering or electron beam evaporation to create conductive metal electrodes (e.g., aluminum, copper, titanium, platinum, tungsten, gold, chromium, ruthenium, and combinations thereof), more preferably aluminum or an aluminum alloy. The aluminum alloy used is preferably aluminum doped with 0.01 to 0.1% copper by weight. More preferably, a stacked layer structure is used: a titanium layer (typically 5 to 30 nanometers thick) as an adhesion layer, and an aluminum-copper alloy layer containing 1% copper (typically 5 to 600 nanometers thick).

[0040] The piezoelectric material substrate 5 used in this application can be made of a single crystal. When the material of the piezoelectric material substrate 5 is a single crystal, it is easier to excite the piezoelectric effect on the surface of the piezoelectric material substrate 5.

[0041] Specifically, the material of the piezoelectric material substrate 5 can be selected from X-cut lithium tantalate, Y+36°-cut lithium tantalate, Y+42°-cut lithium tantalate, Y+162°-cut lithium tantalate, Z-cut lithium tantalate, X-cut lithium niobate, Y-cut lithium niobate, Y+36°-cut lithium niobate, Y+64°-cut lithium niobate, Y+128°-cut lithium niobate, Y+163°-cut lithium niobate, Z-cut lithium niobate, scandium-doped aluminum nitride (Sc x Al 1-x N, where x is 0 to 0.5 in atomic percentage), preferably lithium tantalate or lithium niobate wafers with a thickness of 300 to 600 micrometers. Lithium tantalate or lithium niobate is suitable for piezoelectric surface wave devices in high-frequency and broadband applications due to its high surface acoustic wave propagation speed and large electromechanical coupling coefficient. Furthermore, the normal direction of the main surface 5(d) of the piezoelectric material substrate 5 is not particularly limited. However, for example, when the piezoelectric material substrate 5 is made of lithium tantalate, it is preferable to use a substrate rotated 36 to 47 degrees (e.g., 42 degrees) relative to the surface acoustic wave propagation direction (X-axis) towards the Y-axis or Z-axis, as lower propagation loss can be obtained. Furthermore, although the size of the piezoelectric material substrate 5 is not particularly limited, for example, the diameter can be 50 to 150 millimeters, and the thickness of the piezoelectric material layer 5(A) can be 300 to 800 nanometers, a preferred range within the broader inventive scope of 0.1 to 1 micrometer.

[0042] The material of the substrate or support substrate can be selected from: <111> , <110> or <100> Oriented silicon wafers, C-axis <0001> Oriented sapphire wafers, spinel wafers, silicon carbide wafers, and glass wafers. In this embodiment, it is preferred to use... <100> A high-resistivity silicon wafer 21 with specific orientation. An exemplary diameter of this silicon wafer is 150 mm ± 0.2 mm, and a thickness of 675 μm ± 15 μm. The silicon may be P-type or N-type doped, and the crystal orientation is... <100> ±0.05°. Orientation direction is... <110> Other exemplary characteristics include: resistivity greater than 3000 ohms. The thickness is less than 5 micrometers, the total thickness variation is less than 20 micrometers, the warpage is less than 20 micrometers, and the curvature is less than 20 micrometers.

[0043] According to this application, the anti-diffusion barrier layer 6 on the piezoelectric material substrate 5(A) is composed of silicon nitride, aluminum oxide, tantalum nitride, or titanium nitride. Silicon nitride (SiN) or silicon tetranitride (Si3N4) is preferred because silicon nitride or silicon tetranitride can effectively prevent tantalum or niobium from diffusing from lithium tantalate or lithium niobate to the supporting substrate. Furthermore, silicon nitride (SiN) xThe wave velocity of surface acoustic waves (SAWs) can easily reach over 8000 m / s, significantly higher than the phase velocity of SAWs in lithium tantalate (approximately 4000 m / s). This allows the waveguide to be confined within the piezoelectric layer through total internal reflection, greatly reducing energy leakage to the substrate. Therefore, the device's quality factor is effectively improved (at least 20% higher than traditional multilayer SAW devices, with performance differences between devices on the same wafer and between wafers in the same batch less than ±5%), laying the foundation for realizing high-performance, low-loss thin-film SAW devices. The thickness of the anti-diffusion barrier layer 6 is typically preferred to be between 1 nm and 10 nm.

[0044] According to this application, the bonding layer 7 on the oxide layer 3 of the multilayer stack 101 and the bonding layer 8 on the diffusion barrier layer 6 of the multilayer stack 102 are composed of amorphous silicon. With the assistance of surface-activated bonding, the amorphous silicon layer can provide a strong bonding force greater than 2.8 joules / square meter.

[0045] The total thickness of the intermediate bonding layers is typically preferred to be between 8 nanometers and 30 nanometers. Furthermore, although there is no particular limitation on the thickness ratio of intermediate layers 7 and 8, for example, they may not be equal (e.g., one is 4 nanometers and the other is 10 nanometers), for example, when the piezoelectric substrate 5 is made of lithium tantalate, it is preferred that the thicknesses of bonding layer 7 and bonding layer 8 are equal.

[0046] The method for forming the intermediate bonding layer 7 on the side of the piezoelectric material substrate 5 and the intermediate bonding layer 8 on the side of the oxide layer 3 is not particularly limited, including sputtering, chemical vapor deposition (CVD), and vapor deposition. Low-temperature physical vapor deposition sputtering is more preferred.

[0047] There are no particular limitations on the method for forming the anti-diffusion barrier layer 6 on the side of the piezoelectric material substrate 5, including sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), and vapor deposition. Atomic layer deposition is more preferred.

[0048] When the intermediate layer 8 on the piezoelectric material layer 5(A) side is disposed on the bonding surface 6(a) of the anti-diffusion barrier layer 6, and the intermediate layer 7 on the substrate side is disposed on the bonding surface 3(c) of the oxide layer 3, the bonding surfaces 7(a) and 8(a) of the intermediate layers 7 and 8 are planarized, and then surface activation bonding activation is performed.

[0049] Planarization refers to fine planarization within a plane, with an arithmetic mean surface roughness Ra < 0.3 nanometers.

[0050] Planarization methods for bonding surfaces 3(c), 5(c), 6(a), 7(a), and 8(a) include grinding, chemical mechanical polishing (CMP), and finishing. Furthermore, the arithmetic mean surface roughness Ra of the planarized surfaces is preferably 0.5 nm or less, more preferably 0.3 nm or less.

[0051] Then, as an activation method for bonded surfaces 4(a), 5(a), 7(a), and 8(a), it is preferable to use a method with an activation level below 1×10⁻⁶. -5 Under high vacuum, each bonded surface 4(a), 5(a), 7(a), and 8(a) were irradiated with argon fast atomic beam (FAB).

[0052] Then, the activated surfaces are brought into contact and bonded under vacuum. The temperature at this time can be ambient temperature, specifically 40°C or lower, more preferably 30°C or lower. Furthermore, the temperature during the bonding process is more preferably 20°C or higher and 25°C or lower. The bonding pressure is preferably 100 to 20,000 Newtons.

[0053] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A guided-wave surface acoustic wave (SAW) device, characterized in that, The wafer substrate includes a multilayer stacked structure bonded by a high-velocity acoustic bonding layer, the multilayer stacked structure comprising: A piezoelectric thin film layer having a first side and a second side, the first side carrying an interdigital transducer (IDT) metal structure for exciting and receiving surface acoustic waves; A high-velocity diffusion-preventing layer is disposed on the second side of the piezoelectric thin film layer, the diffusion-preventing layer being used to prevent atomic diffusion in the piezoelectric thin film layer during high-temperature processing; and The high-velocity bonding layer is divided into a first part and a second part. The first part is disposed on the surface of the anti-diffusion barrier layer, and the second part is disposed on the surface of the carrier wafer. The high-velocity bonding layer has a higher sound velocity than the low-velocity layer in the stacked structure, thereby guiding and confining surface acoustic waves.

2. The waveguide device according to claim 1, characterized in that, The sound velocity of the anti-diffusion barrier layer is higher than that of the first and second portions of the bonding layer.

3. The waveguide device according to claim 1, characterized in that, said piezoelectric thin film layer is selected from any one of lithium tantalate (LiTa03), lithium niobate (LiNb03), aluminum nitride (AIN), scandium-doped aluminum nitride (Sc x Al 1-x N, where x < 0.5), zinc oxide (ZnO), and lead zirconate titanate (PZT).

4. The waveguide device according to claim 3, characterized in that, The thickness of the piezoelectric thin film layer is from 0.1 micrometers to 1 micrometer.

5. The waveguide device according to claim 1, characterized in that, The high sonic velocity anti-diffusion barrier layer is selected from any of aluminum oxide (AI2O3), silicon oxide (SiO2), silicon nitride (SiN x ), hafnium oxide (HfO2), tantalum nitride (TaN), and titanium nitride (TiN).

6. The waveguide device according to claim 5, characterized in that, The thickness of the anti-diffusion barrier layer is less than 1 / 20 of the wavelength of the acoustic wave at the operating frequency of the waveguide device, and is thinner than the total thickness of the first and second parts of the high-velocity bonding layer.

7. The waveguide device according to claim 1, characterized in that, Both parts of the bonding layer are made of the same material.

8. The waveguide device according to claim 7, characterized in that, The two parts of the bonding layer are selected from any one of the following materials: amorphous silicon (A-Si), polycrystalline silicon, monocrystalline silicon, alumina, and silicon nitride.

9. The waveguide device according to claim 7, characterized in that, The two parts of the bonding layer have the same thickness.

10. The waveguide device according to claim 1, characterized in that, The total thickness of the two parts of the bonding layer is less than 1 / 20 of the wavelength of the acoustic wave at the operating frequency of the waveguide device.

11. The waveguide device according to claim 10, characterized in that, The thickness of the anti-diffusion barrier layer is less than the total thickness of the two parts of the bonding layer.

12. The waveguide device according to claim 1, characterized in that, The carrier wafer is selected from the following materials: (a) a silicon substrate (Si) containing a silicon dioxide buried layer (BOX); (b) silicon carbide (SiC); (c) sapphire; (d) spinel; and (e) diamond.

13. The waveguide device according to claim 12, characterized in that, The silicon-supported wafer also includes a trap-rich polycrystalline silicon layer disposed beneath the silicon dioxide buried layer.

14. The waveguide device according to claim 1, characterized in that, The two parts of the bonding layer are bonded by a room temperature surface activated bonding (SAB) process at a temperature below 5 × 10⁻⁶. -6 Torr bonding under vacuum.

15. The waveguide device according to claim 14, characterized in that, The piezoelectric thin film layer is selected from lithium tantalate (LiTaO3) and lithium niobate (LiNbO3) crystals; the bonding layer is amorphous silicon; the diffusion barrier layer is used to prevent lithium, tantalum, niobium and oxygen atoms from migrating into the silicon-based bonding layer and the supporting substrate at annealing temperatures of up to 600°C and above.

16. The waveguide device according to claim 14, characterized in that, The room temperature surface activation bonding process reduces the thermal expansion coefficient (CTE) mismatch between the piezoelectric wafer and the carrier wafer, allowing for a wider range of material choices for the piezoelectric thin film layer and the carrier wafer.

17. The waveguide device according to claim 1, characterized in that, The bonding layer provides reliable bonding at room temperature, and the diffusion barrier layer protects the bonding layer from the diffusion of atoms in the piezoelectric thin film layer.

18. The waveguide device according to claim 1, characterized in that, Compared to conventional multilayer SAW devices without the aforementioned anti-diffusion barrier layer, the SAW filter has a quality factor (Q) that is improved by at least 20%, and the performance difference between devices on the same wafer and between wafers in the same batch is less than ±5%.

19. A method for manufacturing the waveguide device of claim 1, characterized in that, Includes the following steps: (a) Depositing a trap-rich polycrystalline silicon film structure on a silicon carrier substrate; (b) Oxidize the surface portion of the trap-rich region to generate a silicon dioxide layer, and further planarize the silicon dioxide layer; (c) Provide a piezoelectric wafer substrate and bond its first side to a temporary silicon wafer carrier; (d) Thinning the piezoelectric wafer substrate from the exposed second side; (e) Ion implantation is performed on the exposed side surface of the piezoelectric wafer substrate by hydrogen ion and helium ion implantation, thereby forming a damage layer at a predetermined depth on the piezoelectric wafer substrate. (f) Apply an anti-diffusion barrier layer to the surface of the piezoelectric layer after injection; (g) Applying a first portion of a bonding layer onto the anti-diffusion barrier layer; (h) Apply the second portion of the bonding layer onto the planarized silicon dioxide layer of step (b); (i) Bonding the piezoelectric wafer substrate portion to the silicon wafer substrate portion; (j) Separate the piezoelectric wafer substrate along the damaged layer and transfer the piezoelectric thin film layer onto the silicon carrier substrate portion; (k) Perform high-temperature annealing up to 600°C to restore the damaged piezoelectric lattice layer caused by the implantation process in step (e); (l) The piezoelectric thin film layer transferred onto the silicon substrate is polished using a chemical mechanical polishing (CMP) process; (m) An interdigitated transducer electrode structure is formed on the polished piezoelectric layer.

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