Method and device for multi-network chip model interconnection simulation

Abstract

This invention provides a method and apparatus for simulating interconnection between multiple network chip models. The method includes: a first simulation process sending a routing configuration request, including a first simulation process identifier, to an interconnect server; when a second simulation process needs to send a message to the first simulation process, the second simulation process encapsulates the message, the second simulation process identifier, and the first simulation process identifier into a message and publishes the message to the interconnect server; the interconnect server receives and parses the message; when the message includes the first simulation process identifier, the interconnect server forwards the message to the first simulation process; the first simulation process receives and parses the message to extract the message. According to the technical solution of this invention, the running speed of the entire chip network simulation can be significantly improved, solving the problem of not being able to start the entire chip network simulation due to insufficient single-machine memory resources, and reducing the development and debugging workload for achieving interoperability of the underlying networks.

Description

Technical Field

[0001] This invention relates to the field of simulation testing technology, and specifically to a method and apparatus for simulating interconnection of multiple network chip models. Background Technology

[0002] Chip simulation models typically run within the operating system as a single process and a single thread. Since the entire process has only one execution flow (one thread), it can only be scheduled by the OS to run on one CPU core at any given time, and cannot utilize multiple cores simultaneously. When simulating network interconnection of network chip models, if the chip simulation model has high processing complexity and the number of chips in the network simulation is large, the simulation model program cannot utilize the computer's multi-core CPU resources in parallel, resulting in slow running speed. In some cases, the large scale of the simulated chip network may even lead to insufficient memory resources on a single machine, preventing the simulation program from starting.

[0003] Therefore, a technical solution is needed that can significantly improve the running speed of the entire chip network simulation, solve the problem that the entire chip network simulation cannot be started due to insufficient single-machine memory resources, and reduce the development and debugging workload for achieving interoperability of the underlying network. Summary of the Invention

[0004] The present invention aims to provide a method and apparatus for simulating interconnection of multiple network chip models, which can significantly improve the running speed of the entire chip network simulation, solve the problem that the entire chip network simulation cannot be started due to insufficient single-machine memory resources, and reduce the development and debugging workload for achieving interconnection of underlying networks.

[0005] According to one aspect of the present invention, a method for simulating interconnection of multiple network chip models is provided, the method comprising:

[0006] The first simulation process sends a routing configuration request, including the identifier of the first simulation process, to the interconnect server. The request is used to instruct the interconnect server to forward the message to the first simulation process when it receives the message including the identifier of the first simulation process. The first simulation process corresponds to a network chip model, and the identifier of the first simulation process corresponds to the identifier of the network chip model.

[0007] When the second simulation process needs to send a message to the first simulation process, the second simulation process encapsulates the message, the second simulation process identifier, and the first simulation process identifier into a message and publishes the message to the interconnect server. Here, the second simulation process corresponds to another network chip model, and the second simulation process identifier corresponds to the identifier of the other network chip model.

[0008] The interconnect server receives and parses the message;

[0009] When the message includes the identifier of the first simulation process, the interconnect server forwards the message to the first simulation process;

[0010] The first simulation process receives and parses the message to extract the packet.

[0011] According to some embodiments, the first simulation process runs on one CPU core of a multi-core CPU, and the second simulation process runs on another CPU core of the multi-core CPU; or, the first simulation process runs on one CPU core of a multi-core CPU, and the second simulation process runs on one CPU core of another multi-core CPU.

[0012] According to some embodiments, the first simulation process and the second simulation process run on the same multi-core CPU of the same server, or the first simulation process runs on the multi-core CPU of one server and the second simulation process runs on the multi-core CPU of another server.

[0013] According to some embodiments, the network chip model is a standalone executable file, which runs as a simulation process on a CPU core when it is executed.

[0014] According to some embodiments, when the receive buffer of the first simulation process is insufficient, the first simulation process sends a cancellation request for the routing configuration including the identifier of the first simulation process to the interconnect server, wherein the cancellation request is used to instruct the interconnect server to return an error message to the second simulation process when it receives a message including the identifier of the first simulation process.

[0015] According to another aspect of the present invention, an apparatus for simulating interconnection of multiple network chip models is provided, the apparatus comprising: at least one server and an interconnection server.

[0016] The at least one server is used to run the first simulation process and the second simulation process, wherein...

[0017] The first simulation process is used to send a routing configuration request including a first simulation process identifier to the interconnect server. The routing configuration request is used to instruct the interconnect server to forward the message to the first simulation process when it receives the message including the first simulation process identifier. The first simulation process corresponds to a network chip model, and the first simulation process identifier corresponds to the identifier of the network chip model.

[0018] When the second simulation process needs to send a message to the first simulation process, the second simulation process encapsulates the message, the first simulation process identifier, and the second simulation process identifier into a message and publishes the message to the interconnect server. The second simulation process corresponds to another network chip model, and the second simulation process identifier corresponds to the identifier of the other network chip model.

[0019] The interconnect server is used to receive and parse the message;

[0020] When the message includes the identifier of the first simulation process, the interconnect server is further configured to forward the message to the first simulation process;

[0021] The first simulation process is also used to receive and parse the message in order to extract the message.

[0022] According to some embodiments, the first simulation process runs on one CPU core of a multi-core CPU, and the second simulation process runs on another CPU core of the multi-core CPU; or, the first simulation process runs on one CPU core of a multi-core CPU, and the second simulation process runs on one CPU core of another multi-core CPU.

[0023] According to some embodiments, the first simulation process and the second simulation process run on the same multi-core CPU of the same server, or the first simulation process runs on the multi-core CPU of one server and the second simulation process runs on the multi-core CPU of another server.

[0024] According to some embodiments, the network chip model is a standalone executable file, which runs as a simulation process on a CPU core when it is executed.

[0025] According to some embodiments, when the receive buffer of the first simulation process is insufficient, the first simulation process is further configured to send a cancellation request for the routing configuration including the identifier of the first simulation process to the interconnect server, wherein the cancellation request is configured to instruct the interconnect server to return an error message to the second simulation process when it receives a message including the identifier of the first simulation process.

[0026] According to an embodiment of the present invention, a first simulation process sends a routing configuration request, including a first simulation process identifier, to an interconnect server. When a second simulation process needs to send a message to the first simulation process, the second simulation process encapsulates the message, the second simulation process identifier, and the first simulation process identifier into a message and publishes the message to the interconnect server. The interconnect server receives and parses the message. When the message includes the first simulation process identifier, the interconnect server forwards the message to the first simulation process, which receives and parses the message to extract the message. For each network chip, the corresponding network chip simulation model is instantiated as an independent simulation process to perform single-machine multi-process or multi-machine multi-process multi-network chip interconnect simulation. The technical solution of the present invention can solve the resource bottleneck problem and optimize the running speed of large-scale network communication chip model interconnect simulation.

[0027] According to embodiments of the present invention, the processes of each chip simulation model forward and exchange message packets through an interconnection server, achieving the goal of parallel operation of the chip simulation models in a network. This is applicable to simulation scenarios such as switch chips, smart network card chips, forwarding chips, and high-speed interconnection chips for data centers. The technical solution according to the embodiments of this application can significantly improve the running speed of the entire chip network simulation, solve the problem that the entire chip network simulation cannot be started due to insufficient single-machine memory resources, and reduce the development and debugging workload for achieving interoperability of the underlying network.

[0028] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit the invention. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0030] Figure 1 A flowchart illustrating a method for simulating multi-network chip interconnection using a network chip simulation model according to an example embodiment is shown.

[0031] Figure 2 This diagram illustrates the principle of message routing and forwarding according to an example embodiment.

[0032] Figure 3 A schematic diagram illustrating the principle of a multi-chip networking simulation scheme according to an example embodiment is shown.

[0033] Figure 4 A schematic diagram illustrating a multi-chip networking simulation process according to an example embodiment is shown.

[0034] Figure 5 A block diagram of a computing device according to an exemplary embodiment is shown. Detailed Implementation

[0035] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0036] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a full understanding of embodiments of the invention. However, those skilled in the art will recognize that the technical solutions of the invention can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of the invention.

[0037] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0038] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0039] It should be understood that although the terms first, second, third, etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Therefore, the first component discussed below may be referred to as the second component without departing from the teachings of the present invention. As used herein, the term "and / or" includes all combinations of any one and more of the associated listed items.

[0040] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of exemplary embodiments, and the modules or processes in the drawings are not necessarily essential for implementing the present invention, and therefore cannot be used to limit the scope of protection of the present invention.

[0041] In traditional implementations, chip simulation models typically run on the operating system in a single-process, single-threaded manner. This means that the entire simulation program contains only one execution flow (i.e., one thread) throughout its lifecycle. Therefore, at any given time, the operating system scheduler can only allocate that thread to a single CPU core for execution. Even if the target computer is equipped with a multi-core or even many-core processor, this single-threaded architecture cannot effectively utilize the parallel computing capabilities of modern hardware.

[0042] This limitation is particularly pronounced when conducting network interconnection simulations of network chip models. In large-scale networking scenarios, it is often necessary to simulate multiple chip instances simultaneously, and to model their interconnection topology, data paths, control logic, and even complex protocol interactions. Each chip model may already contain highly detailed logic gate-level or transaction-level modeling, and its internal state updates, event processing, and packet forwarding operations incur huge computational overhead. If dozens or even hundreds of such chip models are integrated into the same simulation environment, the overall computational load will increase exponentially.

[0043] However, because the simulation program still uses a traditional single-threaded architecture, the simulation logic of all chip models must be executed serially—that is, the state updates and communication interactions of each chip within each time step must be processed sequentially. This not only severely restricts the simulation throughput and real-time performance but also results in an extremely slow overall simulation speed, making it difficult to meet the needs of R&D iterations or large-scale verification. More seriously, as the network scale expands, the state data, buffers, and connection tables of all chip models must reside in the address space of the same process, which can easily lead to the rapid exhaustion of single-machine memory resources (especially physical memory and virtual address space). In extreme cases, the system may refuse to start the simulation program directly due to insufficient memory allocation, making large-scale chip network simulation simply infeasible in a single-machine environment.

[0044] To address this, the present invention proposes a method and apparatus for multi-network chip model interconnection simulation, which can significantly improve the running speed of the entire chip network simulation, solve the problem that the entire chip network simulation cannot be started due to insufficient single-machine memory resources, and reduce the development and debugging workload for achieving interconnection of underlying networks.

[0045] According to embodiments of the present invention, the processes of each chip simulation model forward and exchange message packets through an interconnection server, thereby achieving the purpose of network interconnection and parallel operation of chip simulation models. This method is applicable to simulation scenarios such as switch chips, smart network card chips, forwarding chips, and high-speed interconnection chips for data centers.

[0046] The following description, in conjunction with the accompanying drawings, illustrates exemplary embodiments of the present invention.

[0047] Figure 1A flowchart illustrating a method for simulating interconnection of multiple network chip models according to an example embodiment is shown.

[0048] According to some embodiments, the method for multi-network chip model interconnection simulation of the present invention is applied to the implementation of an apparatus for multi-network chip model interconnection simulation. The apparatus includes at least one server and an interconnection server, wherein the at least one server is used to run a first simulation process and a second simulation process.

[0049] See Figure 1 In S101, the first simulation process sends a request for routing configuration, including the identifier of the first simulation process, to the interconnect server.

[0050] According to some embodiments, a corresponding routing configuration item is established for each simulation process on the interconnect server, and the corresponding routing configuration item uniquely corresponds to the logical identifier of the corresponding network chip.

[0051] According to some embodiments, the application request is used to instruct the interconnect server to forward a message including the identifier of the first simulation process to the first simulation process, the first simulation process corresponding to a network chip model, and the first simulation process identifier corresponding to the identifier of the network chip model.

[0052] According to some embodiments, the network chip model is a standalone executable file, which runs as a simulation process on a CPU core when it is executed.

[0053] According to some embodiments, the single-chip simulation model corresponding to the network chip is instantiated as an independent simulation process, or the single-chip simulation model corresponding to the network chip is split into subsystem modules, and each subsystem module is instantiated as an independent simulation process.

[0054] According to some embodiments, in the first simulation process, a routing configuration request is sent to the corresponding routing configuration item on the interconnect server. This routing configuration item uniquely corresponds to the logical identifier of the network chip. The number of routing configuration items is consistent with the number of chip models used for network simulation.

[0055] According to some embodiments, a corresponding routing configuration item is set for the simulation process of each chip simulation model. Suppose that to perform network simulation of N chip models, N routing configuration items need to be defined, and each routing configuration item corresponds to a chip simulation process that receives message packets.

[0056] According to some embodiments, after the first simulation process sends a routing configuration request to the first routing configuration item on the interconnect server, the first simulation process will receive the logical identifier of the unique corresponding network chip of the corresponding routing configuration item.

[0057] See Figure 2 According to some embodiments, each routing configuration item can be named with "chip_n" as a suffix, where n represents a specific unique chip process identifier. For example, the routing configuration item identifier corresponding to chip 1 is "Topic_to_chip_1", and the routing configuration item identifier corresponding to chip 2 is "Topic_to_chip_2". Packet sending routing selection is the selection of routing configuration items. When sending a packet, the routing configuration item corresponding to the destination chip identifier is selected. For example, a packet going to destination chip 2 selects the routing configuration item with the routing configuration item identifier "Topic_to_chip2".

[0058] In S103, when the second simulation process wants to send a message to the first simulation process, the second simulation process encapsulates the message, the second simulation process identifier, and the first simulation process identifier into a message and publishes the message to the interconnect server.

[0059] According to some embodiments, the second simulation process corresponds to another network chip model, and the second simulation process identifier corresponds to the identifier of the other network chip model.

[0060] According to some embodiments, the first simulation process runs on one CPU core of a multi-core CPU, and the second simulation process runs on another CPU core of the multi-core CPU. Alternatively, the first simulation process runs on one CPU core of a multi-core CPU, and the second simulation process runs on one CPU core of another multi-core CPU.

[0061] According to some embodiments, the first simulation process and the second simulation process run on the same multi-core CPU of the same server, or the first simulation process runs on the multi-core CPU of one server and the second simulation process runs on the multi-core CPU of another server.

[0062] According to some embodiments, in the second simulation process, data including a message, a second simulation process identifier, and a first simulation process identifier are encapsulated into a message. The message includes a source chip identifier, a destination chip identifier, a message length, a message type, and message payload data, wherein the message payload data is used to store the message data content, and / or custom payload additional message control information, and / or is a null value.

[0063] According to some embodiments, the message content is encapsulated in the following data format after the simulation model has processed the message data:

[0064] {

[0065] "src_chip": "0", / / Source chip identifier

[0066] "dst_chip": "1", / / Destination chip identifier

[0067] "length": 1024, / / Message length in bytes

[0068] "type": "req", / / Message type, which can be a custom type such as req, ack, data, etc.

[0069] "payload": "" / / Message payload data, can be empty or used to carry other special control information.

[0070] }

[0071] According to some embodiments, in the message, src_chip indicates which chip sends the message, dst_chip indicates which destination chip the message needs to be sent to, length indicates the length of the message, type indicates the type of the message, and payload can be used to store message payload data or to customize and include some additional message control information.

[0072] In S105, the interconnected server receives and parses the message.

[0073] According to some embodiments, after the interconnect server receives the message, it parses the message according to the message encapsulation format, confirms the corresponding routing configuration item identifier according to the destination chip identifier in the message, and confirms whether there is a corresponding routing configuration item according to the routing configuration item identifier.

[0074] In S107, when the message includes the identifier of the first simulation process, the interconnect server forwards the message to the first simulation process.

[0075] According to some embodiments, after the interconnect server parses the message received in the routing configuration item, if the parsed message includes the first simulation process identifier and there is a routing configuration item corresponding to the first simulation process identifier, the interconnect server forwards the message to the first simulation process.

[0076] In S109, the first simulation process receives and parses the message to extract the packet.

[0077] According to some embodiments, after the first simulation process receives the message forwarded by the interconnect server, it parses the message data according to the message encapsulation format.

[0078] According to some embodiments, when the receive buffer of the first simulation process is insufficient, the first simulation process sends a cancellation request for the routing configuration including the identifier of the first simulation process to the interconnect server, wherein the cancellation request is used to instruct the interconnect server to return an error message to the second simulation process when it receives a message including the identifier of the first simulation process.

[0079] According to some embodiments, when the receive buffer space of the simulation process is full, a route configuration cancellation request is sent to cause the simulation process to cancel the configuration with the corresponding route configuration item, and the simulation process stops receiving messages. When there is free space in the receive buffer space, the simulation process resends the route configuration request to the corresponding route configuration item and resumes sending messages to the corresponding route configuration item.

[0080] According to some embodiments, the present invention supports message backpressure processing. If the message receiving process at the receiving end processes messages slowly, causing the message receiving buffer to run out, the process cancels the configuration of that routing configuration item and stops receiving message messages for that routing configuration item. At this time, the sending end can no longer publish message messages for that routing configuration item. When there is free message receiving buffer space, the sending and receiving of message messages will be resumed.

[0081] The implementation process of this invention will be described in detail below with reference to typical application scenarios.

[0082] According to some embodiments, eight chip simulation models are interconnected, with chip models 1, 2, 3, and 4 sending messages to each other and chip models 5, 6, 7, and 8 sending messages to each other. An interconnection server is started to act as a message broker. Simulation processes for four chip simulation models are started on server 1 (or computer), with the simulation processes identified as 1, 2, 3, and 4 representing different chips; simulation processes for four chip simulation models are started on server 2 (or computer), with the simulation processes identified as 5, 6, 7, and 8 representing different chips.

[0083] All chip model processes on servers 1 and 2 are configured with routing configuration items consistent with their own chip identifiers. The QoS (Quality of Service) level for message delivery is set to 2, ensuring that message information is sent only once and is not lost. When a process on server 1 with chip identifier 0 needs to send a data packet to a process on server 2 with chip identifier 7, the chip 0 process selects the routing configuration item corresponding to chip 7 based on the dst_chip in the message to publish the message. Since the process on server 2 with chip identifier 7 has configured this routing configuration item, it will immediately receive the message sent by chip 0. Similarly, message transmission and reception between other chips are processed in the same way.

[0084] According to some embodiments, different message messages can be sent simultaneously or at different times, and different processes can process messages in parallel at the same time. The message processing order is based on the order of receipt.

[0085] This invention effectively solves the resource bottleneck problem and optimizes the running speed of large-scale network communication chip model interconnection simulation. It splits the network simulation chip model into multiple individual chips and deploys them into processes of multiple operating systems (for example, for network simulation with 64 chip simulation models, before splitting, 64 instances of the chip simulation model were instantiated in one process; after splitting, these 64 instances are instantiated into 64 separate processes, meaning each process runs only one instance of the chip simulation model). The processes of each chip simulation model forward and exchange message packets through an interconnection server, achieving the goal of parallel operation of the chip simulation models in a network interconnection. This invention is applicable to simulation scenarios such as switch chips, smart network card chips, forwarding chips, and high-speed interconnection chips for data centers.

[0086] Figure 3 A schematic diagram illustrating the principle of a multi-chip networking simulation scheme according to an example embodiment is shown.

[0087] See Figure 3 In this embodiment, multiple chip models are instantiated as simulation processes, and efficient, asynchronous data exchange is performed through an interconnect server. During multi-chip network simulation, each chip model is instantiated as a simulation process. After the simulation process processes the packet data, it encapsulates the packet data into a message and sends it to the interconnect server. Simultaneously, each simulation process also receives messages forwarded from other simulation processes by the interconnect server, achieving bidirectional communication for sending and receiving network packet messages. Multiple chip models run in multiple OS processes, and multiple CPUs participate in parallel operation, significantly improving the overall speed of the chip network simulation.

[0088] This embodiment performs multi-chip network simulation. Through multi-machine, multi-process distributed simulation, each network chip simulation model is mapped to an independent OS process, and an interconnect server serves as the communication hub to realize message information exchange between model simulation processes. This invention uses chip identifiers for precise design of routing configuration items, and customizes routing configuration items containing "target chip ID and related identifiers" to achieve targeted message transmission.

[0089] Compared with existing technologies, this invention enables parallel utilization of multiple CPUs in large-scale network simulation models. Multiple chip models run in multiple OS processes, and the parallel participation of multiple CPUs significantly improves the overall speed of chip network simulation. The large-scale distributed deployment of the present invention reduces single-machine memory resource usage. By distributing chip models across different computers for large-scale network simulation, the single-machine memory requirements are reduced, solving the problem of insufficient single-machine memory preventing the entire chip network simulation from starting. The simple implementation of distributed interconnection of chip models in this invention utilizes an interconnection server. Network message sending and receiving functions can be achieved simply by calling interfaces, without needing to implement underlying network interconnection, reducing development and debugging workload and improving development efficiency.

[0090] Figure 4 A schematic diagram illustrating a multi-chip networking simulation process according to an example embodiment is shown.

[0091] See Figure 4 The following describes the workflow of a multi-network chip interconnect simulation system.

[0092] According to some embodiments, the simulation process instantiation module instantiates the corresponding network chip simulation model into an independent simulation process. The routing configuration item establishment module establishes corresponding routing configuration items based on the network chip information of the network. Process 1 and Process 2 request configuration from "Route Configuration Item 1" and "Route Configuration Item 2" respectively. The simulation model outputs the processed network packet data to the packet message encapsulation module, which encapsulates the received packet data into a message. The packet sending module publishes the message sent to destination chip 1 to its corresponding "Route Configuration Item 1". The interconnect server forwards the message to Process 1, which is configured with "Route Configuration Item 1". The packet receiving module receives the message forwarded by the interconnect server, parses the packet data, and performs subsequent processing. The packet sending module continues to publish the message sent to destination chip 2 to its corresponding "Route Configuration Item 2". The interconnect server forwards the message to Process 2, which is configured with "Route Configuration Item 2". The packet receiving module receives the message forwarded by the interconnect server, parses the packet data, and performs subsequent processing.

[0093] This invention maps each network chip simulation model to an independent OS process, using an interconnect server as the communication hub to achieve message exchange between model processes, thus realizing a multi-chip simulation model networking interconnection scheme. This system significantly improves the overall running speed of chip network simulation, solves the problem of insufficient single-machine memory resources preventing the entire chip network simulation from starting, and reduces the development and debugging workload for achieving interoperability of the underlying network.

[0094] Figure 5A block diagram of a computing device according to an exemplary embodiment of the present invention is shown.

[0095] like Figure 5 As shown, the computing device 30 includes a processor 12 and a memory 14. The computing device 30 may also include a bus 22, a network interface card 16, and an I / O interface 18. The processor 12, memory 14, network interface card 16, and I / O interface 18 can communicate with each other via the bus 22.

[0096] Processor 12 may include one or more general-purpose CPUs (Central Processing Units), microprocessors, or application-specific integrated circuits, for executing relevant program instructions. According to some embodiments, computing device 30 may also include a high-performance display adapter (GPU) 20 for accelerating processor 12.

[0097] Memory 14 may include a machine system readable medium in the form of volatile memory, such as random access memory (RAM), read-only memory (ROM), and / or cache memory. Memory 14 is used to store one or more programs containing instructions, as well as data. Processor 12 may read the instructions stored in memory 14 to perform the methods described above according to embodiments of the present invention.

[0098] The computing device 30 can also communicate with one or more networks via the network interface card 16. The network interface card is used for data processing or external communication, and the processor 12 is used for processing the data scheduled by the network interface card.

[0099] Bus 22 can include address bus, data bus, control bus, etc. Bus 22 provides a path for exchanging information between components.

[0100] It should be noted that, in specific implementations, the computing device 30 may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the device described above may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0101] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method. The computer-readable storage medium may include, but is not limited to, any type of disk, including floppy disks, optical disks, DVDs, CD-ROMs, microdrives, as well as magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic cards or optical cards, nanosystems (including molecular memory ICs), network storage devices, cloud storage devices, or any type of medium or device suitable for storing instructions and / or data.

[0102] This invention also provides a computer program product comprising a computer program operable to cause a computer to perform some or all of the steps of any of the methods described in the above method embodiments.

[0103] Those skilled in the art will clearly understand that the technical solutions of the present invention can be implemented by means of software and / or hardware. In this specification, "unit" and "module" refer to software and / or hardware capable of independently performing or cooperating with other components to perform a specific function, wherein the hardware may be, for example, a field-programmable gate array (FPGA), an integrated circuit, etc.

[0104] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0105] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0106] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some service interface; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0107] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0108] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0109] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage device. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention.

[0110] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0111] Exemplary embodiments of the present invention have been specifically shown and described above. It should be understood that the present invention is not limited to the detailed structures, arrangements, or implementations described herein; rather, the present invention is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended provisions.

Claims

1. A method for simulating interconnection of multiple network chip models, characterized in that, The method includes: The first simulation process sends a routing configuration request, including the identifier of the first simulation process, to the interconnect server. The request is used to instruct the interconnect server to forward the message to the first simulation process when it receives the message including the identifier of the first simulation process. The first simulation process corresponds to a network chip model, and the identifier of the first simulation process corresponds to the identifier of the network chip model. When the second simulation process needs to send a message to the first simulation process, the second simulation process encapsulates the message, the second simulation process identifier, and the first simulation process identifier into a message and publishes the message to the interconnect server. Here, the second simulation process corresponds to another network chip model, and the second simulation process identifier corresponds to the identifier of the other network chip model. The interconnect server receives and parses the message; When the message includes the identifier of the first simulation process, the interconnect server forwards the message to the first simulation process; The first simulation process receives and parses the message to extract the packet.

2. The method according to claim 1, characterized in that, The first simulation process runs on one CPU core of a multi-core CPU, and the second simulation process runs on another CPU core of the multi-core CPU; or, the first simulation process runs on one CPU core of a multi-core CPU, and the second simulation process runs on one CPU core of another multi-core CPU.

3. The method according to claim 2, characterized in that, The first simulation process and the second simulation process run on the same multi-core CPU of the same server, or the first simulation process runs on the multi-core CPU of one server and the second simulation process runs on the multi-core CPU of another server.

4. The method according to claim 1, characterized in that, Also includes: The network chip model is an independent executable file. When the executable file is run, it runs as a simulation process on a CPU core.

5. The method according to claim 1, characterized in that, The method further includes: When the receive buffer of the first simulation process is insufficient, the first simulation process sends a cancellation request for the routing configuration including the identifier of the first simulation process to the interconnect server, wherein the cancellation request is used to instruct the interconnect server to return an error message to the second simulation process when it receives a message including the identifier of the first simulation process.

6. A device for simulating interconnection of multiple network chip models, characterized in that, The device includes: at least one server and an interconnect server. The at least one server is used to run the first simulation process and the second simulation process, wherein... The first simulation process is used to send a routing configuration request including a first simulation process identifier to the interconnect server. The routing configuration request is used to instruct the interconnect server to forward the message to the first simulation process when it receives the message including the first simulation process identifier. The first simulation process corresponds to a network chip model, and the first simulation process identifier corresponds to the identifier of the network chip model. When the second simulation process needs to send a message to the first simulation process, the second simulation process encapsulates the message, the first simulation process identifier, and the second simulation process identifier into a message and publishes the message to the interconnect server. The second simulation process corresponds to another network chip model, and the second simulation process identifier corresponds to the identifier of the other network chip model. The interconnect server is used to receive and parse the message; When the message includes the identifier of the first simulation process, the interconnect server is further configured to forward the message to the first simulation process; The first simulation process is also used to receive and parse the message in order to extract the message.

7. The apparatus according to claim 6, characterized in that, The first simulation process runs on one CPU core of a multi-core CPU, and the second simulation process runs on another CPU core of the multi-core CPU; or, the first simulation process runs on one CPU core of a multi-core CPU, and the second simulation process runs on one CPU core of another multi-core CPU.

8. The apparatus according to claim 7, characterized in that, The first simulation process and the second simulation process run on the same multi-core CPU of the same server, or the first simulation process runs on the multi-core CPU of one server and the second simulation process runs on the multi-core CPU of another server.

9. The apparatus according to claim 6, characterized in that, Also includes: The network chip model is an independent executable file. When the executable file is run, it runs as a simulation process on a CPU core.

10. The apparatus according to claim 6, characterized in that, When the receive buffer of the first simulation process is insufficient, the first simulation process is further configured to send a cancellation request for the routing configuration including the identifier of the first simulation process to the interconnect server, wherein the cancellation request is configured to instruct the interconnect server to return an error message to the second simulation process when it receives a message including the identifier of the first simulation process.

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