Embedded device for always-on daisy chain level connectivity system and method of operation thereof

Abstract

This disclosure provides an embedded device for a daisy-chain cascaded system and a method for operating the same. The embedded device according to this disclosure may include: an Ethernet switch integrated circuit configured to have a bypass mode; a microprocessor that determines whether the embedded device needs a hot restart and generates an activation bypass signal or a deactivation bypass signal based on the determination result; and a bypass control circuit configured to receive the activation bypass signal or the deactivation bypass signal from the microprocessor and generate a bypass control signal based on the activation bypass signal or the deactivation bypass signal, wherein the Ethernet switch integrated circuit is configured to: receive the bypass control signal from the bypass control circuit; and activate or deactivate the bypass mode based on the bypass control signal, wherein the microprocessor is further configured to initiate a hot restart process for the embedded device in response to the Ethernet switch integrated circuit activating the bypass mode.

Description

Technical Field

[0001] This disclosure relates to an embedded device, and more particularly to an embedded device for a daisy-chain cascade system and a method of operating the same. Background Technology

[0002] A daisy chain is a common network topology, typically consisting of multiple nodes (or devices) connected linearly to form a ring structure. Each node is directly connected to its two adjacent nodes, forming a closed loop. A network system formed through a daisy chain can be called a daisy chain cascade system.

[0003] One of the main problems with traditional daisy-chain cascading systems is that restarting any intermediate device in the topology can cause network outages. Such outages can lead to data loss between upstream and downstream devices, and sometimes even serious consequences, especially when downstream network devices are streaming audio / video or downloading software during a hot reboot of an intermediate device (e.g., due to a firmware update).

[0004] Therefore, a method is needed to reduce the loss of network communication data between upstream and downstream network devices during hot restarts of intermediate devices. Summary of the Invention

[0005] This disclosure provides an embedded device and its operation method for a daisy-chain cascade system. According to this disclosure, when the embedded device (as an intermediate device) in the daisy-chain cascade system needs to be hot-rebooted, the switch chip of the embedded device can be controlled to operate in bypass mode, thereby reducing the impact on network communication between upstream and downstream network devices in the daisy-chain cascade system due to the hot restart of the intermediate device.

[0006] According to one aspect of this disclosure, an embedded device for a daisy-chain cascaded system is provided, the device comprising: an Ethernet switch integrated circuit configured to have a bypass mode; a microprocessor configured to be connected to the Ethernet switch integrated circuit and configured to determine whether the embedded device needs to be warm-rebooted, and generate an activation bypass signal or a deactivation bypass signal based on the determination result; and a bypass control circuit configured to be connected to the Ethernet switch integrated circuit and the microprocessor respectively, and configured to receive the activation bypass signal or the deactivation bypass signal from the microprocessor, and generate a bypass control signal based on the activation bypass signal or the deactivation bypass signal, wherein the Ethernet switch integrated circuit is configured to: receive the bypass control signal from the bypass control circuit; and activate or deactivate the bypass mode based on the bypass control signal, wherein the microprocessor is further configured to initiate a warm-reboot process of the embedded device in response to the Ethernet switch integrated circuit activating the bypass mode.

[0007] In one embodiment, when the microprocessor determines whether the embedded device needs to be warm-rebooted, the microprocessor notifies the upstream and downstream network devices connected to the embedded device to suspend their communication with the embedded device.

[0008] In one embodiment, when the Ethernet switch integrated circuit activates bypass mode, the microprocessor notifies the upstream and downstream network devices respectively connected to the embedded device to continue their communication with the embedded device.

[0009] In one embodiment, the bypass control circuit includes a D flip-flop, wherein the D flip-flop is configured to lock the Ethernet switch integrated circuit in bypass mode for a period of time based on a bypass control signal.

[0010] In one embodiment, the bypass control circuit is further configured to receive a network reset signal from the microprocessor and, based on the bypass control signal and the network reset signal, send a reset signal to the Ethernet switch integrated circuit for controlling the reset of the Ethernet switch integrated circuit.

[0011] In one embodiment, when the bypass control signal indicates that the bypass mode of the Ethernet switch integrated circuit is activated, the bypass control circuit determines the reset signal based solely on the bypass control signal, thus bypassing the network reset signal.

[0012] In one embodiment, the bypass control circuit further includes an OR gate or a non-inverting tri-state buffer, wherein the input of the OR gate or non-inverting tri-state buffer is a bypass control signal from a D flip-flop and a network reset signal from a microprocessor, and the output is a reset signal for controlling the reset of the Ethernet switch integrated circuit.

[0013] In one embodiment, the bypass control circuit further includes an AND gate configured to receive a system reset signal from a power management integrated circuit and a network reset signal from a microprocessor, and generate a reset signal for sending to the OR gate.

[0014] In one embodiment, an indicator light is used to indicate that the bypass mode is activated when the Ethernet switch integrated circuit is activated.

[0015] In one embodiment, when the Ethernet switch integrated circuit activates bypass mode, the Ethernet switch integrated circuit provides a reference clock signal to the microprocessor.

[0016] In one embodiment, whether the embedded device needs to be warm-rebooted is determined in response to at least one of the following: a new firmware download of the Ethernet switch integrated circuit is completed, network settings are restored, factory settings are restored, and software is updated.

[0017] In one embodiment, the embedded device includes at least one of the following: a multimedia terminal, a set-top box, a game console, a wireless microphone receiver, a smart device docking station, and a wireless access point device.

[0018] According to another aspect of this disclosure, an operating method for an embedded device in a daisy-chain cascade system is provided, wherein the daisy-chain cascade system includes an embedded device, an upstream network device and a downstream network device connected to the embedded device, the embedded device including an Ethernet switch integrated circuit, a microprocessor and a bypass control circuit interconnected thereto, the method comprising: the microprocessor determining whether the embedded device needs to be warm-rebooted, and generating an activation bypass signal or a deactivation bypass signal based on the determination result; the bypass control circuit receiving the generated activation bypass signal or deactivation bypass signal from the microprocessor, and generating a bypass control signal based on the activation bypass signal or deactivation bypass signal, the Ethernet switch integrated circuit receiving the bypass control signal from the bypass control circuit; the Ethernet switch integrated circuit activating or deactivating a bypass mode based on the bypass control signal, and the microprocessor initiating a warm-reboot process for the embedded device in response to the Ethernet switch integrated circuit activating the bypass mode.

[0019] In one embodiment, the method further includes: when it is determined whether the embedded device needs to be warm-rebooted, the microprocessor notifies the upstream network device and the downstream network device respectively connected to the embedded device to suspend their communication with the embedded device.

[0020] In one embodiment, the method further includes: when it is determined that the Ethernet switch integrated circuit is in bypass mode, the microprocessor notifies the upstream network devices and downstream network devices respectively connected to the embedded device to continue their communication with the embedded device.

[0021] In one embodiment, the method further includes: locking the Ethernet switch integrated circuit in bypass mode for a period of time based on a bypass control signal indicating activation of bypass mode.

[0022] In one embodiment, when the bypass control signal indicates activation of the bypass mode of the Ethernet switch integrated circuit, the bypass control circuit generates a reset signal for the Ethernet switch integrated circuit based solely on the bypass control signal, bypassing the network reset signal received from the microprocessor.

[0023] In one embodiment, when the Ethernet switch integrated circuit enters bypass mode, the Ethernet switch integrated circuit provides a reference clock signal to the microprocessor.

[0024] In one embodiment, whether the embedded device needs to be warm-rebooted is determined in response to at least one of the following: a new firmware download of the Ethernet switch integrated circuit is completed, network settings are restored, factory settings are restored, and software is updated.

[0025] In one embodiment, the embedded device includes at least one of the following: a multimedia terminal, a set-top box, a game console, a wireless microphone receiver, a smart device docking station, and a wireless access point device.

[0026] This disclosure determines the subsequent actions of intermediate devices in a daisy-chain cascade system by monitoring whether a warm restart is imminent. When a warm restart is required, the intermediate device is set to operate in bypass mode, thereby reducing the impact on network communication between upstream and downstream network devices connected to the intermediate device in the daisy-chain cascade system. Therefore, this disclosure provides a daisy-chain cascade system and its operating method that ensures communication between devices is not interrupted by warm restarts and remains always operational. Attached Figure Description

[0027] Figure 1 A portion of an Always-On Daisy-Chaining (AODC) cascaded system according to an embodiment of the present disclosure is shown;

[0028] Figure 2 A flowchart illustrating an operation method of an embedded device in a daisy-chain cascade system according to an embodiment of the present disclosure is shown.

[0029] Figure 3 A portion of a daisy-chain cascade system including exemplary bypass control circuitry, according to an embodiment of the present disclosure, is shown; and

[0030] Figure 4 A circuit diagram of a bypass control circuit according to an embodiment of the present disclosure is shown. Detailed Implementation

[0031] Before proceeding with the detailed description below, it may be advantageous to define certain words and phrases used throughout this patent document. The terms “transmit,” “receive,” and “communication,” and their derivatives, cover both direct and indirect communication. The terms “comprising” and “including,” and their derivatives, mean including but not limited to. The term “or” is inclusive, meaning and / or. The phrase “at least one of…” when used with a list of items means that different combinations of one or more of the listed items may be used, and that only one item from the list may be required.

[0032] Furthermore, the various functions described below can be implemented or supported by one or more computer programs, each computer program being formed by computer-readable program code and embodied in a computer-readable medium. The terms "application" and "program" refer to one or more computer programs, software components, instruction sets, procedures, functions, objects, classes, instances, associated data, or portions thereof suitable for implementation in appropriate computer-readable program code. The phrase "computer-readable program code" includes any type of computer code, including source code, object code, and executable code. The phrase "computer-readable medium" includes any type of medium that can be accessed by a computer, such as read-only memory (ROM), random access memory (RAM), hard disk drive, optical disc (CD), digital video disc (DVD), or any other type of storage. "Non-transitory" computer-readable media excludes wired, wireless, optical, or other communication links that transmit transient electrical or other signals. Non-transitory computer-readable media includes media that can permanently store data and media that can store and later rewrite data, such as rewritable optical discs or erasable memory devices.

[0033] It should be understood that the terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Unless the context clearly indicates otherwise, the singular forms “a,” “one,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one.

[0034] The various embodiments discussed below for describing the principles of this disclosure in this patent document are for illustrative purposes only and should not be construed in any way as limiting the scope of this disclosure.

[0035] The following description, with reference to the accompanying drawings, is provided to aid in a thorough understanding of the various embodiments of this disclosure as defined by the claims and their equivalents. This description includes various specific details to aid understanding but should be considered exemplary only. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the various embodiments described herein without departing from the scope and spirit of this disclosure. Furthermore, for clarity and brevity, descriptions of well-known functions and structures may be omitted.

[0036] Unless otherwise defined, all terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of those skilled in the art as described herein. Common terms as defined in dictionaries are to be interpreted as having a meaning consistent with the context in the relevant technical field and should not be interpreted ideally or overly formally unless expressly defined in this disclosure.

[0037] The following discussion Figures 1 to 4 The various embodiments used to describe the principles of this disclosure in this patent document are for illustrative purposes only and should not be construed as limiting the scope of this disclosure in any way. Those skilled in the art will understand that the principles of this disclosure can be implemented in any suitably arranged system or device.

[0038] This document discloses an embedded device for a daisy-chain cascading system and its operation method. By using the embedded device according to the embodiments of this disclosure as an intermediate device, the daisy-chain cascading system can maintain "Always-On Daisy-Chaining" (AODC) by preventing the loss of communication data between upstream and downstream devices due to hot restarts of the intermediate device. This embedded device is implemented using an Ethernet switch integrated circuit with bypass mode (this Ethernet switch integrated circuit typically has two or more ports, for example, a three-port Ethernet switch integrated circuit).

[0039] A hot reboot (or hot reset) process is entirely software-controlled and typically occurs after a new firmware download is complete, during network settings restoration, factory reset, or after a software update. For example, after a new firmware download, the embedded device may need a hot reboot to verify the firmware upgrade as a final step. AODC is essentially an "altruistic" feature: during a hot reboot (or hot reset) of the embedded device containing the Ethernet switch integrated circuit, the network connections downstream and upstream of that embedded device remain available. In other words, the "always-on" daisy-chain topology network connections are always effective for upstream and downstream devices because they are no longer affected by reboots of devices in the chain. That is, the embedded device, as a node in the cascaded network, does not significantly impact the operation of the entire network due to its own operational status. This AODC cascading method and corresponding system utilize streamlined additional hardware circuitry and require only minimal software processing from the microprocessor's bootloader and applications.

[0040] Figure 1 A portion of an AODC cascade system according to an embodiment of the present disclosure is shown.

[0041] A daisy-chain cascading system may include multiple cascaded upstream network devices, embedded devices, and downstream network devices. Specifically, the daisy-chain cascading system according to this disclosure may include a first embedded device, a first upstream network device and a first downstream network device respectively connected to the first embedded device, a second embedded device, a first downstream network device and a second upstream network device respectively connected to the second embedded device, a third embedded device, a second upstream network device and a third downstream network device respectively connected to the third embedded device, and so on.

[0042] It is important to note that the term "connection" as used in this document can refer to either a "direct connection" or an "indirect connection," meaning that there may be other devices between the two connected devices. For example, "the first embedded device is connected to the first upstream network device" can include either a direct connection between the first embedded device and the first upstream network device without any other devices in between, or an indirect connection between the first embedded device and the first upstream network device. In the case of an "indirect connection," the first embedded device and the first upstream network device can be connected together through one or more other devices (e.g., another embedded device).

[0043] As an illustration. Figure 1The daisy-chain cascading system shown herein illustrates only one embedded device 10 and upstream network device 400 and downstream network device 500 respectively connected to the embedded device 10. The embedded device described herein can be one of the following: a multimedia terminal, a set-top box, a game console (e.g., a video game console), a wireless microphone receiver, a smart device docking station, and a wireless access point device (e.g., a conferencing access device), or other similar devices.

[0044] The embedded device 10 according to embodiments of the present disclosure may include: a microprocessor 100; a bypass control circuit 200 connected to the microprocessor 100; and an Ethernet switch integrated circuit 300 configured to have a bypass mode and connected to the bypass control circuit 200 and the microprocessor 100, respectively.

[0045] The microprocessor 100 can be configured to determine whether the embedded device needs a warm reboot and generate an activation bypass signal or a deactivation bypass signal based on the determination result. Specifically, when the microprocessor 100 determines that the embedded device needs a warm reboot, it generates an activation bypass signal; when the microprocessor 100 determines that the embedded device does not need a warm reboot, it generates a deactivation bypass signal. In one example, whether the embedded device needs a warm reboot is determined in response to the occurrence of at least one of the events that will cause a warm reboot, such as the completion of a new firmware download for the Ethernet switch integrated circuit, network settings being restored, factory settings being restored, and software being updated.

[0046] The bypass control circuit 200 can be configured to receive an activation bypass signal or a deactivation bypass signal from the microprocessor 100, and generate a bypass control signal based on the activation or deactivation bypass signal. Then, the bypass control circuit 200 sends the generated signal to the Ethernet switch integrated circuit 300 and the microprocessor 100, respectively.

[0047] The Ethernet switch integrated circuit 300 can be configured to: receive a bypass control signal from a bypass control circuit; and activate or deactivate a bypass mode based on the bypass control signal. In one embodiment, the Ethernet switch integrated circuit activates the bypass mode based on determining that the bypass control signal indicates activation of the bypass mode; otherwise, the Ethernet switch integrated circuit deactivates the bypass mode.

[0048] Then, the microprocessor can initiate a warm restart process for the embedded device in response to the Ethernet switch integrated circuit entering bypass mode. More specifically, the microprocessor can receive a bypass control signal from the bypass control circuit and determine that the Ethernet switch integrated circuit is in bypass mode based on the bypass control signal, thereby initiating the warm restart process for the embedded device.

[0049] In other words, according to embodiments of this disclosure, whether the Ethernet switch integrated circuit 300 enters bypass mode is controlled by the bypass control circuit 200. Specifically, the bypass control circuit 200 can control whether the Ethernet switch integrated circuit 300 activates bypass mode by sending a bypass control signal to the Ethernet switch integrated circuit 300. The bypass control signal sent by the bypass control circuit 200 is generated based on signals received from the microprocessor 100 for activating or deactivating bypass mode (e.g., both an activation bypass signal and a deactivation bypass signal). The microprocessor 100 determines the signals for activating or deactivating bypass mode based on whether the embedded device needs to be restarted.

[0050] In a further embodiment, when the bypass mode is activated, the Ethernet switch integrated circuit 300 may also ignore or bypass the reset signal sent from the microprocessor 100 at this time. To this end, the Ethernet switch integrated circuit 300 may also receive a reset signal from the bypass control circuit 200, which is generated by the bypass control circuit 200 based on the bypass control signal and the network reset signal received from the microprocessor 100. In an alternative embodiment, the bypass control circuit 200 may also determine the aforementioned reset signal for the Ethernet switch integrated circuit 300 based on the bypass control signal, the network reset signal received from the microprocessor 100, and a system reset signal (e.g., received from the power management integrated circuit (PMIC) 600). In a further embodiment, when the bypass control signal indicates activation of the bypass mode of the Ethernet switch integrated circuit 300, the reset signal may be determined by activating only the bypass control signal, without considering the network reset signal and / or the system reset signal received from the microprocessor 100.

[0051] An example of the Ethernet switch integrated circuit 300 could be the integrated 3-port Ethernet switch chip KSZ8863 (e.g., KSZ8863RLL, KSZ8863MLL, or KSZ8863FLL). When pin 24SMTXER3 / MII_LINK_3 of the KSZ8863 is high, the KSZ8863 automatically switches to bypass mode. In this mode, the switching function between port 1 and port 2 of the KSZ8863 is maintained. Packets with destination addresses to port 3 are dropped and bypass the internal buffer memory, allowing the buffer memory to transfer data more efficiently between port 1 and port 2. In this disclosure, pin 24 of the Ethernet switch integrated circuit 300 can be kept high, thus enabling a functional daisy-chain connection between port 1 and port 2 even during the entire hot restart of the microprocessor 100.

[0052] During the hot restart of the embedded device containing the Ethernet switch integrated circuit, the bypass control circuit 200 can control the Ethernet switch integrated circuit in the embedded device 10 to remain in bypass mode. When the Ethernet switch integrated circuit remains in bypass mode, the network connections to the downstream and upstream of the embedded device remain available. That is, communication between the upstream and downstream network devices connected to the embedded device 10 can continue without interruption through bypass mode. In other words, the impact of the hot restart of the embedded device 10, which is a node in the cascaded network, on the communication between upstream and downstream network devices is reduced.

[0053] After the embedded device containing the Ethernet switch integrated circuit completes a warm restart, the bypass control circuit 200 can disable the bypass mode of the Ethernet switch integrated circuit based on a disable bypass signal sent by the microprocessor. Specifically, the microprocessor monitors in real time whether the embedded device has completed a warm restart, and in response to determining that the embedded device has completed a warm restart, generates a disable bypass signal and sends this information to the embedded device.

[0054] In a further embodiment, the microprocessor can notify upstream and downstream network devices to temporarily suspend their communication with the embedded device after determining that the embedded device requires a warm restart. Once the Ethernet switch integrated circuit activates bypass mode, the microprocessor notifies the upstream and downstream network devices to resume their communication with the embedded device. In one example, the microprocessor's notification to the upstream and downstream network devices to resume their communication with the embedded device also responds to receiving a bypass control signal from the bypass control circuitry instructing the Ethernet switch integrated circuit to activate bypass mode. This minimizes the impact of a warm restart of the embedded device on the communication of upstream and downstream network devices.

[0055] In one embodiment, when the Ethernet switch integrated circuit 300 activates bypass mode, an indicator light can be used to indicate that bypass mode is activated.

[0056] In one embodiment, when the Ethernet switch integrated circuit 300 is in bypass mode, it provides a reference clock signal to the microprocessor 100. The Ethernet switch integrated circuit 300 can be enabled in its clock mode to output the reference clock signal. The reference clock signal can be a 50MHz reference clock signal (REFCLK) and can be generated using an external 25MHz or 50MHz crystal or oscillator.

[0057] According to the above embodiments, the embedded device serving as an intermediate device in the daisy-chain cascading system includes an Ethernet switch integrated circuit with a bypass mode and a bypass control circuit for controlling the bypass mode operation of the Ethernet switch integrated circuit. These components can utilize the bypass mode of the Ethernet switch integrated circuit to solve the problem of communication loss between upstream and downstream network devices caused by hot restarts in traditional daisy-chain cascading systems. Therefore, the daisy-chain cascading system can be kept always on by using the embedded device described in the above embodiments as an intermediate device in the daisy-chain cascading system.

[0058] Although the bypass control circuit 200 is shown in the figure as being integrated with the embedded device 10, the bypass control circuit 200 may also not be integrated with the embedded device, for example, as a separate component.

[0059] According to embodiments of this disclosure, the Ethernet switch integrated circuit can be put into bypass mode before the embedded device 10 is warm-rebooted based on the detection of whether the embedded device 10 needs to be warm-rebooted, so that upstream and downstream devices can communicate normally through the port of the Ethernet switch integrated circuit operating in bypass mode.

[0060] Figure 2 An operation method of an embedded device 10 for an AODC cascade system according to an embodiment of the present disclosure is shown.

[0061] The method includes, for example Figure 2 The steps are shown. In step S210, the microprocessor determines whether the embedded device 10 needs a hot reboot (or hot reset). This determination can be implemented in software, such as a program in the microprocessor. In one example, the embedded device 10 needs a hot reboot (or hot reset) when at least one of the following events is detected or determined to have occurred in the Ethernet switch integrated circuit 300: new firmware download completed, network settings restored, factory settings restored, and software update.

[0062] In step S220, the microprocessor generates an activated bypass signal or a deactivated bypass signal based on the determined result, and sends the generated signal to the bypass control circuit. Specifically, when the microprocessor 100 determines that the embedded device needs a warm restart, it generates an activated bypass signal; otherwise, it generates a deactivated bypass signal. In a further embodiment, the activated bypass signal and the deactivated bypass signal can be implemented as having a high level or a low level. Both the activated bypass signal and the deactivated bypass signal can be active low.

[0063] In one example, when the microprocessor 100 determines whether the embedded device needs a warm reboot, the microprocessor 100 notifies the upstream and downstream network devices respectively connected to the embedded device to suspend their communication with the embedded device.

[0064] In step S230, the bypass control circuit 200 sends a bypass control signal to the Ethernet switch integrated circuit 300 to activate or deactivate the bypass mode of the Ethernet switch integrated circuit 300. In one embodiment, the bypass control signal is determined by the bypass control circuit 200 based on an activation or deactivation bypass signal received from the microprocessor 100.

[0065] In step S240, the Ethernet switch integrated circuit 300 activates or deactivates its bypass mode based on the received bypass control signal.

[0066] Specifically, the Ethernet switch integrated circuit 300 can determine whether the bypass control signal indicates activation of the bypass mode. In an example where the activation and deactivation bypass signals can be implemented as either high or low levels, the bypass control signal can be implemented as active high. When the deactivation bypass signal remains high and the activation bypass signal outputs a low-level pulse, the bypass control signal outputs a high level, indicating that the bypass control signal indicates activation of the bypass mode, and the bypass mode of the Ethernet switch integrated circuit 300 can be locked (or activated). Conversely, when the activation bypass signal remains high and the deactivation bypass signal outputs a low-level pulse, the bypass control signal outputs a low level, indicating that the bypass control signal indicates deactivation of the bypass mode, and the bypass mode of the Ethernet switch integrated circuit 300 is deactivated (or disabled).

[0067] In step S250, the microprocessor can control the embedded device to initiate a warm restart process. When the Ethernet switch integrated circuit 300 enters bypass mode, communication between the upstream network device 400 and the downstream network device 500, respectively connected to the Ethernet switch integrated circuit, is maintained without interruption during the warm restart process of the embedded device. Therefore, in response to the Ethernet switch integrated circuit activating bypass mode, the microprocessor can notify the upstream and downstream network devices respectively connected to the embedded device to continue their communication with the embedded device. More specifically, the microprocessor can receive a bypass control signal from the bypass control circuit and determine that the Ethernet switch integrated circuit is in bypass mode based on the bypass control signal, thereby initiating the warm restart process of the embedded device.

[0068] After the embedded device's hot restart (or hot reset) process is completed, the bypass mode of the Ethernet switch integrated circuit 300 can be deactivated. In one example, the microprocessor 100 monitors whether the embedded device's hot restart process has ended. If it has, it sends a disable bypass signal to the bypass control circuit, which can then generate a bypass control signal indicating that the bypass mode is disabled. Thus, the Ethernet switch integrated circuit 300 can disable the bypass mode based on the bypass control signal received from the bypass control circuit.

[0069] Afterward, the Ethernet switch integrated circuit 300 can remain in normal operating mode until it is determined that the embedded device 10 needs to be hot-rebooted (or hot-reset) again. That is, in one embodiment, it is possible to continuously monitor whether the embedded device 10 needs to be hot-rebooted (or hot-reset), and execute the necessary actions when it is determined that the Ethernet switch integrated circuit 300 needs to be hot-rebooted (or hot-reset). Figure 2 The method shown.

[0070] According to the above embodiments, the Ethernet switch integrated circuit of the embedded device, which is an intermediate device, can be controlled to work in bypass mode before the hot restart process is started, so as to achieve the purpose of not affecting the communication between the upstream and downstream network devices connected to it during the hot restart process of the intermediate device.

[0071] Figure 3 A portion of an AODC cascade system including exemplary bypass control circuitry, according to an embodiment of the present disclosure, is shown.

[0072] For the sake of brevity, the following has been omitted. Figure 3 Zhongyu Figure 1 Instead of describing the same parts and elements, only the differences between the two figures are described.

[0073] like Figure 3 As shown, the bypass control circuit 200 may include an OR gate 202 and a D flip-flop 203. The D flip-flop 203 is connected to the OR gate 202.

[0074] The D flip-flop can also be connected to the microprocessor 100 and configured to receive signals from the microprocessor for activating or deactivating bypass mode, such as the activation and deactivation bypass signals described above. The D flip-flop can also be connected to the Ethernet switch integrated circuit 300 and configured to generate a bypass control signal based on the received signals and output the bypass control signal to the Ethernet switch integrated circuit 300, thereby locking the Ethernet switch integrated circuit 300 in bypass mode for a period of time. Specifically, the D flip-flop 203 can maintain the state of the activation and deactivation bypass signals received from the microprocessor 10 until the next rising edge of the clock pulse signal, thereby achieving bypass mode locking. In alternative embodiments, the D flip-flop can be replaced with other components capable of locking signal states, such as other flip-flops.

[0075] OR gate 202 can be connected to microprocessor 100 and Ethernet switch integrated circuit 300. The input of OR gate 202 can be a bypass control signal and a network reset signal from D flip-flop 203, and the output can be a reset signal for the Ethernet switch integrated circuit.

[0076] In an optional embodiment, when a system reset signal from the PMIC 600 is present, the bypass control circuit 200 may further include an AND gate 201 connected to both the PMIC 600 and the microprocessor 100. In this case, the inputs to the AND gate 201 can be a network reset signal from the microprocessor 100 and a system reset signal from the PMIC 600. The AND gate 201 outputs the result of an AND operation on these two input signals as a reset signal to the OR gate 202. In embodiments including the AND gate 201, the inputs to the OR gate 202 are changed to the reset signal received from the AND gate 201 and the bypass control signal.

[0077] OR gate 202 can perform an OR operation on two input signals: when the bypass mode is activated, the bypass control signal is high. Through the OR gate or non-inverting tri-state buffer in the bypass control circuit, the system reset signal issued by the microprocessor and / or the system reset signal from the PMIC 600 can be ignored (bypassed) to avoid the bypass mode of the Ethernet switch integrated circuit being disabled due to reset.

[0078] In one example, OR gate 202 can be optional, meaning the bypass control circuit 200 only includes D flip-flop 203. In this case, the bypass control circuit can lock the Ethernet switch integrated circuit in bypass mode for a period of time, provided there is no reset signal.

[0079] In an alternative embodiment, OR gate 202 may be replaced with a non-inverting tri-state buffer or a circuit component with similar output logic.

[0080] According to the above embodiments, the bypass control circuit may include a component (e.g., a D flip-flop) for generating a bypass control signal and holding the bypass control signal for a period of time, thereby locking the Ethernet switch integrated circuit 300 in bypass mode during the warm start of the Ethernet switch integrated circuit 300.

[0081] Furthermore, the bypass control circuit may also include components (such as OR gates or non-inverting tri-state buffers) for ignoring (bypassing) system reset signals from the microprocessor and / or from the PMIC 600, thereby preventing the Ethernet switch integrated circuit 300 from being reset by the system reset signals from the microprocessor and / or from the PMIC 600 and thus disabling the bypass mode of the Ethernet switch integrated circuit. The specific components described above are exemplary; other components or sets of components with similar functions are also possible.

[0082] According to the above embodiments, the bypass control circuit in this disclosure is composed of commonly used, low-cost electronic components, solving the problem of communication data loss during hot restarts in traditional daisy-chain cascade systems with minimal modifications. Furthermore, the adaptive software modifications resulting from the introduction of the bypass control circuit are easily implemented by those skilled in the art based on the aforementioned hardware changes.

[0083] The present invention will be described in detail below using the integrated 3-port Ethernet switch chip KSZ8863 (e.g., KSZ8863RLL, KSZ8863MLL, or KSZ8863FLL) as an example of an Ethernet switch integrated circuit. The KSZ8863, supplied by Microchip, is equipped with two physical layer transceivers (PHYs). It communicates with the MAC (Media Access Control) via standard RMII (Reduced Media Independent Interface) and is controlled via SMI (Serial Management Interface). This switch chip can be easily used to replace the original PHY in any embedded network system, and its two external network ports are equivalent, so either one can be used as an upstream or downstream port.

[0084] The KSZ8863 provides a bypass mode for system-level power saving. Normally, when the Central Processing Unit (CPU) (connected to port 3) enters power-saving or hibernation mode, the CPU can control pin 24SMTXER3 / MII_LINK_3 by connecting it to a high level. This allows the KSZ8863 to detect this change and automatically switch to bypass mode. In this mode, switching between port 1 and port 2 is maintained. Data packets with destination addresses to port 3 are discarded and bypass the internal buffer, allowing the buffer to transfer data more efficiently between port 1 and port 2.

[0085] The bypass control circuit can have three input signals from the microprocessor and two output signals connected to the Ethernet switch KSZ8863. One of these output signals can be connected to pin #24SMTXER3 for bypass mode control, and the other can be connected to pin #47RSTn for Ethernet switch reset control. In the embodiments of this disclosure, SMTXER3 of the KSZ8863 is used only for bypass mode control and is not used as RMII_RXERR for the RMII link.

[0086] The following is combined Figure 4 This section describes in detail the main components of the bypass control circuit used to control the bypass mode of the KSZ8863. The bypass control circuit may include D flip-flops (in... Figure 4 (marked as "U1") and OR gates (in) Figure 4 (It is marked as "U2" in the middle). Figure 4 In this context, signals prefixed with "PHY_" originate from the microprocessor; signals prefixed with "KSZ8863_" are essentially outputs to the Ethernet switch. "KSZ8863_BYPASS" is a special signal that serves as both the output of a D flip-flop and the input of the KSZ8863, which is also connected to the microprocessor's input.

[0087] The D flip-flop (U1) in this bypass control circuit can be implemented as a D flip-flop with a P / N (Product Number) of NL17SZ74. It is a key component of the bypass mode lockout circuit, used to remember the current state. The output logic after asynchronous setting or asynchronous clearing will persist until the next power cycle. Both the active bypass signal (PHY_LOCK) and the deactivated bypass signal (PHY_UNLOCK) are active low. Specifically, when the deactivated bypass signal (PHY_UNLOCK) remains high, the active bypass signal (PHY_LOCK) outputs a low-level pulse, and the output of the D flip-flop—the bypass control signal (KSZ8863_BYPASS)—outputs a high level, at which point the bypass mode is locked. Conversely, when the active bypass signal (PHY_LOCK) remains high, and the deactivated bypass signal (PHY_UNLOCK) outputs a low-level pulse, the output of the D flip-flop—the bypass control signal (KSZ8863_BYPASS)—outputs a low level, and the bypass mode is deactivated. In one embodiment, the D flip-flop always operates in asynchronous mode. U1 allows the activation and deactivation of the bypass signal to persist until the next rising edge of the clock pulse, thus achieving bypass mode locking.

[0088] The function table of U1 is shown in Table 1 below, where H represents high level, L represents low level, X represents any level, and ↑ represents the rising edge of the level signal. The non-rising edge of the signal level is represented by NC, which indicates normally closed.

[0089]

[0090] Table 1

[0091] The OR gate (U2) of the bypass control circuit can be implemented as an OR gate with P / N number NL17SZ32; if either input A or B is high, the output Y will be high, Y will be low when both inputs are low, and Y will be high when one of the two inputs is high. This OR gate is used to bypass the microprocessor's system reset signal output during a warm restart. In this digital system, the reset signal is active low. In the example according to this disclosure, input A is the network reset signal (PHY_RESET), input B is the bypass mode control signal (KSZ8863_BYPASS), and the output is the Ethernet switch integrated circuit reset signal (KSZ8863_RESET). That is, the Ethernet switch integrated circuit reset signal (KSZ8863_RESET) is low only when both the network reset signal (PHY_RESET) and the bypass control signal (KSZ8863_BYPASS) are low. Through unit U2, when the bypass mode is activated, the bypass control signal (KSZ8863_BYPASS) is high; thus, the circuit will ignore (bypass) the system reset signal issued by the microprocessor to prevent the bypass mode of the Ethernet switch integrated circuit from being disabled.

[0092] The function table of an OR gate can be shown in Table 2 below:

[0093]

[0094] Table 2

[0095] In an alternative embodiment, a non-inverting tri-state buffer with negative / OE (output enable) control (such as the NL17SZ125) can be used instead of the above OR gate. As long as the output has an external pull-up resistor, the input and / OE will essentially exhibit the same OR logic as U2 described above. The function table of this non-inverting tri-state buffer can be represented as shown in Table 3 below, where H represents high level, L represents low level, and Z represents high impedance state:

[0096]

[0097] Table 3

[0098] Under the control of the bypass control circuit, the KSZ8863 Ethernet switch chip can operate in different modes, which are described in detail below:

[0099] Normal working mode

[0100] 1. For normal power-on or cold restart, the output signal Q (pin #5) of U1 is low.

[0101] 2. Since the output Q of U1 is directly connected to KSZ8863_BYPASS, KSZ8863 is in normal mode.

[0102] 3. Since the output Q of U1 is also the input B of U2, KSZ8863_RESET is equal to PHY_RESET.

[0103] 4. The microprocessor can be reset using PHY_RESET just like any other peripheral device.

[0104] 5. The bootloader stored in the embedded device is responsible for resetting the KSZ8863 and initializing it with appropriate settings.

[0105] 6. Applications stored in embedded devices use the RMII interface for data communication and use SMI to obtain port link status, speed, etc.

[0106] Bypass mode activated

[0107] 1. When there is a low pulse at the PHY_LOCK input, the D flip-flop U1 will be triggered, and the output signal Q will be high.

[0108] 2. When KSZ8863 enters bypass mode, KSZ8863_RESET will always be high, regardless of whether PHY_RESET is low or high.

[0109] 3. In this state, data transactions on the RMII bus will be ignored; therefore, the KSZ8863 will not be affected by the BSP driver.

[0110] 4. Both upstream and downstream ports can still function to maintain the viability of an effective daisy chain.

[0111] 5. The PHY_RESET output from the microprocessor will be ignored so that the KSZ8863 can remain in bypass mode.

[0112] Bypass mode disabled

[0113] 1. When there is a low pulse at the PHY_UNLOCK input, the D flip-flop will be cleared and the output Q will become low.

[0114] 2. When KSZ8863_BYPASS returns to low level, KSZ8863 is in normal operating mode. RMII can then be accessed.

[0115] 3. At the same time, KSZ8863_RESET is equal to PHY_RESET, and the microprocessor can reset KSZ8863 normally.

[0116] 4. This mode is similar to the normal working mode, the only difference being that the switch must first be initialized by the bootloader in the microprocessor.

[0117] Bypass mode detection

[0118] 1. The KSZ8863_BYPASS is connected to an input pin of the microprocessor to allow the microprocessor to detect bypass mode; this input pin can be an open-drain pin because it already has an external pull-up resistor.

[0119] 2. The bootloader or application stored in the microprocessor uses this input to know whether the Ethernet switch is currently in bypass mode.

[0120] 3. When KSZ8863_BYPASS is high, it indicates that KSZ8863 is in bypass mode; otherwise, it indicates that KSZ8863 is in normal operating mode.

[0121] 4. The debug LED of KSZ8863_BYPASS can help indicate that bypass mode is activated.

[0122] Clock mode

[0123] 1. To achieve reliable bypass mode operation, the KSZ8863 Ethernet switch chip must provide a 50MHz REFCLK (reference clock information) to the microprocessor MCU. Clock mode #3 can be used: KSZ8863RLL RMII in RMII clock mode (output 50MHz REFCLK clock), PHY / MAC RMII in normal mode (input 50MHz REFCLK clock).

[0124] 2. For the KSZ8863RLL, an external 25MHz or 50MHz crystal or oscillator must be used, and the clock mode must be properly booted.

[0125] According to embodiments of this disclosure, a software or computer program designed to adapt to the above-described structure is also provided. Corresponding software or computer programs can be designed based on the methods and apparatus provided according to embodiments of this disclosure. For example, the bootloader stored in the microprocessor should be able to detect the bypass mode state, the application should lock the bypass mode circuitry before restarting, and the program should also make adaptive modifications from an external 50MHz reference clock from the Ethernet switch being used for the MCU's MAC (as mentioned above in clock mode #3), such as disabling the internal phase-locked loop (PLL) of ENETPLLx that generates the 50MHz reference clock, and configuring the pin direction of ENET_REF_CLK as input. In embodiments, the bypass mode circuitry should be locked before a hot restart of the Ethernet switch chip; this bypass mode lock state can be retained until the bypass mode is disabled. Before entering bypass mode, all relevant external network devices (e.g., upstream and downstream network devices connected to ports #1 and #2 respectively) can be notified, for example, to suspend their communication with this embedded device. During this period, all data traffic at port #3 of the Ethernet switch integrated circuit (where port #3 is connected to the embedded device containing the Ethernet switch integrated circuit) will be ignored. The duration of the bypass mode "locked" state is approximately a few seconds (2-3 seconds), depending on the time required to shut down all *.par files used for storage by the data subsystem, stop critical services, and other routine tasks before restarting.

[0126] According to the above embodiments of this disclosure, compared to the communication interruption between upstream and downstream devices during the entire hot restart process of the intermediate device in a traditional daisy chain cascade system, the method and apparatus of this disclosure can greatly shorten the time that communication between upstream and downstream devices is affected by hot restart.

[0127] According to embodiments of this disclosure, a computer-readable storage medium storing the aforementioned software or computer program may also be provided, wherein when the computer program is executed by at least one processor, it causes the at least one processor to perform or assist in performing any of the methods described above according to exemplary embodiments of this disclosure. Examples of computer-readable storage media herein include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R, BD-R BD-RE, Blu-ray or optical disc storage, hard disk drive (HDD), solid-state drive (SSD), card storage (such as multimedia cards, secure digital (SD) cards, or ultra-fast digital (XD) cards), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid-state drive, and any other device configured to store a computer program and any associated data, data files, and data structures in a non-transitory manner and to provide the computer program and any associated data, data files, and data structures to a processor or computer so that the processor or computer can execute the computer program. The instructions or computer program in the aforementioned computer-readable storage medium can run in an environment deployed in computer devices such as clients, hosts, agent devices, servers, etc. Furthermore, in one example, the computer program and any associated data, data files, and data structures are distributed across a networked computer system, such that the computer program and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner through one or more processors or computers.

[0128] Those skilled in the art will understand that the illustrative embodiments described above are not intended to be limiting. It should be understood that any two or more of the embodiments disclosed herein can be combined in any combination. Furthermore, other embodiments may be utilized and other changes may be made without departing from the spirit and scope of the subject matter presented herein. It will be readily understood that aspects of the invention disclosed herein, as generally described herein and illustrated in the accompanying drawings, can be arranged, substituted, combined, separated, and designed in a variety of different configurations, all of which are contemplated herein.

[0129] Those skilled in the art will understand that the various illustrative logic blocks, modules, circuits, and steps described herein can be implemented in hardware, software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps are described above in the form of sets of functions. Whether such sets of functions are implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described sets of functions in different ways for each specific application, but such design decisions should not be construed as departing from the scope of this application.

[0130] The various illustrative logic blocks, modules, and circuits described in this application may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternatives, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration.

[0131] The steps of the methods or algorithms described in this application may be embodied directly in hardware, in a software module executed by a processor, or in a combination of both. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read and write information to / from the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative, the processor and storage medium may reside as discrete components in the user terminal.

[0132] In one or more exemplary designs, the functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, the latter including any medium that facilitates the transfer of a computer program from one location to another. Storage media may be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0133] The above description is merely an exemplary embodiment of this application and is not intended to limit the scope of protection of this application. The scope of protection of this application is determined by the appended claims.

Claims

1. An embedded device for a daisy-chain cascade system, comprising: Ethernet switch integrated circuit, which is configured to have bypass mode; as well as A microprocessor configured to connect to an Ethernet switch integrated circuit and configured to determine whether the embedded device needs a hot reboot, and generate an activation bypass signal or a deactivation bypass signal based on the determination result; as well as A bypass control circuit is configured to connect to both the Ethernet switch integrated circuit and the microprocessor, and is configured to receive an activation bypass signal or a deactivation bypass signal from the microprocessor, and generate a bypass control signal based on the activation or deactivation bypass signal. The Ethernet switch integrated circuit is configured as follows: Receive bypass control signals from the bypass control circuit; Bypass mode is activated or deactivated based on bypass control signals. The microprocessor is also configured to initiate a hot restart process for the embedded device in response to the Ethernet switch integrated circuit activating bypass mode.

2. The embedded device as described in claim 1, wherein, When the microprocessor determines whether the embedded device needs to be warm-rebooted, the microprocessor notifies the upstream and downstream network devices connected to the embedded device to suspend their communication with the embedded device.

3. The embedded device as described in claim 2, wherein, When the Ethernet switch integrated circuit activates bypass mode, the microprocessor notifies the upstream and downstream network devices connected to the embedded device to continue their communication with the embedded device.

4. The embedded device as described in claim 3, wherein, The bypass control circuit includes: D flip-flop, The D trigger is configured to lock the Ethernet switch integrated circuit in bypass mode for a period of time based on a bypass control signal.

5. The embedded device as described in claim 4, wherein, The bypass control circuit is also configured to receive a network reset signal from the microprocessor and, based on the bypass control signal and the network reset signal, send a reset signal to the Ethernet switch integrated circuit for controlling the reset of the Ethernet switch integrated circuit.

6. The embedded device as claimed in claim 5, wherein, When the bypass control signal indicates that the bypass mode of the Ethernet switch integrated circuit is activated, the bypass control circuit determines the reset signal based solely on the bypass control signal, thus bypassing the network reset signal.

7. The embedded device as claimed in claim 6, wherein, The bypass control circuit also includes: OR gate or non-inverting tri-state buffer, The inputs of the OR gate or non-inverting tri-state buffer are the bypass control signal from the D flip-flop and the network reset signal from the microprocessor, and the output is a reset signal used to control the reset of the Ethernet switch integrated circuit.

8. The embedded device as claimed in claim 7, wherein, The bypass control circuit further includes an AND gate configured to receive a system reset signal from a power management integrated circuit and a network reset signal from a microprocessor, and generate a reset signal to be sent to the OR gate.

9. The embedded device according to any one of claims 1 to 7, wherein, When the Ethernet switch's integrated circuit activates bypass mode, an indicator light is used to indicate that bypass mode is activated.

10. The embedded device according to any one of claims 1 to 7, wherein, When the Ethernet switch integrated circuit activates bypass mode, it provides a reference clock signal to the microprocessor.

11. The embedded device according to any one of claims 1 to 7, wherein, Whether the embedded device needs to be warm-rebooted is determined in response to at least one of the following: the new firmware download of the Ethernet switch integrated circuit is completed, the network settings are restored, the factory settings are restored, and the software is updated.

12. The embedded device according to any one of claims 1 to 7, wherein, The embedded device includes at least one of the following: a multimedia terminal, a set-top box, a game console, a wireless microphone receiver, a smart device docking station, and a wireless access point device.

13. A method of operating an embedded device in a daisy-chain cascading system, wherein the daisy-chain cascading system includes an embedded device, an upstream network device and a downstream network device connected to the embedded device, the embedded device including an Ethernet switch integrated circuit, a microprocessor and a bypass control circuit interconnected, the method comprising: The microprocessor determines whether the embedded device needs a hot reboot, and generates an activation bypass signal or a deactivation bypass signal based on the determination result; as well as The bypass control circuit receives and generates an activation bypass signal or a deactivation bypass signal from the microprocessor, and generates a bypass control signal based on the activation bypass signal or the deactivation bypass signal. The bypass control signal is received from the bypass control circuit by the Ethernet switch integrated circuit; The bypass mode is activated or deactivated by the Ethernet switch integrated circuit based on the bypass control signal. The microprocessor responds to the Ethernet switch integrated circuit by activating the bypass mode, thus initiating the hot restart process of the embedded device.

14. The method of claim 13, further comprising: When it is determined whether the embedded device needs to be warm-rebooted, the microprocessor notifies the upstream and downstream network devices connected to the embedded device to suspend their communication with the embedded device.

15. The method of claim 14, further comprising: When the Ethernet switch integrated circuit is determined to be in bypass mode, the microprocessor notifies the upstream and downstream network devices connected to the embedded device to continue their communication with the embedded device.

16. The method of claim 15, further comprising: The Ethernet switch integrated circuit is locked in bypass mode for a period of time based on the bypass control signal indicating activation of bypass mode.

17. The method of claim 16, further comprising: When the bypass control signal indicates that the bypass mode of the Ethernet switch integrated circuit is activated, the bypass control circuit generates a reset signal for the Ethernet switch integrated circuit based solely on the bypass control signal, thus bypassing the network reset signal received from the microprocessor.

18. The method of any one of claims 13 to 17, wherein, When the Ethernet switch integrated circuit enters bypass mode, it provides a reference clock signal to the microprocessor.

19. The method of any one of claims 13 to 17, wherein, Whether the embedded device needs to be warm-rebooted is determined in response to at least one of the following: the new firmware download of the Ethernet switch integrated circuit is completed, the network settings are restored, the factory settings are restored, and the software is updated.

20. The method of any one of claims 13 to 17, wherein, The embedded device includes at least one of the following: a multimedia terminal, a set-top box, a game console, a wireless microphone receiver, a smart device docking station, and a wireless access point device.

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