A multi-protocol adaptive dynamic switching system and method based on FPGA

Abstract

This invention provides a multi-protocol adaptive dynamic switching system and method based on FPGA. The system includes an optical fiber interface module, an optical fiber interface management module, and a line rate dynamic adaptive module. The optical fiber interface module is used for optical fiber data transmission and reception, and protocol identification processing. The optical fiber interface management module is used for link initialization and real-time monitoring of link status. The line rate dynamic adaptive module is used to retrieve the DRP parameter set corresponding to the protocol type from its internal storage unit to adjust the line rate of data transmission. The optical fiber interface management module is also used for reset control and line rate adjustment procedures. This invention overcomes the shortcomings of existing FPGA high-speed communication links, such as rigid protocol configuration, inability to link protocol and physical layer line rates, and insufficient system autonomous operation and maintenance capabilities. It realizes a multi-protocol adaptive switching system that can automatically identify protocol types and dynamically match physical layer line rates without manual intervention.

Description

Technical Field

[0001] This invention belongs to the field of electronic engineering technology, specifically relating to a multi-protocol adaptive dynamic switching system and method based on FPGA. Background Technology

[0002] With the increasing demand for high-speed data transmission in fields such as industrial measurement and control, communications, and heterogeneous computing in data centers, FPGA (Field-Programmable Gate Array) has become the core processing carrier for high-speed communication links due to its high parallelism and low latency hardware characteristics. Currently, FPGA high-speed transceivers are commonly used in various communication protocols such as Aurora, SRIO, and bare protocols to meet the interconnection needs between different devices. For example, in UAVs and radar signal processing systems, FPGAs, as the core communication hub, need to support hot backup and dynamic switching of multiple fiber optic links. For instance, the main link uses the Aurora protocol to transmit high-definition images, while the backup link uses the SRIO protocol to transmit control commands. When the main link is interrupted by interference, it needs to seamlessly switch to the backup link. Some temporarily accessed devices may use bare protocols to transmit emergency data.

[0003] However, existing FPGA high-speed communication link technologies still have the following significant limitations.

[0004] (1) Lack of flexibility in static rate configuration and protocol adaptation Existing fiber optic communication protocols and line rates are usually fixed, meaning they can only be statically configured for a single protocol and line rate. They lack the ability to dynamically adjust to multiple protocols. Switching communication protocols requires manual modification or modification of DRP parameter values ​​by the host computer, and may even require reloading the FPGA bit stream, which can delay the switching time by 3 to 5 minutes. This cannot meet the low latency requirements of industrial real-time measurement and control and emergency communication.

[0005] (2) Lack of linkage adaptation mechanism between protocol identification and line rate Existing technologies have not yet established a linkage adaptation mechanism between protocol identification and physical layer parameters. Under the premise that multiple protocol link layers and logic layers are pre-built in the same bit stream of FPGA, the physical layer line rate cannot be automatically matched with the protocol type, resulting in poor link compatibility in multi-protocol coexistence scenarios. A large amount of additional adaptation logic needs to be developed, which increases the complexity of system integration.

[0006] (3) Insufficient system self-configuration capability Traditional solutions rely on manual intervention from the host computer for protocol switching, lacking autonomous identification and configuration capabilities. In scenarios such as unattended industrial monitoring and control and field operations, they are unable to cope with sudden link protocol switching needs, and the system's autonomous operation and maintenance capabilities are insufficient. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a multi-protocol adaptive dynamic switching system and method based on FPGA, so as to overcome the defects of rigid protocol configuration, inability to link protocol and physical layer line rate and insufficient system autonomous operation and maintenance capability in the existing FPGA high-speed communication link, and realize a multi-protocol adaptive switching system that can automatically identify protocol type and dynamically match physical layer line rate without manual intervention.

[0008] In a first aspect, the present invention provides a multi-protocol adaptive dynamic switching system based on FPGA, the system comprising an optical fiber interface module, an optical fiber interface management module, and a line rate dynamic adaptive module. The fiber optic interface module is used for the transmission and reception of fiber optic data and protocol identification processing. It includes a high-speed transceiver, a protocol identification submodule, and a protocol logic layer processing submodule. The high-speed transceiver includes a control interface, a dynamic reconfiguration interface, and a data output interface. The fiber optic interface management module is connected to the control interface of the high-speed transceiver. It is used to send initialization commands to the high-speed transceiver to establish a physical layer link and to monitor the link status lock signal output by the high-speed transceiver in real time. The high-speed transceiver is used to provide a high-speed serial data interface. After the physical layer link is established under the control of the fiber optic interface management module, it converts the fiber optic serial data received from the external fiber optic link into parallel data and outputs it through the data output interface. The protocol identification submodule is connected to the data output interface of the high-speed transceiver. It is used to extract frame structure features from parallel data and compare the frame structure features with the pre-stored protocol feature library to identify the protocol type of the current link. The protocol logic layer processing submodule is used to call the corresponding protocol parsing logic according to the protocol type to parse parallel data; The line rate dynamic adaptive module is connected to the protocol identification submodule and the dynamic reconfiguration interface respectively. It retrieves the DRP parameter set corresponding to the protocol type from its internal storage unit and writes it to the high-speed transceiver through the dynamic reconfiguration interface to adjust the line rate when the high-speed transceiver transmits data with the external optical fiber link. The fiber optic interface management module is also used to send a reset signal to the high-speed transceiver or re-trigger the protocol type identification and line rate adjustment process when an abnormal link status lock signal or a change in protocol type is detected.

[0009] Optionally, the protocol identification submodule is specifically used for: The first 8 bytes of parallel data output from the high-speed transceiver are extracted as feature fields. The frame synchronization word, protocol identifier bit or check word information in the feature fields are extracted and compared with the pre-stored protocol feature library to identify the protocol type.

[0010] Optionally, the line rate dynamic adaptive module includes a protocol type detection unit, an internal storage unit, a dynamic reconfiguration state machine, and a configuration result feedback unit; The protocol type detection unit is used to continuously monitor the protocol type of the current link at a preset period and store the protocol type detection results. Internal storage unit is used to pre-store a mapping table of different protocol types and their corresponding dynamic reconfiguration port parameter sets; The dynamic reconfiguration state machine is used to read dynamic reconfiguration port parameters from the internal storage unit and convert the dynamic reconfiguration port parameters into configuration signals that conform to the dynamic reconfiguration port interface timing. The configuration result feedback unit is used to monitor the configuration process and output an indication signal indicating whether the configuration was successful or failed.

[0011] Optionally, the linear rate dynamic adaptive module is specifically used for: The protocol type detection unit compares the protocol type identified in this cycle with the protocol type in the previous cycle. If the comparison result indicates that the protocol type has changed, then according to the protocol type identified this time, the DRP parameter set corresponding to the protocol type identified this time is read from the internal storage unit through address mapping. The read DRP parameter set is input to the dynamic reconfiguration state machine, which converts the read DRP parameter set into timing signals of the dynamic reconfiguration port interface according to a preset timing sequence, and writes the timing signals into the high-speed transceiver through the dynamic reconfiguration interface. The configuration result feedback unit receives and outputs feedback signals indicating whether the configuration was successful or failed.

[0012] Optionally, the dynamically reconfigurable port pre-stored parameter set includes at least the parameters used to configure the internal phase-locked loop of the high-speed transceiver. , , and Parameters, line rate of high-speed transceiver Determined by the following formula:

[0013] in, This indicates the reference clock frequency input to the high-speed transceiver.

[0014] Optionally, the fiber optic interface management module is specifically used for: The fiber optic link status is monitored at fixed time intervals. If an abnormal link status lock signal is detected, a reset command is sent to the high-speed transceiver to re-establish the physical layer link. If a change in protocol type is detected, the line rate dynamic adaptive module is triggered to re-execute the DRP parameter set retrieval and writing process.

[0015] Optionally, the fiber optic interface management module also includes: The clock buffer unit is used to buffer and divide the external input reference clock through a phase-locked loop to provide a stable clock for the system. The reset management unit is used to perform hardware reset and software reset using a hierarchical reset mechanism to complete the module initialization.

[0016] Optionally, the protocol logic layer processing submodule specifically includes: Based on the protocol type, the corresponding protocol parsing logic is invoked to perform frame verification, payload data extraction, or format conversion on the parallel data before outputting it through the user's fiber optic data interface.

[0017] Optionally, the link status lock signal includes the lock status signal of the clock data recovery circuit or an indication signal that the physical layer link bit error rate is lower than a preset threshold.

[0018] Secondly, the present invention provides an FPGA-based multi-protocol adaptive dynamic switching method, applied to the aforementioned FPGA-based multi-protocol adaptive dynamic switching system, comprising: The fiber optic interface management module sends initialization commands to the high-speed transceiver to establish a physical layer link with the external fiber optic link and monitors the link status lock signal output by the high-speed transceiver. After the physical layer link is successfully established, the protocol identification submodule extracts frame structure features from the parallel data output by the high-speed transceiver and compares the frame structure features with the pre-stored protocol feature library to identify the protocol type of the current link. The line rate dynamic adaptive module retrieves the corresponding pre-stored dynamic reconfiguration port parameter set from the internal storage unit according to the identified protocol type, and writes it to the high-speed transceiver through the dynamic reconfiguration interface to adjust the line rate of the high-speed transceiver to match the protocol type. The parallel data is parsed and processed by the protocol logic layer processing submodule, which calls the corresponding protocol parsing logic according to the protocol type. The link status is monitored in real time through the fiber optic interface management module. When an abnormal link status lock signal or a change in protocol type is detected, the physical layer link establishment or line rate dynamic adaptation process is triggered to be re-executed.

[0019] The present invention has at least the following beneficial effects: First, by extracting frame structure features from parallel data through the protocol identification submodule and comparing them with a pre-stored protocol feature library, the protocol type of the current link is automatically identified, and the line rate dynamic adaptive module is activated to adjust the line rate. This solves the configuration limitation of existing technologies that only adapt to a single line rate for a single protocol when switching line rates, and realizes seamless switching of line rates for multiple protocols without manual intervention, thus meeting the needs of multi-protocol switching; Second, the line rate dynamic adaptive module receives the protocol identification result, retrieves the pre-stored DRP parameter set from the internal storage unit, and writes it to the high-speed transceiver through the dynamic reconfiguration interface to achieve automatic adjustment of physical layer parameters. This establishes a linkage adaptation logic between protocol type and physical layer line rate. Based on the pre-built multi-protocol link layer logic on the FPGA, it realizes the automatic calling of physical layer parameters according to the protocol identification result, improves link compatibility in multi-protocol coexistence scenarios, and reduces the development cost of additional adaptation logic. Third, the fiber optic interface management module sends initialization commands to establish physical layer links, monitors link status lock signals, and sends reset signals to restart the process if an anomaly is detected. This helps reduce link switching latency and enhances the system's autonomous configuration capabilities. Attached Figure Description

[0020] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.

[0021] Figure 1 This is an architecture diagram of a multi-protocol adaptive dynamic switching system based on FPGA in one embodiment of this application; Figure 2 This is a flowchart of another embodiment of the FPGA-based multi-protocol adaptive dynamic switching method in this application; Among them, 101 is the fiber optic interface module, 102 is the fiber optic interface management module, 103 is the line rate dynamic adaptive module, 101A is the high-speed transceiver, 101B is the protocol identification submodule, and 101C is the protocol logic layer processing submodule. Detailed Implementation

[0022] The technical solution of the present invention will now be described in detail and completely with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0023] In the description of this invention, it should be noted that the terms "upper", "lower", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0024] To facilitate understanding, the technical terms used in this application will be explained below.

[0025] FPGA (Field-Programmable Gate Array) is a type of semiconductor device. Unlike traditional Application-Specific Integrated Circuits (ASICs), the hardware structure of an FPGA can be reconfigured through software programming after the design is completed, offering high flexibility and customizability. An FPGA consists of numerous logic blocks, interconnect resources, and I / O ports. Each logic block can implement basic logic functions (such as AND gates and OR gates), and they are connected through flexible interconnect structures to form complex digital circuits. The core advantage of FPGA lies in its programmability: designers can configure the FPGA using software tools to generate different hardware functions according to their needs.

[0026] A high-speed transceiver is a circuit used for high-speed data transmission in digital systems.

[0027] Example 1 like Figure 1 As shown, this embodiment provides a multi-protocol adaptive dynamic switching system based on an FPGA. The system uses a Xilinx Kintex-7 series FPGA (XC7K325T) as its core hardware platform and utilizes its embedded GTX high-speed transceiver 101A as the physical layer communication interface. Specifically, the system includes a fiber optic interface management module 102, a fiber optic interface module 101, and a line rate dynamic adaptive module 103.

[0028] The fiber optic interface module 101 is used to realize the transmission and reception of fiber optic data and protocol identification processing. In this embodiment of the invention, the fiber optic interface module 101 integrates three core sub-units: a high-speed transceiver 101A (GTX), a protocol identification sub-module 101B, and a protocol logic layer processing sub-module 101C.

[0029] The high-speed transceiver 101A, serving as the physical layer interface to the external fiber optic link, mainly consists of three parts: a transmitter, a receiver, and a clock recovery circuit. The components of the high-speed transceiver 101A are described below.

[0030] The main function of the transmitter is to convert parallel data into serial data and transmit it through a high-speed serial link. The specific implementation process is as follows: The transmitter first encodes the input parallel data, typically using 8B / 10B or 64B / 66B encoding. The purpose of encoding is to increase data redundancy, improve data immunity to interference, and enhance transmission reliability.

[0031] The encoded data is fed into a serializer, which converts the data from parallel to serial form. A serializer typically consists of multiple shift registers, each corresponding to one data bit. Under the control of a clock signal, the shift registers output the data bit by bit, forming a serial data stream. To improve signal transmission distance and interference immunity, the transmitter usually uses differential driving to convert the serial stream into a differential signal. A differential signal consists of a set of signals with opposite phases and equal amplitudes, which can effectively suppress common-mode noise and electromagnetic interference.

[0032] The main function of the receiver is to convert the received serial differential signal into parallel data, and then perform data decoding and verification. The specific implementation process is as follows: The receiver first converts the received differential signal into a single-ended signal using a differential receiver. The differential receiver utilizes the phase difference and amplitude of the differential signal to suppress common-mode noise and electromagnetic interference, improving the signal-to-noise ratio. The deserializer converts the received single-ended signal from serial to parallel format. The deserializer typically consists of multiple shift registers, each corresponding to one data bit. Under the control of a clock signal, the shift registers read the data bits sequentially, forming a parallel data stream. The decoder decodes the parallel data stream to reconstruct the original data. Simultaneously, the receiver also verifies the data to detect errors during data transmission. If an error is detected, the receiver takes appropriate corrective measures or reports it to the upper-level system.

[0033] Clock recovery circuits are a crucial component of high-speed serial transceivers. They are responsible for extracting the transmitter's clock signal from the received serial data stream and synchronizing it to the receiver's clock domain. There are many methods for implementing clock recovery circuits, such as those based on phase-locked loops (PLLs) or delay-line-based clock recovery circuits (DLLs). The performance of the clock recovery circuit directly affects the data transmission rate and bit error rate of the high-speed serial transceiver.

[0034] In this embodiment of the invention, the high-speed transceiver 101A provides three key interfaces: a control interface (for receiving control commands such as initialization and reset), a dynamic reconfiguration port (DRP, for dynamically modifying the parameters of the transceiver's internal registers), and a data output interface (for outputting parallel data after serial-to-parallel conversion).

[0035] Specifically, the fiber optic interface management module 102 is connected to the control interface of the high-speed transceiver 101A. The core functions of the fiber optic interface management module 102 include two aspects: First, upon system power-on or reset, it sends an initialization command to the high-speed transceiver 101A to initiate the physical layer link establishment process, driving the internal CDR circuit of the high-speed transceiver 101A to lock the external input clock; second, it monitors the link status lock signal output by the high-speed transceiver 101A in real time (e.g., the RXCDRLOCK signal inside the GTX). When this signal is high, it indicates that the physical layer link has been successfully established, the clock has been locked, and the bit error rate is lower than a preset threshold (e.g., ...). In this embodiment of the invention, the fiber optic interface management module 102 is implemented by a finite state machine (FSM) inside the FPGA, with a clock frequency of 100MHz.

[0036] After receiving the initialization command from the fiber optic interface management module 102 and successfully establishing the physical layer link, the high-speed transceiver 101A enters normal operating mode. At this time, the high-speed transceiver 101A performs serial-to-parallel conversion on the high-speed serial data (e.g., line rate of 1.25Gbps, 2.5Gbps, or 5Gbps) received from the external fiber optic link, outputs parallel data with a bit width of 16 bits or 32 bits, and transmits it to the subsequent protocol identification submodule 101B through the data output interface.

[0037] The protocol identification submodule 101B is directly connected to the data output interface of the high-speed transceiver 101A. The core function of the protocol identification submodule 101B is to parse parallel data in real time and identify the communication protocol running on the current link (e.g., Aurora, SRIO, or a user-defined raw protocol). In specific implementation, the protocol identification submodule 101B internally includes a shift register and feature comparison logic. It extracts the first 8 bytes from the data stream (parallel data) as a feature field, extracts information such as the frame synchronization word (e.g., 0xBC in the Aurora protocol), protocol identifier bits, or checksum from this field, and then compares this feature information with a protocol feature library pre-stored in the FPGA block random access memory (BRAM). Once a match is successful, the corresponding protocol type code is output (e.g., 3b001 represents Aurora, 3b010 represents SRIO, and 3b100 represents a raw protocol). In this embodiment of the invention, the protocol identification period is designed to be configurable, with a default value of 1ms, to ensure the real-time performance and accuracy of the identification.

[0038] The protocol logic layer processing submodule 101C is also connected to the data output interfaces of the protocol identification submodule 101B and the high-speed transceiver 101A. The protocol logic layer processing submodule 101C has pre-built link layer parsing logic for various protocols, such as frame verification and flow control for the Aurora protocol, and transaction layer parsing for the SRIO protocol. Upon receiving the protocol type output by the protocol identification submodule 101B, the protocol logic layer processing submodule 101C automatically calls the corresponding parsing logic through a multiplexer (MUX) to process the parallel data output by the high-speed transceiver 101A, including frame verification, payload data extraction, and byte order conversion. Finally, it outputs the valid user data to other user logic within the FPGA through a standard FIFO (First-In-First-Out) interface.

[0039] The line rate dynamic adaptive module 103 is one of the core innovations of this invention. The line rate dynamic adaptive module 103 is connected to the protocol identification submodule 101B and the dynamic reconfiguration port of the high-speed transceiver 101A, respectively. Internally, it integrates a protocol type detection unit, an internal memory unit (BRAM), a DRP reconfiguration state machine, and a configuration result feedback unit. The internal memory unit pre-stores a "protocol type-DRP parameter" mapping table. This table, based on system requirements, pre-calculates and stores the DRP configuration parameter sets required for different protocols and their corresponding line rates (mainly including parameters used to configure the GTX internal CPLL or QPLL). , , In one feasible implementation, the DRP configuration parameter set is shown in Table 1.

[0040] Table 1

[0041] Table 1 shows the DRP encoding values, which users need to enter when using the system. However, the data in the calculation formula provided by Xilinx is the attribute encoding value. Table 2 shows the conversion of Table 1 into an attribute encoding table.

[0042] Table 2

[0043] When the protocol identification submodule 101B identifies a new protocol type, its protocol type detection unit detects this change and triggers the parameter reading process. Using address mapping, the corresponding DRP parameter set is read from a specified address range in the internal storage unit and sent to the DRP reconfiguration state machine. Following the DRP port read / write timing specified in the Xilinx GTX manual (write address first, then data, waiting for the DRPRDY signal to go high), the DRP reconfiguration state machine sequentially writes the parameters into the corresponding address registers of the high-speed transceiver 101A through the dynamic reconfiguration interface, thereby dynamically adjusting its physical layer line rate to precisely match the newly identified protocol type.

[0044] Finally, the fiber optic interface management module 102 also undertakes global monitoring responsibilities. During system operation, it continuously monitors the link status lock signal. If this signal changes from high to low (indicating link lockout or abnormality), or if it receives a protocol type change indication from the protocol identification submodule 101B, it will immediately intervene: for link abnormalities, it sends a reset signal to the high-speed transceiver 101A, forcing it to re-execute the physical layer link establishment process; for protocol type changes, it triggers the line rate dynamic adaptation module 103 to re-execute the aforementioned DRP parameter retrieval and writing process, thereby achieving fully automatic, closed-loop link maintenance and dynamic switching.

[0045] The following details the specific working process of the line rate dynamic adaptive module 103 when switching the protocol type from Aurora (1.25Gbps) to SRIO (2.5Gbps).

[0046] First, assume the system is currently transmitting data stably at a line rate of 1.25Gbps using the Aurora protocol. At this time, the protocol type encoding output by the protocol identification submodule 101B is 3b001 (corresponding to Aurora). The protocol type detection unit inside the line rate dynamic adaptive module 103 compares the currently identified protocol type with the result of the previous cycle (also 3b001) in each detection cycle (1ms). If the result is determined to be "unchanged," no action is triggered, and the process returns to continue monitoring.

[0047] Subsequently, the external link protocol was changed to the SRIO protocol. The feature fields extracted from the parallel data by the protocol identification submodule 101B no longer matched the Aurora feature, but instead matched the pre-stored SRIO feature library, thus outputting a new protocol type code 3b010.

[0048] The protocol type detection unit of the line rate dynamic adaptive module 103 detects this change (from 3b001 to 3b010) in the next detection cycle, determines the result as "protocol type change", and immediately triggers the dynamic configuration process. Based on the new protocol type encoding 3b010, it generates a corresponding BRAM read address (e.g., base address + offset 0x010), and reads the pre-stored DRP parameter set corresponding to the SRIO 2.5Gbps line rate from the internal BRAM through address mapping. Referring to the partial parameter examples shown in Table 1, for a 2.5Gbps line rate, assuming a reference clock frequency of 200MHz, the read DRP encoded value is: M=16. =1, =3, D=2, converted to attribute code value: M=1, =5, =5, D=4, substitute into the formula to get the output line rate, in Mbps.

[0049] Specifically, the line rate of the high-speed transceiver 101A Determined by the following formula:

[0050] in, This indicates the reference clock frequency input to the high-speed transceiver 101A.

[0051] The read parameter set is loaded into the DRP reconfiguration state machine in parallel. Upon startup, the state machine first pulls the DRPEN (enable) signal high, then writes the address corresponding to the first parameter (e.g., DRP address 0x05 for parameter M) to the DRPADDR port, simultaneously pulling the DRPWE (write enable) signal high and writing the parameter value to the DRPDI port. After several clock cycles, the DRPRDY signal is detected as high, indicating that the write operation is complete. The state machine then continues writing the next parameter, sequentially configuring all key parameters such as N1 (address 0x5E), N2, and D. The entire DRP configuration process typically takes tens to hundreds of microseconds.

[0052] After all parameters are written, the configuration result feedback unit detects that the state machine has entered the IDLE state without reporting any errors, and outputs a high-level "configuration successful" pulse signal. This signal is synchronized to the fiber optic interface management module 102 for monitoring by the upper-layer system. Simultaneously, the PLL inside the high-speed transceiver 101A relocks according to the newly written parameters, dynamically switching the line rate from 1.25Gbps to 2.5Gbps, successfully matching the physical layer requirements of the SRIO protocol. Subsequently, the protocol logic layer processing submodule 101C automatically calls the SRIO protocol parsing logic according to the new protocol type code 3b010 to correctly parse subsequent data. The entire switching process, from protocol change to line rate adjustment completion, takes less than 1 millisecond, achieving seamless switching at the millisecond level.

[0053] The following details the monitoring and handling process of link anomalies by the fiber optic interface management module 102.

[0054] Assume the system is operating stably with the SRIO protocol. Due to an unexpected fiber optic cable break or a severe degradation in signal quality, the CDR circuit inside the high-speed transceiver 101A is unable to recover the correct clock from the received data, causing its output link state lock signal (e.g., the RXCDRLOCK signal inside the GTX) to change from high to low.

[0055] The fiber optic interface management module 102 samples this signal every monitoring cycle (e.g., 10ms). When a low level is sampled, it is determined that the "link state lock signal is abnormal". According to the preset logic, the module immediately sends a reset pulse signal to the control interface of the high-speed transceiver 101A (e.g., pulling high the RXPMARESET or GTTXRESET pin of GTX). After receiving the reset signal, the high-speed transceiver 101A jumps to the reset state in its internal state machine, clears the FIFO and registers, restarts the initialization process of the PMA layer, and attempts to lock the external clock again.

[0056] While sending the reset signal, the fiber optic interface management module 102 also records the current state through a state machine and waits to re-monitor the link state lock signal. Once the signal returns to a high level, it indicates that the physical layer link has been successfully rebuilt. Subsequently, the system process automatically returns to the protocol identification step, where the protocol identification submodule 101B restarts the identification of the protocol type on the new link, thereby triggering the subsequent line rate adaptation and data transmission process. Through this mechanism, the system can autonomously complete the re-establishment of the link and the restoration of communication without manual intervention after a link anomaly.

[0057] Example 2 In this embodiment of the invention, the core functions of protocol detection, DRP parameter table mapping and calling, and dynamic reconfiguration can be embedded into a customized ASIC (an integrated circuit designed for specific application requirements). By pre-setting the protocol type, rate parameter mapping circuit and configuration instruction control logic inside the ASIC, the ASIC can dynamically adjust the port parameters of the high-speed transceiver directly through the hardware circuit according to the link protocol detection results during operation, thereby realizing adaptive configuration of the line rate.

[0058] Compared to FPGAs, ASICs offer higher performance and lower power consumption, making them suitable for large-scale deployments. Unlike general-purpose processors or programmable logic devices (such as FPGAs), ASICs have fixed functionality once manufactured and cannot be reconfigured via software. They excel at performing specific tasks, offering efficiency and optimization, but lack flexibility and adaptability. The ASIC design process involves multiple steps, such as requirements analysis, circuit design, placement and routing, and verification testing, typically resulting in a long development cycle and high costs.

[0059] Example 3 As attached Figure 2 The illustrated FPGA-based multi-protocol adaptive dynamic switching method includes the following steps: Step 21: Send an initialization command to the high-speed transceiver through the fiber optic interface management module to establish a physical layer link with the external fiber optic link, and monitor the link status lock signal output by the high-speed transceiver. Step 22: After the physical layer link is successfully established, the frame structure features are extracted from the parallel data output by the high-speed transceiver through the protocol identification submodule, and the frame structure features are compared with the pre-stored protocol feature library to identify the protocol type of the current link. Step 23: The line rate dynamic adaptive module retrieves the corresponding pre-stored dynamic reconfiguration port parameter set from the internal storage unit according to the identified protocol type, and writes it to the high-speed transceiver through the dynamic reconfiguration interface to adjust the line rate of the high-speed transceiver to match the protocol type. Step 24: The parallel data is parsed and processed by calling the corresponding protocol parsing logic through the protocol logic layer processing submodule according to the protocol type. Step 25: Monitor the link status in real time through the fiber optic interface management module. When an abnormal link status lock signal or a change in protocol type is detected, trigger the re-execution of the physical layer link establishment or line rate dynamic adaptation process.

[0060] This method achieves millisecond-level seamless multi-protocol switching through a hardware-automated protocol identification, line rate dynamic adaptation, and link status monitoring process. It utilizes a protocol identification submodule to extract frame features from received data and compare them with a pre-stored feature library, automatically determining various protocol types such as Aurora and SRIO without manual intervention. Then, a line rate dynamic adaptation module retrieves the corresponding DRP parameter set from the internal storage unit based on the identification results and writes it to the high-speed transceiver, establishing a hardware-level linkage mechanism of "protocol identification → rate adaptation → physical layer configuration," enabling dynamic matching of line rate with protocol type. Simultaneously, the fiber optic interface management module monitors link status lock signals in real time, autonomously triggering a reset or reconfiguration process when link anomalies or protocol changes are detected, forming a closed-loop maintenance mechanism. This completely solves the core defects of existing technologies, such as reliance on manual intervention, switching delays of several minutes, and the inability to perform autonomous maintenance.

[0061] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of protection of this application is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this application as described above, which are not provided in detail for the sake of brevity.

[0062] One or more embodiments in this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of this application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments in this application should be included within the protection scope of this application.

Claims

1. A FPGA-based multi-protocol adaptive dynamic switching system, characterized in that, It includes a fiber optic interface module, a fiber optic interface management module, and a line rate dynamic adaptive module; The fiber optic interface module is used for the transmission and reception of fiber optic data and protocol identification processing, including a high-speed transceiver, a protocol identification submodule, and a protocol logic layer processing submodule; the high-speed transceiver includes a control interface, a dynamic reconfiguration interface, and a data output interface. The fiber optic interface management module is connected to the control interface of the high-speed transceiver and is used to send initialization commands to the high-speed transceiver to establish a physical layer link and to monitor the link status lock signal output by the high-speed transceiver in real time. The high-speed transceiver is used to provide a high-speed serial data interface. After the physical layer link is established under the control of the fiber optic interface management module, it converts the fiber optic serial data received from the external fiber optic link into parallel data and outputs it through the data output interface. The protocol identification submodule is connected to the data output interface of the high-speed transceiver and is used to extract frame structure features from the parallel data and compare the frame structure features with a pre-stored protocol feature library to identify the protocol type of the current link. The protocol logic layer processing submodule is used to call the corresponding protocol parsing logic according to the protocol type to parse the parallel data; The line rate dynamic adaptive module is connected to the protocol identification submodule and the dynamic reconfiguration interface respectively. It retrieves the DRP parameter set corresponding to the protocol type from its internal storage unit and writes it to the high-speed transceiver through the dynamic reconfiguration interface to adjust the line rate when the high-speed transceiver transmits data with the external optical fiber link. The fiber optic interface management module is also used to send a reset signal to the high-speed transceiver or re-trigger the protocol type identification and line rate adjustment process when the abnormal link status lock signal or the change in protocol type is detected.

2. The FPGA-based multi-protocol adaptive dynamic switching system of claim 1, wherein, The protocol identification submodule is specifically used for: The first 8 bytes are extracted from the parallel data output by the high-speed transceiver as a feature field. The frame synchronization word, protocol identifier bit or check word information in the feature field is extracted and compared with the pre-stored protocol feature library to identify the protocol type.

3. The FPGA-based multi-protocol adaptive dynamic switching system of claim 1, wherein, The line rate dynamic adaptive module includes a protocol type detection unit, an internal storage unit, a dynamic reconfiguration state machine, and a configuration result feedback unit. The protocol type detection unit is used to continuously monitor the protocol type of the current link at a preset period and store the protocol type detection results. The internal storage unit is used to pre-store a mapping table of different protocol types and their corresponding dynamic reconfiguration port parameter sets; The dynamic reconfiguration state machine is used to read dynamic reconfiguration port parameters from the internal storage unit and convert the dynamic reconfiguration port parameters into configuration signals that conform to the dynamic reconfiguration port interface timing. The configuration result feedback unit is used to monitor the configuration process and output an indication signal indicating whether the configuration is successful or failed.

4. The FPGA-based multi-protocol adaptive dynamic switching system of claim 3, wherein, The line rate dynamic adaptive module is specifically used for: The protocol type detection unit compares the current identified protocol type with the protocol type of the previous cycle. If the comparison result indicates a change in the protocol type, then based on the currently identified protocol type, the DRP parameter set corresponding to the currently identified protocol type is read from the internal storage unit through address mapping. The read DRP parameter set is input to the dynamic reconfiguration state machine, which converts the read DRP parameter set into timing signals of the dynamic reconfiguration port interface according to a preset timing sequence, and writes the timing signals into the high-speed transceiver through the dynamic reconfiguration interface. The configuration result feedback unit receives and outputs feedback signals indicating whether the configuration was successful or failed.

5. The FPGA-based multi-protocol adaptive dynamic switching system according to claim 4, characterized in that, The dynamic reconfiguration port pre-storage parameter set at least includes parameters for configuring a phase-locked loop inside a high-speed transceiver 、 、 and The line rate of the high-speed transceiver is determined by the following formula: wherein, represents a reference clock frequency input to the high-speed transceiver.

6. The FPGA-based multi-protocol adaptive dynamic switching system of claim 1, wherein, The fiber optic interface management module is specifically used for: The fiber optic link status is detected at fixed time intervals; if an abnormality is detected in the link status lock signal, a reset command is sent to the high-speed transceiver to re-establish the physical layer link; if a change in protocol type is detected, the line rate dynamic adaptive module is triggered to re-execute the DRP parameter set retrieval and writing process.

7. The FPGA-based multi-protocol adaptive dynamic switching system of claim 1, wherein, The fiber optic interface management module also includes: The clock buffer unit is used to buffer and divide the external input reference clock through a phase-locked loop to provide a stable clock for the system. The reset management unit is used to perform hardware reset and software reset using a hierarchical reset mechanism to complete the module initialization.

8. The FPGA-based multi-protocol adaptive dynamic switching system according to claim 1, characterized in that, The protocol logic layer processing submodule specifically includes: Based on the protocol type, the corresponding protocol parsing logic is invoked to perform frame verification, payload data extraction, or format conversion on the parallel data, and then output through the user's fiber optic data interface.

9. The FPGA-based multi-protocol adaptive dynamic switching system according to claim 1, characterized in that, The link state lock signal includes the lock state signal of the clock data recovery circuit or an indication signal that the physical layer link bit error rate is lower than a preset threshold.

10. A multi-protocol adaptive dynamic handover method based on FPGA, applied to the multi-protocol adaptive dynamic handover system based on FPGA as described in any one of claims 1 to 9, characterized in that, include: The fiber optic interface management module sends initialization commands to the high-speed transceiver to establish a physical layer link with the external fiber optic link and monitors the link status lock signal output by the high-speed transceiver. After the physical layer link is successfully established, the protocol identification submodule extracts frame structure features from the parallel data output by the high-speed transceiver, and compares the frame structure features with the pre-stored protocol feature library to identify the protocol type of the current link. The line rate dynamic adaptive module retrieves the corresponding pre-stored dynamic reconfiguration port parameter set from the internal storage unit according to the identified protocol type, and writes it to the high-speed transceiver through the dynamic reconfiguration interface to adjust the line rate of the high-speed transceiver to match the protocol type. The parallel data is parsed and processed by the protocol logic layer processing submodule by calling the corresponding protocol parsing logic according to the protocol type. The fiber optic interface management module monitors the link status in real time. When the link status lock signal is detected to be abnormal or the protocol type is changed, the physical layer link establishment or line rate dynamic adaptation process is triggered to be re-executed.

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